GN1090

1.0Gb/s to 14.5Gb/s 4-Channel Array Receiver

with Control and Monitoring

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Features Applications
• Typical power dissipation 240mW (total for 4 channels • 40Gb/s Ethernet
and control) • Infiniband DDR and FDR
• Four independent receiver channels • Compatible with QSFP+ transceiver modules

A
• Compatible with 250μm pitch PIN diode arrays • Active optical cables
• 1.0Gb/s to 14.5Gb/s per channel rates supported

ND
• I2C digital interface for external micro communication Description
• Comprehensive set of digital diagnostic and The GN1090 is a 4-channel array receiver designed for
monitoring parameters parallel and multi-channel datacom and telecom modules
• On-chip control and monitoring with One Time and AOC.
Programmable (OTP) storage The receiver is an advanced design optimised for excellent
• Transimpedance amplifier with limiting output across optical performance while achieving low power

•
entire input signal range
Limiting amplifier with programmable output swing
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consumption. It features a high-gain transimpedance
amplifier and limiting amplifier with output pre-emphasis
to compensate for connector and PCB trace losses.
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• Output equalization for connector and PCB
compensation It is compatible with an external microcontroller using an
• Detection of loss of Rx data, optional squelch when no I2C interface to enable a user to monitor performance over
input data temperature and life.
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• Multiplexed RSSI current output for optical alignment Enables use of low-cost microprocessors with minimal
• Monitoring of Rx power resources to deliver a DDMI monitoring solution. All
sensors and multiplexed ADC are integrated, minimizing
• Individual channel LOS and global hardware output
external MCU requirements.
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LOS status
• Available as bare die dimensions: Digital diagnostic and monitoring parameters are
1.8mm x 2.0mm x 200μm measured by an integrated ADC and can be read out by a
microcontroller.
• Operating ambient temperature range:
–40oC to +85oC
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• Pb-free/RoHS-compliant
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Final Data Sheet Rev.5
GENDOC-057589 September 2015 Proprietary & Confidential
 Channel 4 Receiver

Channel 2 Receiver

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Channel 1 Receiver

Supply Regulator

on
PINK1 OUTP1
Trans-Impedance Limiting CML
PINA1 Amplifier Amplifier Driver
OUTN1

Signal Offset Pre-

A
RSSI Control
Detect Correction emphasis

LOS

ND
RSSI1 Control
RSSI
Select Registers LOS
RSSI2
Digital Fault
A–>D
Diagnostics Logic
Converter LOS

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SDA
Interface
I2C

SCL
OTP Temperature VDD
Memory Sensor Sensor
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CS

Digital Controller and Diagnostics

Figure A: GN1090 Functional Block Diagram

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Final Data Sheet Rev.5
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Revision History

Version ECO Date Changes and/or Modifications

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September Updates to Table 2-4: DC Electrical Characteristics and Table 2-5: AC
5 027525
2015 Electrical Characteristics. Converted document to Final Data Sheet status.

4 026529 June 2015 Updates.

on
3 024392 February 2015 Updates.

2 024186 February 2015 Updates.

September Corrections to pin #35 and pin #37 in Figure 1-1, Table 1-1 and Table 1-2.
1 022032
2014 Update to Chip Select/Reset (CS).

September Converted document to Preliminary Data Sheet. Updates throughout

A
0 020068
2014 entire document.

December
F 015618 Updates throughout entire document.
2013

ND
E 011910 March 2013 Added Pad Co-ordinates. Updates to Register Information.

December
D 009886 Updates to Pad Assignments and Positions and Register Information.
2012

C 158650 October 2012 Updates.

September
B 158546 Updated format.
2012

November

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A 157344 New document.
2011

Contents
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1. Pad Assignment ...............................................................................................................................................5
1.1 Pad Assignments and Positions ....................................................................................................5
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1.2 Pad Descriptions .................................................................................................................................6

1.3 Pad Co-ordinates ................................................................................................................................7
2. Electrical Characteristics................................................................................................................................9
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2.1 Absolute Maximum Ratings ...........................................................................................................9

2.2 ESD Protection .....................................................................................................................................9
2.3 Operating Conditions .................................................................................................................... 10
2.4 DC Electrical Characteristics ........................................................................................................ 10
2.5 AC Electrical Characteristics ......................................................................................................... 11
h-

2.6 GN1090 Rx Digital Pins Pull-up/Pull-down Status ............................................................... 13

3. Detailed Description.................................................................................................................................... 14
3.1 Summary ............................................................................................................................................. 14
3.2 Transimpedance Amplifier ........................................................................................................... 14
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3.2.1 Signal Detect and LOS ....................................................................................................... 14

3.3 Limiting Amplifier ............................................................................................................................ 14
3.3.1 Polarity Invert........................................................................................................................ 14
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3.3.2 Rx Output Level Control ................................................................................................... 14

3.3.3 Output Pre-Emphasis......................................................................................................... 14
3.3.4 Squelch ................................................................................................................................... 15
3.4 Digital Interface ................................................................................................................................ 15
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3.4.1 Digital Diagnostics.............................................................................................................. 15

3.4.2 I2C Interface Bus Protocol................................................................................................. 16

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 3.5 Device Reset ...................................................................................................................................... 19
3.6 Chip Select/Reset (CS) .................................................................................................................... 20
3.7 RSSI Pin Configuration ................................................................................................................... 20

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4. Register Information.................................................................................................................................... 22
4.1 Register Map Structure .................................................................................................................. 22
4.2 Control and Status Register (CSR) Map ................................................................................... 23

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4.3 Register Descriptions ..................................................................................................................... 31
4.3.1 Global Status Registers...................................................................................................... 31
4.3.2 Per Channel Status Registers........................................................................................... 31
4.3.3 Global Control Registers ................................................................................................... 32
4.3.4 Per Channel Control Registers........................................................................................ 33

A
5. Digital Control Block.................................................................................................................................... 36
6. Application Information............................................................................................................................. 37

ND
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Final Data Sheet Rev.5
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1. Pad Assignment

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1.1 Pad Assignments and Positions
The GN1090 is available as a bare die product, with the pad positions suitable for wire

on
bonding to 250μm pitch PIN diode arrays. Pad assignments are shown in Figure 1-1, as
viewed from the top of the die.

PINA1

PINA2

PINA3

PINA4
PINK1

PINK2

PINK3

PINK4
TEST

TEST
VSS

VSS

VSS

VSS

A
57 56 55 54 53 52 51 50 49 48 47 46 45 44

ND
VSS 1 43 VSS

VDD 2 42 VDD

VDD 3 41 VDD

RSSI1

VSS
4

5
ht 40 RSSI1

39 VSS
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RSSI2 6 38 RSSI2

I2C_1 7 37 VSS

LOS 8 36 LOS
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I2C_0 9 35 VSS

CS 10 34 CS

VSS 11 33 VSS
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SCL 12 32 SCL

VSS 13 31 VSS

SDA 14 30 SDA
h-

VSS 15 29 VSS

16 17 18 19 20 21 22 23 24 25 26 27 28
VSS

OUTN1

OUTP1

VSS

OUTN2

OUTP2

VSS

OUTN3

OUTP3

VSS

OUTN4

OUTP4

VSS
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Figure 1-1: GN1090 Pad Assignment (and position on die)

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Note:
Die Thickness = 200μm ±10% typically.
Die Size: x = 1.8mm, y = 2.0mm (tolerance +10μm to +40μm).
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Final Data Sheet Rev.5
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1.2 Pad Descriptions

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Table 1-1: GN1090 Pad Assignments and Positions

Pad Number Pad Name Pad Type Description

on
1, 5, 11, 13, 15, 16, 19, 22,
Grounding for IC. Use as many ground bonds as possible for best
25, 28, 29, 31, 33, 35, 37, VSS GND
performance.
39, 43, 44, 53, 54, 57

Provides power to IC. Use as many VDD connections as possible

2, 3, 41, 42 VDD Power
for best performance.

A
Analogue monitor of mean PD current (multiplexed).
4, 40 RSSI1 Analogue
Open-drain PMOS current source.

ND
Analogue monitor of mean PD current (multiplexed).
6, 38 RSSI2 Analogue
Open-drain PMOS current source.

7 I2C_1 Digital Input Inverse of bit [2] of I2C address.

8, 36 LOS Digital Output Global hardware LOS status output.

9 I2C_0 Digital Input Inverse of bit [1] of I2C address.

10, 34

12, 32
CS

SCL
Digital Input

Digital Input ht
Chip Select.

I2C clock interface.

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14, 30 SDA Digital I/O I2C data interface.

17 OUTN1 H/S Output Negative differential output for channel 1.

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18 OUTP1 H/S Output Positive differential output for channel 1.

20 OUTN2 H/S Output Negative differential output for channel 2.

21 OUTP2 H/S Output Positive differential output for channel 2.

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23 OUTN3 H/S Output Negative differential output for channel 3.

24 OUTP3 H/S Output Positive differential output for channel 3.

26 OUTN4 H/S Output Negative differential output for channel 4.

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27 OUTP4 H/S Output Positive differential output for channel 4.

45 PINK4 H/S Input PD cathode connection for channel 4.

46 PINA4 H/S Input PD anode connection for channel 4.

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47 PINK3 H/S Input PD cathode connection for channel 3.

48 PINA3 H/S Input PD anode connection for channel 3.

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49 PINK2 H/S Input PD cathode connection for channel 2.

50 PINA2 H/S Input PD anode connection for channel 2.

51 PINK1 H/S Input PD cathode connection for channel 1.

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52 PINA1 H/S Input PD anode connection for channel 1.

55, 56 TEST I/O Do not connect.

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Final Data Sheet Rev.5
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1.3 Pad Co-ordinates

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Table 1-2: Pad Co-ordinates

Pad Pad Type & Pad Opening

Pad Name Pad X Pad Y

on
Number (μm)

1 VSS -780.000 763.000 Double Pad 129 x 69

2 VDD -780.000 601.000 Double Pad 129 x 69

3 VDD -780.000 439.000 Double Pad 129 x 69

A
4 RSSI1 -780.000 306.000 Single Pad 69 x 69

5 VSS -780.000 203.000 Single Pad 69 x 69

ND
6 RSSI2 -780.000 100.000 Single Pad 69 x 69

7 I2C_1 -780.000 -3.000 Single Pad 69 x 69

8 LOS -780.000 -106.000 Single Pad 69 x 69

9 I2C_0 -780.000 -209.000 Single Pad 69 x 69

10

11
CS

VSS
-780.000

-780.000
-312.000

-415.000
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Single Pad 69 x 69

Single Pad 69 x 69
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12 SCL -780.000 -518.000 Single Pad 69 x 69

13 VSS -780.000 -621.000 Single Pad 69 x 69

14 SDA -780.000 -724.000 Single Pad 69 x 69

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15 VSS -780.000 -820.000 Corner Pad

16 VSS -687.000 -880.000 Corner Pad

17 OUTN1 -594.000 -880.000 Octagonal Pad 69 x 69

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18 OUTP1 -444.000 -880.000 Octagonal Pad 69 x 69

19 VSS -346.000 -880.000 Single Pad 69 x 69

20 OUTN2 -248.000 -880.000 Octagonal Pad 69 x 69

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21 OUTP2 -98.000 -880.000 Octagonal Pad 69 x 69

22 VSS 0.000 -880.000 Single Pad 69 x 69

23 OUTN3 98.000 -880.000 Octagonal Pad 69 x 69

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24 OUTP3 248.000 -880.000 Octagonal Pad 69 x 69

25 VSS 346.000 -880.000 Single Pad 69 x 69

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26 OUTN4 444.000 -880.000 Octagonal Pad 69 x 69

27 OUTP4 594.000 -880.000 Octagonal Pad 69 x 69

28 VSS 687.000 -880.000 Corner Pad

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29 VSS 780.000 -820.000 Corner Pad

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Final Data Sheet Rev.5
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Table 1-2: Pad Co-ordinates (Continued)

Pad Pad Type & Pad Opening

Pad Name Pad X Pad Y
Number (μm)

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30 SDA 780.000 -724.000 Single Pad 69 x 69

on
31 VSS 780.000 -621.000 Single Pad 69 x 69

32 SCL 780.000 -518.000 Single Pad 69 x 69

33 VSS 780.000 -415.000 Single Pad 69 x 69

34 CS 780.000 -312.000 Single Pad 69 x 69

A
35 VSS 780.000 -209.000 Single Pad 69 x 69

36 LOS 780.000 -106.000 Single Pad 69 x 69

ND
37 VSS 780.000 -3.000 Single Pad 69 x 69

38 RSSI2 780.000 100.000 Single Pad 69 x 69

39 VSS 780.000 203.000 Single Pad 69 x 69

40 RSSI1 780.000 306.000 Single Pad 69 x 69

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41 VDD 780.000 439.000 Double Pad 129 x 69

42 VDD 780.000 601.000 Double Pad 129 x 69

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43 VSS 780.000 763.000 Double Pad 129 x 69

44 VSS 780.000 880.000 Single Pad 69 x 69

45 PINK4 630.000 880.000 Octagonal Pad 69 x 69

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46 PINA4 505.000 880.000 Octagonal Pad 69 x 69

47 PINK3 380.000 880.000 Octagonal Pad 69 x 69

48 PINA3 255.000 880.000 Octagonal Pad 69 x 69

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49 PINK2 130.000 880.000 Octagonal Pad 69 x 69

50 PINA2 5.000 880.000 Octagonal Pad 69 x 69

51 PINK1 -120.000 880.000 Octagonal Pad 69 x 69

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52 PINA1 -245.000 880.000 Octagonal Pad 69 x 69

53 VSS -360.000 880.000 Single Pad 69 x 69

54 VSS -455.000 880.000 Octagonal Pad 69 x 69

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55 TEST -555.000 880.000 Octagonal Pad 69 x 69

56 TEST -655.000 880.000 Octagonal Pad 69 x 69

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57 VSS -755.000 880.000 Octagonal Pad 69 x 69

Note: Referenced to the centre of the die.

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Final Data Sheet Rev.5
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2. Electrical Characteristics

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2.1 Absolute Maximum Ratings
Table 2-1: Absolute Maximum Ratings

on
Parameter Value Unit Notes

Supply Voltage: -0.5 to 4.6 V 1

-0.5 to VDD+0.5

A
Voltage at any input or output V 1

Junction temperature range -40 to 125 o 2

C

ND
Reflow Profile (TMAX) 255 + 5 o 3
C

Storage Temperature -40 to 150 oC —

Notes:
1. Compliant with JEDEC JESD8C.01.
2. The user should ensure that there is sufficiently low thermal resistance to the circuit board and within the module to
maintain this junction temperature.

ht
3. Exposed to re-flow temperature for 3s maximum.

Table 2-1 lists the absolute maximum ratings for the GN1090. Conditions exceeding the
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limits listed may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
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2.2 ESD Protection

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All of the IC pads are protected against ESD. The ESD voltage compliance is listed in
Table 2-2 with the appropriate testing methods.

Table 2-2: ESD Protection

h-

Pads ESD Voltage Remarks

Non high-speed
± 2kV JESD 22-A114-B (Human Body Model)
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pads

All other pads

except PINK[1:4] and ± 1kV JESD 22-A114-B (Human Body Model)
PINA[1:4]
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Note: The Transimpedance Amplifier input pins PINK[1:4] and PINA[1:4] have limited ESD protection, and will not
meet the above requirements. These pins only have to withstand up to 100V stress due to wire bonding and are not
exposed to external stress at module pins.
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Final Data Sheet Rev.5
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2.3 Operating Conditions

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Table 2-3: Operating Conditions

Parameter Unit Symbol Min Typ Max Notes

on
Ambient Operating oC Tamb -40 — +85 1
Temperature

Supply Voltage V VDD 2.97 3.3 3.63 —

PSU Noise mVrms 50 — — 2

A
Data Rate Gb/s 1.0 10.3125 14.5 —

ND
Notes:
1. The junction temperature of the GN1090 should be maintained at less than 105°C to ensure that parametric performance is maintained within
this specification. The user should ensure that there is sufficiently low thermal resistance to the circuit board and within the module to maintain
this junction temperature
2. Applies for noise >1kHz on host VDD.

2.4 DC Electrical Characteristics

DC electrical characteristics are specified over the recommended operating conditions,
unless otherwise stated: ht
lig
• Typical values are for VDD = 3.3V, Tamb = 25oC

Table 2-4: DC Electrical Characteristics

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Parameter Conditions Symbol Min Typ Max Units Notes

Rx Output
Tr

Swing =
600mVppd
pre-emphasis =
Supply Current 36ps with 30%; IIDD — 73 110 mA —
over
h-

temperature
and supply
voltages

Supply Current
At nominal IIDDPD — 2 2.5 mA —
Power-down
ec

Power Dissipation PD — 241 400 mW —

Junction Temperature
mt

Sensor Measurement TJACC -3.0 — +3.0 o —

C
Accuracy

Voltage (PINK-PINA) VPINK-VPINA 1.5 2.4 3.13 V —

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Table 2-4: DC Electrical Characteristics (Continued)

Parameter Conditions Symbol Min Typ Max Units Notes

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Control Digital Input and Output Specifications

CS, I2C_0, I2C_1 Input

VIL -0.3 — 0.8 V —

on
Low Voltage

CS, I2C_0, I2C_1 Input

VIH 2.0 — VDD+0.3 V —
High Voltage

CS, I2C_0, I2C_1 Input VIL = 0V or IIL

— ±5 — μA —

A
Current VIH = VDD IIH

SDA, SCL Input Low

VIL -0.5 — 0.3 VDD V —
Voltage

ND
SDA, SCL Input High
VIH 0.7 VDD — — V —
Voltage

LOS Output Low Voltage IOL = 100μA VOL — — 0.2 V —

High-speed Receiver Input and Output Specifications

ht Ω
Output Termination Differential ROUT 75 100 125 —

Temination Mismatch — — 5 % —
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LOS Assert Range 1 — 63 μA mean —

LOS Step Size — 1 — μA —

RSSI Range 2 — 1600 μA —

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RSSI Accuracy — ±10 ±25 % —

RSSI Compliance Voltage

1.5 — — V 1
(sourcing)
Tr

Notes:
1. Compliance voltage relative to VDD.

2.5 AC Electrical Characteristics

h-

AC electrical characteristics are specified over the recommended operating conditions:

• Typical values are for VDD = 3.3V, and Tamb = 25oC

ec

• Specifications assume default setting and 50Ω transmission lines on the

RX_OUTP/N I/Os
• Signal outputs are assumed to be AC-coupled through 100nF capacitors
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Final Data Sheet Rev.5
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Table 2-5: AC Electrical Characteristics

Parameter Conditions Symbol Min Typ Max Units Notes

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Data Input and Output Parameters

on
Data Rate NRZ 1.0 10.3 14.5 Gb/s —

20% - 80%
(output
Output Rise/Fall Time — 15 21 ps 1, 2
pre-emphasis
optimized)

A
Common Mode AC Noise — — 10 mVrms —

12-2xsqrt

ND
0.01-4GHz SDD22 — — dB 3
(fGHz)
Differential Mode Return Loss
6.3-13log10
4-11GHz SDD22 — — (fGHz/5.5)
dB 3

0.01-2.5GHz SCC22 — — 7-1.6FGHz dB 3

Common Mode Return Loss
2.5-11GHz SCC22 — — 3 dB 3

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Output Voltage Swing 200 — 1000 mVpp —

Output Voltage Swing Step

— 50 — mVpp —
Size
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1Gb/s — 15 35 pspp
Output Deterministic Jitter DJ 1
10.3125Gb/s — 5 13 pspp
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Output Random Jitter RJ — — 3 psrms 1

Channel Skew — — 125 ps —

Input Referred Noise — 0.9 1.4 μArms 3

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Input Overload — — 1.8 mApp —

Input Sensitivity — 16.0 28.0 μApp 4

Optical Sensitivity (MM) 10.3125Gb/s — -15.0 -12.5 dBm 5

h-

Optical Sensitivity (SM) 10.3125Gb/s — -17.5 -15.0 dBm 6

3dB Bandwidth 8 — 12 GHz 3

LF Cut-off — 125 — kHz —

ec

Output Pre-emphasis — — 6 dB —

Output Pre-emphasis Step

— 5 — % —
Size
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Receiver Control Signals

Reset Assert Time — 2 — μs 7

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Rx LOS Assert Time — — 50 μs 8

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Final Data Sheet Rev.5
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Table 2-5: AC Electrical Characteristics (Continued)

Parameter Conditions Symbol Min Typ Max Units Notes

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Rx LOS De-Assert Time — — 50 μs 8

Rx Squelch Assert Time — — 50 μs 9

on
Rx Squelch De-assert Time — — 50 μs 10

Squelch Breakthrough Voltage — — 1 mVpp —

Sleep Assert Time — 5 — μs —

μs

A
Sleep De-assert Time — 5 — —

Notes:

ND
1. Applies to chip only (excludes board effects). Measured at 10.3125Gb/s maximum data rate. Results at higher data rate may vary.
2. Tested with 10.3125Gb/s 1/4 rate 1010.
3. Guaranteed by design.
4. 1E-12 BER, PRBS 231, 10.3125Gb/s.
5. Unstressed sensitivity in dBm (OMA). Assumes 0.5 A/W responsivity, > 3.0 dB ER, 1E-12 BER, PRBS 231, 10.3125Gb/s. Sensitivity (and resulting Input
Sensitivity in μApp) at different data rates may vary. Results are dependent on customer ROSA design and photodiode.
6. Unstressed sensitivity in dBm (OMA). Assumes 0.9 A/W responsivity, > 4.5 dB ER, 1E-12 BER, PRBS 231, 10.3125Gb/s. Sensitivity (and resulting Input

ht
Sensitivity in μApp) at different data rates may vary. Results are dependent on customer ROSA design and photodiode.
7. Applies to the CS pin when the “CS as reset” function is enabled.
8. Detected Loss of Signal will be signalled on the LOS pin within the maximum time, i.e. LOS goes to logic HIGH, and cleared to a logic LOW within the
maximum time on receiving valid data.
lig
9. The Rx outputs are put into a squelched state within the maximum specified time from detecting loss of signal.
10. The Rx outputs revert to normal logic levels within the maximum specified time from receiving valid input data.

2.6 GN1090 Rx Digital Pins Pull-up/Pull-down Status

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Table 2-6: GN1090 Rx Digital Pins Pull-up/Pull-down Status

Tr

Pin Function Description Direction Status

7 I2C_1 Inverse of bit [2] of I2C address Input 1MΩ pull-up

Open-drain with 100kΩ

h-

8, 36 LOS Global hardware LOS status output Output

pull-up

9 I2C_0 Inverse of bit [1] of I2C address Input 1MΩ pull-up

10, 34 CS Chip Select Input 1MΩ pull-up

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12, 32 SCL I2C clock interface Input High-impedance

14, 30 SDA I2C data interface Input/Output Open-drain

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Final Data Sheet Rev.5
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3. Detailed Description

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3.1 Summary
The GN1090 is a highly-integrated 4-channel array receiver with a receive path

on
containing a high-gain transimpedance amplifier and a high-sensitivity limiting
amplifier. The transimpedance amplifier includes a receive amplitude level sensor,
which can detect loss of signal. The output of the limiting amplifier contains a
pre-emphasis stage, which is programmable to compensate for module connector and
PCB trace losses.

A
The received optical power is measured as the RSSI current, which is available as digital
output of the Analog-to-Digital Converter (ADC) over the I2C interface (or additionally at

ND
the RSSI1 or RSSI2 ports).
An extensive set of integrated digital diagnostic and monitoring parameters together
with on-chip ADCs enables use with cost-effective external micro-controllers.

3.2 Transimpedance Amplifier

3.2.1 Signal Detect and LOS

ht
lig
The LOS threshold is programmable between 1.0μA and 63.0μA mean average current.
The LOS threshold can be adjusted via the I2C interface.
ue

3.3 Limiting Amplifier

3.3.1 Polarity Invert

Tr

This feature allows for polarity inversion of the data for simpler routing and more
flexible module design. Data polarity is inverted when the POLARITY_INVERT register
bit (4) from the RXn_CTRL register is a logic HIGH.
h-

3.3.2 Rx Output Level Control

The level at the Rx outputs can be controlled from a minimum of 200mV to a maximum
ec

of 1000mV in 50mV steps.

3.3.3 Output Pre-Emphasis

mt

The GN1090 has an optional output eye adjustment, which uses pre-emphasis to
compensate for high-frequency losses introduced by any connectors in the Rx electrical
path and PCB traces. The pre-emphasis can be set by I2C. The pre-emphasis is capable of
Se

equalizing an SFI channel.

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Final Data Sheet Rev.5
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3.3.4 Squelch
The Rx outputs are squelched if a Loss of Signal condition is detected. In this condition,
the outputs are forced to DC state midway between a logic LOW and a logic HIGH.

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3.4 Digital Interface

on
The GN1090 incorporates a digital diagnostic capability to monitor system operating
characteristics, i.e. received optical power, to be communicated to the host over a serial
interface. It is intended to support SFF-8436 diagnostics on the module microcontroller.

A
The GN1090 has a slave interface (SDA, SCL) to download control and digital diagnostics
monitoring information to a host processor. The slave interface cannot initiate data
transmission. The host processor provides the interface master, which initiates data

ND
transmission.
The I2C serial interfaces supports a single-master fast-mode (400kb/s) signalling. The
GN1090 acts as an I2C slave with a default addresses of B8h.

3.4.1 Digital Diagnostics

ht
The GN1090 continuously samples the parameters listed below and stores latest results
in local registers as defined in the Control and Status Register Map:
lig
Chip Junction Temperature
Chip VDD
Received Optical Power (RSSI Current) for each channel
ue

Start
Tr

Temperature
conversion
h-

VDD conversion
ec

N
Last Y
RSSI conversion
mt

channel?

Figure 3-1: DDM State Machine

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Final Data Sheet Rev.5
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3.4.2 I2C Interface Bus Protocol
Note: Ensure there is no I2C communications on the bus until the device is powered-up,
otherwise the I2C bus may not function correctly and the device will need to be reset.

ly
The host-supplied SCL input to GN1090 is used to positive edge clock data into GN1090
and negative clock data out of GN1090.

on
The SDA pin is bi-directional for serial data transfer. This pin is open-drain and may be
wire-OR’ed with any other open-drain devices on the same bus.
The SDA and SCL pins are normally pulled HIGH with external 10kΩ resistors. Data on
SDA may only change during SCL LOW periods. Data changes during SCL HIGH periods

A
indicate a start or stop condition.
A HIGH-to-LOW transition of SDA with SCL HIGH is a start condition, which must precede
any other command.

ND
A LOW-to-HIGH transition of SDA with SCL HIGH is a stop condition.
All addresses and data words are transmitted serially to or from the GN1090 in 8-bit
words. Every byte on the SDA line will be 8 bits long. Data is transferred MSB first.
After sending each 8-bit word, the transmitter releases the SDA line for one bit time,
during which the receiver is allowed to pull the SDA line LOW to acknowledge (ACK) that

ht
it has received each word. Device address bytes and data bytes initiated from the host
microcontroller are acknowledged by the GN1090. Read data bytes transmitted from
the GN1090 are acknowledged by the host for all but the final byte, for which the host
lig
will respond with a stop instead of an ACK.
The I2C interface and all registers will be reset when the active-low CS pin is held LOW
for a minimum of 2μs (when configured as a reset pin with the CS_RESET register). The
CS pin features a weak pull-up to force it to a HIGH state when unconnected.
ue

tSU:STA tSU:DAT tHD:DAT tSU:STO tBUF

Tr

SDA
h-

SCL

tHD:STA tHIGH tLOW tr tf

ec

Figure 3-2: I2C Interface Timing Parameters

mt
Se

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Final Data Sheet Rev.5
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Table 3-1: I2C Interface Timing
Fast Mode 1MHz Mode

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Parameter Symbol Unit
Min Max Min Max

on
SCL clock frequency fSCL 0 400 0 — kHz

Bus free time between STOP

tBUF 1.3 — — — μs
and start conditions

Hold time start condition tHD:STA 0.6 — TBD — μs

A
Low period of the SCL clock tLOW 1.3 — TBD — μs

High period of the SCL clock tHIGH 0.6 — TBD — μs

ND
Set up time for a repeated
tSU:STA 0.6 — TBD — μs
START condition

Data hold time tHD:DAT 0 — TBD — μs

Data set-up time tSU:DAT 100 — 0 — ns

Rise time for both SDA and

tr — 300 50 — ns

ht
SCL

Fall time for both SDA and SCL tf — 300 — 150 ns

Set-up time for STOP

lig
tSU:STO 0.6 — — 150 μs
condition

3.4.2.1 Read and Write Operations

ue

The GN1090 uses auto-increment addressing, so that access to a single register address
can be followed by multiple reads or writes, which automatically access subsequent
registers. This process continues until the host issues a STOP command.
Tr

The GN1090 maintains a single byte data word address pointer containing the last
address accessed during the latest read or write operation, incremented by one. The
address pointer is incremented whenever a data word is received or sent by the device.
This address stays valid between operations as long as power is maintained.
h-

A random access read operation requires a “dummy” write operation to load in the
target byte address. This is accomplished by the following sequence:
1. The target 8-bit data word address is sent following the device address write word
and acknowledged by the GN1090.
ec

2. The host then generates another START condition (aborting the dummy write
without incrementing the counter) and a current address read by sending a device
read address.
mt

3. The GN1090 acknowledges the device address and serially clocks-out the
requested data word.
4. The host does not respond with an acknowledge, but does generate a STOP
Se

condition once the data word is read.

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Final Data Sheet Rev.5
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 _
S SLAVE ADDRESS W A/A REGISTER ADDRESS A Sr SLAVE ADDRESS R A DATA A/A P
(n bytes
+ ack.)*

ly
write
read direction
of transfer
* not shaded because may change
transfer direction of Sr = repeated START condition at this point

on
data and acknowledge bits
depends on R/W bits.

A current address read operation requires only the device address read word be sent.
Once acknowledged by the GN1090, the current address data word is serially
clocked-out. The host does not respond with an acknowledge, but does generate a

A
STOP condition once the data word is read.

ND
S SLAVE ADDRESS R/W A DATA A DATA A P

data transferred
(read) (n bytes + acknowledge)

Sequential reads are initiated by either a current address read or a random access
address read. To specify a sequential read, the host responds with an acknowledge
(instead of a STOP) after each data word. As long as the GN1090 receives an
acknowledge, it will serially clock-out sequential data words. The sequence is
terminated when the host responds with a NACK and a STOP instead of an ht
lig
acknowledge.

If the register address is not valid, either by direct write or by incrementing, a write will
be ignored and a read will return a 0.
ue

A device Write requires a sequence of:

• Start
Tr

• Device Address (7 bits)

• R/W set to 0
• Acknowledge
• Register address (8 bits) plus Acknowledge
h-

• Data to be written (8 bits) plus acknowledge

For a single Write, the host sends a STOP. For multiple Writes, the device has
incremented the register pointer and many 8-bit data plus ACK sequences can be sent
ec

(until the register address pointer becomes invalid). The sequence is finally terminated
with a STOP.

S SLAVE ADDRESS R/W A REGISTER ADDRESS A DATA A DATA A/A P

mt

data transferred
‘0’ (write) (n bytes + acknowledge)

from master to slave

A = acknowledge (SDA LOW)
Se

A = not acknowledge (SDA HIGH)

from slave to master S = START condition
P = STOP condition

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Final Data Sheet Rev.5
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3.4.2.2 I2C Time-out Feature
When enabled, the I2C time-out will monitor the SDA signal that is driven out by the
slave. If this signal has been driven LOW by the slave for more than 256μs (typical),

ly
potentially indicating that the I2C communication has been interrupted, the I2C slave
will be reset. It will then be able to receive I2C communications as normal. Enabling this
feature means that the I2C SCL clock frequency cannot be lower than 2kHz.

on
3.5 Device Reset
The GN1090 includes a Power On Reset (POR).

A
The reset sets registers and state machines into their pre-determined default states. If
the OTP has been programmed, the OTP contents will be downloaded after reset
de-assertion.

ND
A “soft reset” can be performed by writing a 0 to the RESET register. All of the digital
circuits are re-initialised except for the I2C interface. The host needs to write a 1 to the
same location to clear the reset.
A soft reset using bit 0 in register 0x3b does not trigger an OTP read.
A soft reset using bit 1 in register 0x3b will trigger an OTP read.
The device can also be programmable via the user interface such that a LOW input on
the Chip Select/Reset (CS) pin will perform a reset.
ht
lig
Soft Reset

Y Y
Reset User Factory Area Download
0x3b [1] 0x3b [0] CRC Check OK?
Register Prog? Factory Area
ue

N N

N N
Tr

Y Y
CS Pin Download
User Area Prog? CRC Check OK?
Reset User Area

Normal
Operation
N
N
Y Y
Factory Area Download
POR CRC Check OK?
Prog? Factory Area
h-

Figure 3-3: Initialization Flow Chart

ec
mt
Se

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Final Data Sheet Rev.5
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3.6 Chip Select/Reset (CS)
The CS pin enables operation of the I2C interface.

ly
If the CS pin is LOW, the I2C interface is disabled and the device will not respond to I2C
commands.
If the CS pin is HIGH, the I2C interface responds to I2C commands as described in

on
Section 3.4.
The CS pin is programmable via the user interface to also:
• Squelch all outputs of the device when set LOW

A
• Reset the device and read the OTP contents into the control registers when set LOW
The default setting for these features is OFF.

ND
3.7 RSSI Pin Configuration
The RSSI pads are intended to provide a measure of the average photodiode current in
up to two of the channel photodiodes, primarily for the active alignment of parallel
optical connectors.

ht
There are two output pads, RSSI_1 and RSSI_2. These pads can be configured to report
any of the channel’s average photodiode current. This configuration is controlled in
registers 34h and 35h. Table 4-2 describes the configuration of these registers.
lig
Figure 3-4 illustrates the connection between the input channels and the RSSI_1 and
RSSI_2 pads.
ue

GN1090 Average
photodiode
currents
Tr CH1

CH2
CH3
CH4

ENABLE ENABLE
(35h[7]) (34h[7])
h-

SMU RSSI_1 RSSI_2 SMU

µA µA

+ CH SELECT CH SELECT +
ec

– (35h[3:0]) (34h[3:0]) –
mt

Figure 3-4: RSSI Pin Configuration

Se

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Final Data Sheet Rev.5
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It is important that the pins RSSI_1 and RSSI_2 are correctly terminated when performing
measurement of the current at either or both pads. When the RSSI currents from two channels
are directed to the RSSI pads, they should BOTH be terminated. Errors will be incurred if one of
the pins is left floating or if there are imbalanced conditions at each pad. If, for example, one of

ly
the RSSI pads (RSSI_1) is left floating, errors can occur if the alternative RSSI pin (RSSI_2) is being
measured. It is imperative for both RSSI pads to be terminated with the same conditions. If
utilising source/measure test equipment, it is recommended to force the same voltage (1V) on

on
to both pins and measure the current on the selected channel.
Invalid Configurations:
1. 34h[3:0] and 35h[3:0] cannot be set to the same value (for example, the same channel

A
cannot be reported to both RSSI pads). This is an invalid state and will cause errors in the
current output on the RSSI pads.
2. When 34h[7] or 35h[7] are set to 0 the read back value of [3:0] in the relevant register will

ND
be invalid.

ht
lig
ue
Tr
h-
ec
mt
Se

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Final Data Sheet Rev.5
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4. Register Information

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4.1 Register Map Structure
The register map is divided into five sections:

on
Table 4-1: Register Map Structure

Range Section

A
00h to 07h Global status information

10h to 17h Parametric and status information by channel

ND
34h to 37h Global setup controls

3Ch to 3Fh Passwords to enable access to the OTP write procedure

Setup controls by channel, intended primarily for configuration at

40h to 74h
power-up.

ht
Note 1: B8h is the write address and B9h is the read address (corresponding to address pads
I2C_0 = HIGH; I2C_1 = HIGH).
lig
The addresses of the first two sections are intended for regular read access by the user in
operational mode.
The third and fifth sections (the control setup sections) are mirrored in OTP memory.
ue

Registers 34h to 37h and 40h to 74h are mirrored in OTP.

Note 2: Users should never attempt to write to the factory area of the register.
Tr
h-
ec
mt
Se

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Final Data Sheet Rev.5
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4.2 Control and Status Register (CSR) Map

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Table 4-2: Control and Status Register Map

Value
Register Bit

on
Register Name R/W OTP Bit Name on Function
Addressh Slice
Reset

Global Status Registers

— — 7:2 RSVD — Reserved.

A
Reports Rx LOS condition on any
R N 1 GLOBAL_RX_LOS 0
channel. Logical OR of LOS flags.
00 STATUS_1

ND
Latched report of Rx LOS condition
on any channel. Logical OR of LOS
R N 0 GLOBAL_RX_LOS_LATCHED 0
flags. Latching is reset on read of
register bit.

3 RX4_LOS — 1 = LOS reported on channel 4

2 RX3_LOS — 1 = LOS reported on channel 3

ht
01 LOS_1_8 R N
1 RX2_LOS — 1 = LOS reported on channel 2

0 RX1_LOS — 1 = LOS reported on channel 1

lig
02 to 04 RSVD — — 7:0 RSVD — Reserved

05 SUPPLY_VOLTAGE R N 7:0 SUPPLY VOLTAGE — 8-bit supply voltage A/D.

06 TEMPERATURE_1 R N 7:0 TEMPERATURE — Temperature MSB.

ue

07 TEMPERATURE_0 R N 7:0 TEMPERATURE — Temperature LSB.

08 to 0F RSVD — — 7:0 RSVD — Reserved.

Tr

Per Channel Status Registers

10 RX1_RSSI_1 R N 7:0 — — Channel 1 RSSI measurement MSB.

11 RX1_RSSI_0 R N 7:0 — — Channel 1 RSSI measurement LSB.

h-

12 RX2_RSSI_1 R N 7:0 — — Channel 2 RSSI measurement MSW.

13 RX2_RSSI_0 R N 7:0 — — Channel 2 RSSI measurement LSW.

14 RX3_RSSI_1 R N 7:0 — — Channel 3 RSSI measurement MSW.

ec

15 RX3_RSSI_0 R N 7:0 — — Channel 3 RSSI measurement LSW.

16 RX4_RSSI_1 R N 7:0 — — Channel 4 RSSI measurement MSW.

17 RX4_RSSI_0 R N 7:0 — — Channel 4 RSSI measurement LSW.

mt

18 to 33 RSVD — — 7:0 RSVD — Reserved.

Se

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Final Data Sheet Rev.5
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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

Global Control Registers

on
0 = RSSI_2 disabled

7 RSSI_2_ENABLE 1 1 = RSSI_2 steers current from

selected RSSI to RSSI_2 analog
output
34 RSSI_2_SELECT R/W Y

A
6:4 RSVD — Reserved.

0 = channel 1
3:0 RSSI_2_SELECT 0x0

ND
3 = channel 4

0 = RSSI_1 Disabled

7 RSSI_1_ENABLE 1 1 = RSSI_1 steers current from

selected RSSI to RSSI_1 analog
output
35 RSSI_1_SELECT R/W Y
6:4 RSVD — Reserved.

3:0

7 ht
RSSI_1_SELECT

RSVD
0x3

—
0 = channel 1
3 = channel 4

Reserved.
lig
1 = Reset state machines and I2C,
6 CS_RESET 0 and read OTP into control registers
when CS pin is taken LOW
ue

1 = Squelch all outputs when CS

5 CS_SQUELCH 0
pin taken LOW

If set, LOS flags in location 1h are

LOS_CHANNEL_LATCH
Tr

CONTROL_ 4 0 latched once set. The flags will be

36 R/W Y _ENABLE
REGISTER_1 reset on reading the registers.

LOS_PIN_POWER_DOWN 0 = LOS inactive on power-down

3 0
_STATE 1 = LOS active on power-down
h-

0 = HIGH for LOS

2 LOS_PIN_POLARITY 0
1 = LOW for LOS

1 SLEEP 0 1 = LOS and RSSI only active

0 POWER_DOWN 0 1 = channel powered-down

ec

Set to allow bits[2:1] of I2C address

7 I2C_ADDR_PAD_EN 0x1 to be set via the via the I2C_1 and
I2C_0 pads.
mt

CONTROL_ 6 I2C_TIMEOUT_EN 0x0 Set to enable I2C time-out.

37 R/W Y
REGISTER_2
5:1 RSVD 0x00 Reserved.
Se

0 I2C_TEST_SPEEDUP 0x0 Set to run I2C at up to 2MHz for test

purposes.

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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

38 to 3A RSVD — — All RSVD — Reserved

on
7:2 RSVD — Reserved

Write 0 to apply reset and 1 to clear

reset. The SOFT_RESET_FULL and
1 SOFT_RESET_FULL 1
SOFT_RESET_PARTIAL bits are

A
3B RESET R/W N mutually exclusive.

Write 0 to apply reset and 1 to clear

reset. The SOFT_RESET_PARTIAL
0 SOFT_RESET_PARTIAL 1

ND
and SOFT_RESET_FULL bits are
mutually exclusive.

Password Registers

Protected setups access password

1 (PASSWORD_0_0 must also be
set).

ht
3C PASSWORD_0_1 W N 7:0 PASSWORD_0_1 —
Set to 0x7D for accessing I2C
features specified in
CONTROL_REGISTER_2[7:6].
lig
Protected setups access password
0 (PASSWORD_0_1 must also be
set).
3D PASSWORD_0_0 W N 7:0 PASSWORD_0_0 —
Set to 0xD1 for accessing I2C
ue

features specified in
CONTROL_REGISTER_2[7:6].

3E PASSWORD_1_1 W N 7:0 PASSWORD_1_1 0xA6 OTP Write password 1.

Tr

3F PASSWORD_1_0 W N 7:0 PASSWORD_1_0 0x8C OTP Write password 0.

h-
ec
mt
Se

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Final Data Sheet Rev.5
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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

Per Channel Control Registers

on
7 RSVD — Reserved.

6 RSVD — Reserved.

1 = disable the LOS function on this

5 LOS_DISABLE —

A
channel

4 POLARITY_INVERT — 1 = inverted signal path polarity

ND
Rate select is used to change the
slew rate of the receiver outputs.
3 RATE SELECT1 —
40 RX1_CTL R/W Y Default settings 00 is
recommended for data rates
10Gb/s and above.
Rate select setting:
2 RATE SELECT0 — 00 → high bit rate
01 → mid bit rate

1
ht SLEEP —
10 and 11 → low bit rate

0 = normal, 1 = sleep mode

lig
0 POWER DOWN — 1 = power-down channel

Adjusts the signal bandwidth for

optimal sensitivity:
— — 7:5 BANDWIDTH_CTRL —
000 = maximum bandwidth
ue

41 RX1_OUTPUT_CTL 111 = minimum bandwidth

OUTPUT AMPLITUDE Set swing 200mVpp to 1000mVpp in

R/W Y 4:0 —
SWING SELECT 50mVpp steps.
Tr

7:5 DELAY — Set pre-emphasis delay.

RX1_ PREEMPH
42 R/W Y Set pre-emphasis magnitude (0%
_CTL 4:0 MAGNITUDE —
to 140% in 5% steps).
h-

7:5 RSVD — Reserved.

0 = Normal
4 FORCE_SQUELCH 0
1 = Squelch forced ON
ec

Sets LOS hysteresis:

000 = 0.5dB
43 RX1_LOS_CTL R/W Y 001 = 1.0dB
3:1 HYSTERESIS — 010 = 1.5dB
mt

011 = 2.0dB
100 = 2.5dB
101 = 3.0dB

0 = Squelch enabled
0 SQUELCH_DISABLE 0
Se

1 = Squelch disabled

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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

Set LOS assert threshold.

44 RX1_LOS_THRESH R/W Y 7:0 LOS_THRESHOLD —

on
Set from 1 to 63μA in 1μA steps.

45 to 4F RSVD — — — RSVD — Reserved.

7 RSVD — Reserved.

6 RSVD — Reserved.

A
1 = disable the LOS function on this
5 LOS_DISABLE —
channel

ND
4 POLARITY_INVERT — 0 = normal, 1 = inverted

Rate select is used to change the

slew rate of the receiver outputs.
3 RATE SELECT1 —
50 RX2_CTL R/W Y Default settings 00 is
recommended for data rates
10Gb/s and above.

ht
Rate select setting:
2 RATE SELECT0 — 00 → high bit rate
01 → mid bit rate
10 and 11 → low bit rate
lig
1 SLEEP — 0 = normal, 1 = sleep mode

0 POWER DOWN — 0 = normal, 1 = disabled

— — 7:5 RSVD — Reserved

ue

51 RX2_OUTPUT_CTL
OUTPUT AMPLITUDE Set swing 200mVpp to 1000mVpp in
R/W Y 4:0 —
SWING SELECT 50mVpp steps.
Tr

7:5 DELAY — Set pre-emphasis delay.

RX2_PREEMPH
52 R/W Y Set pre-emphasis magnitude (0%
_CTL 4:0 MAGNITUDE —
to 140% in 5% steps).

7:5 RSVD — Reserved.

h-

0 = Normal
4 FORCE_SQUELCH —
1 = Squelch forced ON

Sets LOS hysteresis:

ec

000 = 0.5dB
53 RX2_LOS_CTL R/W Y 001 = 1.0dB
3:1 HYSTERESIS — 010 = 1.5dB
011 = 2.0dB
mt

100 = 2.5dB
101 = 3.0dB

0 = Squelch enabled
0 SQUELCH_DISABLE —
1 = Squelch disabled
Se

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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

Set LOS assert threshold.

54 RX2_LOS_THRESH R/W Y 7:0 — —

on
Set from 1 to 63μA in 1μA steps.

55 to 5F RSVD — — — RSVD — Reserved.

7 RSVD — Reserved.

6 RSVD — Reserved.

A
1 = disable the LOS function on this
5 LOS_DISABLE —
channel.

ND
4 POLARITY_INVERT 0 = normal, 1 = inverted

Rate select is used to change the

slew rate of the receiver outputs.
3 RATE SELECT1 —
60 RX3_CTL R/W Y Default settings 00 is
recommended for data rates
10Gb/s and above.

ht
Rate select setting:
2 RATE SELECT0 — 00 → high bit rate
01 → mid bit rate
10 and 11 → low bit rate
lig
1 SLEEP 0 = normal, 1 = sleep mode

0 POWER DOWN 0 = normal, 1 = disabled

— — 7:5 RSVD — Reserved.

ue

61 RX3_OUTPUT_CTL
OUTPUT AMPLITUDE Set swing 200mVpp to 1000mVpp in
R/W Y 4:0 —
SWING SELECT 50mVpp steps.
Tr

7:5 DELAY — Set pre-emphasis delay.

RX3_PREEMPH
62 R/W Y Set pre-emphasis magnitude (0%
_CTL 4:0 MAGNITUDE —
to 140% in 5% steps).

7:5 RSVD — Reserved.

h-

0 = Normal
4 FORCE_SQUELCH —
1 = Squelch forced ON

Sets LOS hysteresis:

ec

000 = 0.5dB
63 RX3_LOS_CTL R/W Y 001 = 1.0dB
3:1 HYSTERESIS — 010 = 1.5dB
011 = 2.0dB
mt

100 = 2.5dB
101 = 3.0dB

0 = Squelch enabled
0 SQUELCH_DISABLE —
1 = Squelch disabled
Se

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Final Data Sheet Rev.5
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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

Set LOS assert threshold.

64 RX3_LOS_THRESH R/W Y 7:0 — —

on
Set from 1 to 63μA in 1μA steps.

65 to 6F RSVD — — All RSVD — Reserved.

7 RSVD — Reserved.

6 RSVD — Reserved.

A
1 = disable the LOS function on this
5 LOS_DISABLE —
channel

ND
4 POLARITY_INVERT — 0 = normal, 1 = inverted

Rate select is used to change the

slew rate of the receiver outputs.
3 RATE SELECT1 —
70 RX4_CTL R/W Y Default settings 00 is
recommended for data rates
10Gb/s and above.

ht
Rate select setting:
2 RATE SELECT0 — 00 → high bit rate
01 → mid bit rate
10 and 11 → low bit rate
lig
1 SLEEP — 0 = normal, 1 = sleep mode

0 POWER DOWN — 0 = normal, 1 = disabled

7:5 RSVD — Reserved.

ue

71 RX4_OUTPUT_CTL R/W Y OUTPUT AMPLITUDE Set swing 200mVpp to 1000mVpp in

4:0 —
SWING SELECT 50mVpp steps.
Tr

7:5 DELAY — Set pre-emphasis delay.

RX4_PREEMPH
72 R/W Y Set pre-emphasis magnitude (0%
_CTL 4:0 MAGNITUDE —
to 140% in 5% steps).

7:5 RSVD — Reserved.

h-

0 = Normal
4 FORCE_SQUELCH —
1 = Squelch forced ON

Sets LOS hysteresis:

ec

000 = 0.5dB
73 RX4_LOS_CTL R/W Y 001 = 1.0dB
3:1 HYSTERESIS — 010 = 1.5dB
011 = 2.0dB
mt

100 = 2.5dB
101 = 3.0dB

0 = Squelch enabled
0 SQUELCH_DISABLE —
1 = Squelch disabled
Se

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Final Data Sheet Rev.5
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Table 4-2: Control and Status Register Map (Continued)

Value
Register Bit
Register Name R/W OTP Bit Name on Function

ly
Addressh Slice
Reset

Set LOS assert threshold.

74 RX4_LOS_THRESH R/W Y 7:0 — —

on
Set from 1 to 63μA in 1μA steps.

75 to 7F RSVD — — All RSVD — Reserved.

The 2 byte registers are stored 'big endian' in 2 bytes (i.e. the most significant byte is

A
contained in the lower address byte and the least significant in the upper).
Note: Registers 80:8F are unused or reserved.

ND
ht
lig
ue
Tr
h-
ec
mt
Se

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Final Data Sheet Rev.5
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4.3 Register Descriptions
Additional details on the operation of each register are described in this section.

ly
4.3.1 Global Status Registers

on
STATUS_1 (00h)
The STATUS_1 register contains an 8-bit digital word that reports the device status. The
active bits are 0 and 1, which are set HIGH to indicate a LOS in any channel.

A
RXN_LOS_FLAGS (01h)

ND
These registers contain the individual LOS flags for the 4 channels.

SUPPLY_VOLTAGE (05h)
This register holds raw precalibration supply voltage ADC readings in 8-bit unsigned
format with a full scale of 2.0V to 4.0V. The host microcontroller is responsible for final
calibration.

TEMPERATURE (06h, 07h) ht

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This register holds raw precalibration temperature ADC readings in 9-bit unsigned
format (data is left justified within the 16-bit field, MSB is bit 15, LSB is bit 7) in
increments of approximately 0.34°C and covering the approximate range of -45°C to
+130°C. The host microcontroller is responsible for final calibration using Equation 4-1 :
ue

TEMPERATURE = slope*TADC+offset Equation 4-1

Where TADC is the raw measured data, slope is a 16-bit fixed point calibrate constant
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and offset is a 16-bit signed 2s complement offset as defined in SFF-8436 for external
calibration.

4.3.2 Per Channel Status Registers

h-

RSSI
These registers hold RSSI current ADC readings in 16-bit unsigned format, covering the
ec

range of 0mA to 2mA.

The 9-bit ADC value is auto-ranged and mapped to five different areas in the 16-bit
RXn_RSSI register depending on the actual RSSI current value. Therefore the RXn_RSSI
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register utilises all 16 bits of the register. This gives an equivalent LSB value of 2mA / 216
= 0.0305μA/bit.
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Table 4-3: RSSI Current Mapping to RXn_RSSI Register

Lower Range Upper Range RXn_RSSI_1 (10h, 12h, 14h, 16h) RXn_RSSI_0 (11h, 13h, 15h, 17h)

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0000h FF80h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0μA 15.6μA 0 0 0 0 0 0 0 d8 d7 d6 d5 d4 d3 d2 d1 d0

on
15.6μA 62.5μA 0 0 0 0 0 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0
62.5μA 250μA 0 0 0 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0
250μA 1000μA 0 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0
1000μA 2000μA d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0

A
The RXn_RSSI register therefore should be interpreted as follows:

ND
RSSI Current (mA) = RXn_RSSI * (2mA/216) Equation 4-2
The RSSI current monitor resolution depends on the actual RSSI current. For currents
less than 15.6μA, the resolution will be ±30.5nA. For currents between 15.6μA and
62.5μA, the resolution will be ±122nA. For currents between 62.5μA and 250μA, the
resolution will be ±488nA. For currents between 250μA and 1000μA, the resolution will

ht
be ±1.95μA. For currents between 1000μA and 2000μA, the resolution will be ±3.91μA.

4.3.3 Global Control Registers

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RSSI_n_SELECT (34h, 35h)
ue

The two output pins, RSSI_1 and RSSI_2, are used to output the RSSI current from any
two of the different channels. There is also an enable bit for this function. When the
enable bits are set LOW and analog RSSI outputs are disabled, the digital monitoring of
RSSI via the ADC remains functional.
Tr

CONTROL_REGISTER_1 (36h)
Global CONTROL_REGISTER_1 controls:
h-

• POWER_DOWN – this powers-down all channels whatever the state of the

individual channel power-down controls
• SLEEP – this puts all channels into sleep mode whatever the state of the individual
ec

channel sleep controls

• LOS_PIN_POLARITY – default = HIGH for LOS
• LOS_PIN_POWER_DOWN_STATE – default = LOS inactive when part
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powered-down via the power-down bit of this register—this bit does not activate
the LOS detection circuit during power-down, it sets the state of the LOS pin during
power-down
• LOS_CHANNEL_LATCH_ENABLE – Latch LOS flags in register 01h
Se

• CS_SQUELCH – see section 3.6 Chip Select/Reset (CS)

• CS_RESET – see section 3.6 Chip Select/Reset (CS)

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CONTROL_REGISTER_2 (37h)
This control register contains an 8-bit digital word that controls the operating mode of
the IC. See Table 4-2.

ly
RESET (3Bh)

on
See section 3.5 Device Reset.

4.3.4 Per Channel Control Registers

A
RXn_CTL (40h, 50h, 60h, 70h)

ND
This register controls:
• Channel POWER_DOWN
• Channel SLEEP mode (RSSI and LOS are functional only)
• RATESELECT[1:0]
• POLARITY_INVERT
• LOS_DISABLE

ht
lig
RXn_OUTPUT_CTL (41h, 51h, 61h, 71h)
This register configures the output swing per channel.
• OUTPUT AMPLITUDE SWING SELECT
ue

Table 4-4: Output Voltage Swing Register Settings

RXn_OUTPUT_CTL
Tr

Output Amplitude Swing

Register Setting
(41h, 51h, 61h and 71h) (mV)

Default value in register 600 0xC

200 0x4
h-

250 0x5

User settings 300 0x6

400 0x8
ec

1000 0x14
mt

RXn_PREEMPH_CTL (42h, 52h, 62h, 72h)

This register configures the output pre-emphasis per channel. Each channel in the
GN1090 has a programmable receive output eye adjustment which uses pre-emphasis
Se

to compensate for high frequency losses introduced by any connectors in the Rx

electrical path and PCB traces. The pre-emphasis can be set by I2C.

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• MAGNITUDE
• DELAY

ly
Table 4-5: Pre-emphasis Delay Register Settings

RXn_PREEMPH_CTL

on
Delay (ps) Register Setting
(42h, 52h, 62h and 72h)

Default value in register 0 0x0

12 0x2

A
24 0x4

User settings 36 0x6

ND
48 0x8

60 0xA

The delay is the length of the pre-emphasis pulse. Pre-emphasis is achieved by delaying
a data signal relative to the main signal path. Subtracting the two signals creates the

ht
pre-emphasis waveform. The amount of delay between the two paths determines the
length of the pre-emphasis pulse.
For different bit rates, the delay parameter may need to be adjusted.
lig
Table 4-6: Pre-emphasis Magnitude Register Settings

RXn_PREEMPH_CTL
ue

Magnitude (%) Register Setting

(42h, 52h, 62h and 72h)

Default value in register 0 0x0

Tr

5 0x1

10 0x2

User settings 15 0x3

h-

20 0x4

25 0x5

The pre-emphasis 'adds' to the amplitude. For instance, if the Rx swing set to 600mV and
ec

pre-emphasis set to 20%, then the peak amplitude is 600+600*20% = 720mV.

mt
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Final Data Sheet Rev.5
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 50mVpp

No Pre-emphasis Low Pre-emphasis

ly
600mVpp 600mVpp

on
150mVpp
100mVpp

A
Mid Pre-emphasis High Pre-emphasis

600mVpp 600mVpp

ND
Figure 4-1: Pre-emphasis and Output Swing

RXn_LOS_CTL (43h, 53h, 63h, 73h)

This register controls the LOS and squelch functions:
ht
lig
• SQUELCH_DISABLE
• HYSTERESIS Level (see below)

000 0.5dB
ue

001 1.0dB

010 1.5dB

011 2.0dB
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100 2.5dB

101 3.0dB
h-

• FORCE_SQUELCH

RXn_LOS_THRESH (44h, 54h, 64h, 74h)

ec

These registers contain the parameters required to set the assert level of the LOS
threshold.
• RXn_LOS_THRESH
mt
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5. Digital Control Block

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Clock and Scan
SCL Reset Control

on
I2C
SDA

A
OTP r

A
Controls b To
OTP Controller i Core Registers Channel
OTP t Registers

ND
Data e
r

ADC
DDMI Controller
Controls

Figure 5-1: Digital Control Block Diagram

ht
lig
ue
Tr
h-
ec
mt
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6. Application Information

ly
A typical application of the GN1090 is shown in Figure 6-1. The GN1090 and the GN1190
4-channel VCSEL Driver are assembled into a 4-channel optical transceiver module
(compatible with QSFP+).

on
Quad Pin
Diode Array
RX1p/n

A
RX2p/n RX1
Quad
Rx Data SERDES
Rx RX3p/n
RX2

ND
GN1090
RX4p/n Quad
Receiver
RX3
Host Microcontroller and Protocol Processor

SCL
ModPrsL SDA RX4
QSFP+ Module Connector

SCL CS

MPO Optical Adaptor

RX_LOS

ht
SDA
ModSelL Micro-
controller
ResetL TX_FAULT
lig
IntL TX_DISABLE
TX_LOS
LPMode TX4
CS
SCL
SDA
TX3
ue

GN1190
TX4p/n Quad
VCSEL
TX2
TX3p/n Driver
Quad
Tr

Tx Data SERDES
Tx TX2p/n TX1

TX1p/n
Quad VCSEL
Array
h-

QSFP+ Module

Figure 6-1: Typical Application (showing a GN1090 and a GN1190 assembled in a QSFP+ module)
ec
mt
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Final Data Sheet Rev.5
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 ly
on
A
DOCUMENT IDENTIFICATION CAUTION

ND
FINAL DATA SHEET ELECTROSTATIC SENSITIVE DEVICES
The product is in production. Semtech reserves the right to make changes to the DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A
product at any time without notice to improve reliability, function or design, in STATIC-FREE WORKSTATION
order to provide the best product possible.

ht
© Semtech 2015
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
lig
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes
no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper
installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to
parameters beyond the specified maximum ratings or operation outside the specified range.
ue

SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN
LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer
purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and
Tr

its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees
which could arise.
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
h-
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Contact Information

Semtech Corporation
Se

200 Flynn Road, Camarillo, CA 93012

Phone: (805) 498-2111, Fax: (805) 498-3804
www.semtech.com

GN1090 38 of 38
Final Data Sheet Rev.5 38
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