Control Engineering Practice 109 (2021) 104752

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Control Engineering Practice

journal homepage: www.elsevier.com/locate/conengprac

Implementation and validation of quadral-duty digital PWM to develop a

cost-optimized ASIC for BLDC motor drive
Pratikanta Mishra a ,∗, Atanu Banerjee a , Mousam Ghosh b , Sushanta Gogoi c ,
Pramod Kumar Meher d
a Department of Electrical Engineering, National Institute of Technology Meghalaya, Shillong 793003, India
b Department of Electrical Engineering, Ramkrishna Mahato Government Engineering College Purulia (Formerly Purulia Government Engineering
College), Purulia 723103, India
c
Department of Electronics and Communication Engineering, National Institute of Technology Meghalaya, Shillong 793003, India
d
Sandhaan Labs Private Limited, Bhubaneswar, 751016, India

ARTICLE INFO ABSTRACT

Keywords: In this paper, a quadral-duty digital pulse width modulation (QDPWM) technique-based low-cost hardware
Application-specific integrated circuit (ASIC) architecture for brushless DC (BLDC) motor drive is proposed. The proposed architecture is developed by
Brushless DC (BLDC) motor incorporating an efficient speed calculation and commutation circuitry to achieve the compactness of the total
Digital pulse-width modulation (DPWM)
architecture. The speed calculation circuit is designed to perform edge detection of the rotor position signal,
Field-programmable gate array (FPGA)
with external noise and glitch resistance. The proposed architecture is implemented in the field-programmable
gate array (FPGA) and application-specific integrated circuit (ASIC) platform using TSMC 180 nm technology
library. The FPGA implementation is compared with existing architectures to validate the resource utilization
of the proposed architecture. The ASIC implementation illustrates that the proposed architecture operating
at 50 MHz, reduces the gate count and power dissipation to approximately half and one-third, respectively,
compared to a standard PI controller based-PWM control architecture. Experimental validation of the FPGA-
based architecture is also performed using a laboratory prototype of the BLDC motor drive hardware setup.
The performance of the drive is examined for various speed commands and loading conditions. Extensive
experimental analysis has been carried out to validate the performance of the proposed architecture-based
drive under dynamic load and speed command variation. The ability of the proposed circuit to tolerate the
noise in Hall position sensor signals is testified by adding intentional glitches into the signal.

1. Introduction Moreover, the presence of dedicated memories and hard multipliers in

ASIC significantly reduces the chip area and dynamic power consump-
Permanent magnet (PM) motors are substantially utilized in various tion compared to the corresponding FPGA implementation (Kuon &
applications due to their higher energy density (Ghosh, Ghosh, Panda, Rose, 2007). The ASICs are preferably developed in digital technology
& Saha, 2018). Among them, PM brushless DC (BLDC) motors are often to utilize the advantages of digital circuits (Dancy, Amirtharajah, &
preferred for low power domestic and industrial applications due to Chandrakasan, 2000). Classical scalar (Kim, Nakazawa, Kim, Park, &
their improved dynamic response, higher efficiency, reduced excitation Yu, 2010) and vector (de Castro, Pereira, de Almeida, & de Oliveira,
losses, low noise production, and maintenance cost (Kumar & Singh, 2018) control, including modern intuitive control techniques such as
2016). However, a converter and controller arrangement is essential fuzzy logic with the genetic algorithm, backpropagation control, par-
for the BLDC motor. To properly accord BLDC motor within the cost ticle swarm optimization, and extended Kalman filter tuned fuzzy
constraints of domestic and low power applications, it is essential that logic (Ansari, Alam, & Jafri, 2011; Lee et al., 2018; Rubaai & Young,
the converter and controller should be compact and simple (Cheng 2016; Zhang, Wang, Liu, & Yuan, 2016) can be effortlessly redesigned
& Tzou, 2003). The control techniques may be implanted on field- digitally (Gabbi et al., 2019) to drive BLDC motor. The design aspect of
programmable gate arrays (FPGA) or digital microcontrollers until the several control ICs in FPGA platform is discussed in the literature (Cho,
design intends to serve a limited number of users. Large scale fabrica- Le, & Jeon, 2009; Curkovic, Jezernik, & Horvat, 2013; Diao et al.,
tion of the controllers is preferred on application-specific integrated cir- 2018; Horvat, Jezernik, & Curkovic, 2014; Kung, Than, & Chuang,
cuits (ASIC) for cost optimization purposes (Akkermans & Stan, 2001). 2018; Lakka, Koutroulis, & Dollas, 2014; Lotfy, Kaveh, Mosavi, &

∗ Corresponding author.
E-mail address: [email protected] (P. Mishra).

https://doi.org/10.1016/j.conengprac.2021.104752
Received 12 September 2020; Received in revised form 30 December 2020; Accepted 26 January 2021
Available online 13 February 2021
0967-0661/© 2021 Elsevier Ltd. All rights reserved.
P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

Rahmati, 2020; Maldonado, Castillo, & Melin, 2013; Prabu, Poongodi, of the controller. However, DDPWM control technique performs well
& Premkumar, 2016; Reddy & Murali, 2016; Shao & Sun, 2005; Yu only for a narrow speed range, and for entire speed range operation,
et al., 2020). DDPWM control is equivalent to the BB control technique. Hence, a
The complete motion control architecture of the BLDC motor with BB control architecture that satisfies cost-optimization, wider speed
the basic PID speed controller and PI current controller is shown as range, and control precision aspects of BLDC motor is essential for
an economical technique (Shao & Sun, 2005). Whereas an advanced better commercialization. A quadral-duty digital pulse width modula-
PI speed controller and event-driven current controller-based IC is tion (QDPWM) technique for BLDC motor control inherits the simple
efficient in inverter switching frequency reduction (Horvat et al., 2014). architecture of the BB controller and provides an improved speed
A precise rotor angle calculation with low-resolution Hall sensor signals control range additionally (Mishra, Banerjee, & Ghosh, 2020). The
for the field-oriented control (FOC) of BLDC motor is mentioned in QDPWM controller is also effective in drive speed ripple and motor
the literature (Reddy & Murali, 2016). In contrast, a simplified FOC is vibration reduction. The QDPWM controller is developed to design only
also proposed for the PM synchronous motor control, which utilizes the in digital technology with reduced computational complexity. Hence,
linear outputs of Hall sensors to determine the coefficients required for QDPWM control technique is one of the most effective algorithms to
the coordinate transform through linear combination methodology (Yu develop a low-cost IC. The commercial aspects of the QDPWM control
et al., 2020). Similarly, a predictive switching control scheme for VSI technique based IC for BLDC motor drive can be better analyzed by
control (Curkovic et al., 2013) and simple sinusoidal PWM (Lakka validating area and the power dissipation of the ASIC implemented
et al., 2014) technique-based ICs can also be found in the literature, architecture of the same.
which consumes a small area and low power with high accuracy. Besides the control circuit, the BLDC motor control IC should consist
Intuitive controller-based ICs, such as fuzzy supervised online coac- of the commutation unit, speed calculation unit, ADCs, and other units
tive neuro-fuzzy interference system (CANFIS) controller (Prabu et al., based on the drive type. In a digital IC, the commutation and the
2016), GA based parameter regulated fuzzy controller (Lotfy et al., speed control units consume a significant area due to the arithmetic
2020), and average interval approximation-based type-2 fuzzy logic operations required in the process (Shao & Sun, 2005). The speed
controller (Maldonado et al., 2013) is proposed for precise motor calculation is generally done by utilizing all three Hall sensors present
control. Hybrid PWM control based application-oriented IC that reduces for position estimation to achieve a better precision (Baszynski & Pirog,
losses and low-frequency harmonics for the rail traction induction 2014). However, in the steady-state operation of the motor, the rotor
motor exists in literature (Diao et al., 2018). Also, multi-axis control ICs position is linearly varying in nature, and its first-order derivative is
based on radial basis function neural network tuned PI controller (Kung almost constant. Hence, the usage of the three Hall sensors for speed
et al., 2018) and a simple PI controller (Cho et al., 2009) are proposed calculation adds to the complexity and cost of the IC, which must be
in the literature. avoided for low-cost applications. The Hall sensors signals used for
The aforementioned designs are intended for precise control of the the speed calculations may sometimes have noise due to mechanical
motor, where low-cost applications of the controller are not explicitly stress, aging, and temperature variations (Pastre, Kayal, & Blanchard,
considered. Hence, these ICs cannot be found among the suitable 2007). Glitches in the Hall sensor signals may especially be observed
controllers in terms of commercial applications. The complexity of in the interior PMBLDC motors due to the uneven distribution of the
any control algorithm-based hardware is proportional to the primary magnetic flux (Seol, Lim, Kang, Park, & Lee, 2017). Many sensor-
arithmetic complexity of the algorithm (Meher & Park, 2014; Ray, less control techniques for BLDC motor have been proposed in the
George, & Meher, 2020). Thus, a control technique that requires fewer literature to avoid these limitations of mechanical sensors (Niapour,
arithmetic operations will be appropriate for cost optimization. Pure Tabarraie, & Feyzi, 2014). However, the sensorless control increases
digital control techniques meant only for digital implementation can the drive complexity and cost due to the online calculations of the
potentially be designed to involve lesser arithmetic units instead of the motor parameters involved with it (Yang & Ting, 2014). This makes
digital implementation of non-digital controllers (Rodriguez & Emadi, Hall sensor-based speed calculation more preferable in low-cost BLDC
2007). Bang–bang (BB) technique performs selective decisions for con- motor drive. Hence, a commercial IC for BLDC motor drive should
trol operation and is capable of dynamic power and on-chip area include a glitch-tolerant Hall sensor-based speed calculation unit.
minimization (Darwish, Mohsen, Saad, & Weldon, 2016). If the simple In this paper, an efficient hardware architecture of a QDPWM
form of BB control technique is utilized for a motor drive, which is based controller for BLDC motor drive is proposed to address the
equivalent to on–off control, then the drive suffers from large torque, issues mentioned above. The overall architecture includes the speed
flux, current, and speed ripples due to the limit cycle problem (Lascu, calculation and commutation circuits for the BLDC motor drive, where
Boldea, & Blaabjerg, 2004). This problem is avoided by using hybrid the speed calculation unit is developed to tolerate external noises
BB controllers such as a vector controller integrated with the BB and glitches in the Hall sensor signals. The proposed architecture is
controller employed to drive a grid-side converter of a doubly-fed compared with the circuits existing in the literature to validate its cost-
induction generator (Liu, Xiahou, Wang, & Wu, 2018). Similarly, a effectiveness. A PI controller based PWM technique is further presented
fuzzy controller analogous to BB controller (Rubaai, Jerry, & Smith, and compared for better contrast. The area and power consumption are
2011) and a combination of BB and Fuzzy-BB controllers (Rubaai & compared with the PI–PWM controller to validate the effectiveness of
Jerry, 2014) is implemented for precise BLDC motor control. However, the proposed design. The dynamic response of the FPGA implemented
these control precisions are achieved by compromising the simplicity architecture-based BLDC motor drive is also presented in the paper.
of the BB control technique, which limits the commercial applicability In this paper, the QDPWM technique is introduced controller in
of the controllers. Section 2.A. The proposed circuit architecture with the state diagram is
A control technique that maintains the BB control technique’s sim- elaborated in Section 2.B. Section 3 details the real-time FPGA and ASIC
plicity is the dual-duty digital pulse width modulation (DDPWM) tech- implementation of the proposed architecture, along with the hardware
nique for BLDC motor control (Milivojevic et al., 2012; Mishra, Baner- validation of the same for BLDC motor drive. Finally, the conclusions
jee, & Ghosh, 2018; Sathyan, Milivojevic, Lee, Krishnamurthy, & Emadi, are drawn in Section 4.
2009) to address the aforementioned issue. A voltage source inverter
(VSI) fed BLDC motor is supplied with two discrete duty ratios based on 2. Quadral-duty digital PWM technique and architecture overview
the range of drive speed variation (Sathyan et al., 2009). A smoother
performance of DDPWM controlled BLDC motor can be achieved if a BLDC motor is advantageous in terms of its high torque to weight
buck converter cascaded VSI is used (Mishra et al., 2018). The DDPWM ratio, better transient response, and high efficiency. In the absence of
control technique is suitable in terms of the cost-optimized architecture a mechanical commutation, BLDC motor is commutated by electronic

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

Fig. 1. Steady-state 𝜔𝑚 response of BLDC motor.

Fig. 2. Schematic of QDPWM controller-based BLDC motor drive.

commutation. Generally, the power to stator windings is fed with a

VSI, which is switched on the basis of the rotor position. The motor
speed is controlled by the integral buck property of the VSI, where
different speed control strategies are implemented based on the specific
application. In this paper, QDPWM technique is used for speed control
and discussed in detail.

2.1. Quadral-duty digital PWM control

In the QDPWM control technique, there are four discrete duty ratios
based on which the VSI feeding the BLDC motor is switched. If the
motor is operating in a torque and speed region corresponding to
two inner duty ratios, then the VSI is switched between high duty
ratio (𝑑high ) and low duty ratio (𝑑low ) at a predetermined sampling
interval (𝑡𝑠 ). The 𝑡𝑠 is obtained by considering the maximum deviation
of speed (𝜔𝑚 ) from the reference speed (𝜔∗𝑚 ) at steady-state operation.
Fig. 1 shows the steady-state 𝜔𝑚 deviation of a BLDC motor from
𝜔∗𝑚 , where 𝜔𝑚𝐻 is the highest speed deviation above 𝜔∗𝑚 and 𝜔𝑚𝐿 is
the highest deviation below 𝜔∗𝑚 . The values of 𝜔𝑚𝐻 and 𝜔𝑚𝐿 can be
expressed (Sathyan et al., 2009) as
( )
𝑇 − 𝑇𝑙 𝑇𝑙 − 𝑇𝑒𝐻 𝐵
𝜔𝑚𝐻 = 𝑒𝐻 + + 𝜔∗𝑚 𝑒− 𝐽 𝑡 (1)
𝐵 𝐵
( )
𝑇 − 𝑇𝑙 𝑇𝑙 − 𝑇𝑒𝐿 𝐵
𝜔𝑚𝐿 = 𝑒𝐿 + + 𝜔∗𝑚 𝑒− 𝐽 𝑡 (2)
𝐵 𝐵
where 𝑇𝑒𝐻 and 𝑇𝑒𝐿 is the electromagnetic torque at the speed 𝜔𝑚𝐻
and 𝜔𝑚𝐿 respectively, 𝑇𝑙 is the load torque applied, J is the moment
of inertia, and B is viscous damping. Therefore, total error in speed is
Fig. 3. Flowchart of QDPWM controller for BLDC motor.
𝛥𝜔𝑚 = 𝜔𝑚𝐻 − 𝜔𝑚𝐿 (3)
𝛥𝑇𝑒 ( 𝐵 )
𝛥𝜔𝑚 = 1 − 𝑒 − 𝐽 𝑡𝑠 (4)
𝐵 [ ] first 𝑡𝑠 and full duty for onward 𝑡𝑠 if 𝜔𝑚 is lesser than 𝜔∗𝑚 . Similarly,
𝛥𝜔 if the vice-versa is true, then the controller generates 𝑑low for first 𝑡𝑠
𝑡𝑠 = −𝜏mech ln 1 − max 𝑚 (5)
𝜔𝑚 (no-load) and zero duty for onward 𝑡𝑠 . Hence, it is evident from the proposed
where 𝜏mech is the mechanical time constant, that is, the ratio of motor controller that the extreme duty ratios will only be supplied when the
inertia to the viscous damping, which can also be referred to as the time load or/and reference speed shift beyond the defined range. Improved
at which the unloaded rotor achieves 63.2% of its rated speed when steady-state performance of the drive can be achieved if the motor is
the rated supply is given to the motor. Whereas, 𝜔max 𝑟 is the maximum supplied with in-between duty ratios (𝑑low and 𝑑high ). Therefore, it is
speed of the BLDC motor considered at no-load. crucial to determine the values of 𝑑low and 𝑑high by considering the
As mentioned in (5), the value of 𝑡𝑠 is calculated at the steady-state steady-state operation of the motor by the process as follows:
for fixed system parameter and no-load condition. However, the value
𝑡𝑠 should be increased, or the duty band should be widened with the 𝑉𝑛𝑠 = 𝑅𝑛𝑠 𝐼𝑛𝑠 + 𝐾𝐸 𝜔𝑠𝑠
𝑚 (6)
increase in load. Similarly, either the value of 𝑡𝑠 should be reduced, or where 𝐼𝑛𝑠 is the stator current, 𝑅𝑛𝑠 is the resistance, and 𝑉𝑛𝑠 is the
the duty band should be made narrower if the load decreases. Hence, voltage across 𝑛𝑡ℎ stator phase, 𝐾𝐸 is the back-EMF constant, and 𝜔𝑠𝑠
𝑚
two extreme duty ratios are included with the present duty ratios at is the steady-state speed of the motor. During the steady-state, the
constant 𝑡𝑠 . The values of the extreme duties are considered as zero armature current is defined as
and full to maintain the controller simplicity, which also improves the
1 ( 𝑠𝑠 )
dynamic response of the motor and widens the speed control to its 𝐼𝑛𝑠 = 𝜔𝑚 𝐵 + 𝑇𝑙 (7)
𝐾𝑇
highest possible range. Fig. 2 illustrates the integrated schematic of the
BLDC motor fed with a VSI and controlled by QDPWM technique. Fig. 3 where 𝐾𝑇 is the torque constant of the motor. Therefore, the duty ratio
shows the flowchart of the QDPWM algorithm executed by the digital from (6) and (7) can be derived as
controller during the rising edge of each clock pulse for BLDC motor 𝑅𝑛𝑠 𝐾𝐸 𝜔𝑠𝑠
𝑚
control. In the QDPWM technique, the controller generates 𝑑high for 𝑑= (𝜔𝑠𝑠
𝑚 𝐵 + 𝑇𝑙 ) + (8)
𝑉DC 𝐾𝑇 𝑉DC

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

Fig. 4. Top-level hardware architecture of the proposed IC.

Fig. 5. State machine diagram of the proposed architecture.

A current limiter is utilized for the QDPWM controlled BLDC motor

drive because the practical feasibility of employing a current con-
troller with continuous variation in duty ratios is highly contradict-
ing (Sathyan et al., 2009). The current limit is determined by, Fig. 6. Experimental setup developed in the laboratory.

𝐼LIM = 𝑘𝜔err
𝑚 (9)

where 𝐼LIM is the current limit, 𝜔err

𝑚 is the speed error, and k is the
proportionality constant that is given as State 1: The elementary state S1 provides information regarding the
up position of the rotor in the form of 𝐻𝑎 , 𝐻𝑏, and 𝐻𝑐 . Moreover, as long
2𝐼LIM
𝑘= (10) as the rotor position is constant, the state machine stays in state S1.
𝛥𝜔𝑚
up State 2: In the next state S2, the speed calculation of the BLDC motor
The upper saturation of 𝐼LIM (𝐼LIM ) is considered as 1.5 times the
is performed. In order to retain the simplicity of the control IC, the
rated current of the motor as the windings can tolerate that amount
computation of 𝜔𝑚 is performed utilizing only one Hall sensor output,
of current for a short duration of time. Whereas, the lower saturation
i.e., 𝐻a . The motor speed is calculated by considering the clock cycles
current limit is considered as 15% of the ratio of rated torque (𝑇rated )
between the Hall sensor edges. A counter (C) is initialized at the rising
to 𝐾𝑇 edge of the Hall sensor signal that performs a counting at every clock
cycle till the next rising edge. The same operation is followed for the
2.2. Proposed architecture falling edge of the Hall sensor signal. The value of count obtained at
each rising or falling edge is then utilized for the motor speed (𝜔𝑚 )
The top-level view of the proposed hardware architecture is shown calculation based on the following formula,
in Fig. 4. Fig. 5 shows the operation performed by the proposed archi- 2𝜋𝑓clk
𝜔𝑚 = (11)
tecture in terms of the state machine diagram. The proposed design has 𝑃𝐶
four states that are (i) position information, (ii) speed calculation, (iii) where 𝑓clk is the clock frequency and P is the number of pole pairs. In
QDPWM based control, and (iv) commutation process. the proposed architecture, the minimum measurable speed has been

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

Fig. 7. Measured 𝜔𝑚 response of BLDC motor for various 𝜔∗𝑚 at loading condition of (a) 0.1 Nm, and (b) 0.3 Nm.

limited to 100 RPM to 10.47 rad/s to avoid the counter register Table 1
Motor parameters.
overflow. Hence, the speed is updated two times the number of poles
in a mechanical revolution or once in an electrical revolution of the Parameters Symbol Value

rotor. Any glitch or external noise in the signal that lasts for a few Rated terminal voltage 𝑉𝑠 24 V
Rated current 𝐼𝑠 8.5 A
clock pulses can lead to spurious detection in rising or falling edges.
Rated power 𝑃𝑠 200 W
Hence, the speed architecture is designed to detect the edges only after Rated speed 𝑁𝑠 3000 RPM
considering the signal for ‘n’ clock pulses. The change in the direction of Rated torque 𝑇rated 0.65 Nm
the motor revolution is updated when the circuit scrutinizes the change Per phase resistance 𝑅𝑛𝑠 27.739 m𝛺
in Hall sensor signal combination for ‘n’ clock pulses. Finally, it can Per phase inductance 𝐿𝑛𝑠 40 μH
Back-emf constant 𝐾𝐸 9.133 V/krpm
be concluded that state S2 retains its current status until a change in
Rotor inertia J 0.0031095 Nms2
the time duration between two consecutive rising and falling edges of
signal 𝐻a is observed.
State 3: In the state S3, the QDPWM controller is fed with the 𝜔𝑚
received from state S2 along with 𝜔∗𝑚 and 𝐼DC . A 16-bit comparator is
used in the controller that compares the value of 𝜔𝑚 with the value of
𝜔∗𝑚 . Based on the comparator decision, duty ratio (d) is fixed, which
is further used to generate PWM signals for the next state S4. The
output value of the comparator is stored in a register to retain the
previous state. A 4:1 duty generator mux based logic is implemented
in the design to select the proper value of d by considering the current
and previous state of comparator. As depicted in Fig. 3, the decision
to forward the selected value of d or to skip the duty is taken by a
2:1 current limiter mux. The select line for the mux is the output of an
8-bit comparator that compares the values of 𝐼LIM and 𝐼DC . The 𝐼LIM Fig. 8. Measured 𝜔𝑚 response of BLDC motor for 𝜔∗𝑚 = 1500 RPM and sudden load
is generated by considering the speed error, as mentioned in (9). The application.
output of the current limiter mux is lastly utilized for 17-bit counter-
based PWM pulse generation using a 17-bit comparator. Hence, the
status of S3 remains preserved if 𝜔𝑚 , 𝜔∗𝑚 , and 𝐼DC are unchanged. (2020). The power circuit of the VSI driven BLDC motor is designed
with IRFZ44 MOSFET (60 V, 50 A) with MCT2E based gate driver. A
State 4: Finally, the commutation in state S4 is performed by the IC
variable DC source (fixed at 24 V and 5.13 A current limit) is chosen
after inspecting the Hall sensor signals at an individual clock pulse. The
as input to the VSI. The proposed control architecture is designed in
signal values are used to detect the back-EMF of the phases, based on
the Altera Cyclone II FPGA. The DC-link current is measured using an
which the required phases are commutated. The value of PWM derived
ACS712 based current sensor module and is fed to the FPGA board
from state S3 is used for the output of state S4, which indicates a stable
through an Arduino MEGA 2560 development board as an 8-bit ADC.
state of S4 until the PWM and Hall sensor output alters.
The Hall position sensor signals are directly supplied to the FPGA from
the motor. The speed command is set and varied with a control panel
3. Experimental validation
developed in MATLAB graphical user interface (GUI). The real-time
low-frequency speed visualization and acquisition have also been per-
The effectiveness of the QDPWM technique for a BLDC motor drive formed using the control panel, and the high-frequency data acquisition
is validated by FPGA and ASIC implementation of the proposed design is made using external static RAM (IS61LV25616).
in Verilog hardware description language (HDL). The performance of The total control architecture with the speed calculation and the
the drive has also been analyzed with the help of experimentally commutation is designed in the FPGA platform. Based on the derived
obtained responses. expressions for the QDPWM controller, the value of 𝑡𝑠 has been calcu-
lated to be 2.314 ms. The electric time constant of the motor used in the
3.1. Performance analysis on FPGA-based prototype paper is approximately 1.44 ms, which suggest a switching frequency
of a few kHz. However, the adoption of switching frequency obtained
The experimental setup comprises a permanent magnet BLDC mo- from the electric time constant will not show any dither in the armature
tor, a VSI with the driver circuit, and the FPGA controller. The devel- current and would not allow a discontinuity in the current (Ghosh,
oped experimental prototype is shown in Fig. 6. The BLDC motor to Ghosh, Kumar Saha, & Kumar Panda, 2017; Scott, McLeish, & Round,
drive by the prototype driver is an 8-pole star-connected machine with 2009). Hence, to enable proper speed control, the authors selected a
three Hall effect based position sensors. The motor is associated with a switching frequency of 433 Hz that is sampled once in every interval.
belt–pulley mechanical loading arrangement. The details of the motor The values of 𝑑high and 𝑑low are considered to be 0.1 and 0.9, respec-
parameters are shown in Table 1, which are similar to Mishra et al. tively, to achieve a good range of speed at variable loading conditions.

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

is not feasible due to the involvement of different FPGA types in

various applications. However, due to the compactness of the pro-
posed architecture, a considerable gap in device utilization is visible
between the proposed and state-of-art architectures. Most architectures
are designed for precise control and are not highly effective in terms
of FPGA resource consumption minimization. Concluding, the choice of
the controller depends on the priority of the application, i.e., a designer
can choose any of the advanced controllers if the control precision
is essential for the application, or the proposed architecture can be
implemented for controller cost reduction.
The dynamic performance of the QDPWM controller-based BLDC
Fig. 9. Measured 𝜔𝑚 response of BLDC motor for a load of 0.2 Nm and varying speed motor drive is analyzed at loading conditions of 0.1 Nm and 0.3 Nm,
references.
which are shown in Fig. 7(a) and Fig. 7(b), respectively. The 𝜔𝑚 value
for the load of 0.1 Nm approaches the speed command of 1000, 1400,
and 1800 RPM with a maximum error of 5.5, 3.9, and 3%. However, the
The value of n (number of clock cycles between edge detection and maximum error value in the case of 0.3 Nm loading reduces to 4.5% for
speed calculation) is considered to be 10. Table 2 shows the post-
1000 RPM and 2.9% for 1400 RPM value of 𝜔∗𝑚 . The settling time for
synthesis resource utilization of total control architecture. As the PI
𝜔𝑚 linearly increases with an increase in 𝜔∗𝑚 , which can be verified from
controller based PWM technique is a standard control algorithm for
the settling times for 1000, 1400, and 1800 RPM value of 𝜔∗𝑚 at 0.1 Nm
BLDC motor drive that is being used for decades (Baszynski & Pirog,
load to be 0.7 s, 1.18 s, and 1.7 s, respectively. With the increment in
2014; Cao, Shi, Niu, Li, & Xia, 2018; Shanmugasundram, Zakariah, &
load to 0.3 Nm, the settling time increases to 1.3 s, 2.86 s, and 3.8 s for
Yadaiah, 2014; Trivedi & Keshri, 2020), a PI–PWM control architecture
𝜔∗𝑚 1000, 1400, and 1800 RPM. (Note that the settling time will further
is also developed for comparison. The PI controller parameters are
decrease if the value of the current limiter proportional constant, k,
fixed using proper tuning techniques and are designed to work at the
increases.)
same constant frequency as that of the QDPWM control hardware.
The post-synthesis resource utilization of the PI–PWM-based overall The tolerance of the QDPWM controller based motor drive is exam-
hardware is also presented in Table 2 for comparison. The QDPWM ined by performing some dynamic variations in load and commanded
controller, along with the speed calculation and commutation architec- speed. The 𝜔𝑚 response for a sudden load application of 0.1 Nm and
ture, utilizes 8% of FPGA resources or logic elements (LE). Whereas the 0.3 Nm when the motor is driven with 𝜔∗𝑚 value of 1500 RPM is shown
conventional PI–PWM controller with the same speed calculation and in Fig. 8. The motor is operating at no load before and after the load
commutation architecture consumes 12% of FPGA resources. However, application. The sudden imposing of load drifted the average motor
if only the controllers are analyzed without the speed calculation and speed from 1513.15 RPM to 1508.82 RPM in case of 0.1 Nm load,
commutation architecture, then the resource consumption of the PI– and 1503.20 RPM in case of 0.3 Nm load. However, the motor speed
PWM controller is approximately 3.21 times higher than the QDPWM still follows the commanded speed. Fig. 9 shows 𝜔𝑚 response of the
controller. drive for continuous variation in the 𝜔∗𝑚 value at a load of 0.2 Nm.
The proposed architecture is also implemented in a Xilinx Virtex-7 The continuous variation in 𝜔∗𝑚 depicts the performance of QDPWM
VC707 FPGA and compared to the state-of-art architectures as shown based BLDC drive in terms of the speed tracking ability. The 𝜔𝑚 value
in Table 3. The comparison is a report of device utilization of the immediately matches with 𝜔∗𝑚 for both increasing and decreasing 𝜔∗𝑚 .
pre-existing architectures found in the literature in the area of motor The operation of the FPGA implemented controller with various
drive control. A direct comparison among the state-of-art controller stimuli generated by the drive setup proves the controller ruggedness.

Fig. 10. PWM pulses generated for 𝜔∗𝑚 = 1000 RPM at (a) load = 0.1 Nm, (b) load = 0.3 and 𝜔∗𝑚 = 1800 RPM at (c) load = 0.1 Nm, (d) load = 0.3.

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

Table 2
FPGA resource utilization of QDPWM based controller.
Module Total LE (33216) Combinational LE with no registers Combinational LE with registers
Total QDPWM controllera 2,571 (8%) 2462 109
Total PI–PWM controllera 3,904 (12%) 3688 216
QDPWM controller 561 (2%) 537 9
PI–PWM controller 1,803 (5%) 1684 119
a
Total controller includes the speed calculation and commutation units.

Table 3
Comparison of the proposed architecture with existing designs.
Literature FPGA device Modules (sampling frequency) Device utilization
Proposed Xilinx Virtex-7 VC707 QDPWM controller with current limiter, speed estimation, Total — 322 LUTs and 86 flip-flops.
position-based commutation. (50 MHz)
Shao and Sun Xilinx XC3S400 Braking, velocity estimation, UART, host communication, and Total — 2612 slices
(2005) ADC. (36 MHz) Speed calculation & PWM — 1772 slices
Horvat et al. Xilinx XC3S1200E ADC, DAC, serial communication, speed/position Total — 3553 (40%) slices.
(2014) measurement, hysteresis controller with the state transition
table, and PLL. (NA)
Reddy and Microsemi SmartFusion® 2 So NA. (100 MHz) Angle estimation — 330 sequential and 670
Murali combinational elements.
(2016)
Yu et al. Xilinx Zynq-7000 XC7Z020 Compensation IP core, vector trans IP core, current/voltage Total — 1124 LUTs.
(2020) PI controller, SVPWM. (50 MHz)
Curkovic Xilinx Spartan 3E ADC, DAC, RS23, speed/position measurement, current Total — 35% LUTs
et al. (2013) controller with state transition table, and PLL. (400 kHz)
Lakka et al. Xilinx XC5VLX110T Clock, modulation index, sine-carrier, adjustable amplitude Total — 3450 (4%) slice registers and 2893 (4%)
(2014) sine, and comparison. (64 MHz) slice LUTs.
Prabu et al. Xilinx XC3S1600E Main controller, position command generator, switching logic Total — 16906 (57.3%) LUTs.
(2016) module, position detection module, and ADC. (NA)
Lotfy et al. Xilinx Fuzzification with (160 MHz) and without (157 MHz) Total — 11805/11566 slice registers and
(2020) pipeline. 8201/9006 LUTs with/without pipeline.
Rule and defuzzification with (184 MHz) and without (110
MHz) pipeline.
Maldonado Xilinx XC3S700A Fuzzification, inference, and defuzzification. (50 MHz) Total — 283 slices and 5234 LUTs.
et al. (2013)
Diao et al. Altera Cyclone EP1C12Q240 PWM generation, along with the speed calculation, PWM — 8896 logic elements
(2018) communication, and protection modules. (30 MHz) Remaining — 3158 logic elements.
Kung et al. Altera Stratix II EP2S60 RBF NN tuned PID controller, embedded processor IP, and RBF NN tuned PID — 8086 ALUTs.
(2018) application IP. (50 MHz) Total — 58.3% LUTs.
Cho et al. Xilinx XC2V6000-FF1152 PID controller, interpolation and kinematics calculator, and Total — 44364 (65%) LUTs.
(2009) pulse generator with computational and interfacing modules.
(36 MHz)

Fig. 10 shows the PWM pulses generated by the controller and Fig. 11 cycle when the edge of the Hall sensor signal is detected. However,
shows the variation in the d with respect to 𝐼DC and 𝜔𝑚 (sensed by the due to the intentional delay of 9 clock cycles, it can be defined that
controller) at the rising edge of each sampling. Figs. 10(a) and 10(b) the speed calculation is not possible in the proposed architecture if
show the PWM pulses and Figs. 11(a) and 11(b) show the d variation the ON or OFF state of the Hall sensor signal lasts for less than
for an 𝜔∗𝑚 value of 1000 RPM at 0.1 Nm and 0.3 Nm loads, respectively. 180 ns. So the maximum possible speed that can be calculated is
Similarly, 10(c) and 10(d) and Figs. 11(c) and 11(d) shows PWM pulses 41.666666×106 RPM or 4.363323×106 rads−1 . Hence, the range of
and the d variation for an 𝜔∗𝑚 of 1800 RPM at 0.1 Nm and 0.3 Nm load, speed calculation in the proposed architecture has been limited from
respectively. In all the cases, the variations of d follow the QDPWM 100 RPM to 41.666666×106 RPM, which is very suitable for most
algorithm, with the current limit constant (k) of 0.25. It can be observed domestic and commercial applications. However, if a low-frequency
that the consistency of 𝑑high and full duty increases in the case of 𝜔∗𝑚 at clock is used for the IC, then a reduction in the design delay should
1800 RPM as compared to 1000 RPM. be considered by the designer.
The tolerance to glitches and noises in the Hall signal during speed
calculation is a relevant part of the proposed architecture. The speed
3.2. ASIC implementation
measurement is performed by utilizing only one Hall sensor signal,
i.e., 𝐻𝑎 , and the value of n is considered as 9 in this paper. Hence,
an intentional glitch of 8 clock pulses is injected in the signal 𝐻𝑎 The proposed hardware architecture is synthesized in the Cadence
to validate the robustness of the speed calculation architecture. The RTL compiler using the TSMC 180 nm technology library. The maxi-
FPGA calculated speed response for each variation in the signal 𝐻𝑎 mum operating frequency has been constrained to 50MHz, and the gate
is shown in Fig. 12 with an 𝜔∗𝑚 of 1500 RPM. It can be verified that equivalent count (GEC) is calculated in terms of NAND2×L. The layout
𝜔𝑚 is calculated after 9 clock cycles (which is an insignificant delay) of the developed ASIC after the sign-off is shown in Fig. 13. The power
of each rising or falling edge of signal 𝐻𝑎, and the glitches have no dissipation and the total area in NAND-GEC of the developed hardware
visible effect on the calculated 𝜔𝑚 . In the proposed controller, there is architecture with QDPWM controller, speed calculation, and commuta-
no considerable latency in speed calculation with a clock of 50 MHz tion circuits are shown in Table 4. The proposed hardware architecture
frequency, which means that the speed is calculated in the same clock is also compared to the synthesized model of a conventional PI–PWM

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

Table 4
ASIC device utilization of QDPWM based controller.
Module Gate equivalent Power (μW)
NAND2 × L
Leakage power Dynamic power Total power
Total QDPWM controllera 4.98 k 1.829 3196.868 3198.697
Total PI–PWM controllera 14.59 k 5.391 6432.518 6437.910
QDPWM controller 1.135 k 0.327 1452.04 1452.368
PI–PWM controller 6.852 k 2.357 2737.833 2740.191
a
Total controller includes the speed calculation and commutation units.

Fig. 11. d values calculated by QDPWM controller based on sensed 𝜔𝑚 and 𝐼DC of BLDC motor for 𝜔∗𝑚 = 1000 RPM (a) load = 0.1 Nm, (b) load = 0.3 and 𝜔∗𝑚 = 1800 RPM (c)
load = 0.1 Nm, (d) load = 0.3.

Fig. 12. 𝜔𝑚 calculated by the FPGA with variation in Hall sensor signals.

Fig. 13. Layout of the proposed QDPWM controller-based ASIC.

controller for BLDC drive working at the same frequency. The PI–PWM
controller, combined with the speed calculator and commutation cir-
cuitry, requires nearly thrice as much area and consumes approximately
two times more power than the proposed hardware architecture. In circuits are also integrated into the design. The FPGA implementation
comparison, only PI–PWM controller architecture consumes almost 1.9 of the proposed architecture shows that it is highly effective in reducing
times more power and requires six times more area than only QDPWM resource utilization over the existing designs. A PI controller based
controller architecture. The reduction in the on-chip area and power PWM generation architecture, which is regarded as a standard control
dissipation is due to the simple architecture of the QDPWM technique. technique to drive BLDC motor, also has been compared with the
QDPWM controller involves a few conditional operations for PWM proposed architecture. The proposed architecture consumes nearly one-
generation decisions in contrast to the complex computations of the third of the area (in terms of NAND2XL equivalent gate count) and half
PI controller. of the power compared to the PI–PWM based control architecture. The
proposed control architecture satisfactorily tracks various commanded
4. Conclusion speeds with a maximum steady-state error of 5.5%. The BLDC motor
drive also responds to the sudden changes in dynamic conditions such
The hardware architecture of a controller for BLDC motor drive as speed command and load, which implies the robustness of the
based on the QDPWM technique has been presented in this paper. In designed architecture. The speed calculation unit is able to tolerate
addition to the computationally simple QDPWM technique, a single glitches and external noises in the Hall sensor signal, which is validated
Hall sensor-based speed calculation and back-EMF based commutation by injecting a glitch of 8 clock cycles. Hence, the proposed architecture

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P. Mishra, A. Banerjee, M. Ghosh et al. Control Engineering Practice 109 (2021) 104752

stands on the optimality of cost and drive performance for commercial- Lakka, M., Koutroulis, E., & Dollas, A. (2014). Development of an FPGA-based SPWM
ization. Besides, it is suitable for low power domestic and industrial generator for high switching frequency DC/AC inverters. IEEE Transactions on Power
Electronics, 29, 356–365. https://doi.org/10.1109/TPEL.2013.2253216.
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Lascu, C., Boldea, I., & Blaabjerg, F. (2004). Variable-structure direct torque control—A
washing machines, HVAC, blowers, and vents. class of fast and robust controllers for induction machine drives. IEEE Transactions
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Declaration of competing interest Lee, J. H., Song, J.-Y., Kim, D.-W., Kim, J.-W., Kim, Y.-J., & Jung, S.-Y. (2018).
Particle swarm optimization algorithm with intelligent particle number control for
optimal design of electric machines. IEEE Transactions on Industrial Electronics, 65,
The authors declare that they have no known competing finan-
1791–1798. https://doi.org/10.1109/TIE.2017.2760838.
cial interests or personal relationships that could have appeared to Liu, Y., Xiahou, K., Wang, L., & Wu, Q. H. (2018). Switching control of GSC of DFIGWTs
influence the work reported in this paper. for disturbance rejection based on bang–bang control. IEEE Transactions on Power
Delivery, 33, 3256–3259. https://doi.org/10.1109/TPWRD.2018.2852942.
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