Q1. What is the difference between latch and flip-flop?

Latch: A level-sensitive memory element that stores data based on the input signal's level (HIGH or
LOW). It continuously responds to inputs when enabled, making it asynchronous.

 Flip-Flop: An edge-triggered memory element that stores data only on the edge (rising or falling)
of a clock signal, ensuring synchronization with a clock pulse.

Differences:

Aspect Latch Flip-Flop

Triggering Level-sensitive (active for input level). Edge-sensitive (active on clock edge).

Clock Dependency May not need a clock signal. Always requires a clock signal.

Operation Responds as long as enabled. Responds only at clock edges.

Speed Faster, less control over timing. Slower, ensures precise timing.

Used in simple storage or transparent Used in complex, synchronized

Usage
circuits. designs.

Q1: Working of J-K Flip-Flop

The J-K flip-flop is an edge-triggered bistable device where:

 J = 1, K = 0: Sets the output to 1 (Set).

 J = 0, K = 1: Resets the output to 0 (Reset).

 J = 0, K = 0: Retains the previous state (No change).

 J = 1, K = 1: Toggles the output (Switches between 0 and 1).

Q2: Merit of J-K Flip-Flop over S-R Flip-Flop

The J-K flip-flop eliminates the undefined state of the S-R flip-flop when S = 1, R = 1. Instead, it toggles
the output, making it more versatile.

Q3: Race-Around Condition

Occurs in a J-K flip-flop when the clock pulse duration is longer than the propagation delay, causing
multiple toggles in a single clock pulse. It can be avoided by using a Master-Slave configuration or edge-
triggering.

Q1: Define Latch

A latch is a level-sensitive memory device that stores data based on the input level. It continuously
updates its output as long as the enable signal is active.

Q2: Define Flip-Flop

A flip-flop is an edge-triggered memory device that stores data only during the transition (rising or falling
edge) of a clock signal.

Q3: Difference between Flip-Flop and Latch

Aspect Latch Flip-Flop

Triggering Level-sensitive (active for input level). Edge-sensitive (active on clock edge).

Clock Dependency May not require a clock. Always requires a clock.

Operation Updates continuously when enabled. Updates only during clock edge.

Usage Simpler, for basic storage. Complex, for synchronized systems.

Q1: Which IC is used for SR Flip-Flop?

IC 7400 (NAND gates) or 7402 (NOR gates) can be used to implement SR flip-flops.

Q2: Applications of Different Flip-Flops

 SR Flip-Flop: Simple memory storage.

 D Flip-Flop: Data synchronization, registers.

 T Flip-Flop: Counters, frequency dividers.

 J-K Flip-Flop: Complex circuits, toggling applications.

Q3: Advantage of Edge Triggering over Level Triggering

Edge triggering avoids the continuous changes of level triggering, ensuring precise and synchronized
state changes, reducing errors.

Q4: Relation Between Propagation Delay and Clock Frequency of Flip-Flop

Clock frequency (fclockf_{clock}fclock) is inversely related to propagation delay (tpt_ptp):

fclock≤1tpf_{clock} \leq \frac{1}{t_p}fclock≤tp1

Higher delay reduces the maximum allowable frequency.

Q5: What is Race Around in Flip-Flop & How to Overcome It?

 Race Around Condition: In a J-K flip-flop, multiple toggles occur during one clock pulse when the
clock duration is greater than the propagation delay.
  Solution: Use Master-Slave Flip-Flops or edge-triggering to restrict toggling.

 Q1: What does mod–N counter mean?

 A mod–N counter is a counter that cycles through N states (0 to N-1) before resetting to
0.


 Q2: What is the function of a counter?

 Counters are used to count events, divide frequencies, or sequence operations in digital
circuits.


 Q3: What is the role of an encoder in communication?

 An encoder converts input data (like binary or analog signals) into a coded format,
optimizing transmission efficiency and security.


 Q4: What is the advantage of using an encoder?

 Encoders reduce input complexity by converting multiple inputs into a smaller coded
format, saving space and improving efficiency.


 Q5: Differentiate between combinational and sequential circuits.

Aspect Combinational Circuit Sequential Circuit

Memory No memory elements. Has memory to store past states.
Output Dependence Depends only on current inputs. Depends on inputs and past states.
Example Adders, multiplexers. Counters, flip-flops.

 Q6: Define synchronous sequential circuits.
 Synchronous sequential circuits use a clock signal to synchronize state changes, ensuring
changes occur only at specific clock edges.


 Q7: Define asynchronous sequential circuits.

 Asynchronous sequential circuits operate without a clock signal and respond to input
changes immediately, making them faster but prone to glitches.


 POST-EXPERIMENT QUESTIONS:
 Q1: Define ‘module’ (MOD) with respect to a counter.
 The MOD number indicates the total number of unique states a counter cycles through
before resetting to 0.
 Q2: Maximum number of states of a counter?
 For an n-bit counter, the maximum number of states is 2ⁿ.
Q1: Define Half Adder

A half adder is a combinational circuit that performs the addition of two binary bits, producing a sum
and a carry as outputs.

Q2: Define Full Adder

A full adder adds three binary bits (two inputs and a carry-in) and produces a sum and a carry-out.

Q3: Define Half Subtractor

A half subtractor is a combinational circuit that subtracts one binary bit from another, producing a
difference and a borrow as outputs.

Q4: Define Full Subtractor

A full subtractor subtracts three bits (two inputs and a borrow-in) and produces a difference and a
borrow-out.

Q5: Applications of Adders

 Binary addition in arithmetic logic units (ALUs).

 Digital counters.

 Data processing in microprocessors.

 Binary multipliers.

Q6: Applications of Subtractors

 Binary subtraction in ALUs.

 Digital comparators.

 Microprocessor arithmetic operations.

 Signal processing for differences.