1
Name: ________________________ Period: ______ Date: _______________ Score: ______________
Digital Electronics – Unit 1 – Activity 1.2.4: Counters
Instructions: Please refer to the PLTW Digital Electronics textbook for more information. This activity uses
the Circuit Design Software (CDS) called Multisim and it is only available on PC.
1. In the CDS, create a circuit using the 74LS74N D Flip Flop. You will need three inputs: (P)reset into Preset,
(T)rigger into Clock-In, and (C)lear into Clear. The inputs should be SPDT switches connected to VCC and
GND, with the specified keyboard shortcuts. There should be two outputs: Q and not Q. Use a blue probe for
Q and a red probe for not Q. Finally, the Data-In pin should be tied to not Q.
2. Start the simulation and follow the instructions:
a. Toggle P and C to 5 Volts. Because the Present and the Clear are Active Low (notice the circle on the
pin), then a High Input will make them inactive. Write the state of the two outputs.
ri
b. Toggle T several times and observe the output probes Q and not Q. Write your observations.
Every two toggles of T, Q and NQ toggle
c. Set the Preset to GND and keep the Clear to 5 V. Write the state of the two outputs.
0 1 Nate
d. Toggle T several times and observe the output probes Q and not Q. Write your observations.
Nothing changes
e. Set the Preset to 5 V and the Clear to GND. Write the state of the two outputs.
f.
Neil 9 0
Toggle T several times and observe the output probes Q and not Q. Write your observations.
Nothing changes
2
3. Now create this circuit in the CDS. This Dual D Flip-Flop circuit is a two-bit binary counter. Recall in Activity
1.1.6, you learned that the output on the first flip-flop (A) changes only when the Clock-In goes from low to
high.
4. Start the simulation and follow the instructions:
a. Toggle the input Clock-In (switch T) until
both outputs A and B are low and switch T
is low.
b. Now, cycle switch T and record what effect
this has on the two outputs in the table. A
“cycle” = toggle from low → high → low.
c. Cycle Switch T again and complete the
table.
Clock-In Output A Output B
Initial Values 0 0
Cycle 1 of Switch T
o l
Cycle 2 of Switch T
l l
Cycle 3 of Switch T
Cycle 4 of Switch T
Cycle 5 of Switch T
Cycle 6 of Switch T
Cycle 7 of Switch T
Cycle 8 of Switch T
Cycle 9 of Switch T
d. Notice the pattern of the outputs. Write what pattern you observe.
It counts to three and when it hits three it starts
back at zero.
e. Predict what outputs you would have for Cycle 10 of Switch T.
3
5. Now, copy your previous circuit and paste a new copy on the same sheet. Modify this new one.
● First modification: Replace the input switch
with a CLOCK_VOLTAGE. This will cause the
input to be automatically and continuously
toggled. Be sure the CLOCK_VOLTAGE is set
to 5 volts, 50% duty cycle, 60 Hz.
● Second modification: Add a four-channel
oscilloscope that is set up to view the three
signals A, B, and Clock-In.
● Third modification: Be sure to set the
oscilloscope’s time-base to 20 ms/div on the
x-axis. Set the vertical bases of the four
channels to 10 volts/div. Also, adjust the Y
position of the three channels such that the
three signals are all visible. See Figure 6.
6. Start the simulation and follow the instructions:
a. Let the simulation run until you have
captured several periods of each signal
(see Figure 6).
b. Using the oscilloscope’s markers,
measure the period of the three signals.
Use this data to calculate the frequency
for each signal. Record your data in the
table with its correct units.
Signal Period Frequency
Clock-In
c. Based on these results, what is the relationship between Period and Frequency?
p
4
7. Create a third circuit by copying the last one. Create the 4-bit binary counter as shown in Figure 7.
8. Analyze the circuit to determine the frequency and period for the signals A, B, C, and D. Use the table to
record your answers.
Signal Period Frequency
Clock-In
IN too
D
IN Sae
C
4ms 25
B
8N 125
A
16ms 62.5
9. Use the 4-bit binary counter to count from 0 to 15 in binary. With such a fast clock speed (1kHz), it is very
difficult to see the binary count. Change the clock frequency to something that allows you to see the four
probes transition more slowly in the simulation. Write down which clock frequency worked best for you.
GHz
10. The 2-bit and 4-bit counters you explored in this activity are referred to as “divide-by-two” counters. Explain
the relationship between each consecutive flip-flop and the order in which they are laid out in the design from
right to left that creates a binary count.
Each ip op represents a le in binary
The maximum number is represented by 2^(number
of ip ops)-1
5
Introduction to Sequential Logic.
Along with combinational logic, sequential logic is a fundamental building block of digital electronics. The
output values of sequential logic depend not only on the current input values (combinational logic), but also on
previous output values. This dependency is aided with a clock signal to control sequencing and memory to
retain previous outputs.
D Flip Flip (74LS74N)
The D flip-flop is one of many different types of flip-flops
that can be used to build a sequential logic circuit.
Counters are one of the most common applications of
flip-flops.
You first used the D flip-flop in Activity 1.1.6 Digital
Component Identification. In this activity you will create a
simple two-bit binary counter using two D flip-flops. It will
count from zero (00) to three (11) in binary. Then you
will create a 4-bit binary counter that counts from zero
(0000) to 15 (1111) in binary.
Inside the D Flip-Flop are a bunch of NAND gates.
● Both inputs to NAND gate #1 are “tied” together.
This makes the NAND into an INVERTER.
● The Data-In and Clock-In go into NAND gate #2.
● The Data-In is inverted and combined with the
Clock-In into NAND gate #3.
● NAND Gate #4 gives the output Q.
● NAND Gate #5 gives the output not Q.
● The Preset and Clear are not shown here.
NAND Gate
● Recall the Truth Table for the NAND gate.
● What happens if the inputs are tied together?
● If the inputs A and B are tied together, then the middle
two rows (1 0) and (0 1) will never happen. If both are
LOW, the output is HIGH. If both are HIGH, the output is
LOW. Thus, the “tied” NAND is an INVERTER.
