Dr.

Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
Unit 3
Computer Arithmetic and Processor Organization

Computer Arithmetic : Addition and Subtraction of Signed Numbers, Design of Fast

Adders, Multiplication of Positive Numbers, Signed-operand Multiplication, Fast
Multiplication, Integer Division, Floating-Point Numbers and Operations

Processor Organization: Fundamental Concepts, Execution of a Complete Instruction,

Multiple-Bus Organization, Hardwired Control and Multi programmed Control

Computer Arithmetic
Addition and Subtraction of Signed Numbers
 The term "signed" in computer code indicates that a variable can hold negative and positive
values.
 A signed number has three representation I) Signed magnitude II) Signed 1’s complement and
III) Signed 2’s complement.

I) Signed magnitude
 Sign-magnitude is a method for representing signed numbers in binary. In this system, the
most significant bit (MSB) is used to indicate the sign of the number, and the remaining bits
represent the magnitude (absolute value) of the number.
 If MSB (Most Significant Bit) is 0 it indicates a positive number, if 1 it indicates a negative
number. The remaining bits represent the magnitude, or the absolute value of the number.
For example
For 8 bit system:
+5 in 8-bit sign-magnitude: 0000 0101 (MSB is 0 for positive)
−5 in 8-bit sign-magnitude: 1000 0101 (MSB is 1 for negative, and the magnitude is 5)

For 4 bit system:

+3 binary representation is 0011 (MSB is 0 for positive)
-3 binary representation is 1011 (MSB is 1 for negative, and the magnitude is 3).

Addition:
When adding two numbers:
 If they have the same sign, you perform normal binary addition and keep the sign.
 If they have different signs, you subtract the smaller magnitude from the larger and keep the
sign of the number with the larger magnitude.
Eg:
+5 and -3 in 4-bit sign-magnitude:
+5 = 0101 −3 = 1011
To add them, since their signs differ, subtract the magnitudes:
5−3=2
The result has the sign of the larger magnitude, which is positive. So the result is:
+2 = 0010

Subtraction:
Subtraction involves carefully handling both the sign and the magnitude.
1) Subtract +5 from +9 (Same Sign)

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
 +9 = 1001
 +5 = 0101
Since the signs are the same, we subtract the magnitudes:
9−5=4.
Result: +4 = 0100.

2) Subtract +5 from +3 (Same Sign, Result is Negative)

 +3 = 0011
 +5 = 0101
Since the signs are the same but 5 is larger than 3, we subtract the smaller magnitude from the larger:
5−3=2.
The result should have the sign of the larger magnitude, so the result is: −2 = 1010.

3) Subtract −3 from +5 (Different Signs)

 +5 = 0101
 −3 = 1011
Since the signs differ, this becomes an addition problem: 5+3=8.
Result: +8 = 1000.

4) Subtract −7 from −2 (Same Sign, Both Negative)

 −2 = 1010
 −7 = 1111
Since both numbers are negative, we subtract their magnitudes: 7−2=5.
The result should have the sign of the larger magnitude, so the result is: −5 = 1101.

5) Subtract +2 from −4 (Different Signs)

 −4 = 1100
 +2 = 0010
Since the signs differ, this becomes an addition problem: 4+2=6.
The result should have the sign of the first number, so the result is: −6 = 1110

II) One’s Complement

 One's complement is a system used to represent signed numbers in binary, where the positive
numbers are represented the same way as in regular binary, and the negative numbers are
represented by inverting (flipping) (changing 0 to 1 and 1 to 0) all the bits of their positive
counterparts.
 In an n-bit system, the range of numbers that can be represented in one's complement is: from
−(2n−1 - 1) to +(2n−1 - 1)
Addition
+5 in binary: 0101
−3 in one's complement: 1100 (invert bits of 0011)
0101 (+5)
+ 1100 (-3)
--------
10001 (5-bit result, ignore the leftmost carry)

Subtraction
+6 in one's complement: 0110
−2 in one's complement: 1101 (invert bits of 0010)

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
0110 (+6)
+ 1101 (-2)
--------
10011 (5-bit result, ignore the leftmost carry)

Overflow Detection
 Overflow happens when adding two numbers in one's complement if the result is outside the
representable range or if there is a carry into the sign bit (MSB) but no carry out of it, or vice
versa.
Eg:
0110 (+6)
+ 0101 (+5)
--------
1011 (interpreted as -4 in one's complement)

III) Two's Complement

 In this system, positive numbers are represented as usual in binary.
 Negative numbers are represented by taking the binary representation of the positive number,
inverting all the bits, and then adding 1.

Addition
o If both numbers have the same sign (both positive or both negative), the operation is
straightforward binary addition.
o If the result exceeds the word size, the overflow bit is discarded.
o For numbers with different signs, subtraction is effectively performed by adding the two's
complement of the negative number.
Eg:
To add 5 and −3 using 4-bit numbers:
5 in binary (4 bits): 0101
−3 in two's complement: 1101 (invert 0011 to 1100, add 1 → 1101)
0101
+ 1101
------
10010 (discard the overflow bit, leaving 0010, which is 2 in decimal)

Subtraction
o Subtraction is performed by converting the number being subtracted into its two's
complement and then adding. This way, subtraction becomes an addition operation.
Eg:
To subtract 3 from 5 (5−3) using 4-bit numbers:
3 in binary: 0011
Two's complement of 3: 1101
0101
+ 1101
------
10010 (discard the overflow bit, result is 0010 or 2 in decimal)

Overflow Detection

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
 In computer arithmetic, overflow occurs when the result of an operation (like addition or
subtraction) exceeds the range that can be represented with the given number of bits.
 Overflow detection is especially important when dealing with signed numbers, as the result
might not fit within the range of the signed number system, leading to incorrect results.
 The carry into the sign bit (MSB) differs from the carry out of the sign bit.
 In two's complement arithmetic, overflow can occur in the following cases:
1) Positive + Positive = Negative → Overflow
2) Negative + Negative = Positive → Overflow
3) Subtraction leading to a result outside the range → Overflow
Eg:
0101 (+5)
+ 0100 (+4)
-------
1001 (-7 in two's complement)

1010 (-6)
+ 1101 (-3)
-------
0111 (+7 in two's complement)

0100 (+4)
- 1101 (-3)
-------
1001 (-7 in two’s complement)

Design of Fast Adders

 A fast adder also known as carry-look ahead adder (CLA) is a type of adder used in digital
logic which improves speed of adding two binary numbers by reducing the amount of time
required to determine carry bits.
 They work by creating two signals P and G known to be Carry Propagator and Carry
Generator. The carry propagator is propagated to the next level whereas the carry generator
is used to generate the output carry , regardless of input carry.
 The block diagram of a 4-bit CLA adder is shown here below –

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
Boolean expressions for designing full adder

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
Advantages –
The propagation delay is reduced.
It provides the fastest addition logic.

Disadvantages –
The Carry Look-ahead adder circuit gets complicated as the number of variables increase.
The circuit is costlier as it involves more number of hardware.

Multiplication of Positive Numbers

 Binary multiplication is one of the four basic operations performed on binary numbers that is
addition, subtraction, multiplication, and division.
 Binary multiplication is similar to multiplication with decimal numbers. The only difference
lies in the representation of numbers. Where binary numbers are written as 0 and 1, decimal
numbers use the digits from 0 to 9.
 The binary multiplication operation is actually a process of addition and shifting operation.
This process has to be continued until all the multiplier is done, and finally, the addition
operation is made.
 The multiplication table for binary numbers is as follows:

Binary Numbers Multiplication Value

0×0 0
1×0 0
0×1 0
1×1 1
 The basic rules for the multiplication of binary numbers are:
Multiplicand Multiplier Product
0 0 0×0=0
0 1 0×1=0
1 0 1×0=0
1 1 1×1=1
Algorithm
Step 1: Registers
C  Single bit (initially 0)
A  n bit (initially 0)
B  n bit multiplicand
Q  n bit multiplier
Count  is a variable which is equal to n

Step 2: Check the Q0 (LSB) value of Q

if Q0 = 1 perform the following
i) Add A A+B
If carry generated store it in C
ii) Shift left to right (starting from C, A, Q)
iii) Reduce the count value

if Q0 = 0 perform the following

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
i) No addition
ii) Just shift
iii) Reduce the count value

Step 3: This process will continue until the count value becomes zero

Step 4: Result is stored in AQ

Example:
Multiplicand (B) = 13  1101 (LSB B0) shift
Multiplier (Q) = 11  1011 (LSB Q0)

C A Q Count
0 0000 1011 Initial condition 4 (max no
of bits)
0 1101 1011 Add A A+B
0 0110 1101 Shift 3
1 0011 1101 Add AA+B
0 1001 1110 Shift 2
0 0100 1111 No add | just shift 1
1 0001 1111 Add AA+B
0 1000 1111 Shift 0

Output
13 X 11 = 143
(143)10 = (1000 1111)2 Additions

Signed-operand Multiplication
 Signed operand multiplication refers to the process of multiplying two binary numbers where
at least one of the numbers is represented with a sign (positive or negative).
 Multiplication of 2's complement signed operands is somewhat different and exhibits
difficulty, especially when the operands are negative: e.g. if we consider, multiplying
unsigned integers 11 (1011) by 13 (1101) to yield a product 143 (10001111). If we interpret
these two numbers in 2's complement representation, we have -5 (1011) multiplied by -3
(1101), giving -113 (10001111). This example reveals that straightforward multiplication will
not work if both the multiplicand and the multiplier are negative.

Page 7
Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
 One simpler technique that is most commonly used is Booth's algorithm. This approach
additionally has the merit of potentially speeding up the multiplication process, relative to a
more straightforward approach.

Booth’s algorithm
 One of the most elegant and widely used schemes for two's complement multiplication was
proposed by Andrew D. Booth sometimes in 1951.
 Booth's algorithm is simple to understand and easy to implement that employs both addition
and subtraction, and it treats positive and negative operands uniformly, with as such no
special actions required for negative numbers separately.

Hardware Implementation of Booths Algorithm

Page 8
Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
Example

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Fast Multiplication
 Fast multiplication has two techniques
1) Bit-pair (Extended Booth)
2) Carry –save Addition (CSA) of summands

Technique 1
Bit-pair (Extended Booth)
1) If the M or Q is negative then find the 2’s complement of respective negative number
2) Find the Recoded multiplier (Q’) by referring Bit-pair recoding table by adding implied zero and
extended sign bit.
3) Multiply with 2n-bit extended for each partial product Pi. Where each partial product should have
two right shifts.
4) Find the final product P of 2n-bits.

Bit-pair recoding of multipliers Truth Table

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Example

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Technique 2
Carry –save Addition (CSA) of summands

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Example

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
Integer Division
Binary Division is performed in the same manner as decimal numbers are divided. However, there
are some specific rules regarding the division among the binary digits 0 and 1 which we need to
follow while performing division of Binary Division. The Binary Division rules is shown in the
Binary Division Table below:
Table of Binary Division Rule

Rules for Binary Division Meaning

If 0 (zero) is divided by another 0

0/0=∞ (zero), then the result is
meaningless.

if 0 (zero) is divided by 1 (one),

0/1=0
then the result will be 0 (zero).

If 1 (one) is divided by 0 (zero),

1/0=∞
then the result is meaningless.

If 1 (one) is divided by another 1

1/1=1 (one), then the
result will be 1 (one).

Example
(11011)2 ÷ (11)2
Solution:
We start by taking the first two digits of the dividend (11)2 which is equal to the divisor.
Step 1: Write 1 as the first digit of the quotient. Then, subtract the divisor from the first part of the
dividend and write down the remainder.
Step 2: Bring down the next digit of the dividend (0). Now we have (0)2 which is less than the
divisor (11)2. So, write 0 in the quotient.
Step 3: Next bring down the next digit of the dividend (1). Now we have (1)2 which is less than the
divisor (11)2. So, write 0 in the quotient. We subtract the divisor from the current part of the
dividend and write down the remainder.
Step 4: Finally, bring down the last digit of the dividend (1). Now we have (11)2 which is equal to
the divisor (11)2. So, write 1 in the quotient and 0 as the remainder.
So, the quotient of (11011)2 ÷ (11)2 is (1001)2 and the remainder is (0)2

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Floating-Point Numbers and Operations

Processor Organization
Fundamental Concepts

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Execution of a Complete Instruction

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
Explain of above

Multiple Bus Organization

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Hardwired Control and Multi programmed Control

 In computer architecture, the control unit is responsible for directing the flow of data and
instructions within the CPU.
 To execute an instruction, the control unit of the CPU must generate the required control
signal in the proper sequence. There are two approaches used for generating the control
signals in proper sequence as Hardwired Control unit and the Micro-programmed control
unit.
Hardwired control unit
 The control hardware can be viewed as a state machine that changes from one state to
another in every clock cycle, depending on the contents of the instruction register, the
condition codes, and the external inputs.
 The outputs of the state machine are the control signals. The sequence of the operation
carried out by this machine is determined by the wiring of the logic elements and hence
named “hardwired”.

Micro-programmed control unit

 The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words.
 Control signals are generated by a program that is similar to machine language programs.

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297
 The micro-programmed control unit is slower in speed because of the time it takes to fetch
microinstructions from the control memory.

1. Control Word: A control word is a word whose individual bits represent various control
signals.
2. Micro-routine: A sequence of control words corresponding to the control sequence of a
machine instruction constitutes the micro-routine for that instruction.
3. Micro-instruction: Individual control words in this micro-routine are referred to as
microinstructions.
4. Micro-program: A sequence of micro-instructions is called a micro-program, which is stored
in a ROM or RAM called a Control Memory (CM).
5. Control Store: the micro-routines for all instructions in the instruction set of a computer are
stored in a special memory called the Control Store.

Types of Micro-programmed Control Unit –

Based on the type of Control Word stored in the Control Memory (CM), it is classified into two
types:
1) Horizontal Micro-programmed Control Unit: The control signals are represented in the
decoded binary format that is 1 bit/CS. Example: If 53 Control signals are present in the processor
then 53 bits are required. More than 1 control signal can be enabled at a time.
2) Vertical Micro-programmed Control Unit: The control signals are represented in the encoded
binary format. For N control signals- Log2(N) bits are required.

The differences between hardwired and micro-programmed control units:

Micro-programmed Control
Hardwired Control
Unit
Unit

Fixed set of logic Microcode stored in memory

Implementation
gates and circuits

Flexibility Less flexible, More flexible, easier to modify

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Dr. Vamshi Krishna K
Associate Professor, Dept. of CSE, KHIT, Guntur
[email protected], 8143260297

Micro-programmed Control
Hardwired Control
Unit
Unit

difficult to modify

Supports complex instruction

Supports limited
Instruction Set sets
instruction sets

Complex design, more difficult

Complexity of Simple design, easy
to implement
Design to implement

Slower operation due to

Speed Fast operation microcode decoding

Debugging and Difficult to debug Easier to debug and test

Testing and test

Smaller size, lower Larger size, higher cost

Size and Cost
cost

Maintenance and Difficult to upgrade

Easier to upgrade and maintain
Upgradability and maintain

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