UNIVERSITY EXAMINATION 2021/2022

EXAMINATION FOR THE DEGREE OF BACHELOR OF TECHNOLOGY IN

ELECTRONICS AND COMPUTER
EEE 2210 ANALOG ELECTRONICS II YEAR II SEMESTER II

Date: Monday, 13th June 2022 Time: 8.30am – 10.30am

INSTRUCTIONS
Attempt all questions in Section A and any two in Section B.

SECTION A

Question One

(a)Distinguish between double-ended and single-ended differential amplifier (4 marks)

(b) Explain swamping as applied in transistor amplifiers (2 marks)

(c) (i)Define SCR (1mark)

(ii)Name the SCR terminals (3marks)

(iii)With the aid of diagrams, explain how an SCR is turned on and off (4 marks)

(d) Define common-mode rejection ratio (2 marks)

(e) Explain how Silicon-Controlled Rectifiers (SCRs) differ from TRIACs, in terms of their
respective behavior (3 marks)

(f) The transconductance of a JFET used as a voltage amplifier is 3000 μmho and drain
resistance is 10 kΩ. Calculate the voltage gain of the amplifier (3 marks)

(g) A certain diff-amp has a differential voltage gain of 2000 and a common-mode gain of
0.2. Determine the CMRR and express it in decibels (4 marks)

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 (h) A unijunction transistor fig 1 with an intrinsic standoff ratio (η) of 0.8 is powered by a 15
volt DC source. Calculate the emitter voltage needed to ”trigger” this UJT into its conductive
state (4 marks)

Fig. 1

Question two (20 marks)

(a) Determine the base-to-collector voltage gain of the amplifier in fig. 2 both without and with
an emitter bypass capacitor if there is no load resistor. Take r’e = 6.98 V (4 marks)

fig 2

(b) Calculate the amount of gate-to-source voltage necessary to regulate a JFET’s drain current at
a value of 2.5 mA, given the following transistor parameters:VGS(off) = 3V, IDSS = 17 mA
(3marks)

(c)(i) Determine the minimum value for the emitter bypass capacitor C2 in figure 3 if the
amplifier must operate over a frequency range from 100Hz to 10kHz. (3 marks)

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 fig. 3

(ii) Determine the base-to-collector voltage gain of the amplifier in fig. 3 both without and with
an emitter bypass capacitor if there is no load resistor. (4 marks)

(iii) Determine the base-to-collector voltage gain in fig. 3 with RE bypassed for the following
circuit values: Rc = 1.8kΩ, RE = 1kΩ, R1 = 33KΩ and R2 = 6.8KΩ (6 marks)

Question three (20 marks)

(a) Extract DC and AC equivalent circuits from figure 4 (6 marks)

Fig. 4

(b) Determine the signal voltage at the base of the transistor in fig.2. Take IE to be 3.8mA

(5marks)

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 fig 2.

(c) The datasheet of a JFET gives the following information: IDSS = 3 mA, VGS (off) =
– 6V and gm (max) = 5000 μS. Determine the transconductance for VGS = – 4V and find
drain current ID at this point. (5 marks)

(d) A certain differential amplifier has a differential voltage gain of 8500 and a common-mode
gain of 0.25. Determine CMRR and express it in dB (4marks)

Question four(20 marks)

(a) A certain JFET has a gm =4mS. With an ac drain resistance of 1.5kΩ, determine the ideal
voltage gain (3 marks)

(b) Determine the total output voltage for the amplifier in fig. 5. IDSS is 4.3mA and VGS(off) is -
2.7V. Take ID = 1.91mA. (5marks)

Fig 5

(c) Determine the gate trigger current and anode current when the switch SW1 is momentarily
closed in fig. 6. Assume VAK = 0.2V, VGK = 0.7V and IH = 5mA. (6marks)

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 Fig. 6

(d) A certain cascaded amplifier arrangement has the following voltage gains: Av1 = 10,Av2 =
15, and Av3 = 20.
(i) Determine the overall voltage gain (1 marks)
(ii) Express each gain in decibels (dB) (3marks)
(iii) Determine the total voltage gain in dB (2 marks)

Question five (20 marks)

(a) For the amplifier in Figure 4 (14 marks)
(i) Determine the dc collector voltage.
(ii) Determine the ac collector voltage.

Fig. 4

(b) (i)Define Programmable unijunction transistor (2 marks)

(ii)Describe operation of a Programmable unijunction transistor (4 marks)

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