366 1/O Interfaces Chap.

bit 5 will cause the CA line to go high. Setting bit 6 causes the 8251A to be
reinitialized and the reset sequence to be reentered (i.e., a return is made to the
top of the flowchart shown in Fig. 9-14 and the next output will be to the mode
register). Bit 7 is used only with the synchronous mode. When set, it causes the
8251A to begin a bit-by-bit search for a syne character or sync characters.
Typical connections to modems for asynchronous and synchronous transmis-
sions are shown in Fig. 9-17. With regard to the synchronous connections it is
assumed that the timing is controlled by the modem and its related communications
equipment. Also, if this equipment is used to detect the sync character(s) at the
beginning of a received message, then it can inform the 8251A of its success over
the SYNDET line. On the other hand, if 8251A searches for the sync character(s),
then it can use the SYNDET line as an output to tell the modem that the sync
character(s) has been found. To satisfy the RS-232-C standard, drivers and receivers
are needed to convert the TTL-compatible signals at TxD and RxD to the proper
voltage levels (see Fig. 9-10).
A program sequence which initializes the mode register and gives a command
to enable the transmitter and begin an asynchronous transmission of 7-bit characters
followed by an even-parity bit and 2 stop bits is:
MOV AL,11111010B
QUT 51H,AL
MOV AL,001100118
OUT 51H,AL

This sequence assumes that the mode and control registers are at address 51H and
the clock frequencies are to be 16 times the corresponding baud rates. The se-
quence:
MOV AL,00111000B
OUT 51H,AL
MOV AL,16H
OUT 51H,AL
OUT 51H,AL
MOV AL,10010100B
OUT 51H,AL

would cause the same 8251A to be put in synchronous mode and to begin searching
for two successive ASCII sync characters. As before, the characters are to consist
of 7 data bits and an even parity bit, but there will, of course, be no stop bits.
The format of the status register is given in Fig. 9-18. Bits 1, 2, and 6 reflect
the signals on the RxRDY, TxE, and SYNDET pins. TxRDY indicates that the
data-out buffer is empty. Unlike the TxRDY pin, this bit is not affected by the
CTS input pin or the TxEN control bit. RxRDY indicates that a character has
been received and is ready to be input to the processor. Either the TxRDY and
RxRDY bits can be used for programmed I/O or the signals on the corresponding
pins can be connected to interrupt request lines to provide for interrupt I/O. The
TxRDY bit is automatically cleared when a character is made available for trans-
mitting and the RxRDY bit is automatically cleared when the character that set it
is input by the processor. Bit 2 indicates that the transmitter shift register is-waiting
Sec. 9-1 Serial Communication Interfaces 367

RS-232-C
driver and receiver

Asynchronous
modem and
communications

8251A co equipment Communication

DTR link

CTS
RTS

TC generator

(a) Asynchronous modem connection

RS-232-C
driver and receiver

BB
ja,|

DSR
BoSray nig pee) modem and
communications

CTs equipment Communication

Donaaaro
TxC P

*May also be used for rate selection — modem line CH.

(b) Synchronous modem connection

NOTE: Control line interfacing depends on modem specifications.

Figure 9-17 8251A modem connections.

to be sent a character from the data-out buffer register. During synchronous trans-
missions, while this bit is set, the transmitter will take its data from the sync
character registers until data are put in the data-out buffer register. Bits 3, 4, and
5 indicate parity, overrun, and framing errors, respectively. When an error is
detected, the bit having the corresponding error type will be set to 1. If the com-
 368 1/O Interfaces § Chap. 9

Indicates data-out buffer register

empty; unlike the TxRDY
pin, this bit is not affected
When 1 it indicates by CTs pin and TxEN
DSR pin is active control bit

| DSR |SYNDET | RxRDY |TxRDY

Same as RxRDY pin

Same as
SYNDET pin
Same as TxE pin

When 1 it indicates
the occurrence of a:

Framing error

Overrun error

Parity error

Figure 9-18 Format of the status register.

plement of the DSR pin is connected to the Data Set Ready (CC) line, then bit 7
reflects the state of the modem and is 1 when the modem is turnedon and is in
its data mode.
Figure 9-19 gives a typical program sequence which uses programmed I/O to
input 80 characters from the 8251A, whose data buffer register’s address is 0050,
and put them in the memory buffer beginning at LINE. The inner loop continually
tests the RxRDY bit until it is set by a character being put in the data-in buffer
register. Then the newly arrived character is moved to the buffer and the error
bits are checked. If the present character arrived before the previous character was
input or a parity or framing error occurred during transmission, then the input

Figure 9-19 Inputting a line of characters through an 8251A.

MOV AL,00110101B ;ENABLE TRANSMITTER AND RECEIVER

OUT 51H, AL ;AND CLEAR ERROR BITS
MOV DI,0 ; INITIALIZE INDEX
MOV CX, 80 ;PUT COUNT IN CX
BEGIN: IN AL,51H ;WAIT FOR INPUT
TEST AL,0O2H
JZ BEGIN
IN AL, 50H ; INPUT CHARACTER AND
MOV LINE(DI],AL ;PUT IN LINE BUFFER
INC DI
IN AL, 51H ;CHECK ERROR
TEST AL,00111000B ;BITS AND
JNZ ERROR ;I1F NO ERROR IS FOUND
LOOP BEGIN ;CONTINUE INPUTTING
JMP SHORT EXIT
ERROR: CALL NEAR PTR ERR ROUT ;ELSE CALL ERR ROUT
 Sec. 9-2 Parallel Communication 369

ceases and a call is made to an error routine that would presumably examine the
individual error bits, print an appropriate message, and clear the error bits.
Because inputting a character automatically resets the RxRDY bit, unless
another character is received before the inner loop is reentered, the inner loop
must cycle until the RxRDY bit is reset to 1 by the next incoming character. If the
incoming characters have fewer than 8 bits, the unused MSBs in the data buffer
register are always zeroed. Also, the parity bit is not passed to the processor and
checks for parity errors can only be made by examining the parity error bit in the
status register. On output, if a character is less than 8 bits long, the unneeded
MSBs in the data-out buffer register are ignored.

9-2 PARALLEL COMMUNICATION

Parallel communication is accomplished by simultaneously transferring bits over

separate lines. Its advantage over serial communication is that for lines with a given
maximum bit rate, higher information rates can be attained due to the use of
several lines. The disadvantage is, of course, the cost of the extra lines and, because
these costs increase with distance, parallel communication is used over long dis-
tances only if high data rates are required.
Unlike serial communication, parallel communication has not been well stand-
ardized. Parallel transfers may be performed by simply putting data in the interface’s
data-in buffer register or taking data out of the interface’s data-out buffer register,
or they may be conducted under the control of handshaking and/or timing signals.
Normally, one character (or other piece of information) is transferred at a time
and there is no problem in determining the end of a character or in finding the
beginning of a transmission. There is no well-defined format for synchronous or
asynchronous transmissions, but if a timing signal is to coordinate the activity
between the device and the interface, the transmission would be considered syn-
chronous. If only handshaking signals are employed, the transmissions would be
asynchronous.
An interface may be designed for only outputting, only inputting, inputting
and outputting over separate sets of lines, or performing I/O over a single set of
bidirectional lines. If an interface is connected to a line printer, it would only output
data, and if it services a card reader, it would only input data. An interface that
services both a paper tape reader and a paper tape punch would require one set
of input lines and one set of output lines, but an interface for a device that does
not input and output data simultaneously could use only one set of bidirectional
lines.
A typical parallel output interface which uses no control lines is given in
Fig. 9-20(a). In this case the contents of the data buffer register would continuaily
be maintained on the data lines connecting the interface and the output device. If
the output device consisted of a latch and a set of relays that are controlled by the
bit settings in the latch, then the computer could control the relays by simply
-outputting data to the data buffer register.
370 1/O Interfaces Chap. 9

Output device

Sey Address : select

Chip

Baa AO

(a) Output oniy

Interface 1/O device

Data-in ready

: tatus register ata out

Data-out ack.

Address
dhamke Chip select

(b) Input and output

Figure 9-20 Representative parallel communication interfaces.

Sec. 9-2 Parallel Communication 371

Figure 9-20(b) shows a representative parallel interface with handshaking

control lines and separate input and output connections to an I/O device. In this
case, an input would be carried out by first putting the data on the data bus and
a 1 on the data-in ready line. The interface would respond by latching the data
into the data-in buffer and putting a 1 on the data-in acknowledge line. Upon
receiving the acknowledgment the device would drop the data and ready signals.
When the data are received by the interface, it would set a “ready” status bit and
perhaps send out an interrupt request. After the CPU takes the data the interface
would clear the “ready” status bit and put the data lines in their high-impedance
state. If an interrupt request were made, it would be handled in the usual manner.
For an output, the interface would set a “‘ready”’ status bit and, perhaps,
make an interrupt request when the data-out buffer is available. After the CPU
outputs the data, the interface would clear the output ‘“‘ready”’ status bit, put the
data on the data-out bus, and signal the I/O device over the data-out ready line.
When the device is ready to accept the data, it would latch the data and then return
an acknowledgment. The interface would then drop its data-out ready signal and
once again set the output “‘ready”’ status bit.

9-2-1 -8255A Programmable Peripheral Interface

Intel’s 8255A programmable peripheral interface provides a good example of a

parallel interface. As shown in Fig. 9-21, the interface contains a control register
and three separately addressable ports, denoted A, B, andC. Whether or not an
8255A is being accessed is determined by the signal on the CS pin and the direction
of the access is according to the RD and WR signals. Which of the four registers
is being addressed is determined by the signals applied to the pins Al and AO.
Therefore, the lowest port address assigned to an 8255A must be divisible by 4.
A summary of the 8255A’s addressing is:
Al AO RD WR cs Transfer Description
0 0 0 1 0 Port A to data bus
0 1 0 1 0 Port B to data bus
1 0 0 1 0 Port C to data bus
0 0 1 0 0 Data bus to port A
0 1 1 0 0 Data bus to port B
1 0 1 0 0 Data bus to port C
1 1 1 0 0 Data bus to control register if D7=1; if D7=0,
input from the data bus is treated as a Set/
Reset instruction
x x x x 1 D7-DO go to high-impedance state
1 1 0 1 0 Illegal combination
x x 1 1 0 D7-DO go to high-impedance state

where 0 is low and 1 is high.

Because the bits in port C are sometimes used as control bits, the 8255A is
designed so that they can be output to individually using a Set/Reset instruction.
When the 8255A receives a byte that is directed to its control register, it examines