GOVERNMENT POLYTECHNIC, KOTDWAR
MID TERM (2023-24) Summer
Total Duration (HH:MM): 2:00
Computer System Organization & Architecture
Maximum Marks: 50
Course Name: Computer System Organization & Architecture Program Name- CSE(IV SEM)
Students will be On completion of this course student will be able to:
C402.1. Know the fundamental blocks of computer and Register Transfer and Micro Operations.
C402.2. Programming the basic Computer as Micro Programmed Control
C402.3. Understand the theory and architecture of central processing unit.
C402.4. Know about the computer arithmetic
C402.5. Realize the function of I/O in different operation modes.
Attempt all questions, Each carry 1 marks. Total Marks 50
Part A Total Marks 10
Q.No Questions Marks CO BL PO Unit DL
1 ISA Stands for….. 1 1 1 1 1
2 CISC Stands for….. 1 3 1 5 1
3 RISC Stands for….. 1 3 1 5 1
4 DMA stands for 1 5 1 7 1
5 The address in the main memory is known as - 1 1 1 2 1
6 Which of the following format is used to store data? 1 1 1 2 1
(a) Decimal (b) Octal (c) BCD (d) Hexadecimal
7 Which of the following memory of the computer is used to 1 1 1 2 1
speed up the computer processing?
(a) Cache memory(b) RAM (c) ROM (d) PRN DRIVE
8 Computer address bus is - 1 1 1 2 1
9 Register is a group of --------. 1 1 1 2 1
10 Who developed the basic architecture of computer? 1 1 1 1 1
Part B Attempt all questions, Each carry 3 marks Total Marks 15
Q.No Questions Marks CO BL PO Unit DL
11 Define address sequencing ? 3 2 1 4 1
12 Differentiate between Computer Organization and Computer 3 1 4 1 2
Architecture ?
13 Explain Instruction format ? 3 3 2 5 2
14 Differentiate between RISC and CISC ? 3 3 4 5 2
15 Differentiate between Assembly Language and Machine 3 2 4 3 2
Language ?
Part C Attempt all questions, Each carry 5 marks Total Marks 25
Q.No Questions Marks CO BL PO Unit DL
16 Define addition and subtraction algorithm ? 5 4 1 6 1
17 Explain Stack organization ? OR 5 3 4 5 3
Explain Vector processing
18 Explain DMA ? OR 5 5 2 7 2
Explain asynchronous data transmission ?
19 Explain Instruction Cycle ? 5 1 2 2 2
20 Explain RTL? OR 5 1 2 2 2
Explain Bus and Memory Transfer ?
BL : Bloom’s Taxonomy Levels
(1- Remembering, 2- Understanding, 3 – Applying, 4 – Analyzing, 5 – Evaluating, 6 - Creating)
CO : Course Outcomes
PO : Program Outcomes
PI : Performance Indicator
DL : Difficulty level (Low-1, Medium-2, High-3)
GOVERNMENT POLYTECHNIC, KOTDWAR
Test 2 TERM (2023-24) Summer
Total Duration (HH:MM): 1:30
Computer System Organization & Architecture
Maximum Marks: 50
Course Name: Computer System Organization & Architecture Program Name- CSE(IV SEM)
Course Outcomes (CO):
1. Students will be
All question compulsory. Total Marks 30
Part A Total Marks 5
Q.No Attempt all questions, Each carry 1 marks. Marks CO BL PO Unit DL
1 ISA Stands for….. 1
2 CISC Stands for….. 1
3 RISC Stands for….. 1
4 DMA stands for 1
5 The address in the main memory is known as - 1
Part B Attempt all questions, Each carry 3 marks Total Marks 15
Q.No Questions Marks CO BL PO Unit DL
11 Define Addition and subtraction algorithm ? 3
12 Define asynchronous data transmission ? 3
13 Differentiate between RISC and CISC ? 3
14 Define is input-output interface ? OR 3
15 Define are Peripheral devices ? write 3 Peripheral devices name. 3
Part C Attempt all questions, Each carry 5 marks Total Marks 10
Q.No Questions Marks CO BL PO Unit DL
3(a) Explain DMA ? 5
3(b) Explain Stack organization ? OR 5
Explain is Vector processing ?
BL : Bloom’s Taxonomy Levels
(1- Remembering, 2- Understanding, 3 – Applying, 4 – Analyzing, 5 – Evaluating, 6 - Creating)
CO : Course Outcomes
PO : Program Outcomes
PI : Performance Indicator
DL : Difficulty level (Low-1, Medium-2, High-3)
