Homework #8 Solutions – Computer Architecture Exercises

Note: All CLO’s in this problem set tie to ABET program-level criterion a.

MIPS Pipeline Architecture: On your answer sheet, fill in the instruction data and check the control lines
that are active. Remember that you ONLY turn in your answer sheet.
• Problem 1: (CLO 1—Comp. Arch.) On your answer sheet, fill in the data values for add $t2,$t0,$t1. Assume that $t0
contains 0x0000 0011 and $t1 contains 0x0000 002c. This will enable you to fill in the numerical data on your answer sheet.
Remember to check the five (5) control lines which are active in the control line list on your answer sheet.

• Problem 2: (CLO 1—Comp. Arch.) On your answer sheet, fill in the data values for and $t9,$t8,$t7. Assume that $t7
contains 0x00ff 0812 and $t8 contains 0xfe77 4956. This will enable you to fill in the numerical data on your answer sheet.
Remember to check the five (5) control lines which are active in the control line list on your answer sheet. Also, remember
that AND is a bitwise logic function (i.e., AND bit 1 of the two operands together, store the result in bit 1 of the destination,
and do the same for bit 2, bit 3, etc.).

• Problem 3: (CLO 1—Comp. Arch.) On your answer sheet, fill in the data values for lw $t0,16($t1). Assume that $t1
contains 0x1001 0248, and that the data memory location contains 0x7a61394f. This will enable you to fill in the numerical
data on your answer sheet. Remember to check the six (6) control lines which are active in the control line list on your
answer sheet.

• Problem 4: (CLO 1—Comp. Arch.) On your answer sheet, fill in the data values for sw $t2,32($t3). Assume that $t3
contains 0x1001 000f, and that $t2 contains 0x000044e3. This will enable you to fill in the numerical data on your answer
sheet. Remember to check the three (3) control lines which are active in the control line list on your answer sheet.
 2 EE 2310, Homework #8

• Problem 1
Branch

Register Write

M
Op Code Control
U Mem/ALU
Decode
X R l
+4
ADD
Register Mem. Write
ADD
Block Left Branch Branch Mem. Read
[$t0] Shift
Rs 2 dd
[$t1] ALU Srce.
Rt Read
Instr. Data 1 [0x11]
P Address [$t2] ALU Data Read M
C Instr. Rd
Read [0x2c] Address Data U
Bits
Write Data 2 M [0x2] [0x3d ] X
0-31
U Write Data
D t X

Sign ALU
Data
Fn. Code
Instruction Bits 0-15
Extend Control Memory
Memory [0x3d]
Bits 16-20 M ALU Bypass
[$t2 ]
Bits 11-15 U [$t2]
IF/ID
[ $t2 ] [$t2] X
Reg. Dist
Instr. ID/EX EX/MEM [$t2] MEM/WB
Bits
0-31 [ 0x3d ]
add $t2,$t0,$t1
 3 EE 2310, Homework #8

• Problem 2.
Branch

Register Write

M
Op Code Control
U Mem/ALU
Decode
X R l
+4
ADD
Register Mem. Write
ADD
Block Left Branch Branch Mem. Read
[$t8] Shift
Rs 2 dd
[$t7] ALU Srce.
Rt Read
Instr. Data 1 [0xfe77 4956]
P Address [$t9] ALU Data Read M
C Instr. Rd
Read [0x00ff 0812] Address Data U
Bits
Write Data 2 M [0x2c] [0x0077 0812] X
0-31
U Write Data
D t X

Sign ALU
Data
Fn. Code
Instruction Bits 0-15
Extend Control Memory
Memory [0x0077 0812]
Bits 16-20 M ALU Bypass
[$t9 ]
Bits 11-15 U [$t9]
IF/ID
[ $t9 ] [$t9 X
Reg. Dist
Instr. ID/EX EX/MEM [$t9] MEM/WB
Bits
0-31 [0x0077 0812]
and $t9,$t8,$t7
 4 EE 2310, Homework #8

• Problem 3:
Branch

Register Write

M
Op Code Control Mem/ALU
U
Decode Result
X
+4
ADD
Register Mem. Write
ADD
Block Left
Branch Branch Mem. Read
[$t1 ] Shift
Rs 2 dd
[$t0 ] ALU Srce.
Rt Read
Instr. Data 1 [0x1001 0248] [0x7a61 394f]
P Address [$t0] ALU Data Read M
Rd
C Instr. Read Address Data U
Bits Write Data 2 M [0x10 [0x1001 0258] X
[0x10] U Write
D t X Data

Sign ALU
Data
Fn. Code
Instruction Bits 0-15
Extend Control Memory
Memory
Bits 16-20 M ALU Bypass
[$t0]
[$t0] [$t0] U
IF/ID Bits 11-15 [$t0]
X
Reg. Dist
Instr. ID/EX EX/MEM [$t0] MEM/WB
Bits
[0x7a61 394f]
lw $t0,16($t1)
 5 EE 2310, Homework #8

• Problem 4:
Branch

Register Write

M
Op Code Control Mem/ALU
U
Decode Result
X
+4
ADD
Register Mem. Write
ADD
Block Left
Branch Branch Mem. Read
[$t3 ] Shift
Rs 2 dd
[$t2 ] ALU Srce.
Rt Read
Instr. Data 1 [0x1001 000-f]
P Address
ALU Data Read M
Rd
C Instr. Read [0x0000 44e3 Address Data U
Bits Write Data 2 M [0x20 [0x1001 0248] X
[0x20] U Write
D t X Data
[0x0000 44e3

Sign ALU
Data
Fn. Code
Instruction Bits 0-15
Extend Control Memory
Memory
Bits 16-20 M ALU Bypass
Bits 11-15 U
IF/ID
X
Reg. Dist
Instr. ID/EX EX/MEM MEM/WB
Bits

sw $t2,32($t3)