DSDV Lab Manual BEC302

Experiment No. 5: To realize using Verilog Behavioral description:

8:1 mux, 8:3 encoder, Priority encoder

(i) 8:1 mux

Logic Symbol:

Truth Table:

Verilog Code:

module mux8to1(i,sel,y);

input [7:0]i;

input [2:0]sel;

output y;

reg y;

always @(i,sel)

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begin

case(sel)

3'b000:y=i[0];

3'b001:y=i[1];

3'b010:y=i[2];

3'b011:y=i[3];

3'b100:y=i[4];

3'b101:y=i[5];

3'b110:y=i[6];

3'b111:y=i[7];

default:y=3'b000;

endcase

end

endmodule

//TEST BENCH

module mux_TB;

reg [2:0]sel;

reg [7:0]in;

wire Out;

mux8to1 MUX(in,sel,Out);

initial

begin

$monitor ($time,"in=%b,sel=%b,Out=%b",in,sel,Out);

end

initial

begin

in=8'b10101010;

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end

initial

begin

#100 sel=3'b000;

#100 sel=3'b001;

#100 sel=3'b010;

#100 sel=3'b011;

#100 sel=3'b100;

#100 sel=3'b110;

#100 sel=3'b111;

#100 $finish;

end

endmodule

//Output Waveform of 8:1 MUX

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(ii) 8:3 Encoder without Priority

Truth Table:

RTL Schematic:

Verilog Code:

module encoder_without_priority(a_in,en,y_op);

input [7:0]a_in;

input en;

output [2:0]y_op;

reg [2:0]y_op;

always@(a_in,en)

begin

if(en==1)

y_op=3'bzzz;

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else

case(a_in)

8'b00000001:y_op=3'b000;

8'b00000010:y_op=3'b001;

8'b00000100:y_op=3'b010;

8'b00001000:y_op=3'b011;

8'b00010000:y_op=3'b100;

8'b00100000:y_op=3'b101;

8'b01000000:y_op=3'b110;

8'b10000000:y_op=3'b111;

default:y_op=3'bxxx;

endcase

end

endmodule

Test Bench:

module encoder_without_priority_TB();

reg [7:0]in;

reg en;

wire [2:0]out;

encoder_without_priority EWP(in,en,out);

initial

begin

$monitor($time,"in=%b,en=%b,out=%b",in,en,out);

end

initial

begin

en=1;

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#50 en=0;

#100 in=8'b00000001;

#100 in=8'b00000010;

#100 in=8'b00000100;

#100 in=8'b00001000;

#100 in=8'b00010000;

#100 in=8'b00100000;

#100 in=8'b01000000;

#100 in=8'b10000000;

#100 $finish;

end

endmodule

Output Waveform:

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(iii) 8:3 Encoder with Priority

Truth Table:

RTL Schematic:

Verilog Code:

module encoder_with_priority(a_in,en,y_op);

input [7:0]a_in;

input en;

output [2:0]y_op;

reg [2:0]y_op;

always@(a_in,en)

begin

if(en==1)

y_op=3'bzzz;

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else

case(a_in)

8'b00000001:y_op=3'b000;

8'b0000001x:y_op=3'b001;

8'b000001xx:y_op=3'b010;

8'b00001xxx:y_op=3'b011;

8'b0001xxxx:y_op=3'b100;

8'b001xxxxx:y_op=3'b101;

8'b01xxxxxx:y_op=3'b110;

8'b1xxxxxxx:y_op=3'b111;

default:y_op=3'bxxx;

endcase

end

endmodule

Test Bench:

module encoder_withpriority_TB();

reg en;

reg [7:0]in;

wire [2:0]out;

encoder_with_priority EP(in,en,out);

initial

begin

$monitor($time,"in=%b,en=%b,out=%b",in,en,out);

end

initial

begin

en=1;

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#100 en=0;

#100 in=8'b00000001;

#100 in=8'b0000001x;

#100 in=8'b000001xx;

#100 in=8'b00001xxx;

#100 in=8'b00011100;

#100 in=8'b00100011;

#100 in=8'b01000000;

#100 in=8'b10000000;

#100 $finish;

end

endmodule

Output Waveform:

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Experiment no.6: To realize using Verilog Behavioral description

(i) 1:8 Demux

Truth Table:

Logic Diagram:

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Verilog code:

module Demux(d,s,y);

input d;

input [2:0]s;

output [7:0]y;

reg [7:0]y;

always @(d or s)

begin

case(s)

3'b000:begin y[0]=d;y[7:1]=0; end

3'b001:begin y[1]=d;y[0]=0; end

3'b010:begin y[2]=d;y[1:0]=0; end

3'b011:begin y[3]=d; y[2:0]=0; end

3'b100:begin y[4]=d; y[3:0]=0;end

3'b101:begin y[5]=d; y[4:0]=0; end

3'b110:begin y[6]=d;y[5:0]=0;end

3'b111:begin y[7]=d;y[6:0]=0; end

//default:y=8'b00000000;

endcase

end

endmodule

Test Bench:

module Demux_TB;

reg d;

reg [2:0]s;

wire [7:0]out;

Demux DM(d,s,out);

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initial

begin

$monitor($time,"d=%b,s=%b,out=%b",d,s,out);

end

initial

begin

d=1;

s=3'b000;

#100 s=3'b001;

#100 s=3'b010;

#100 s=3'b011;

#100 s=3'b100;

#100 s=3'b101;

#100 s=3'b110;

#100 s=3'b111;

#100 $finish;

end

endmodule

Output Waveforms:

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(ii) 3:8 Decoder

Verilog Code:

module decoder_three_to_eight(in,out);

input [3:0]in;

output [7:0]out;

reg [7:0]out;

always@(in)

begin

case(in)

3'b000:out[0]=1;

3'b001:out[1]=1;

3'b010:out[2]=1;

3'b011:out[3]=1;

3'b100:out[4]=1;

3'b101:out[5]=1;

3'b110:out[6]=1;

3'b111:out[7]=1;

default:out=8'bxxxxxxxx;

endcase

end

endmodule

Test bench:

module decoder_TB();

reg [3:0]in;

wire [7:0]out;

decoder_three_to_eight DEC(in,out);

initial

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begin

monitor($time,"in=%b,out=%b",in,out);

end

initial

begin

in=3'b000;

#100 in=3'b001;

#100 in=3'b010;

#100 in=3'b011;

#100 in=3'b100;

#100 in=3'b101;

#100 in=3'b110;

#100 in=3'b111;

end

endmodule

Output Waveform:

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(iii) 2-bit Comparator:

Logic Symbol:

Truth Table:

Logic Equations:

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Verilog code:

module Comparator2bit(a,b,altb,aeqb,agtb);

input [1:0]a,b;

output altb,aeqb,agtb;

reg altb,aeqb,agtb;

always @(a,b)

begin

altb=0;aeqb=0;agtb=0;

if(a>b)

agtb=1;

else if(a<b)

altb=1;

else

aeqb=1;

end

endmodule

Test bench:

module comparator2_TB();

reg [1:0]a,b;

wire altb,aeqb,agtb;

Comparator2bit COM(a,b,altb,aeqb,agtb);

initial

begin

$monitor($time,"a=%b,b=%b,altb=%b,aeqb=%b,agtb=%b",a,b,altb,aeqb,agtb);

end

initial

begin

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a=2'b00;

b=2'b01;

#100 a=2'b10;

b=2'b00;

#100 a=2'b11;

b=2'b11;

#100 $finish;

end

endmodule

Output waveform:

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Experiment No:7

Aim: To realize using Verilog Behavioral description:

(i) JK Flip-flop:

RTL Schematic:

Truth Table:

Verilog Code:

module JK_FF(jk,clk,rst,q,qb);

input [1:0]jk;

input clk,rst;

output q,qb;

reg q,qb;

always @(posedge clk)

begin

if(rst==1)

begin

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q=0;

qb=1;

end

else

begin

case(jk)

2'b00:begin q=q;qb=qb;end

2'b01:begin q=0;qb=1;end

2'b10:begin q=1;qb=0;end

2'b11:begin q=1;qb=1;end

endcase

end

end

endmodule

Test Bench:

module JK_FF_TB;

reg [1:0]jk;

reg clk,rst;

wire q,qb;

JK_FF jkff(jk,clk,rst,q,qb);

initial

begin

$monitor($time,"jk=%b,clk=%b,rst=%b,q=%b,qb=%b",jk,clk,rst,q,qb);

end

initial

begin

clk=1'b0;

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forever #10 clk=~clk;

end

initial

begin

rst=1'b1;

#10 rst=1'b1; jk=2'b11;

#20 rst=1'b0; jk=2'b00;

#20 rst=1'b0;jk=2'b01;

#20 rst=1'b0;jk=2'b10;

#20 rst=1'b0;jk=2'b11;

#50 $finish;

end

endmodule

Output Waveforms:

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(ii) SR Flip-flop:

RTL Schematic:

Truth Table:

Verilog Code:

module SR_FF(sr,clk,rst,q,qb);

input [1:0]sr;

input clk,rst;

output q,qb;

reg q,qb;

always @(posedge clk)

begin

if(rst==1)

begin

q=0;qb=1;

end

else

begin

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case(sr)

2'b00: begin q=q;qb=qb;end

2'b01:begin q=0;qb=~q; end

2'b10:begin q=1; qb=~q; end

2'b11:begin q=1’bx;qb=1’bx; end

endcase

end

end

endmodule

Test Bench:

module SR_FF_TB;

reg [1:0]sr;

reg clk,rst;

wire q,qb;

SETRESET_FF srff(sr,clk,rst,q,qb);

initial

begin

$monitor($time,"sr+%b,clk=%b,rst+%b,q=%b,qb=%b",sr,clk,rst,q,qb);

end

initial

begin

clk=1'b0;

forever #10 clk=~clk;

end

initial

begin

rst=1'b1;

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#10 rst=1'b1; sr=2'b11;

#20 rst=1'b0; sr=2'b00;

#20 rst=1'b0; sr=2'b01;

#20 rst=1'b0;sr=2'b10;

#20 rst=1'b0; sr=2'b11;

#50 $finish;

end

endmodule

Output Waveform:

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(iii) T Flip-flop:

RTL Schematics:

Truth Table:

Verilog Code:

module T_FF(t,clk,rst,q,qb);

input t,clk,rst;

output q,qb;

reg q,qb;

always@(posedge clk)

begin

if(rst==1)

begin

q=0;qb=1;end

else

begin

if(t==0)begin

q=q;

qb=~q;

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end

else

begin

q=~q; qb=~qb;end

end

end

endmodule

Test bench:

module T_FF_TB;

reg t,clk,rst;

wire q,qb;

SR_FF tff(t,clk,rst,q,qb);

initial

begin

$monitor($time,"t=%b,clk=%b,rst=%b,q=%b,qb=%b",t,clk,rst,q,qb);

end

initial

begin

clk=1'b0;

forever #10 clk=~clk;

end

initial

begin

rst=1;

#10 rst=1;

t=1'b0;

#20 rst=0;

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t=1'b0;

#20 rst=0;

t=1'b1;

#50 $finish;

end

endmodule

Output Waveform:

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(iv) D-Flip flop:

RTL Schematic:

Truth Table:

Verilog Code:

module D_FF(d,rst,clk,q,qb);

input d,rst,clk;

output q,qb;

reg q,qb;

always @(posedge clk)

begin

if(rst==1)

begin

q=0;

qb=1;

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end

else

begin

q=d;

qb=~d;

end

end

endmodule

Test Bench:

module D_FF_TB;

reg D,rst,clk;

wire q,qb;

D_FF dff(D,rst,clk,q,qb);

initial

begin

$monitor($time,"D=%b,rst=%b,clk=%b,q=%b,qb=%b",D,rst,clk,q,qb);

end

initial

begin

clk = 1'b0;

forever #10 clk = ~clk ;

end

initial

begin

rst = 1'b1;

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#10;

rst=1'b1;

#10

rst = 1'b0;

D = 1'b0;

#40;

D = 1'b1;

#40;

$finish ;

end

endmodule

Output Waveforms:

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Experiment No.8: To realize Counters-up/down(BCD and Binary) using Verilog

Behavioral description.

(i) Binary UP/DOWN counter:

Truth table:

Verilog code:

module Binary_counter(clk,rst,updown,count);

input clk,rst,updown;

output [3:0]count;

reg [3:0]count=0;

always @(posedge (clk)or posedge(rst))

begin

if(rst==1)

count<=0;

else

begin

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if(updown==1)//UP mode is selected

begin

if(count==15)

count<=0;

else

count=count+1;

end

if(updown==0)//DOWN Mode is selected

begin

if(count==0)

count<=15;

else

count=count-1;

end

end

end

endmodule

Test Bench:

module Binary_counter_TB;

reg clk,rst,updown;

wire [3:0]count;

Binary_counter BINC(clk,rst,updown,count);

initial

begin

clk=1'b0;

forever #10 clk=~clk;

end

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initial

begin

$monitor($time,"clk=%b,rst=%b,updown=%b,count=%b",clk,rst,updown,count);

end

initial

begin

rst=0;

updown=1'b1;

//#10 rst=1;

#310 updown=1'b0;

//count=4'b0000;

//#20 rst=0;updown=1'b0;

#800 $finish;

end

endmodule

Output Waveform:

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(ii) BCD UP/DOWN Counter:

Truth Table:

Verilog Code:

module BCD_Counter(clk,rst,count);

input clk,rst;

output [3:0]count;

reg [3:0]count;

always@(posedge(clk))

begin

if(rst)

count=4'd0;

else if(count<4'd9)

count<=count+4'd1;

else

count=0;

end

endmodule

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Test Bench:

module BCD_counter_TB;

reg clk,rst;

wire [3:0]count;

BCD_Counter BCD(clk,rst,count);

initial

begin

clk=1'b0;

forever #10 clk=~clk;

end

initial

begin

$monitor($time,"clk=%b,rst=%b,count=%b",clk,rst,count);

end

initial

begin

rst=0;

#300 $finish;

end

endmodule

Output Waveform:

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