F R A U N H O F E R re s ear c h I n s t i t u t ion for M i c ro s y s t em s an d So l i d S tat e Te c hno l o g ie s E M F T

1 2 3

1 Ultra-thin silicon device wafer From ultra-thin silicon

2 25 μm microcontroller chip in
flexible foil package dies to flexible chip foil
packages
3 Technology example for
plasma dicing

Applications Technical Innovation

Fraunhofer Research Institution
for Microsystems and Lower height for chip packages is crucial Fraunhofer EMFT follows a so-called
Solid State Technologies EMFT for electronic components in mobile and hybrid integration approach: We combine
wearable applications. Furthermore, the ca- ultra-thin and flexible silicon ICs with film
Hansastrasse 27 d pability to bend and mount chip packages based circuitries and further thin elec-
80686 München onto curved surfaces or into application tronic components. For the realization
Phone: +49 89 54 75 90 specific formed housings will allow for the of the complete flex integration process
Fax: +49 89 54 75 95 50 distribution of electronic and sensing sys- Fraunhofer EMFT uses and offers its
E-Mail: [email protected] tems in industrial production environments long-term experience and technological
as well as in potentially any object of our equipment for:
daily life, e.g. • Advanced wafer thinning (grinding,
Project Manager: • Healthcare wet or dry etching, CMP polishing)
Christof Landesberger • Wearable electronics • Thin wafer handling, temporary
Christof.Landesberger@ • Sensors on curved surfaces bonding, specific focus on mobile
emft.fraunhofer.de • Robotics electrostatic carriers (e-carrier)
• Smart packaging • Die separation: here we propose
www.emft.fraunhofer.de • Internet of things-applications the patented “dicing-by-thinning”
concept, specific target is plasma
dicing of ultra-thin wafers using
e-carrier substrates for wafer handling
 4 5

• Ultra-fine line patterning of metal State of Development Outlook

wiring on flexible films (PET, PEN, PI)
by roll-to-roll processing allowing The “Dicing-by-Thinning” concept was The technological concept allows for subse-
line / space geometries of 20 µm used to prepare 25 µm thin microcont- quent adaptation to a continuous roll-
• High accuracy die bonding by roller devices, front side chip grooves were to-roll process for chip embedding in
1 automated equipment or 2
performed by standard sawing process, film substrates. This would enable extre-
self-alignment techniques wafer thinning was done by grinding mely thin and flexible packages for any
• Roll-to-roll and sheet-to-sheet (DISCO DFG 8540) and chemical mecha- type of functional IC devices in high
processes for printing, lithography, nical polishing (CMP, Avanti). volume and at low cost. Fraunhofer
metallization, etching, laser treatment, EMFT intends to foster cooperative works
electroplating, lamination, coating, For preparation of the first „Thin Chip with industrial partners for equipment
electrical testing and others Foil Package“ demonstrators we used development and product applications.
polyimide films, which were tempora- We consider our concept for a “Thin
According to our patented “Thin Chip Foil rily attached onto silicon carrier wafers. Chip Foil Package” as a key enab-
Package” the ultra-thin dies are placed and This configuration allows to process thin ling technology for many future
embedded in a cavity of a multi-layer film film interconnects and the redistribu- products which require extremely flat
laminate. Thereby the fragile IC is securely tion layer by standard lithographic patter- form factor or mechanical flexibility.
embedded in the center layer of a plane- ning processes and equipment. It also
parallel film package. The foil package allows for preparing a large number of film Funding
represents a fan-out interposer for the I/O packages in parallel. Thin ICs were placed
contact pads of the IC device (see figure on the base film at high alignment accu- Parts of this work were funded by
below). racy (die bonder Panasonic FCB3). Figures the Bayerisches Staatsministerium
2 and 5 show the technological result of a für Wirtschaft, Infrastruktur, Verkehr
set of chip foil packages after separation und Technologie under contract
and removal from the carrier and figure 4 no. VI/3-3622/452/3 and by the
shows a microscopic view on the surface of European Commission under
the finally embedded and electrically inter- contract number 258203 (FP7).
connected ultra-thin microcontroller device.

4 Microscopic view on the surface of the

finally embedded and electrically interconnected
ultra-thin microcontroller device
5 Fan-out Demonstrator of a flexible “Chip Foil
Package”