Model Predictive Critical Soft-Switching Enabling High-Performance Software-Defined Power

Electronics: Converter Configuration, Efficiency, and Redundancy

Liwei Zhou

Submitted in partial fulfillment of the

requirements for the degree of
Doctor of Philosophy
under the Executive Committee
of the Graduate School of Arts and Sciences

COLUMBIA UNIVERSITY

2022
 © 2022

Liwei Zhou

All Rights Reserved

 Abstract
Model Predictive Critical Soft-Switching Enabling High-Performance Software-Defined Power
Electronics: Converter Configuration, Efficiency, and Redundancy
Liwei Zhou

Advanced power electronic techniques are crucial to enable high-performance energy con-
version systems for the applications of various load and source interfaces, e.g., electric vehicle
battery charger, solar power, wind power, motor traction, grid-connection. Also, the improvements
on electrification for energy conversion contributes to the Carbon Neutrality with the reduction
of fuel combustion. The control and design of the power conversion systems largely determine
the efficiency, power density and system cost which typically need specialized design procedures.
Since the types of interfaced energy sources may vary, the corresponding control algorithms and
hardware configurations will be different. Thus, the power electronics system design is conven-
tionally a specific routine based on the desired source and load requirements. Generally speaking,
two main perspectives need to be considered when designing a power conversion system: (1) the
power converter circuitry topology with the corresponding hardware components, e.g., low/high
power circuits design, passive components design; (2) control algorithms and functions design,
e.g., voltage/current control techniques, active/reactive power balancing and adjustment. However,
the repetitive and specific power electronics design procedures for different load/source require-
ments are time-consuming and costly.
This thesis proposes a software-defined power electronics concept to develop a generalized
auto-converter module (ACM) by leveraging variable-frequency critical-soft-switching, model pre-
dictive control techniques and high-performance litz-PCB inductors. The software-defined power
electronics techniques can be applied to various types of electrified load/source applications with-
out the need of repetitive hardware components and software algorithms designing procedures.
The fundamental unit for the generalized concept, auto-converter module, is a type of MPC-based
power module. A hierarchical control architecture is designed to manage the local ACMs and sat-
isfy different load/source energy conversion requirements with high efficiency, high power-density
and high-reconfigurability.
To achieve high-performance for the software-defined power electronics system, several ad-
vanced technologies are developed and integrated including variable-frequency critical-soft-switching,
modular model predictive control, litz-PCB inductor design. Firstly, a variable-frequency critical-
soft-switching technique is developed to adjust the switching frequency for the zero-voltage soft-
switching. Doing so, the switching losses can be largely reduced with high efficiency. Secondly,
the critical-soft-switching inductor is designed based on litz-PCB winding structure and neural
network model to optimize the inductor losses and reduce the volume for the application of high
frequency and large current ripple. Thirdly, a modular model predictive control method is de-
signed for each of the local ACM to improve the dynamic performance and attenuate the oscil-
lation caused by the variable frequency operation. Lastly, a hierarchical control architecture is
developed to generalize the software-defined power electronics with multi-layer structure, central
control layer, local module control layer and application layer. The hierarchical control archi-
tecture can be widely applied to different types of load/source interfaces, e.g., single/three-phase
grid-connected inverters, motor traction inverter, battery charger, solar energy and so on. Lever-
aging the hierarchical control architecture and software-defined power electronics, the repetitive
power converter hardware components and software algorithms design procedures can be simpli-
fied and standardized. Also, for different power converter applications, the efficiency and power
density are both improved with better dynamic performance.
 Table of Contents

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xviii

Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Motivations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: Variable-Frequency Critical-Soft-Switching for Modular Power Converters . . . 9

2.1 Critical soft switching principles for DC/DC converter . . . . . . . . . . . . . . . . 12

2.2 Variable-switching constant-sampling frequency critical-soft-switching control . . 16

2.2.1 Frequency Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.2.2 Model Predictive Controller . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Chapter 3: High Performance Inductor Design Enabling Critical-Soft-Switching . . . . . . 37

3.1 Theoretical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.1 Critical Soft Switching Parameters . . . . . . . . . . . . . . . . . . . . . . 40

i
 3.1.2 Iterative Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2 Structural Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.1 Coil Structure Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.2 Core Structure Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.2.3 Neural Network Modeling of Litz/Solid PCB Structure . . . . . . . . . . . 64

3.3 Prototyping Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.3.1 Prototype Finalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.3.2 Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.3.3 Observations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Chapter 4: Model Predictive Control for Modular Power Converters . . . . . . . . . . . . . 79

4.1 𝐿𝐶 𝐿 System Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.1.1 DC/AC 𝐿𝐶 𝐿 Plant Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.1.2 Zero-Sequence Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.2 Control Structures Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.2.1 PI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

4.2.2 PI Control with Notch Filter . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.3 Cascaded PI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.4 Cascaded Modular Model Predictive Control . . . . . . . . . . . . . . . . 89

4.3 Optimal Control Design for Resonance Damping and Dynamic Performance . . . . 93

4.3.1 Control Plant Model Analysis . . . . . . . . . . . . . . . . . . . . . . . . 93

4.3.2 Mechanism of Inner-loop MMPC for Active Damping . . . . . . . . . . . 101

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 4.3.3 Cascaded Control Design for Dynamic Performance . . . . . . . . . . . . 102

4.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4.4.1 State Estimation Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

4.4.2 Steady State Common Mode Test . . . . . . . . . . . . . . . . . . . . . . 109

4.4.3 Dynamic and Stability Performance Test . . . . . . . . . . . . . . . . . . . 109

4.4.4 Comparison with the State of Art . . . . . . . . . . . . . . . . . . . . . . . 110

4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Chapter 5: Hierarchical Software-Defined Control Architecture with MPC-Based Power

Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.1 System Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.1.1 Local Power Module Modeling . . . . . . . . . . . . . . . . . . . . . . . . 115

5.1.2 Application Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.2 Hierarchical Control Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.2.1 Single-Phase Grid Interface Control . . . . . . . . . . . . . . . . . . . . . 123

5.2.2 Three-Phase Grid Interface Control . . . . . . . . . . . . . . . . . . . . . 129

5.2.3 Motor Drive Interface Control . . . . . . . . . . . . . . . . . . . . . . . . 130

5.3 Merits and Validations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.3.1 Reconfigurability with Unified Power Modules . . . . . . . . . . . . . . . 132

5.3.2 Improved Dynamic Performance with MPC-Based Local Layer Power Mod-
ule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5.3.3 Non-Isolated Applications with Central Layer Zero-Sequence Control . . . 136

5.3.4 Robust MPC Free of Application Model Parameters Influence . . . . . . . 136

5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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Chapter 6: Design Case of Three-Phase Grid-Tied Inverter with High Efficiency and Power
Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

6.1 Non-Isolated System and Critical Soft Switching . . . . . . . . . . . . . . . . . . 142

6.1.1 Non-isolated System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6.1.2 Critical Soft Switching Analysis . . . . . . . . . . . . . . . . . . . . . . . 142

6.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.2.1 Central Level Grid Current/Zero-Sequence Voltage Control . . . . . . . . . 146

6.2.2 Local Level Model Predictive Control . . . . . . . . . . . . . . . . . . . . 149

6.2.3 Local Level Luenberger Observer . . . . . . . . . . . . . . . . . . . . . . 152

6.2.4 Local Level Variable Frequency Control . . . . . . . . . . . . . . . . . . . 154

6.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

6.3.1 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.3.2 State Estimation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

6.3.3 Steady State Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

6.3.4 Model Predictive Control Transient Results . . . . . . . . . . . . . . . . . 168

6.3.5 Efficiency and Power Density Results . . . . . . . . . . . . . . . . . . . . 168

6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

Chapter 7: Design Case of MPC-Based Regulated Third Harmonic Injection for Zero-
Sequence Stabilized 𝐿𝐶 𝐿 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . 170

7.1 System Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

7.1.1 DC/AC 𝐿𝐶 𝐿 Converter Modeling . . . . . . . . . . . . . . . . . . . . . . 172

7.1.2 Common Mode Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 175

7.2 Control Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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 7.2.1 Phase-locked-loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

7.2.2 Central Level Output Current Control . . . . . . . . . . . . . . . . . . . . 178

7.2.3 Zero-sequence Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . 179

7.2.4 Local Level Per Phase LC Filter MPC . . . . . . . . . . . . . . . . . . . . 180

7.2.5 Modular MPC Concept Based on Software-Defined Architecture . . . . . . 180

7.3 Regulated Third Harmonic Injection . . . . . . . . . . . . . . . . . . . . . . . . . 183

7.3.1 Third Harmonic Sinusoidal Injection (Sin-RTHI) . . . . . . . . . . . . . . 183

7.3.2 Triangular Space Vector Injection (Tri-RTHI) . . . . . . . . . . . . . . . . 184

7.3.3 Advantages of Zero-sequence Controlled RTHI . . . . . . . . . . . . . . . 185

7.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

7.4.1 Third Harmonic Injection Test . . . . . . . . . . . . . . . . . . . . . . . . 188

7.4.2 Leakage Current Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Conclusion or Epilogue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

Chapter 8: Conclusion and Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

8.2 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

8.2.1 Journals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

8.2.2 International Conferences . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

8.2.3 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

v
 List of Figures

1.1 Degree of electrification: typical fuel efficiency improvement and electric traction
motor power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2 Global electric passenger car stock from 2010 to 2020. . . . . . . . . . . . . . . . 3

1.3 (a) Different applications of power electronics and (c) the typical power converter
structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 The design procedures for (a) conventional power electronics system and (c) software-
defined power electronics architecture. . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 The negative inductor current paths of DC/DC Buck converter. . . . . . . . . . . . 12

2.2 Gate signals and inductor current for critical soft switching. . . . . . . . . . . . . . 12

2.3 The critical soft switching operation regions for different devices. . . . . . . . . . . 15

2.4 The thermal, soft switching, frequency and device current constraints of 𝑓𝑠𝑤 with
the function of duty and 𝐼 𝐿,𝑎𝑣𝑒 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.5 The feasible trajectories of maximum frequency control method with certain duty. . 19

2.6 Discrete frequency controller with equally segmented bandwidth. . . . . . . . . . . 20

2.7 Equally segmented switching frequency with the function of duty cycle at the rated
load current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.8 Variable PWM carrier signals and constant sampling signals of the VSCS-MPC
method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.9 MPC optimization search tree implementing process. . . . . . . . . . . . . . . . . 23

2.10 Explicit MPC piecewise affine regions with prediction horizon of 5. . . . . . . . . 23

vi
2.11 Proposed variable-switching constant-sampling frequency critical-soft-switching
Model-predictive control diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.12 The waveforms of PWM carriers and trigger of the sampling and control. . . . . . 24

2.13 (a) Inductor current and output voltage waveforms and (b) the zoomed waveforms
with output current load step from 10A to 15A based on VSCS-MPC of current load. 26

2.14 (a) Inductor current and output voltage and (b) the zoomed waveforms with output
current load step from 15A to 10A based on VSCS-MPC of current load. . . . . . . 26

2.15 Inductor current and output voltage waveforms with output voltage reference step
from 100V to 120V based on VSCS-MPC of current load. . . . . . . . . . . . . . . 27

2.16 (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 100V to 80V based on VSCS-MPC of current load. . . . . . . 27

2.17 (a) Inductor current, output voltage and (b) zoomed waveforms with inductor cur-
rent reference step from 5A to 8A based on VSCS-MPC of resistive load. . . . . . 27

2.18 (a) Inductor current, output voltage and (b) zoomed waveforms with inductor cur-
rent reference step from 8A to 5A based on VSCS-MPC of resistive load. . . . . . 28

2.19 (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 50V to 80V based on VSCS-MPC of resistive load. . . . . . . 28

2.20 (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 80V to 50V based on VSCS-MPC of resistive load. . . . . . . 28

2.21 (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 100V to 120V based on PI controller. . . . . . . . . . . . . . . 29

2.22 (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 100V to 80V based on PI controller. . . . . . . . . . . . . . . . 29

2.23 VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from
1A to 4A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.24 VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from
4A to 1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

vii
2.25 VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from
6A to 9A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.26 VSCS-MPC of resistive load: (a) Output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from
9A to 6A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.27 VSCS-MPC of resistive load: (a) Output voltage, inductor current, output current
experimental and (b) zoomed waveforms with output voltage reference step from
50V to 80V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.28 VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with output voltage reference step from
80V to 50V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.29 PI of resistive load: (a) output voltage, inductor current, output current experi-
mental and (b) zoomed waveforms with output voltage reference step from 50V to
80V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.30 PI of resistive load: (a) output voltage, inductor current, output current experi-
mental and (b) zoomed waveforms with output voltage reference step from 80V to
50V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.31 Soft switching performance of upper switch during turn-on and turn-off transients. . 32

2.32 Testbench of multi-phase DC/DC converter. . . . . . . . . . . . . . . . . . . . . . 32

2.33 Efficiency curve comparison of critical soft switching and hard switching. . . . . . 33

2.34 The switching loss break down distribution comparison of (a) hard switching and
(b) soft switching at 1kW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1 The inductor design for non-isolated (1) DC/DC and (2) three-phase DC/AC appli-
cations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 Gate signals and inductor current for critical soft switching. . . . . . . . . . . . . . 41

3.3 The distribution of (a) wire (b) PCB and (c) foil coils in E core window. . . . . . . 45

3.4 Round wire winding inductor design flowchart. . . . . . . . . . . . . . . . . . . . 48

3.5 (a) 3D litz PCB routing method, 3D view of (b) separated and (c) integrated routing
example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

viii
3.6 Four types of litz PCB routing structures with different strand number and trace
width: (a) Litz PCB 4×7 Strands, 16mils trace width (b) Litz PCB 4×10 Strands,
8mils trace width (c) Litz PCB 4×2×5 Strands, 8mils trace width and (d) Litz PCB
4×16 Strands, 5mils trace width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.7 Comparison of resistance factor with different frequencies (a) for a single PCB with
different combinations of strand number and trace width (b) for different stacked
number of the desired 4x10 strand type of litz PCB and solid PCB structures. . . . 55

3.8 3D view of a four layer, 40 strand litz PCB design. . . . . . . . . . . . . . . . . . . 58

3.9 (a) Top layer (b) second layer (c) third layer and (d) bottom layer of litz PCB design
in top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.10 Four types of core structures: (a) EE core (b) EI core (c) II core and (d) EA core. . 60

3.11 The analysis of magnetic flux paths for different core structures. . . . . . . . . . . 61

3.12 Analysis of EE/EI core inductor performances with different winding distributions. 63

3.13 Four-layer neural network model for resistance factor of the proposed (a) litz and
(b) solid PCB winding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.14 Training and testing losses of the (a) litz and (b) solid PCB winding neural network
model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.15 (a) Litz PCB and (b) solid PCB winding prototypes. . . . . . . . . . . . . . . . . . 67

3.16 Resistance factor measurements of different layers of litz/solid PCB windings and
round normal/litz wires with different frequencies. . . . . . . . . . . . . . . . . . . 69

3.17 Proposed inductor prototypes: (a) EE, 10 turns, litz wire (b) EE, 6 turns, litz wire
(c) EE, 4 turns, litz PCB (d) EE, 4 turns, solid PCB (e) EA, 5 turns, litz PCB (f)
EA, 5 turns, solid PCB (g) EI, 4 turns, litz PCB (h) EI, 4 turns, Solid PCB (i) II, 8
turns, Litz PCB (j) II, 8 turns, Solid PCB. . . . . . . . . . . . . . . . . . . . . . . 69

3.18 Testbench for inductor loss measurement. . . . . . . . . . . . . . . . . . . . . . . 71

3.19 (a) Inductor voltage, inductor current and output voltage and (b) the zoomed wave-
forms at 500kHz switching frequency, 500V input voltage and 0.5 duty cycle. . . . 71

3.20 Thermal behaviors of the designed and commercial inductors at 500kHz, 50A peak
current: (a) EE core, litz PCB (b) EA core, solid PCB (c) SER inductor (d) AGM
inductor (e) AGP-332 inductor (f) AGP-562 inductor (g) WE-0068 inductor (h)
WE-1022 inductor (i) DMT2-20 inductor. . . . . . . . . . . . . . . . . . . . . . . 72

ix
3.21 Comparisons of Power losses with volume and cost among the proposed prototypes
and commercial products: (a) Losses and volume comparison (b) Losses and cost
comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.22 Comparison of inductor core and copper losses break down at 100kHz, 500kHz
and 1MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.23 Ratings of performance for four of the desired inductor prototypes. . . . . . . . . . 75

4.1 Non-isolated 𝐿𝐶 𝐿 inverter with low leakage current. . . . . . . . . . . . . . . . . 81

4.2 Equivalent 𝐿𝐶 𝐿 circuit with consideration of ESR. . . . . . . . . . . . . . . . . . 81

4.3 𝐿𝐶 𝐿 plant model with consideration of ESR. . . . . . . . . . . . . . . . . . . . . 81

4.4 𝐿𝐶 𝐿 plant model transfer function bode plots with consideration of ESR. . . . . . 82

4.5 Leakage current bypassing paths with the modified non-isolated topology. . . . . . 86

4.6 Equivalent common mode circuit of the modified non-isolated topology. . . . . . . 86

4.7 Control diagrams of the (a) PI (b) notch filtered PI (c) cascaded PI and (d) active-
damping MPC for the transformerless 𝐿𝐶 𝐿 inverter. . . . . . . . . . . . . . . . . . 87

4.8 Plant models of the (a) PI (b) notch filtered PI (c) cascaded PI and (d) active-
damping MPC for the transformerless 𝐿𝐶 𝐿 inverter. . . . . . . . . . . . . . . . . . 94

4.9 Typical LQR control diagram with delay compensation. . . . . . . . . . . . . . . . 95

4.10 Comparison of bode plots for three control strategies (a) from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 and
(b) from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑣 𝐶 𝑓 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4.11 Bode plots for cascaded PI control from (a) 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 and (b) 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑣 𝐶 𝑓
with the inner loop 𝐾 𝑝,𝑣𝐶 𝑓 gain swept from 1 to 625. . . . . . . . . . . . . . . . . 96

4.12 The cascaded MMPC control parameter design flow chart. . . . . . . . . . . . . . 97

4.13 The bode plots of the PI control, notch filtered PI control and cascaded MMPC
methods transfer functions from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 with the cascaded MMPC (a)
weighing factor Q/R swept from 100 to 800 at the 𝐾 𝑝 gain of 10 and (b) 𝐾 𝑝 gain
swept from 10 to 40 at the Q/R of 400. . . . . . . . . . . . . . . . . . . . . . . . . 98

x
4.14 The step responses of the cascaded MMPC close loop transfer function from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟
to 𝑖 𝐿 𝑓 𝑔 with (a) weighing factor Q/R swept from 100 to 800 and (b) 𝐾 𝑝 gain swept
from 10 to 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

4.15 The zeros and poles plots of the cascaded MMPC from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 with (a)
weighing factor Q/R swept from 100 to 800 and (b) 𝐾 𝑝 gain swept from 10 to 40. . 99

4.16 Comparison of the experimentally captured estimation and measurement of (a)

switch side inductor current (b) output capacitor voltage and (c) grid side inductor
current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

4.17 Steady state waveforms of switch side inductor current, output capacitor voltage,
grid side inductor current and DC bus voltage. . . . . . . . . . . . . . . . . . . . . 105

4.18 Steady state waveforms of three-phase grid voltage, leakage current, DC bus volt-
age and zero-sequence grid voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.19 (a) Transient and (b) zoomed transient waveforms of switch side inductor current,
output capacitor voltage, grid side inductor current and DC bus voltage with 𝑖 𝐿 𝑓 𝑔,𝑞
from 3A to 10A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.20 Cascaded MMPC transient captured ADC readings of grid side inductor current 𝑞
component (a) from 2A to 8A and (b) from 8A to 2A with 𝐾 𝑝 gain of 10, 20, 30
and 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

4.21 Comparison of PI, notch filtered PI and MMPC transient captured ADC readings of
(a) grid side inductor current 𝑞 component from 2A to 8A and (b) zoomed waveforms.107

4.22 Comparison of PI and MMPC transient captured ADC readings of (a) grid side
inductor current 𝑞 component from 8A to 2A and (b) zoomed waveforms. . . . . . 107

4.23 Waveforms comparison of inductor current, output capacitor voltage, grid current
and DC bus voltage for (a) PI control with 𝐾 𝑝 of 20 (b) notch filtered PI control
with 𝐾 𝑝 of 20 (c) PI control with 𝐾 𝑝 of 2 (d) MMPC control with 𝐾 𝑝 of 20 and (e)
cascaded PI control with 𝐾 𝑝 of 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.1 Hirarchical control architecture with MPC-based power module. . . . . . . . . . . 114

5.2 Local MPC-based power module. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.3 (a) Single-phase grid (b) three-phase grid and (c) three-phase motor traction topo-
logical applications of the multi-layer control architecture. . . . . . . . . . . . . . 122

xi
5.4 Equivalent common-mode circuit of the formulated (a) Single-phase grid (b) three-
phase grid and (c) three-phase motor inverters. . . . . . . . . . . . . . . . . . . . . 122

5.5 (a) Single-phase and (b) three-phase PLL control blocks. . . . . . . . . . . . . . . 123

5.6 Single-phase grid application of the hierarchical architecture. . . . . . . . . . . . . 124

5.7 Three-phase grid application of the hierarchical architecture. . . . . . . . . . . . . 125

5.8 Motor drive application of the hierarchical architecture. . . . . . . . . . . . . . . . 126

5.9 Grid service control blocks in the central control for single/three-phase grid inter-
faced renewable energy applications. . . . . . . . . . . . . . . . . . . . . . . . . . 127

5.10 Prototype of the hierarchical control structure. . . . . . . . . . . . . . . . . . . . . 132

5.11 (a) Single-phase and (b) Three-phase grid interfaces grid current, capacitor voltage,
inductor current and DC voltage steady state waveforms. . . . . . . . . . . . . . . 133

5.12 Captured ADC readings of motor (a) speed step from 0 to 470 rpm and (b) torque
step from 5 to -5 Nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

5.13 (a) Single-phase and (b) Three-phase grid interfaces grid current, capacitor voltage,
inductor current and DC voltage transient waveforms. . . . . . . . . . . . . . . . . 134

5.14 Captured ADC readings of grid current steps from (a) 2A to 8A and (b) 8A to 2A
for the proposed MPC and conventional PI methods. . . . . . . . . . . . . . . . . . 134

5.15 The comparison of leakage current and common mode voltage for the (a) pro-
posed grid connected topology with zero-sequence voltage control (c) proposed
three-phase grid connected topology without zero-sequence voltage control and
(d) traditional topology without zero-sequence voltage control. . . . . . . . . . . . 135

5.16 The comparison of leakage current, shaft voltage and common mode voltage for the
(a) conventional motor connected topology (b) proposed motor connected topology
with zero-sequence voltage control. . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6.1 Conventional (a) 𝐿 and (b) 𝐿𝐶 𝐿 types of non-isolated inverters. . . . . . . . . . . 141

6.2 Proposed modified non-isolated inverter composed of per phase power modules. . . 141

6.3 Three inductor size comparison for implementing low, medium and high frequency
converters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

xii
6.4 Critical soft switching working principles for DC and AC current modes. . . . . . . 143

6.5 Turn-on and turn-off loss comparison of typical SiC MOSFET C3M0021120K. . . 144

6.6 The critical soft switching operation regions for different devices. . . . . . . . . . . 144

6.7 Proposed control diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

6.8 Equivalent circuit for state space equation. . . . . . . . . . . . . . . . . . . . . . . 148

6.9 MPC optimization search tree implementing process. . . . . . . . . . . . . . . . . 148

6.10 Diagram of the state estimator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

6.11 (a) VDF-CSS and (b) VCF-CSS AC current ripple . . . . . . . . . . . . . . . . . . 152

6.12 Control diagram of power module with VCF-CSS, MPC and estimator. . . . . . . . 154

6.13 Control diagram of power module with VDF-CSS and MPC. . . . . . . . . . . . . 154

6.14 The relationship of PWM carriers and fundamental sampling signals for VDF-CSS. 155

6.15 Hardware prototypes of (a) integrated prototype (b) power board (c) medium fre-
quency inductor and (d) high frequency inductor. . . . . . . . . . . . . . . . . . . 158

6.16 Switching frequency of VCF-CSS and VDF-CSS for (a) medium frequency and
(b) high frequency applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

6.17 Captured experimental readings of sampling measurement in blue lines and esti-
mation in red lines of (a) switch side inductor current (b) capacitor voltage and (c)
grid side inductor current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

6.18 Captured experimental readings of switching frequency in blue lines and grid side
inductor current in red lines of (a) VCF-CSS and (b) VDF-CSS at medium fre-
quency of 40kHz-240kHz with 45𝜇H switch side inductor. . . . . . . . . . . . . . 159

6.19 Captured experimental readings of switching frequency in blue lines and grid side
inductor current in red lines of (a) VCF-CSS and (b) VDF-CSS at high frequency
of 360kHz-1.08MHz with 4.5𝜇H switch side inductor. . . . . . . . . . . . . . . . . 160

6.20 (a) The inductor current, capacitor voltage, grid current and DC bus voltage with
constant switching frequency and (b) zoomed waveforms. . . . . . . . . . . . . . . 160

xiii
6.21 Medium frequency of 40kHz-240kHz with 45𝜇H switch side inductor (a) VCF-
CSS and (b) zoomed steady state waveforms of inductor current, capacitor voltage,
grid current and DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.22 High frequency of 360kHz-1.08MHz with 4.5𝜇H switch side inductor (a) VCF-
CSS and (b) zoomed steady state waveforms of inductor current, capacitor voltage,
grid current and DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

6.23 Medium frequency of 40kHz-160kHz with 45𝜇H switch side inductor (a) VDF-
CSS and (b) zoomed steady state waveforms of inductor current, capacitor voltage,
grid current and DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

6.24 High frequency of 360kHz-1.08MHz with 4.5𝜇H switch side inductor (a) VDF-
CSS and (b) zoomed steady state waveforms of inductor current, capacitor voltage,
grid current and DC bus voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

6.25 The drain-source voltage and current across the upper switch for soft switching
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

6.26 (a) VCF-CSS and (b) zoomed transient waveforms of inductor current, capacitor
voltage and DC bus voltage with a current step of 4A. . . . . . . . . . . . . . . . . 163

6.27 (a) VDF-CSS and (b) zoomed transient waveforms of inductor current, capacitor
voltage and DC bus voltage with a current step of 4A. . . . . . . . . . . . . . . . . 163

6.28 The efficiency curves comparison of VCF-CSS, VDF-CSS and constant frequency. 164

6.29 The loss comparison between the conventional 𝐿𝐶 𝐿 inverter and the developed
inverter with VF-CSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

6.30 The (a) power-frequency and (b) efficiency-power density diagrams of SiC and
GaN based applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

7.1 (a) Conventional 𝐿𝐶 𝐿 converter with monolithic control and (b) modified non-
isolated three-phase 𝐿𝐶 𝐿 converter with modularized MPC. . . . . . . . . . . . . 172

7.2 (a) 𝑑-axis (b) 𝑞-axis and (c) 0-axis equivalent circuit of the modified topology on
DC/AC side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.3 Equivalent common mode circuit of the (a) conventional and (b) proposed non-
isolated DC/AC converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

7.4 Proposed modular MPC control diagram of the non-isolated DC/AC converter. . . . 177

xiv
7.5 (a) Conventional (b) proposed regulated third harmonic injection methods and (c)
the detailed control diagram of the zero sequence stabilized RTHI. . . . . . . . . . 182

7.6 (a) Sinusoidal THI and (b) Triangular space vector injection. . . . . . . . . . . . . 182

7.7 (a) Sinusoidal RTHI and (b) zoomed waveforms. . . . . . . . . . . . . . . . . . . 186

7.8 (a) Triangular RTHI and (b) zoomed waveforms. . . . . . . . . . . . . . . . . . . . 187

7.9 (a) The transients from sinusoidal RTHI to constant zero-sequence voltage control
and (b) zoomed waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

7.10 (a) The transients from triangular RTHI to constant zero-sequence voltage control
and (b) zoomed waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

7.11 The leakage currents and common mode voltages in Sin-RTHI, Tri-RTHI, Constant-
𝑣 0 , proposed topology without Constant-𝑣 0 control and conventional modes. . . . . 189

xv
 List of Tables

2.1 System Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.1 High frequency high power inductor design parameters . . . . . . . . . . . . . . . 46

3.2 Theoretical inductor design results at 1MHz . . . . . . . . . . . . . . . . . . . . . 47

3.3 High Frequency Behavior Comparison of Litz PCB . . . . . . . . . . . . . . . . . 56

3.4 Four core structures design results by sweeping the air gap or winding height and
turn number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.5 Loss comparison of the four-layer neural network with different neuron number
combinations in two hidden layers. . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.6 Overall Comparisons of the proposed prototypes, commercial inductors and theo-
retical design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.1 System Parameter Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

4.2 Control Parameters of Different Methods . . . . . . . . . . . . . . . . . . . . . . . 105

7.1 The comparison of proposed and conventional methods. . . . . . . . . . . . . . . 189

xvi
 Acknowledgements

During the whole period of pursuing my Ph.D. degree, I have received numerous invaluable
help and inspirations.
Firstly, I would like to express my deepest and most sincere appreciation to my advisor, Prof.
Matthias Preindl. His selfless support and precious guidance have continuously motivated me
throughout my entire Ph.D. period. Without his countless support and precious advice, it is impos-
sible for me to achieve my desired academic goal. His gentle character and courteous manner of
supervision set an ideal example for me in the aspect of positively influencing other people. His
intelligent expertise in power electronics enlightened me all the time to come up with novel ideas
for my research.
I would also appreciate my thesis defense committee professors: Prof. Peter Kinget, Prof.
Xiaofan Jiang, Prof. James Anderson and Prof. Bolun Xu. Their invaluable suggestions and
comments helped me a lot on improving my thesis.
I would also like to express my gratitude to my colleagues in MPLAB: Weizhong Wang,
Michael Eull, Matthew Jahnes, Jingping Nie, Youssef Fahmy, Bernard Steyaert, Alan Li, Noah
Silverman and Alexandre Msellati. I am greatly honored to have been working with you and
studying the exciting research together.
I would also like to express my special love to my girlfriend, Yanjing Chen for her countless
support and understanding which brightened my life outside of my research.
Finally, I would like to express the love and appreciations from the bottom of my heart to my
mother, Yinhui Wu, my father, Chengtao Zhou, my paternal grandfather, Jianrong Zhou, my pater-
nal grandmother, Guixin Li, my maternal grandfather, Minglue Wu and my maternal grandmother,
Guangqing Liu. Their unconditional love and endless support encourage me throughout all my
life.

xvii
 Dedication

This thesis is dedicated to my mother, Yinhui Wu, my father, Chengtao Zhou, my pater-
nal grandfather, Jianrong Zhou, my paternal grandmother, Guixin Li, my maternal grandfather,
Minglue Wu and my maternal grandmother, Guangqing Liu, for their endless love and support
throughout my life.

xviii
 Chapter 1: Introduction

1.1 Background

The power electronics (PE) are widely applied in the electrified energy conversion systems
ranged from low power chip level supplies, consumer electronics, middle power domestic compli-
ance, server power supplies, to high power electric vehicle charger, solar energy, E-motor traction,
wind power generation and so on. The power electronics techniques mainly focus on leverag-
ing electronics knowledge to design and control the electric power conversion systems. With the
increasing of global carbon dioxide emissions, the electrification of energy conversion system is at-
tracting significant research interests. Especially in the transportation systems, the carbon dioxide
generated by burning fossil fuels accounts for the majority of greenhouse gas (GHG) emissions. In
the automobile industry, the traditional internal combustion engines are the main source of GHG
emissions. The fuel burning efficiency is positively related to the degree of electrification in the
automotive propulsion system as is shown in Fig. 1.1 [1]. From hybrid electric vehicle (HEV) to
plug-in hybrid electric vehicle (PHEV) then to all-electric vehicle (BEV), the ratio of electrifica-
tion is scaled up. Accordingly, the GHG emissions are reduced due to the improvement of fuel
efficiency. Besides the attenuation of GHG emissions, the electric vehicles also have comfortable
driving experience, intelligent autopilot techniques and safe propulsion system. Thus, the global
electric vehicle stock is surging in the recent 10 years as is shown in Fig. 1.2 1 . Power elec-
tronics techniques are crucial to the electrification of transportation since the EV battery charg-
ing/discharging, electric motor traction and automotive electronics system are all relying on the
design and control techniques of PE. Besides the automobile industry, there are various appli-
cations in the electrified energy conversion systems that require power electronics, such as solar
1 IEA, Global electric passenger car stock, 2010-2020, IEA, Paris https://www.iea.org/data-and-
statistics/charts/global-electric-passenger-car-stock-2010-2020

1
energy, wind power, grid-connected power supplies and so on as is shown in Fig. 1.3(a). The main
components of PE system is power converters to transform the electric power between alternate
current (AC) and direct current (DC) formats. Four typical power converters include DC/DC con-
verter, DC/AC inverter, AC/DC rectifier and AC/AC converter as is shown in Fig. 1.3(b). Thus,
generally speaking, the PE techniques focus on the design and development of hardware/software
based on the four types of power converters.
Power electronics design and development are typically specialized field for different types
of electrified energy conversion systems. The design of the power electronics devices is always
application-oriented since the requirements of different electrified load/source may vary. Thus, the
corresponding hardware and software design will be diverse. Conventionally, to design a power
converter, the specific parameter configuration requirement should firstly be comprehensively ana-
lyzed. On one hand, for the hardware part, the rated voltage/current/power requirements determine
the device selection and PCB board design. The power converter topologies can also vary and are
largely dependent on the interfaced load/source. Different types of interfaced load/source would
also require disparate sensing circuits. On the other hand, for the software part, various types of
applications need different number of sampling information, I/O channels, control function algo-
rithms and so on. The different detailed configuration requirements of various industrial products
make the power electronics design an application-oriented profession. The existing studies rarely
focus on the generalization of the electrified energy conversion system.
The traditional power electronics design procedures can be generally summarized as five steps,
converter configuration, hardware design, software/control design, experimental validation and
standard compliance. Since the first step of power converter configuration depends on the in-
terfaced load/source characteristics, rated input/output voltage/current level and power demands,
the subsequent procedures will be largely diverse. A concept of power electronics building block
(PEBB) has been proposed to standardize the hardware components for stackable energy conver-
sion systems [2, 3, 4, 5, 6, 7, 8, 9, 10]. The PEBB concept is more focusing on the physical
components design to generalize the hardware power modules with extensible voltage/current ca-

2
pacity. On the contrary, some studies have also developed power electronics control architectures
in a high level perspective to cover various applications [11, 12, 13, 14, 15, 16]. Besides the gen-
eralized hardware and software control architecture designs for power electronics, some research
developed modular concept for power converters to further generalize the power electronics de-

Figure 1.1: Degree of electrification: typical fuel efficiency improvement and electric traction
motor power.

Figure 1.2: Global electric passenger car stock from 2010 to 2020.

3
 (a)

(b)

Figure 1.3: (a) Different applications of power electronics and (c) the typical power converter
structures.

sign procedures [17, 18, 19]. Other technical concepts studied the building of universal platform
or infrastructure for the real-time power electronics testing and design [20, 21, 22].

1.2 Motivations

The typical power electronics design procedures are demonstrated in Fig. 1.4(a). Various
types of applications are featured with different power converter, hardware and software control
configurations. Thus, it is hard to generalize a universal design protocol that can cover all types
of electrified energy load/source. The specificity of power electronics design is mainly reflected in
the following three aspects.

4
 (a)

(b)

Figure 1.4: The design procedures for (a) conventional power electronics system and (c) software-
defined power electronics architecture.

Firstly, the characteristics of the interfaced loads/sources to the power converters are disparate.
For example, the energy loads/sources can be divided into DC and AC. DC types of electric power
include battery, solar energy, automotive 48-volt system and other low voltage power supplies.
Among the DC electric power loads/sources, the required voltage/current or power control algo-
rithms are different. Battery charging/discharging processes are typically featured with constant
current (CC) and constant voltage (CV) control modes. The photo-electric effect in the solar en-
ergy system requires a maximum power point tracking (MPPT) technique to perform an optimal
energy transformation efficiency. Grid-tied inversion systems demand a phase-locked loop (PLL)
to synchronize the power converter with the grid frequency. Motor traction inverter of the electric
vehicle needs to sample the rotor position for the speed and torque control.
Secondly, the difference of rated voltage and current configurations can lead to huge divergence

5
on the power converter and the corresponding sensor circuit design. The rated voltage/current
values limit the selection of power switches for the tolerable maximum current/voltage across
the switch. The sensor circuit design is also sensitive to the current/voltage ranges which could
influence the sampling resolution and accuracy.
Thirdly, the time scales of the power electronics signals are different for various types of com-
municated information. The updating frequencies of the communication signals can be ranged
from 𝑛𝑠 to 𝑚𝑖𝑛 according to the control needs and micro-controller computation capability. For
instance, the protection signals by detecting voltage/current samples may be iterated within 𝑛𝑠 to
𝜇𝑠. The voltage/current signals for power control purposes can be updated with the time periods
from 𝜇𝑠 to 𝑚𝑠. Other grid service commands, user interfaced data monitoring may not require fast
updating period which could be ranged from 𝑚𝑠 to 𝑠.
Since the existence of the three aspects of specificity for the power electronics design, the
power converters need to be specifically designed based on the demands. The targets for the power
converters design mainly include high energy conversion efficiency, high power density, low cost
to improve the energy conversion performance. In detail, the high efficiency means low power
losses during the energy conversion processes. The high power density requests a high power level
and low volume in the mean time. Low cost pursues less cost on the hardware components per
volume of the energy conversion system.
Comprehensively considering the specificity feature of power electronics design and the tar-
get of improving the energy conversion performance, the dissertation develops a software-defined
power electronics architecture to abstractly generalize the electrified energy conversion system and
improve the energy conversion performance by leveraging advanced control, estimation algorithms
and novel design techniques.

1.3 Contributions

The study of the dissertation develops a software-defined power electronics architecture by

leveraging model predictive control (MPC), state estimation, variable-frequency critical-soft-switching

6
(VF-CSS) control algorithms and advanced inductor design techniques to abstractly generalize the
energy conversion system with high performance.

• Variable-Frequency Critical-Soft-Switching Control: A VF-CSS method is developed by

leveraging the variable-frequency controller to achieve critical-soft-switching operation of
the power modules. The energy conversion efficiency is improved by 3% compared to the
conventional fixed frequency hard switching.

• High Performance Inductor Design Enabling Critical-Soft-Switching: For the power

module, the most crucial magnetic component of switch side inductor is designed based on
litz type of PCB winding and optimal core structure to reduce the inductor losses, volume
and cost. A neural network model is built to automatically analyze the litz type of PCB
winding design for optimal configuration. The total inductor loss, volume and temperature
rise are reduced by 4 times, 40% and 50◦ C compared to the existing commercial inductors.

• Model Predictive Control for Modular Power Converters: A modular model predic-
tive control method is proposed to be combined with the variable-Frequency Critical-Soft-
Switching Control for the improvement of dynamic performance, especially during tran-
sients. The extra oscillation caused by the variable frequency control can be attenuated by
the MPC. Also, the developed MPC enhances the control bandwidth with higher reference
tracking speed and less overshoot issue.

• Hierarchical Software-Defined Control Architecture with MPC-Based Power Module:

A multi-layer software-defined power electronics architecture is designed based on the afore-
mentioned VF-CSS and modular MPC to abstractly generalize the electrified energy con-
version system. The proposed software-defined power electronics architecture is mainly
featured with four merits: (1) generalized design procedures to reduce the repetitive power
electronics design processes; (2) reconfigurable architecture to form different power con-
verter topologies with the corresponding control functions; (3) wide application interfaces
to be applicable for various types of electrified load/source; (4) redundant mechanism with

7
 self-healing to diagnose and substitute the fault circuit components. Based on the gener-
alized architecture, several design cases have been implemented experimentally including
isolated/non-isolated DC/DC converter, grid-tied inverter, battery charger and motor traction
inverter to validate the feasibility of the proposed concept.

• High Effciency and Power Density Grid-Tied Inverter Design: A design case of high
performance grid-tied inverter is developed based on the VF-CSS and modular MPC tech-
niques to achieve high efficiency, power density and low cost. The VF-CSS contributes
to an efficiency above 99% at the rated power of 15kW. A power density of 10.4kW/L is
achieved based on the designed litz type of PCB inductor and above 1MHz switching fre-
quency. The modified power module combined with a zero-sequence voltage control method
enables non-isolated inverter topology with low leakage current and low cost.

• MPC-Based Regulated Third Harmonic Injection for Zero-Sequence Stabilized 𝐿𝐶 𝐿

Inverter: Another design case of regulated third harmonic injection (THI) method is devel-
oped based on MPC and zero-sequence-voltage stabilization of the modified 𝐿𝐶 𝐿 inverter
topology to improve the DC bus utilization. Different from the conventional THI methods,
the proposed technique implemented the third harmonic injection with MPC regulation in
the zero-sequence frame. The robustness is improved with the MPC regulation. The THI
distortion on the output side is bypassed by the modified power module. Also no extra op-
timization algorithms are needed to minimize the output THI distortion. The computation
burden compared to the conventional THI method is reduced correspondingly.

8
Chapter 2: Variable-Frequency Critical-Soft-Switching for Modular Power

Converters

Wide-bandgap devices (WBG) are attracting more and more attention in the field of power
conversion system. Silicon carbide (SiC) and Gallium Nitride (GaN) MOSFETs are two types of
semiconductor that have been widely used in industrial applications due to the superior character-
istics in high power and high frequency behaviors [23], [24]. Applying wide-bandgap devices in
power converters can achieve high switching frequency with high power level [25]. This charac-
teristic could decrease the inductance/capacitance values to improve the power density [26]. One
issue that should be carefully considered is the switching losses which are mainly caused by the
overlapping voltage and current waveforms during turn-on and turn-off switching periods [27],
[28]. The switching losses could be influenced by many factors such as the device intrinsic fea-
tures, peripheral circuits, gate driver behavior, soft switching design, controlling strategy, etc [29].
For the generality point of view, an effective way to decrease the switching losses is by combining
the last two parts: soft switching design and controlling strategy. Firstly, soft switching is a key
technique to reduce the switching losses in power converters [30]. The principle of soft switching
is to avoid the overlapping area of switch voltage and current waveforms [31]. It can be divided
into zero-voltage soft switching (ZVS) and zero-current soft switching (ZCS). ZVS aims at mini-
mizing the voltage across the switch during switching transients and ZCS deals with the switching
tail current to minimize the losses during transient periods. To realize the soft switching opera-
tion, auxiliary circuits can be added to handle the turn-on and turn-off instants for switching losses
minimization [32]. However, the active auxiliary circuits will induce more cost and controlling
complexity. Another way to implement soft switching is by designing the passive component val-
ues, such as filtering inductance and capacitance, and power converter operating parameters, such

9
as current ripple, switching frequency, dead time, etc [33]. The passive soft switching methods
could be implemented based on a common characteristic of the MOSFETs: turn-on losses of the
most MOSFETs are much greater than the turn-off losses. So, the soft switching strategy can be
designed to replace the higher turn-on losses with lower turn-off losses [34]. For the state of the art
of passive soft switching techniques in DC/DC buck modules, the primary method is to enlarge the
inductor current ripple with bidirectional flowing paths at peak/valley points. This operating mode
can be implemented by synthesizing the filtering inductor design, switching frequency configura-
tion, power rating requirement and MOSFET characteristic analysis. [35] studied the passive soft
switching technique without adding active auxiliary circuit or passive snubbers and implemented
the soft switching on a bidirectional three-phase paralleled buck converter to achieve high effi-
ciency and power-density specifically in IGBT devices. [36] focused on the passive soft switching
analysis for interleaved multi-phase DC/DC converter specifically in the application of energy stor-
age systems. The current ripple balancing issue is studied for efficiency improvement. The fore-
mentioned techniques have developed convincing methods to achieve ZVS operation. However,
the transient performance of soft switching is another key topic that merits attention. A steadily
fast control method can avoid the oscillation or overshoot issues during the dynamic period to fur-
ther improve the soft switching losses. Specifically, the second part is the controlling strategy: a
better controlling method can achieve superior dynamic performance and accurate tracking behav-
ior. A fast and stable controller will cause less oscillation on the output waveforms which means
the soft switching operation can be achieved accurately and maintained steadily, especially during
the transient period. Thus, the switching losses induced by the hard switching will be decreased
accordingly. The most commonly used controlling method is PI controller. It is simple to design
and implement with good performance. However, the overshoot and dynamic oscillation issues are
the main drawbacks due to the integral process. Another more advanced controlling method that
has better dynamic performance is model predictive control (MPC) [37], [38]. It can generate the
optimal input values for the system by predicting multiple steps based on the state space equations
and cost function [39]. Compared to PI controller, MPC has been validated to have faster tracking

10
speed and better transient behavior if designed properly [40].
This chapter proposes a controlling method based on the above mentioned two aspects to im-
prove the efficiency and power density of the DC/DC converter. Firstly, a critical soft switching
method is designed to achieve the soft switching operation without auxiliary circuits. The bound-
ary constraints of typical WBG devices are derived according to the dead time and peak/valley
inductor currents. The controlling method is designed based on the critical soft switching bound-
ary constraints. Then, the variable-switching constant-sampling frequency critical-soft-switching
model-predictive-control (VSCS-MPC) method is proposed. For the general purpose, both the
current source load and resistive load converters are validated with the proposed MPC method.
The controlling method mainly includes two parts: frequency controller and MPC controller. Fre-
quency controller is designed to reduce the switching losses of the converter under critical soft
switching by controlling the inductor current ripple. The expected switching frequency is calcu-
lated according to the measured inductor current, output voltage and duty cycle. For the consid-
eration of system stability to generate the PWM signals, the switching frequency are discretized
into equally segmented bandwidth for the purpose of maintaining a constant sampling frequency.
If the calculated frequency belongs to certain range of the bandwidth, a fixed switching frequency
will be delivered to the PWM. And the MPC controller will receive the measured output voltage
and inductor current to generate the optimal duty cycle for tracking the voltage/current references.
In order to alleviate the calculation burden in high frequency application, an oversampling method
is designed based on the segmented frequency controller. Specifically, the MPC, frequency con-
troller and sampling will be updated based on a constant fundamental frequency, 𝑓𝑠,𝑏𝑎𝑠𝑒 , and the
PWM switching frequency will be determined by the discretized frequency controller according to
the equally segmented bandwidth range. Thus, the switching frequency will be adjusted steadily
at a certain integral multiple, n, times of the fundamental frequency to achieve the soft switching
operation when the calculated frequency is within certain bandwidth range. The system oscillation
will be mitigated by avoiding a time-varying sampling frequency and instantaneously changed
switching frequency. By combining the two controllers, the proposed VSCS-MPC can achieve

11
high efficiency and superior dynamic performance robustly. The analytical tests are implemented
on a SiC testbench to verify the proposed controlling method.

2.1 Critical soft switching principles for DC/DC converter

In this section, the critical soft switching technique is introduced with the derived boundary
conditions of dead time and peak/valley inductor current by datasheet and integral equations. The
main purpose of the critical soft switching method is to replace the large turn-on loss of upper
switch with small turn-off loss of lower switch [41], [42]. Fig. 2.1 shows the current paths of
DC/DC converter during lower switch turn-off period. For the critical soft switching, a large
current ripple is required to ensure negative valley inductor current to be lower than a threshold
current level as is shown in Fig. 2.2. In the turn-off transient period of lower switch, the negative
inductor current will discharge the upper switch output capacitor, 𝐶𝑜𝑠𝑠,𝑚1 . The ZVS of upper
switch can be achieved if the 𝐶𝑜𝑠𝑠,𝑚1 is fully discharged before it turns on. The ZVS operation

M1 iCDS,m1
+ L
Uin
_ iDS,m2 +
iL
C uo
M2 iCDS,m1
_

Figure 2.1: The negative inductor current paths of DC/DC Buck converter.

M1

M2
IL,max
IL,ave
0
IL,min
ton toff td

Figure 2.2: Gate signals and inductor current for critical soft switching.

12
depends on the interlock time between two switches and the value of inductor valley current. The
inductor valley current is expressed as

𝐼 𝐿,𝑚𝑖𝑛 = −𝐼 𝐷𝑆,𝑀2 + 𝐼𝐶𝐷𝑆,𝑀1 − 𝐼𝐶𝐷𝑆,𝑀2 . (2.1)

𝐼 𝐷𝑆,𝑀1 and 𝐼 𝐷𝑆,𝑀2 are the drain current through the upper and lower switches, 𝐼𝐶𝐷𝑆,𝑀1 and 𝐼𝐶𝐷𝑆,𝑀2
are the current through the upper and lower switch output capacitance, respectively. Since

𝑑𝑈𝐷𝑆,𝑀1
𝐼𝐶𝐷𝑆,𝑀1 = 𝐶𝐷𝑆,𝑀1 (2.2)
𝑑𝑡

𝑑𝑈𝐷𝑆,𝑀2
𝐼𝐶𝐷𝑆,𝑀2 = 𝐶𝐷𝑆,𝑀2 (2.3)
𝑑𝑡

and (𝑈𝐷𝑆,𝑀1 +𝑈𝐷𝑆,𝑀2 ) equals to the input source voltage, 𝑈𝑖𝑛 , which is a constant value, 𝐼 𝐿,𝑚𝑖𝑛
could be expressed as

𝑑𝑈𝐷𝑆,𝑀2
𝐼 𝐿,𝑚𝑖𝑛 = −𝐼 𝐷𝑆,𝑀2 − (𝐶𝐷𝑆,𝑀1 + 𝐶𝐷𝑆,𝑀2 ) . (2.4)
𝑑𝑡

Similarly, the maximum positive value is

𝑑𝑈𝐷𝑆,𝑀2
𝐼 𝐿,𝑚𝑎𝑥 = 𝐼 𝐷𝑆,𝑀1 + (𝐶𝐷𝑆,𝑀1 + 𝐶𝐷𝑆,𝑀2 ) . (2.5)
𝑑𝑡

13
The above current equations can be further analyzed by the integral calculation over interlock time,
𝑇𝑑 , and drain-source voltage, 𝑈𝑑𝑠 , respectively, and expressed as

∫ 𝑇𝑑
[𝐼 𝐿,𝑚𝑖𝑛 − 𝐼 𝐷𝑆,𝑀2 (𝑡)] 𝑑𝑡 = 𝑄 𝑚𝑖𝑛 = (2.6a)
0
∫ 𝑈𝑖𝑛
−[𝐶𝐷𝑆,𝑀1 (𝑈𝐷𝑆,𝑀2 ) + 𝐶𝐷𝑆,𝑀2 (𝑈𝐷𝑆,𝑀2 )] 𝑑𝑈𝐷𝑆,𝑀2
0
∫ 𝑇𝑑
[𝐼 𝐿,𝑚𝑎𝑥 − 𝐼 𝐷𝑆,𝑀1 (𝑡)] 𝑑𝑡 = 𝑄 𝑚𝑎𝑥 = (2.6b)
0
∫ 0
[𝐶𝐷𝑆,𝑀1 (𝑈𝐷𝑆,𝑀2 ) + 𝐶𝐷𝑆,𝑀2 (𝑈𝐷𝑆,𝑀2 )] 𝑑𝑈𝐷𝑆,𝑀2
𝑈𝑖𝑛

where 𝑄 𝑚𝑖𝑛 ≤ 0 and 𝑄 𝑚𝑎𝑥 ≥ 0 are the total charge moved in the output capacitors. Assuming
that 𝐼 𝑑𝑠 is varying linearly with time, the left side of the two equations in equation (2.6) can be
calculated as

∫ 𝑇𝑑
[𝐼 𝐿,𝑚𝑖𝑛 − 𝐼 𝐷𝑆,𝑀2 (𝑡)] 𝑑𝑡 = (2.7a)
0
∫ 𝑇𝑑
𝐼 𝐿,𝑚𝑖𝑛 1
[𝐼 𝐿,𝑚𝑖𝑛 − (𝐼 𝐿,𝑚𝑖𝑛 − 𝑡)] 𝑑𝑡 = 𝐼 𝐿,𝑚𝑖𝑛𝑇𝑑
0 𝑇𝑑 2
∫ 𝑇𝑑
[𝐼 𝐿,𝑚𝑎𝑥 − 𝐼 𝐷𝑆,𝑀1 (𝑡)] 𝑑𝑡 = (2.7b)
0
∫ 𝑇𝑑
𝐼 𝐿,𝑚𝑎𝑥 1
[𝐼 𝐿,𝑚𝑎𝑥 − (𝐼 𝐿,𝑚𝑎𝑥 − 𝑡)] 𝑑𝑡 = 𝐼 𝐿,𝑚𝑎𝑥 𝑇𝑑 .
0 𝑇𝑑 2

So, the critical soft switching can be achieved with the inequalities of 𝐼 𝐿,𝑚𝑖𝑛(𝐿,𝑚𝑎𝑥) and 𝑇𝑑

1
2 𝐼 𝐿,𝑚𝑖𝑛𝑇𝑑 ≤ 𝑄 𝑚𝑖𝑛 ≤ 0 (2.8a)
1
2 𝐼 𝐿,𝑚𝑎𝑥 𝑇𝑑 ≥ 𝑄 𝑚𝑎𝑥 ≥ 0. (2.8b)

Thus, the minimum negative and maximum positive inductor current can be derived with the vari-
ables of dead time, 𝑇𝑑 , and the integration of output capacitors with drain-source voltages. The
design of the converter should satisfy the two inequalities to guarantee the critical soft switching
operation. The integral of switch output capacitance to drain-source voltages can be calculated

14
based on the datasheet provided by the device manufacturer. So the integrations of equation can
be calculated by tracing several discrete voltage intervals multiplied by the corresponding capaci-
tance value and then accumulating together. According to the relation waveform of switch output
capacitance and drain-source voltage, the right side of inequalities (2.8) can be derived by tracing
n points on the curve of switch output capacitance, 𝐶𝑜𝑠𝑠 , and summing up the n intervals together.
Then, the model of critical soft switching method can be expressed with the function image in
Fig. 2.3. It can be shown that the blue regions are the feasible soft switching range according to
the constraints of inequalities (2.8) with the maximum and minimum dead time requirement. Also,
the soft switching ranges of typical GaN and SiC devices are given in Fig. 2.3. During controlling
part in the following sections, the dead time and peak/valley inductor currents can be controlled
within the critical soft switching region to reduce the switching losses with optimal frequency.

Figure 2.3: The critical soft switching operation regions for different devices.

15
2.2 Variable-switching constant-sampling frequency critical-soft-switching control

This section gives the detailed controlling method of the proposed variable-switching constant-
sampling frequency critical-soft-switching model-predictive-control strategy. The VSCS-MPC in-
cludes two parts: frequency controller to achieve the critical soft switching operation; MPC con-
troller to track the output voltage/current and improve the dynamic performance. The implemen-
tation of MPC controller has large computation burden. So, an explicit MPC method is applied
to solve the optimization problem offline. And due to the characteristic of MPC, a fixed sam-
pling time period is required. Thus, to combine the MPC and variable frequency controller, the
switching frequency is equally segmented based on a fundamental frequency, 𝑓𝑠,𝑏𝑎𝑠𝑒 . The MPC
and freqeuncy controller is updated with 𝑓𝑠,𝑏𝑎𝑠𝑒 to guarantee enough computation time. And the
frequency controller will calculate the expected soft switching frequency and transfer it into a dis-
crete value for PWM based on the pre-designed bandwidth ranges. Thus, the switching frequency
for PWM is discretized to be n times larger than the fundamental frequency, 𝑓𝑠,𝑏𝑎𝑠𝑒 , which avoids
the oscillation of the time-varying switching frequency.

2.2.1 Frequency Controller

For the frequency controller, the main purpose is to operate the converter in critical soft switch-
ing region and reduce the switching losses. In every fundamental time period, the frequency con-
troller receives the duty cycle and inductor current values from the MPC controller to calculate
the desired switching frequency. Then, the switching frequency is discretized based on the band-
width ranges to derive a fixed value for the PWM. The calculation of the switching frequency is
based on the critical soft switching constraints which have been derived in section II. The design
of the frequency controller includes the constraints and methodology which have been shown as
following.

16
Figure 2.4: The thermal, soft switching, frequency and device current constraints of 𝑓𝑠𝑤 with the
function of duty and 𝐼 𝐿,𝑎𝑣𝑒 .

Constraints

The principle of the frequency controller is to generate the feasible switching frequency based
on the critical soft switching boundary conditions. In every calculating period, the frequency con-
troller receives the information of duty cycle and inductor current from the MPC controller. Then
an expected switching frequency is pre-calculated for discretization based on the bandwidth ranges
and send to the PWM module. During the calculation of the expected switching frequency, four
parts of constraints need to be taken into consideration: critical soft switching threshold current,
𝐼𝑡ℎ , maximum device current, 𝐼𝑚𝑎𝑥 , maximum thermal rising, 𝑃𝑡ℎ𝑒𝑟𝑚𝑎𝑙,𝑚𝑎𝑥 and frequency ranges.
The contraints could be expressed as

△𝑖 𝐿
𝐼𝑡ℎ ≤ 𝐼 𝑝𝑒𝑎𝑘 = 𝐼 𝐿,𝑎𝑣𝑒 + ≤ 𝐼𝑚𝑎𝑥 (2.9)
2

△𝑖 𝐿
− 𝐼𝑚𝑎𝑥 ≤ 𝐼𝑣𝑎𝑙𝑙𝑒𝑦 = 𝐼 𝐿,𝑎𝑣𝑒 − ≤ −𝐼𝑡ℎ (2.10)
2
𝑇 𝑗,𝑚𝑎𝑥 − 𝑇𝑐𝑎𝑠𝑒
𝑃𝑠𝑤 + 𝑃𝑐𝑜𝑛 ≤ 𝑃𝑡ℎ𝑒𝑟𝑚𝑎𝑙,𝑚𝑎𝑥 = (2.11)
𝑅𝑡ℎ,𝐽−𝐶

17
 𝑓𝑠𝑤,𝑚𝑖𝑛 ≤ 𝑓𝑠𝑤 ≤ 𝑓𝑠𝑤,𝑚𝑎𝑥 (2.12)

where 𝐼 𝑝𝑒𝑎𝑘 , 𝐼𝑣𝑎𝑙𝑙𝑒𝑦 , 𝑇 𝑗,𝑚𝑎𝑥 , 𝑇𝑐𝑎𝑠𝑒 and 𝑅𝑡ℎ,𝐽−𝐶 are the peak, valley points of inductor current, junc-
tion, case temperatures and thermal resistance, respectively. The inductor current ripple is the
function of three variables, (𝐼 𝐿,𝑎𝑣𝑒 , 𝑑, 𝑓𝑠𝑤 ), and can be derived as

𝑑 (1 − 𝑑)𝑈𝑖𝑛
Δ𝑖 𝐿 = . (2.13)
𝑓𝑠 𝐿

So the derived constraints (2.9)-(2.12) can also be expressed as the function of (𝐼 𝐿,𝑎𝑣𝑒 , 𝑑, 𝑓𝑠𝑤 )
with the help of the substitution in (2.13). Thus, the constraints of 𝑓𝑠𝑤 with respect to (𝐼 𝐿,𝑎𝑣𝑒 , 𝑑)
can be plotted in the 3D coordinate system as is shown in Fig.2.4 where the two surfaces represent
the upper and lower limits of the frequency controller, respectively. The calculation of expected
switching frequency is based on the boundaries of the constraints to mainly satisfy the critical soft
switching.

Methodology

The operating trajectories of the frequency controller can be illustrated in Fig. 2.5. With the
variation of inductor current and duty cycle, the maximum feasible frequency under the critical
soft switching constraints can be derived by the function of 𝑓𝑠𝑤 with respect to (𝐼 𝐿,𝑎𝑣𝑒 , 𝑑) (bold red
lines in Fig. 2.5). Based on the derived critical soft switching boundary conditions, the maximum
frequency controller trajectories are divided by positive/negative inductor current conditions and
the expected switching frequency can be expressed as

(1 − 𝑑)𝑑𝑈𝑖𝑛
𝑓𝑠,𝑐𝑎𝑙 = , 𝐼 𝐿,𝑎𝑣𝑒 ≥ 0 (2.14a)
2(𝐼 𝐿,𝑎𝑣𝑒 + 𝐼𝑡ℎ )𝐿
(1 − 𝑑)𝑑𝑈𝑖𝑛
𝑓𝑠,𝑐𝑎𝑙 = , 𝐼 𝐿,𝑎𝑣𝑒 ≤ 0 (2.14b)
2(𝐼𝑡ℎ − 𝐼 𝐿,𝑎𝑣𝑒 )𝐿

where the threshold current of critical soft switching constraints, 𝐼𝑡ℎ , is based on the results derived
in the second section.

18
 Figure 2.5: The feasible trajectories of maximum frequency control method with certain duty.

After the calculation of the expected switching frequency, the values are then discretized by
a pre-designed bandwidth ranges which are the integral multiple of the fundamental frequency,
𝑓𝑠,𝑏𝑎𝑠𝑒 . The fundamental frequency for MPC and frequency controller is set to be 30kHz, thus the
discretized frequency for PWM signals could be n times of 𝑓𝑠,𝑏𝑎𝑠𝑒 . It should be noted that when a
certain discrete bandwidth range of the switching frequency is derived, the integral multiple value
of n is rounded down to guarantee the soft switching is maintained by choosing a relatively lower
switching frequency. The implementation of the frequency controller is shown in Fig. 2.6. Also,
to make a better explanation of the discrete frequency controller, the function curve of calculated
switching frequency with duty cycle is drawn in Fig. 2.7 under the rated current load. It can be
seen that the vertical axis of the switching frequency is equally segmented with the bandwidth of
30kHz. The PWM frequency is discretized and assigned as the lowest value at each range of duty
cycle. The relationship of PWM carrier signals and sampling signals are shown in Fig. 2.8 with a
varying switching frequency from 4 𝑓𝑠,𝑏𝑎𝑠𝑒 to 𝑓𝑠,𝑏𝑎𝑠𝑒 .

2.2.2 Model Predictive Controller

MPC aims at tracking the output voltage/current according to the pre-defined references. In
every calculating period of fundamental frequency, 𝑓𝑠,𝑏𝑎𝑠𝑒 , the MPC controller receives the mea-
sured inductor current, input/output voltage values and generates the optimal duty cycle for both

19
 (×

N*fs_base

4*fs_base
3*fs_base
2*fs_base
fs_base

Figure 2.6: Discrete frequency controller with equally segmented bandwidth.

Discretized Switching Frequency at IL,rated

105
4.5
4.2
3.9
3.6
3.3
3
n*f s,base (Hz)

2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
0 0.2 0.4 0.6 0.8 1
Duty Cycle

Figure 2.7: Equally segmented switching frequency with the function of duty cycle at the rated
load current.

20
PWM module and frequency controller. The MPC formulations for both current source load and
resistive load are shown in this section.
Firstly, the state equations of the DC/DC converter with LC filters and current source load can
be expressed as

𝑇𝑠 𝑈𝑖𝑛𝑇𝑠
𝑖 𝐿 (𝑘 + 1) = 𝑖 𝐿 (𝑘) − 𝑢 𝑜 (𝑘) + 𝑑 (𝑘) (2.15a)
𝐿 𝐿
𝑇𝑠 𝑇𝑠
𝑢 𝑜 (𝑘 + 1) = 𝑖 𝐿 (𝑘) + 𝑢 𝑜 (𝑘) − 𝑖 𝑜 (𝑘). (2.15b)
𝐶 𝐶

For the resistive load, the term 𝑖 𝑜 (𝑘) in (2.15) can be replaced with 𝑢 𝑜 (𝑡)/𝑅𝑙𝑜𝑎𝑑 and 𝑢 𝑜 (𝑘)/𝑅𝑙𝑜𝑎𝑑 ,
respectively, where 𝑅𝑙𝑜𝑎𝑑 is the output resistor. For the flexibility of implementing the explicit
MPC and the convenience of experimentally adjusting the input voltage during test, the last term
of (2.15), 𝑈𝑖𝑛 𝑑 (𝑘), can be replaced by the phase leg output voltage, 𝑢 𝑥 (𝑘). The state-space model

Figure 2.8: Variable PWM carrier signals and constant sampling signals of the VSCS-MPC
method.

21
with current source load are in standard matrix format of

𝑋 𝑘+1 =𝐴𝑖 𝑋 𝑘 + 𝐵𝑖 𝑢𝑖𝑘 , (2.16a)

   𝑇 
 1 − 𝑇𝑠   𝑠 0 
𝐿  𝐿
𝐴𝑖 =   , 𝐵𝑖 =  (2.16b)
  
,
 𝑇𝑠 1   0 − 𝑇𝑠 
 𝐶   𝐶 
  
   
 𝑖 𝐿 (𝑘)   𝑈𝑖𝑛 𝑑 (𝑘) 
𝑋𝑘 =   , 𝑢𝑖𝑘 =  (2.16c)
   
.
 𝑢 (𝑘)   𝑖 (𝑘) 
 𝑜   𝑜 
   

The state-space model with resistive load is

𝑋 𝑘+1 = 𝐴𝑟 𝑋 𝑘 + 𝐵𝑟 𝑢𝑟 𝑘 , (2.17a)
   𝑇 
 1 − 𝑇𝐿𝑠   𝑠 
 𝐿 
𝐴𝑟 =   , 𝐵𝑟 =  (2.17b)
 
,
 𝑇𝑠 1 − 𝑇𝑠   0 
 𝐶 𝑅𝐶   
   
 
 𝑖 𝐿 (𝑘)  h i
𝑋𝑘 =   , 𝑢𝑟 𝑘 = 𝑈𝑖𝑛 𝑑 (𝑘) . (2.17c)
 
 𝑢 (𝑘) 
 𝑜 
 

To derive the state matrix for MPC formulation, the output current is regarded as the input vari-
able. So, in the implementation of the control, the current load can be measured and adjusted as a
constraints for the input vector. In the standardized state matrix, the voltage/current references can
be defined as 𝑋¯ and the tracking errors between the measurement and the references are expressed
as 𝑋˜ which are composed of

   
 𝑖 𝐿𝑟   𝑖 𝐿𝑟 − 𝑖 𝐿 (𝑘) 
𝑋¯ 𝑘 = 
 ˜
 , 𝑋𝑘 =  (2.18)
  
.
 𝑢   𝑢 − 𝑢(𝑘) 
 𝑜𝑟   𝑜𝑟 
   

Thus, the cost function includes two terms

𝑁𝑐
∑︁ 𝑝 −1
𝑁∑︁
𝑚𝑖𝑛 𝑋˜ 𝑘𝑇 𝑄 𝑋˜ 𝑘 + △𝑢𝑇𝑘 𝑅△𝑢 𝑘 . (2.19)
𝑘=0 𝑘=0

22
 MPC Controller Dynamic System

H1X(k)<K1

H2X(k)<K2
Region:
X(k) r UN = UN(1) X(k+1) = X(k)
H3X(k)<K3
FrX(k)+Gr AX(k)+Bu(k)

HnX(k)<Kn

Region Feedback Duty Cycle

Search Law Update

Figure 2.9: MPC optimization search tree implementing process.

For the penalties of the cost function, 𝑄 and 𝑅 represent the weighing factor matrices that are
implemented on the state values and input values, respectively. For the state value part, more
weight is addressed on output voltage in current source load converter because the inductor current
is restricted by the current load. For the input value part, more weight is addressed on duty cycle
to stabilize the system behavior. Typical values for 𝑄 and 𝑅 are [1, 0; 0, 1000] and [1000, 0; 0, 1],
respectively. The constraints of the MPC controller can be expressed as

𝑋˜ 𝑘+1 = 𝐴 𝑋˜ 𝑘 + 𝐵𝑢 𝑘 ∈ X (2.20)

Figure 2.10: Explicit MPC piecewise affine regions with prediction horizon of 5.

23
 △𝑢 𝑘 = 𝑢 𝑘 − 𝑢 𝑘−1 ∈ U (2.21)
   
 −𝐼 𝐿,𝑚𝑎𝑥   𝐼 𝐿,𝑚𝑎𝑥 
 ≤ 𝑋𝑘 ≤  (2.22)
   
 .

 0 

 𝑈
 𝑖𝑛


   
With current source load, the input constraint is

   
 0   𝑈𝑖𝑛 
 ≤ 𝑢𝑖𝑘 ≤  (2.23)
   
 .
 𝑖 (𝑘)   𝑖 (𝑘) 
 𝑜   𝑜 
   

Controlling Power module

iL(k)
io(k) MPC S1
uo(k) Controller d(k)
Us
(fs_base) /ux(k) PWM + iL io
Us
d(k) + L +
Signals - C
ux iC uo
iL(k) Frequency fs(k) S2 - -
Controller (nfs_base)
Us (fs_base)

Frequency bandwidth: fs_base nfs_base

Figure 2.11: Proposed variable-switching constant-sampling frequency critical-soft-switching

Model-predictive control diagram.

Figure 2.12: The waveforms of PWM carriers and trigger of the sampling and control.

24
The second term of 𝑢𝑖𝑘 is the output current from the known current source load. The controller
assigns the measured value by setting the constraints as is shown in (2.23). This configuration
allows a real-time adjustment of the output current that is compatible with explicit MPC. With
resistive loads, the input constraint is simplified as

h i h i
0 ≤ 𝑢𝑟 𝑘 ≤ 𝑈𝑖𝑛 . (2.24)

To achieve a high frequency for the DC/DC converter and reduce the calculation load of the
controller, the MPC problem is solved explicitly by generating a piecewise affine feedback law
[43]. Fig. 2.9 shows the mechanism of explicit MPC implementation process. The state model and
constraints of the dynamic system are built offline to generate an online search tree and feedback
law for optimization. In each controlling time period, the active region, r, is searched with the
matrices 𝐻𝑟 and 𝐾𝑟 . Then, in each of the specific active region, the corresponding feedback law
matrices, 𝐹𝑟 and 𝐺 𝑟 , are applied to calculate the optimal input values with the prediction horizon.
Only the first value of the input matrix is applied to the dynamic system for MPC control.
In every fundamental time period, the pre-designed search tree can find the optimal duty cycle
based on the updated state values of inductor current/output voltage. Explicit MPC avoids the time-
consuming online optimization process, thus it is suitable for high frequency control. A generated
piecewise affine region block with one input variable of phase leg output voltage, 𝑢 𝑥 , and two state
variables of output voltage, 𝑢 𝑜 , and inductor current, 𝑖 𝐿 , are shown in Fig. 2.10 with a prediction
horizon of 5. Based on the implementing process of Fig. 2.9, the colored areas represent the n
regions for MPC to search and optimize according to the feedback law. Specifically, the matrices
𝐻𝑟 and 𝐾𝑟 will lead to an active region. The matrices 𝐹𝑟 and 𝐺 𝑟 will help calculate the optimal
duty cycle for the PWM signals.
The whole controlling diagram of VSCS-MPC is shown in Fig. 2.11. At each sampling period
of 𝑇𝑠,𝑏𝑎𝑠𝑒 , the frequency controller receives the measurement of inductor current from ADC and
duty cycle from MPC controller. The discretized frequency (n times of 𝑓𝑠,𝑏𝑎𝑠𝑒 ) will be generated

25
 60

60
40

40
20

20
0

0
-20

-20

100

100

50

50

0
0.0098 0.00985 0.0099 0.00995 0.01 0.01005 0.0101 0.01015 0.0102

0.0098
Ready 0.00985 0.0099 0.00995 0.01 0.01005 0.0101 0.01015based
Sample 0.0102
T=0.020

Ready Sample based T=0.020

(a) (b)

Figure 2.13: (a) Inductor current and output voltage waveforms and (b) the zoomed waveforms
with output current load step from 10A to 15A based on VSCS-MPC of current load.
60 60
60
60
40 40
40
40
20 20
20 20
0 0
0 0
-20 -20
-20 -20

100 100
100 100

50 50
50 50

0
0 0
0

0.005 0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014 0.015
0.005 0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014 0.015 0.0098
0.0098 0.00985
0.00985 0.0099
0.0099 0.00995
0.00995 0.01
0.01 0.01005
0.01005 0.0101
0.0101 0.01015
0.01015 0.0102
0.0102
Ready
Ready Ready
Ready

(a) (b)

Figure 2.14: (a) Inductor current and output voltage and (b) the zoomed waveforms with output
current load step from 15A to 10A based on VSCS-MPC of current load.

from the frequency controller and delivered to update the carrier for the PWM signals. This mech-
anism will guarantee the consistency of sampling, triggering of the control and updating of the
PWM. Thus, the discrete frequency bandwidth could avoid a time-varying switching frequency
and improve the system stability. Specifically, an example of the discrete frequency controller to
trigger the sampling and control is shown in Fig. 2.12. It can be seen that the PWM frequency is 6
times greater than the fundamental frequency.

Table 2.1: System Parameters

Parameters Values
Input voltage 100-200 V
Output voltage 0-200 V
Output current 0-20 A
Resistive load 11 Ω
Capacitor 36 𝜇 F
Inductor 20, 110 𝜇 H
Switching frequency 10-100 kHz

26
 60 60
60

40 40
40

20 20
20

0 0
0

-20 -20
-20

120
120 120

100
100 100

80
80 80

0.005
0.005 0.006
0.006 0.007
0.007 0.008
0.008 0.009
0.009 0.01
0.01 0.011
0.011 0.012
0.012 0.013
0.013 0.014
0.014 0.015
0.015 0.0098 0.0099 0.01 0.0101 0.0102 0.0103 0.0104
Ready
Ready
Ready

(a) (b)

Figure 2.15: Inductor current and output voltage waveforms with output voltage reference step
from 100V to 120V based on VSCS-MPC of current load.

60 60

40 40

20 20

0 0

-20 -20

100 100

80 80

60 60

0.005 0.006 0.007 0.008 0.009 0.01 0.011 0.012 0.013 0.014 0.015 0.0098 0.0099 0.01 0.0101 0.0102 0.0103 0.0104
Ready Ready

(a) (b)

Figure 2.16: (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 100V to 80V based on VSCS-MPC of current load.

(a) (b)

Figure 2.17: (a) Inductor current, output voltage and (b) zoomed waveforms with inductor current
reference step from 5A to 8A based on VSCS-MPC of resistive load.

27
 (a) (b)

Figure 2.18: (a) Inductor current, output voltage and (b) zoomed waveforms with inductor current
reference step from 8A to 5A based on VSCS-MPC of resistive load.

(a) (b)

Figure 2.19: (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 50V to 80V based on VSCS-MPC of resistive load.

(a) (b)

Figure 2.20: (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 80V to 50V based on VSCS-MPC of resistive load.

28
 (a) (b)

Figure 2.21: (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 100V to 120V based on PI controller.

(a) (b)

Figure 2.22: (a) Inductor current, output voltage and (b) zoomed waveforms with output voltage
reference step from 100V to 80V based on PI controller.

0.6ms
0.6ms
udc udc

fsw=10kHz fsw=20kHz fsw=10kHz fsw=20kHz

iL iL

io io

(a) (b)

Figure 2.23: VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from 1A to 4A.

29
 0.3ms 0.3ms
udc udc

iL fsw=20kHz fsw=10kHz iL fsw=20kHz fsw=10kHz

io io

(a) (b)

Figure 2.24: VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from 4A to 1A.

(a) (b)

Figure 2.25: VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from 6A to 9A.

(a) (b)

Figure 2.26: VSCS-MPC of resistive load: (a) Output voltage, inductor current, output current
experimental and (b) zoomed waveforms with inductor current reference step from 9A to 6A.

30
 (a) (b)

Figure 2.27: VSCS-MPC of resistive load: (a) Output voltage, inductor current, output current
experimental and (b) zoomed waveforms with output voltage reference step from 50V to 80V.

(a) (b)

Figure 2.28: VSCS-MPC of resistive load: (a) output voltage, inductor current, output current
experimental and (b) zoomed waveforms with output voltage reference step from 80V to 50V.

udc 1.8ms udc 1.8ms

iL fsw=20kHz fsw=20kHz iL fsw=20kHz fsw=20kHz

io io

(a) (b)

Figure 2.29: PI of resistive load: (a) output voltage, inductor current, output current experimental
and (b) zoomed waveforms with output voltage reference step from 50V to 80V.

31
 udc 1.8ms udc 1.8ms

iL fsw=20kHz fsw=20kHz iL fsw=20kHz fsw=20kHz

io io

(a) (b)

Figure 2.30: PI of resistive load: (a) output voltage, inductor current, output current experimental
and (b) zoomed waveforms with output voltage reference step from 80V to 50V.

Figure 2.31: Soft switching performance of upper switch during turn-on and turn-off transients.

Power Inductor
supply

Gate Input
DC
Current
Load Sensors Drivers Capacitors Source
SiC
Output MOSFET
Capacitors Controller
Voltage
Sensors

Figure 2.32: Testbench of multi-phase DC/DC converter.

32
 Efficiency
Efficiency
100%
1

99%
0.99

98%
0.98

97%
0.97

96%
0.96

95%
0.95

94%
0.94
Soft
Series1 switching
Series1
93%
0.93
Hard
Series2 switching
Series2
92%
0.92
200
1 400
2 600
3 800
4 1000
5
Load (W)

Figure 2.33: Efficiency curve comparison of critical soft switching and hard switching.

Loss(W)
Loss(W)
30 30
25 25
20 20
15 15
10 10
5 5
0 0
M1 turn M1 turn on M2 turn M2 M1, M2 M1 turn M1 turn on M2 turn M1, M2 M1, M2
off off conduction conduction off off conduction conduction
(dead (on time) (dead (on time)
time) time)

(a) (b)

Figure 2.34: The switching loss break down distribution comparison of (a) hard switching and (b)
soft switching at 1kW.

2.3 Results

Analytical tests are implemented to verify the proposed controlling method. The simulated and
experimental waveforms of VSCS-MPC and PI results are shown in this section to verify the better
dynamic performance of MPC in maintaining the soft switching operation. Firstly, the VSCS-MPC
is tested with current source load. And the simulation results are shown in Fig. 2.13 to Fig. 2.22.

33
The parameters of the converter are: L=20𝜇H, C=36𝜇F, load=5-20A, 𝑈𝑖𝑛 =100-200V, 𝑢 𝑜 =0-200V.
And the switching frequency ranges are 30k-600kHz. The MPT tool box is used for generating the
piece wise affine search tree [44]. Fig. 2.13 and Fig. 2.14 show the inductor currents and output
voltages with the current load variations from 10A to 15A and 15A to 10A, respectively. From the
zoomed inductor waveforms, it can be seen that the critical soft switching operation is maintained
during the transient period since the ripple currents are remained negative for soft switching turning
on the upper switch. Fig. 2.15 and Fig. 2.16 show the inductor currents and output voltages with
the output voltage reference variations from 100V to 120V and 100V to 80V, respectively. Also
the zoomed inductor waveforms show that the critical soft switching operation can be maintained
during the transient period.
Besides the current source load, the resistive load case is also verified with simulated and
experimental tests. As is shown in Table 2.1, the parameters of the converter are: L=110𝜇H,
C=36𝜇F, load=1-10A, 𝑈𝑖𝑛 =100-200V, 𝑢 𝑜 =0-200V. And the switching frequency ranges are 10k-
100kHz with 10kHz of fundamental frequency. Fig. 2.17 to Fig. 2.20 show the simulated results
of inductor current control and output voltage control with VSCS-MPC. Fig. 2.23 to Fig. 2.28
represent the experimental results of inductor current and output voltage control under various
testing conditions. For the inductor current control, Fig. 2.17 and Fig. 2.18 show the inductor
current reference steps from 5A to 8A and 8A to 5A in simulation. And Fig. 2.23, 2.24, 2.25, 2.26
give the experimental results of inductor current reference step from 1A to 4A, 4A to 1A, 6A to 9A
and 9A to 6A, respectively. For the output voltage control, Fig. 2.19 and Fig. 2.20 show the output
voltage reference steps from 50V to 80V and 80V to 50V in simulation. Fig. 2.27 and Fig. 2.28
represent the output voltage reference steps from 50V to 80V and 80V to 50V, experimentally.
Besides the proposed VSCS-MPC results, the traditional PI controlling method is also tested
for comparison. Fig. 2.21 and Fig. 2.22 show the simulated results of output voltage reference
steps from 100V to 120V and 100V to 80V with PI controller. Fig. 2.29 and Fig. 2.30 represent
the experimental results of output voltage reference steps from 50V to 80V and 80V to 50V with
PI controller.

34
 It can be seen from the VSCS-MPC and PI comparison that there exists oscillation during the
transient period of PI results which means the soft switching is lost. Thus, more hard switching
losses will be generated. Also, the dynamic period of VSCS-MPC is shorter than the PI method.
The transient period of VSCS-MPC is 0.4ms to track the references while PI is 1.8ms. And the
overshoot of PI in transient is higher than VSCS-MPC. The typical soft switching performance
of the upper switch is captured with drain-source voltage and gate-source voltage. The turn-on
and turn-off periods in Fig. 2.31 show that the upper switch is zero voltage turned on. The test
bench is shown in Fig. 2.32 for the validation of the proposed controlling method. The hardware
is designed as a three-phase power converter. Each phase has 2×Wolfspeed C2M0025120D SiC
devices with 25mΩ 𝑅𝑑𝑠,𝑜𝑛 , 2×gate drivers, one phase leg output current sensor. Also, for testing
DC/DC with LC filter, a component board is connected between the converter board and the load.
It includes three phase capacitors, 3 capacitor output voltage sensors and 3 output current sensors.
And the resistive load is composed of three paralleled power resistors, TE1500B33RJ. Each has
33Ω, 1.5kW. Finally, the efficiency curve comparison between critical soft switching and hard
switching is drawn in Fig. 2.33. It can be seen that with the proposed VSCS-MPC method,
the efficiency of the DC/DC converter can reach up to 99%. For further detailed analysis, the
comparison of break down switching loss distribution between soft switching and hard switching
is shown in Fig. 2.34. It can be seen the turn-on loss is much larger than other types of switching
losses and dominates the hard switching which could be avoided by soft switching.

2.4 Summary

This chapter develops a VSCS-MPC method for DC/DC converter. The critical soft switching
boundary conditions are derived. The switching losses are reduced under critical soft switching
operation through discrete frequency controller. An equally segmented frequency bandwidth range
is designed to steadily adjust the switching frequency with constant sampling period. The system
stability is improved due to a fixed sampling frequency. Explicit MPC controller is designed for
tracking the output voltage/current. Because of the fast response and better dynamic behavior of

35
MPC, the hard switching is avoided during transient period compared to the traditional PI controller
and the efficiency is further improved. The system volume is reduced with small inductor by
applying a high switching frequency.

36
 Chapter 3: High Performance Inductor Design Enabling

Critical-Soft-Switching

Electrified energy conversion systems especially for the electric vehicle and more electric air-
plane systems are developing towards the directions of higher power density, higher efficiency and
lower cost. The key components of DC/DC and DC/AC power converters need to be carefully
designed to achieve the goals. A promising method to increase the power density while reducing
the losses is by leveraging the critical soft switching technique. It permits to increase switching
frequency by a factor of 5 and reduce the required inductance by a factor of 20. Thus, the volume
of filtering components can be decreased. However, a large current ripple is required for achiev-
ing critical soft switching operation with high frequency. Thus, the inductor needs to be carefully
designed to handle large current ripple for the critical soft switching.
Inductor has been playing an essential role in the energy conversion system of DC/DC and
DC/AC power converters to filter out the switching-frequency ripple. In a power converter circuit,
the inductor accounts for a significant part of the total power losses. Especially for the application
of high power, high frequency power converters with critical soft switching operation of large
current ripple, the system efficiency is highly related to the electromagnetic performance of the
inductor. Also, the volume of the inductor is crucial to the power density of the energy conversion
system. Thus, the design and optimization of inductor for critical soft switching contributes to the
efficiency and power density of the power converter.
Many references have studied and summarized the magnetic design procedures for power con-
verters [45], [46], [47]. Also some advanced methods such as the Artificial Neural Network (ANN)
[48], [49] or Fuzzy Logic [50] algorithms have been developed. However, there exist deviations
between the theoretical analysis and assembled prototypes, especially in the high frequency/high

37
power applications. The deviations are mainly caused by two factors. First is the structure and spa-
tial layout differences of the core/coil. The topology of the core, winding method of the coil and
even the distance among the conductors will bring differences on the performance of the inductor,
such as inductance, flux density, copper/core losses, etc [51], [52]. Second is the high frequency
electromagnetic behaviors of the coil excited by a high current ripple in the conductor. A high
frequency current excitation will result in significant AC losses which may dominate the whole
copper losses. This AC losses are caused by the skin and proximity effects of the conductors and
are difficult to analyze theoretically [53]. This chapter focuses on the structural optimization of
core and coil to reduce the volume, cost and total losses especially considering the high frequency
copper losses which is barely mentioned in many of the inductor design references.
For the evaluation of inductor design, some key aspects need to be carefully considered such
as the efficiency, volume, fabrication and cost. Firstly, for the efficiency, the inductor losses are
mainly composed of core and copper losses. The core losses are caused by the alternating magne-
tization in a magnetic core which include hysteresis loss and eddy current loss [54]. The selection
of core material influences the core losses. Ferrite core is a desired option for high frequency in-
ductor design considering its low power loss density. Due to the large permeability, the air-gap
is commonly added for a ferrite core to avoid saturation. Based on the targeted frequency range
of 100kHz to 1MHz, ferrite core is selected for the core structure design. The copper losses are
induced by the equivalent resistance of the winding. Using thicker winding could reduce the resis-
tivity of the conductor. Thus the DC copper losses will be reduced. However for the high frequency
current excitations, the skin and proximity effects will result in significant AC losses. The litz type
of conductor could be adopted for reducing the AC losses by winding multiple strands of con-
ductors in parallel [55, 56, 57, 58, 59, 26]. Specifically, [55] and [56] analyze the litz and solid
types of round wire for the inductor thermal behavior. A preliminary litz PCB winding model was
designed in [57] to reduce the AC resistance. [58] and [59] designed two-layer litz PCB inductors
for domestic induction heating and wireless charging coil, respectively. However, multi-layer (>2)
litz PCB winding has not been studied in depth which is addressed in this chapter for a better AC

38
resistance reduction. Secondly, for the consideration of volume and fabrication, different structures
of the core are suitable for various winding method. Considering the PCB winding’s convenience
for manufacturing, fabrication and high space utilization, E cores with PCB windings can combine
dense designs that can be mass-produced. Thirdly, for the cost, the litz wire cost more than the
normal solid wire. However, if PCB is applied for the winding fabrication, the cost will be largely
reduced when demanding a mass-production. So, this chapter developed a litz type of PCB 3D
layout to apply the litz conductor in PCB winding.
This chapter is arranged as following. First part is the theoretical design procedures of inductor
optimization. High current ripple/switching frequency requirements of critical soft switching are
illustrated to specify the targeted application of the design. An iterative optimization method is de-
veloped to find the optimal number of turns, air-gap with the desired operating range of frequency
for the reduction of total losses. The theoretical analysis will provide the guideline of structural
inductor design. Second part is the structural design of core and coil. Based on the analysis in first
part, the specific structures of core and coil are further optimized. For the coil, the high frequency
AC losses are analyzed with the skin and proximity effects. A 3D litz PCB routing method is
developed to emulate the twisted litz wire for the reduction of AC resistance. The ratio of AC to
DC resistance, space utilization between multi-layer litz PCB and solid PCB are analyzed in detail.
For the core, four types of core structure, E-E, E-I, I-I, E-Air (E-A) are developed based on the
window/air-gap space and PCB winding parallelization. The trade-off of different core structures
is illustrated with the combination of litz/solid PCB winding. Two 4-layer neural-network models
are designed to analyze the AC resistance factor of the proposed solid/litz PCB winding. A gen-
eralized PCB-based inductor design method is developed leveraging the neural network model to
reduce the losses. Finally, depending on the theoretical and structural design of core and coil, ten
prototypes are finalized with different combination of E-E/E-I/I-I/E-Air cores and litz/solid PCB
windings. The finalized prototypes are emphasized on different merits of the key factors for induc-
tor design, such as losses, volume and cost, which could provide practical references for industrial
inductor design with various trade off requirements. The experimental results verify the theoretical

39
and structural analysis.

3.1 Theoretical Design

The designed inductor is targeted for critical soft switching converter operating at a high current
ripple. The main purpose of the critical soft switching technique is to reduce the total switching
losses by replacing the large turn-on loss of upper switch with small turn-off loss of lower switch.
Critical soft switching permits to increase switching frequency by a factor of 5, and reduce the
required inductance by a factor of 20. For the total losses of a non-isolated power converter, as is
shown in Fig. 3.1(a) of a DC/DC converter or Fig. 3.1(b) of a three-phase DC/AC converter, the
high current ripple inductor losses on the switch side account for a significant part of the power
conversion losses. The critical soft switching method could be applied by adjusting the current
ripple to certain values which requires the inductance to be designed within a certain range [30],
[42], [60]. So the critical soft switching parameters and loss optimization for inductor design are
performed in this section theoretically.

3.1.1 Critical Soft Switching Parameters

In a buck module of Fig. 3.1(a), the turn-on losses are much higher than the turn-off losses.
A critical soft switching technique could be implemented to replace the large turn-on losses of the
upper switch with small turn-off losses of the lower switch. The principle is to enlarge the current
ripple on the inductor and make sure the peak/valley points of the inductor current is beyond certain
threshold. Thus the current direction of the inductor is bidirectional and the soft switching turn-on
of both switches will be guaranteed [61]. The soft switching waveforms during switching transient
are illustrated in Fig. 3.2. Also, the soft switching turn-on transient of upper switch is shown in
Fig. 3.1(a).
A negative current from the inductor is expected to fully discharge the output capacitor of
upper switch before it is turned on [61]. Thus the large turn-on losses will be minimized by soft
switching. So, the critical soft switching requirements of inductor current are

40
 (a) (b)

Figure 3.1: The inductor design for non-isolated (1) DC/DC and (2) three-phase DC/AC applica-
tions.

Figure 3.2: Gate signals and inductor current for critical soft switching.

𝐼 𝐿,𝑝𝑒𝑎𝑘 ≥ 𝐼𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 (3.1)

𝐼 𝐿,𝑣𝑎𝑙𝑙𝑒𝑦 ≤ −𝐼𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 . (3.2)

In the inductor design perspective of soft switching, the current ripple is the key parameter that
will influence the inductance. And the soft switching requirements of peak/valley inductor currents
limit the range of current ripple. For a general design application, both AC (60Hz) and DC currents
are taken into consideration for the peak/valley inductor currents requirements of soft switching.
The current ripple is the function of switching frequency, inductance and DC voltage

𝑑 (1 − 𝑑)𝑈𝑖𝑛
Δ𝑖 𝐿 = . (3.3)
𝑓𝑠 𝐿

41
 For DC current, the maximum inductance for soft switching can be derived accordingly as

𝑑 (1 − 𝑑)𝑈𝑖𝑛
𝐿 𝑚𝑎𝑥,𝐷𝐶 = min . (3.4)
𝑑 𝑚𝑖𝑛 ≤𝑑≤𝑑 𝑚𝑎𝑥 2(|𝐼 𝐿,𝑎𝑣𝑒 | + 𝐼𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 ) 𝑓𝑠

For AC current, the most critical soft switching operating points of sinusoidal waveforms are
the peak/valley points. The maximum inductance requirement is

𝑑 (1 − 𝑑)𝑈𝑖𝑛
𝐿 𝑚𝑎𝑥,𝐴𝐶 = min √ . (3.5)
𝑑 𝑚𝑖𝑛 ≤𝑑≤𝑑 𝑚𝑎𝑥 2( 2|𝐼 𝐿,𝑟𝑚𝑠 | + 𝐼𝑡ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 ) 𝑓𝑠

According to equation (3.3), the switch side inductor current ripple is largely determined by
the DC bus voltage. For the DC/DC converters in Fig. 3.1(a), the input and output voltage levels
can be selected arbitrarily with the desired power and voltage requirements. However, for the
three-phase DC/AC converter in Fig. 3.1(b), the DC bus voltage is generally depending on the grid
voltage. The typical three-phase grid voltage for the US is line-to-line 480𝑉𝐿−𝐿 which is line-to-
neutral 277𝑉𝐿−𝑁 . And the DC side voltage should be at least twice higher than the AC grid voltage
amplitude which is 783V. Since it is common to configure the DC voltage 10% higher than the AC
voltage limit to avoid duty cycle saturation issue, we designed the DC bus voltage as 850V. For the
current rating of switch side inductor design, a high power DC/AC converter power module with
rated power of 11-13kW requires 16𝐴 𝑅𝑀𝑆 . And based on equation (3.5), the required maximum
ripple current for the designed inductor to handle is 50A. And for the selection of winding gauge
under soft switching operation, the equivalent RMS of current ripple is lower than 30A based on
the the relationship of triangular current ripple peak-to-peak value, 𝐼𝑟𝑚𝑠,𝑡𝑟𝑖𝑎𝑛𝑔𝑙𝑒 , and RMS value,
√
𝐼𝑟𝑚𝑠,𝑡𝑟𝑖𝑎𝑛𝑔𝑙𝑒 : 𝐼𝑟𝑚𝑠,𝑡𝑟𝑖𝑎𝑛𝑔𝑙𝑒 = 𝐼 𝑝−𝑝,𝑡𝑟𝑖𝑎𝑛𝑔𝑙𝑒 / 3. Thus, a gauge 8 wire is capable of handling 40A at 60
◦C according to the AWG Table.

3.1.2 Iterative Optimization

The iterative optimization is based on the soft switching parameters of current ripple, minimum
requirement of inductance, voltage level and power ratings for specific switching frequency. An

42
inductor design optimization method is developed in this section to iteratively sweep the switching
frequency and number of turns for finding the optimal inductor parameters. The theoretical analysis
of the design procedure includes the core selection, coil design, air-gap adjustment and iterative
searching for switching frequency and turn number.

Core selection

The core of the inductor is an essential part that is functioned for magnetization at specific
frequency. The performance of the inductor is largely influenced by the core size and structure.
Some key factors need to be considered for the selection of core: the core losses (including the
hysteresis losses and the eddy current losses), the flux density saturation issues, the area product
(AP) power capability checking.
The core size could be designed based on the AP power capability checking method [46]. The
AP checking method has been developed to evaluate the power capability of the core based on
the comparison of two values: electrical requirements of current and flux density, geometrical
capability of the core, respectively. The electrical requirement, 𝐴𝑃𝑒 is related to the inductance, 𝐿,
peak current, 𝐼 𝑝𝑘 , peak flux density, 𝐵 𝑝𝑘 , current density, 𝐽𝑟𝑚𝑠 , window utilization factor, 𝐾𝑢 and
can be expressed as

2 104
𝐿𝐼 𝑝𝑘
𝐴𝑃𝑒 = . (3.6)
𝐵 𝑝𝑘 𝐽𝑟𝑚𝑠 𝐾𝑢

The geometrical capability of the core, 𝐴𝑃𝑔 is defined as the product of window area, 𝑊𝑎 , and
effective cross section area, 𝐴𝑐 ,

𝐴𝑃𝑔 = 𝑊𝑎 𝐴𝑐 . (3.7)

In the iterative optimization procedure of inductor design, the AP checking is implemented in

each round to check the power handling capability of the core for specific peak current, peak flux
density and inductance. If the calculated 𝐴𝑃𝑒 is equal or less than the 𝐴𝑃𝑔 , the design parameters

43
are regarded as effective. Otherwise, bigger core or combining more cores in parallel should be
implemented to increase the core volume, 𝑉𝑐𝑜𝑟𝑒 , and 𝐴𝑃𝑔 for the satisfaction of AP checking.

Coil and air-gap design

For the coil design of the inductor, the number of turns, 𝑁, combined with the air-gap, 𝑙 𝑔 ,
determines the inductance. The cross section area and the length of the coil conductor influences
the copper losses. Thus, the number of turns, air-gap and cross section area are the three key factors
that need to be considered in coil design [62], [63].
In an air-gaped inductor, the inductance could be derived as

4𝜋𝑁 2 𝐴𝑐 10−4
𝐿= 𝐹 𝑓 𝑟𝑖𝑛𝑔𝑒 (3.8)
𝑙 𝑔 + (𝐿 𝑀 𝑃𝐿 /𝜇𝑟 )

where 𝐿 𝑀 𝑃𝐿 , 𝜇𝑟 are the magnetic path length, relevant permeability and 𝐹 𝑓 𝑟𝑖𝑛𝑔𝑒 represents the
fringing effect that can be expressed as

𝑙𝑔
𝐹 𝑓 𝑟𝑖𝑛𝑔𝑒 = √ 𝑙𝑛(2𝑊ℎ /𝑙 𝑔 ) + 1 (3.9)
𝐴𝑐

where 𝑊ℎ is the window height.

The total losses of the inductor, 𝑃𝑡𝑜𝑡𝑎𝑙 , are composed of core losses, 𝑃𝑐𝑜𝑟𝑒 , and copper losses,
𝑃𝑐𝑜 𝑝 𝑝𝑒𝑟 . And the copper losses are the sum of DC losses, 𝑃 𝐷𝐶 , and AC losses, 𝑃 𝐴𝐶 [64]

𝑃𝑡𝑜𝑡𝑎𝑙 = 𝑃𝑐𝑜𝑟𝑒 + 𝑃𝑐𝑜 𝑝 𝑝𝑒𝑟 = 𝑃𝑐𝑜𝑟𝑒 + 𝑃 𝐷𝐶 + 𝑃 𝐴𝐶 . (3.10)

The core losses are calculated by the Steinmetz’s equation with frequency, 𝑓𝑠𝑤 , peak flux den-
sity, 𝐵 𝑝𝑘 , and the coefficients, 𝑎, 𝑏 and 𝑘

𝑎
𝑃𝑐𝑜𝑟𝑒 = 𝑘 · 𝑓𝑠𝑤 · 𝐵 𝑏𝑝𝑘 . (3.11)

The peak flux density, 𝐵 𝑝𝑘 , is expressed with the turn number, 𝑁, peak inductor current, 𝐼 𝑝𝑘 ,

44
 (a) (b) (c)

Figure 3.3: The distribution of (a) wire (b) PCB and (c) foil coils in E core window.

magnetic path length, 𝐿 𝑀 𝐿𝑇 , and permeability, 𝜇𝑟 ,

4𝜋𝑁 𝐼 𝑝𝑘 10−2
𝐵 𝑝𝑘 = . (3.12)
𝑙 𝑔 + (𝐿 𝑀 𝑃𝐿 /𝜇𝑟 )

The copper losses can be derived in detail as

2 2
𝑃𝑐𝑜 𝑝 𝑝𝑒𝑟 = (𝐼 𝐷𝐶 + 𝐼 𝐴𝐶,𝑟𝑚𝑠 )𝑅 𝐷𝐶 𝑅𝐹 (3.13)

where 𝐼 𝐷𝐶,𝑟𝑚𝑠 and 𝐼 𝐷𝐶,𝑟𝑚𝑠 are the DC and AC components of RMS currents. 𝑅 𝐷𝐶 is the DC
resistance which is relevant to the mean length per turn, 𝐿 𝑀 𝐿𝑇 , number of turns, 𝑁, cross section
area, 𝐴, and resistivity, 𝜌, of the coil conductor in (3.14). 𝑅𝐹 is the ratio of AC and DC resistance
called resistance factor. However, the AC resistance, 𝑅 𝐴𝐶 = 𝑅 𝐷𝐶 𝑅𝐹, is a much more complex
variable that depends on the frequency, coil structure and routing method and will be analyzed in
next section.

𝜌𝑁 𝐿 𝑀 𝐿𝑇
𝑅 𝐷𝐶 = (3.14)
𝐴

45
Turn number and air-gap adjustment

The adjustments of turn number and air-gap mainly aim at avoiding saturation and tuning the
inductance as is shown in (3.8) and (3.12). In the optimization procedure of inductor design,
the number of turns are swept from the maximum allowable value to find the minimum inductor
losses. In the mean time, the air-gap is adjusted accordingly to maintain a desired inductance. The
maximum allowable turn number, 𝑁𝑚𝑎𝑥 , is restricted by the window area, 𝑊𝑎 , and the cross section
area of the coil conductor. The derivation of 𝑁𝑚𝑎𝑥 is different for the wired coil and PCB coil in
Fig. 3.3. For the wired coil with diameter of 𝑑

𝑊𝑤 (2𝑊ℎ + 𝑙 𝑔 )
𝑁𝑤𝑖𝑟𝑒,𝑚𝑎𝑥 = . (3.15)
𝑑 𝑑

For the PCB coil with thickness of ℎ and length of 𝑙 𝑃𝐶 𝐵

𝑊𝑤 (2𝑊ℎ + 𝑙 𝑔 )
𝑁 𝑃𝐶𝐵,𝑚𝑎𝑥 = . (3.16)
𝑙 𝑃𝐶 𝐵 ℎ

For both wired and PCB coil inductors in (3.15) and (3.16), 𝑊𝑤 and 𝑊ℎ are the window width and
height, respectively.

Iterative Searching

For the iterative searching of the inductor optimization, the number of turns is swept to find
the minimum inductor losses at each operating point of desired switching frequency. Specifically,

Table 3.1: High frequency high power inductor design parameters

Parameter Values
DC bus voltage 850V
AC RMS current 16A
AC current ripple 50A
Switching frequency range 100kHz-1MHz
Core volume 0.011L
Winding gauge AWG8

46
at each frequency point, the turn number is swept from the largest allowable value to find the
optimal turn number for minimum inductor losses while checking the saturation issue of the flux
density. Thus, at each frequency value, the optimal values of turn number, airgap, core/copper
losses, inductance and peak flux density are derived for the following sections of structural design.
The theoretical design algorithm of flow chart is shown in Fig. 3.4. The theoretical inductor
optimization is calculated based on the high frequency high power critical soft switching converter
with the parameters in table 3.1 where the switching frequency is swept from 100kHz to 1MHz. At
each switching frequency point, the optimal turn number, airgap, inductor losses, inductance and
peak flux density are derived to achieve the minimum inductor losses. The E42/21/20-3F36 from
Ferroxcube is chosen as the core cell which is a kind of ferrite material. It is a medium to high
frequency power material suitable for a frequency ranged from 500kHz to 1MHz. And it has low
power loss density at a wide temperature range from 25 to 100 ◦ C. The design algorithm is aimed at
optimizing the inductor parameters at every specific frequency point. And the maximum frequency
point (1MHz) could be chosen as the most strict condition which will be feasible to be applied to
any of the lower frequency range without violating the 𝐵𝑚𝑎𝑥 and AP checking. Specifically, the
turn number, air-gap, inductance at 1MHz could be picked as the optimal parameters to operate in
the lower frequency ranges. The optimization results of inductor design parameters at 1MHz are
shown in table 3.2.

Table 3.2: Theoretical inductor design results at 1MHz

Parameter Values
Frequency 1MHz
Turn number 10
Air gap 1.38 cm
Core loss 15.3 W
Copper loss 24.1 W
Inductance 4.1 𝜇H
Peak flux density 0.2 T

47
 Figure 3.4: Round wire winding inductor design flowchart.

3.2 Structural Optimization

The geometrical structure of the inductor is an essential part that will influence the electrical and
magnetic performances. This section covers both the coil structure and core geometrical topology.
Specifically, for the coil structure design, different types of coil including litz PCB, solid PCB,
litz wire, solid wire are taken into account for the considerations of high frequency AC losses,
space utilization. A 3D litz PCB routing method is developed for PCB application of litz wire.
For the core geometrical topology design, three types of core structures, E-E, E-I and I-I cores
are analyzed and compared based on the window area and air-gap for the coil space utilization.
Finally, considering different merits of trade off, three optimal prototypes are derived, fabricated
and validated.

48
3.2.1 Coil Structure Design

The high frequency AC losses are analyzed in a solid coil conductor. For the reduction of AC
losses, a 3D litz PCB routing method is developed with n layers of PCB board to emulate the litz
wire. The comparison of litz and solid PCB coil is derived with high resolution FEA simulation.

High frequency AC loss analysis

The copper losses are generated by the coil conductor which include DC losses and AC losses
as is shown in (3.13). The DC, AC rms currents and DC resistance, 𝐼 𝐷𝐶,𝑟𝑚𝑠 , 𝐼 𝐴𝐶,𝑟𝑚𝑠 and 𝑅 𝐷𝐶 ,
could be directly derived mathematically. However, the AC resistance, 𝑅 𝐴𝐶 , is complicate to
derive theoretically, especially in the high frequency applications. The Dowell’s equation could
be applied to estimate the AC resistance [53], [64], [65], [66]. To analyze the AC losses of the
conductor geometrically, the traditional coil structure could be mainly divided into rectangular foil
solid conductor, round wire solid conductor and round wire litz conductor. The complexity of
estimating the AC resistance results from the factors of skin effect and proximity effect.
The skin effect is induced by the internal current of the conductor which generates a magnetic
field that makes the current density lower in the center and higher in the surface. On the other
hand, the proximity effect is induced by the adjacent conductors that produce magnetic fields and
influence the current density distribution: higher in the outer wire and lower in the inner wire. Thus,
both the skin and proximity effects will distort the current density distribution of the conductor and
the AC resistance will be increased by the rise of frequency.
In PCB solid winding conductor, the AC resistance can be derived in (3.17) as

𝐿 𝑃𝐶 𝐵 ℎ 𝑠𝑖𝑛ℎ(ℎ/𝛿) + 𝑠𝑖𝑛(ℎ/𝛿) 1
𝑅 𝐴𝐶,𝑃𝐶 𝐵 = 𝑅𝑠𝑘𝑖𝑛 + 𝑅 𝑝𝑟𝑜𝑥 = ( ) + ℎ𝑤 2 𝜎𝐵𝑛2𝑊 3 (3.17)
2𝜎𝑊 ℎ 𝛿 𝑐𝑜𝑠ℎ(ℎ/𝛿) − 𝑐𝑜𝑠(ℎ/𝛿) 12

where 𝐿 𝑃𝐶 𝐵 , ℎ, 𝑊, 𝛿, 𝜎, 𝑤, 𝐵𝑛 are the length, thickness, width, skin depth, conductivity, angular
frequency, average external magnetic field of the PCB winding.

49
 In rectangular foil solid conductor, the AC resistance can be derived in (3.18)

𝑙𝑤 𝑚 ′ 2 2 2 ′
𝑅 𝐴𝐶, 𝑓 𝑜𝑖𝑙 = [𝜁1 + 𝜂𝑤 (𝑚 − 1)𝜁2 ] (3.18)
𝛿𝜎ℎ𝑤 3
′
where 𝜁1 is the skin effect factor

′ ′
′ 𝑠𝑖𝑛ℎ(2Δ ) + 𝑠𝑖𝑛(2Δ )
𝜁1 = ′ ′ (3.19)
𝑐𝑜𝑠ℎ(2Δ ) − 𝑐𝑜𝑠(2Δ )
′
and 𝜁2 represents the proximity effect factor

′ ′
𝑠𝑖𝑛ℎ(Δ ) − 𝑠𝑖𝑛(Δ )
′
𝜁1 = ′ ′ . (3.20)
𝑐𝑜𝑠ℎ(Δ ) + 𝑐𝑜𝑠(Δ )
′
Δ is the revised penetration ratio and is expressed as

√︂
′ ℎ𝑤 𝑑𝑤
Δ = . (3.21)
ℎ𝑐 𝛿

𝑚, 𝛿, 𝑙 𝑤 , 𝜎, ℎ𝑤 , ℎ𝑐 , 𝑑 𝑤 are the layer number, skin depth, layer mean length, material conductivity,
layer width, core window size and foil conductor thickness, respectively.
In round wire solid conductor, the AC resistance can be derived based on the Dowell’s equation
in (3.22)

√︁
𝑙 𝑤 𝑚𝑁 ′ 2 𝜋/4𝑑𝑁 2 2 ′
𝑅 𝐴𝐶,𝑤𝑖𝑟𝑒 = √︁ [𝜁1 + ( ) (𝑚 − 1)𝜁2 ] (3.22)
𝛿𝜎 𝜋/4𝑑 3 ℎ𝑤

where 𝑑, 𝑁 are the diameter and turn number of the round wire solid coil.
The mathematical calculation for PCB, foil and round conductor AC resistance are based on the
parameters in Fig. 3.3.
The AC resistance is highly relevant to the frequency of the current excitation and a higher fre-
quency will result in a thinner skin depth, 𝛿, which is derived by resistivity, 𝜌, switching frequency,
𝑓𝑠𝑤 , and permeability, 𝜇

50
 √︂
𝜌
𝛿= . (3.23)
𝑓𝑠𝑤 𝜋𝜇
′
This skin depth, 𝛿, will affect the revised penetration ratio, Δ , in (3.21) and thus influence the
′ ′
skin and proximity effect factors, 𝜁1 , 𝜁2 , in (3.19) and (3.20). Finally, the AC resistance will be
increased with the rise of frequency as is shown in (3.18) for foil conductor and (3.22) for round
conductor, respectively.
Due to high AC resistance of solid conductor, the AC copper losses could be increased signif-
icantly in high switching frequency power converter filtering system. The resistance factor 𝑅𝐹,
defined as the ratio of AC and DC resistance, can be applied to describe the performance of copper
losses for specific coil.

𝑅 𝐴𝐶
𝑅𝐹 = (3.24)
𝑅 𝐷𝐶

According to (3.18) and (3.22), the penetration ratio, switching frequency and number of turns/layers
are the dominating factors that affect the resistance factor. A typical option to eliminate the AC
resistance is by replacing the round solid wire with litz wire. Litz wire is fabricated by twist-
ing multiple stranded wires to reduce the skin and proximity effects. For the skin effect, because
each strand has much smaller cross section area, the influence of skin depth turns to be negligi-
ble compared to the current conducting diameter. For the proximity effect, the evenly distributed
spiral strands could counteract the magnetic fields in adjacent strands. So, the proximity effect
will be largely reduced. Thus, in strand level of each bundle, both skin and proximity effects are
decreased effectively with litz structure. For stacked layers or multiple turns of the coil, the bundle
level skin and proximity effects could also result in extra AC losses due to the adjacent bundles of
wire. Despite of the bundle level effect, the litz wire is superior than solid wire in the aspect of AC
losses.
In litz winding conductor, the AC resistance can be derived as [67]

51
 4𝑙 𝑤 𝑚𝑁 𝜁 𝜋2 𝑛𝑠 𝑝 𝑓 24
𝑅 𝐴𝐶,𝑙𝑖𝑡𝑧 =√ [𝜓1 (𝜁) − (16𝑚 2 − 1 + 2 )𝜓2 (𝜁)] (3.25)
2
2𝑛 𝑠 𝜎𝜋𝑑 𝑠 24 𝜋

where 𝑚, 𝑁, 𝑙 𝑤 , 𝑛 𝑠 , 𝑑 𝑠 , 𝜁 are the layer number of the winding, turn number of litz wire per layer,
number of strands per bundle and strand diameter, respectively. The variables of 𝜓1 (𝜁) and 𝜓2 (𝜁)
are the skin effect and proximity effect losses which are expressed as Bessel functions and can be
derived by a Talyor-series expansion [67]

√ 1 1
𝜓1 (𝜁) = 2 2(𝜁 + 8 𝜁 3 − 14 𝜁 5 + ...) (3.26a)
32 32
√ 1 3 1 7
𝜓2 (𝜁) = 0.5 2(− 5 𝜁 + 12 𝜁 + ...). (3.26b)
2 2

3D litz PCB routing method for AC losses reduction

Although litz wire could reduce the AC losses significantly, the cost and insulation restrict the
litz wire from wide application because each strand of the bundle inside the litz wire needs to be
insulated. On the other hand, the PCB winding has the merits of inherent insulation capability,
convenience of assembly and high window space utilization. This chapter develops a 3D litz PCB
routing method to combine the advantages of both litz wire and PCB winding. The method is
designed by applying the litz structure of round twisted wire to PCB routing for multiple layers.
The 3D routing method is aimed at emulating the twisted litz wire by following two principles:
(a) Each of the strand in the PCB board should go through all the layers evenly and spirally to
counteract the adjacent magnetic field; (b) The length of each strand should be equivalent to avoid
uneven magnetic field among different strands.
Thus, a routing method is implemented in Fig. 3.5 which could be extended and applied to
arbitrary number of strands and layers for a better emulation of round litz wire. Specifically,
starting from the top-right corner of the figure, each strand will be spirally and evenly routed

52
 (a) (b)

(c)

Figure 3.5: (a) 3D litz PCB routing method, 3D view of (b) separated and (c) integrated routing
example.

through all layers of the PCB board. To achieve this goal, the litz PCB is composed of six types of
routing modes: left-right, right-left, external-via-up, external-via-down, internal-via-up, internal-
via-down. The left-right and righ-left modes are the wires that are routing directly from side to side
of certain copper layer. The external-via-up and external-via-down are the vias that are distributed
on both sides of PCB edges to connect between adjacent copper layers. If more than 4 layers are
designed for the PCB, the internal-via-up and internal-via-down will be added which are the vias
distributed inside the PCB away from the edges to connect between adjacent copper layers.

Litz PCB design procedure

Based on the 3D litz PCB routing method, a specific litz PCB winding design procedure is
shown in this subsection which includes the routing method, copper thickness, strand number,
trace width and layer number.
Firstly, the thickness of the PCB copper layer, 𝑡 𝑃𝐶 𝐵 , is designed according to the skin depth
equation in (3.23). To avoid the conductor being influenced by the skin effect from both top and

53
 (a) (b)

(c) (d)

Figure 3.6: Four types of litz PCB routing structures with different strand number and trace width:
(a) Litz PCB 4×7 Strands, 16mils trace width (b) Litz PCB 4×10 Strands, 8mils trace width (c)
Litz PCB 4×2×5 Strands, 8mils trace width and (d) Litz PCB 4×16 Strands, 5mils trace width.

bottom surfaces of the PCB winding, the thickness of copper trace should be less than twice of the
skin depth

𝑡 𝑃𝐶 𝐵 ≤ 2𝛿. (3.27)

The targeted maximum switching frequency is 1MHz. Given the resistivity of copper and the tar-
geted maximum switching frequency, the skin depth is calculated as 0.0652mm. So, the thickness
of the PCB copper layer should be less than twice of the skin depth which is 0.1304mm. Because
the fabrication of PCB copper thickness is measured with ounce, 3oz (0.1067mm) is the most

54
 1.5
4x7 strands
1.4

Resistance Factor
1.3
4x2x5 strands
1.2
4x16 strands
1.1
4x10 strands
1
0 200 400 600 800 1000
Frequency (kHz)
4x7 strands 4x10 strands 4x2x5 strands 4x16 strands

(a)

9
Solid 16 layers
8
7 Solid 12 layers
Resistance Factor

6
5 Solid 8 layers

4 Litz 4x4 layers

3 Litz 4x3 layers

Solid 4 layers
2 Litz 4x2 layers
1 Litz 4x1 layers
0
0 200 400 600 800 1000
Frequency (kHz)
litz 4x1 layers litz 4x2 layers litz 4x3 layers litz 4x4 layers
Solid 4 layers Solid 8 layers Solid 12 layers Solid 16 layers

(b)

Figure 3.7: Comparison of resistance factor with different frequencies (a) for a single PCB with
different combinations of strand number and trace width (b) for different stacked number of the
desired 4x10 strand type of litz PCB and solid PCB structures.

satisfied thickness option.

Secondly, the number of strand, 𝑁 𝑠 , and trace width per strand, 𝑊𝑠 , are the two key parameters
that need to be designed. These two parameters influence the proximity effect and window space
utilization. A suitable combination of strand number and trace width could result in lower resis-
tance factor thus lower AC losses, especially, when multiple layers of PCB need to be stacked for

55
the coil fabrication. Theoretically, the more number of strand and the thinner trace width, the less
AC resistance will be induced. However, there exist the restriction of PCB minimum trace width
and window space utilization. The minimum trace width per strand is restricted by the minimum
diameter of the via hole, 𝑑 ℎ,𝑚𝑖𝑛 . The minimum spacing between adjacent strands in the same layer
is restricted by the minimum outer diameter of the via, 𝑑𝑣,𝑚𝑖𝑛 . And the number of strands per layer
will be defined by the core window width, 𝑊𝑤 , strand trace width, 𝑊𝑠 , and trace spacing, 𝑆𝑡 . The
combination of (𝑁 𝑠 , 𝑊𝑠 ) could be designed iteratively starting from the minimum requirement of
via size and window width to find the optimal resistance factor

(𝑁 𝑠 , 𝑊𝑠 ) 𝑜 𝑝𝑡𝑖𝑚𝑎𝑙 = argmin 𝑅𝐹 (𝑁 𝑠 , 𝑊𝑠 , 𝑆𝑡 ) (3.28)

(𝑁 𝑠 ,𝑊𝑠 )

where 𝑁 𝑠 ranges from 0 to 𝑊𝑤 /(𝑑 ℎ,𝑚𝑖𝑛 + 𝑑𝑣,𝑚𝑖𝑛 ). The strand number could be swept with a certain
step to iteratively find the optimal resistance factor with reasonably tuned values of strand width
and trace spacing.
The core E42/21/20 with a window width of 9mm from Ferroxcube is taken as an example for
the design of litz PCB winding. Four types of routing structures with different strand number and
trace width are designed and simulated with high resolution FEA analysis in ANSYS. The PCB
is set to be four layers with different combinations of (strand number, trace width) as is shown in
Fig. 3.6: (4×7 Strands, 16 mils), (4×10 Strands, 8 mils), (4×2×5 Strands, 8 mils), (4×16 Strands,
5 mils). In each of the subfigure, a small length of four-layer litz PCB routing structure is shown
and the current is expected to flow from left-bottom of the input terminal to the right-top of the
output terminal.

Table 3.3: High Frequency Behavior Comparison of Litz PCB

Parameter 4×7 4×10 4×2×5 4×16
AC loss (mW) @60Hz 108.4 154.1 154.9 149.4
AC loss (mW) @500kHz 134.1 163.4 177.5 167.4
AC loss (mW) @1MHz 160.4 176.5 192.5 181
RF=Rac/Rdc (pu) @500kHz 1.24 1.06 1.15 1.12
RF=Rac/Rdc (pu) @1MHz 1.48 1.14 1.24 1.21

56
 From Fig. 3.6(a) to 3.6(d), the strand number is increased from 28 to 64. Accordingly, due
to the core window width limitation, the trace width per strand is reduced from 16 mils to 5 mils.
Specifically, in Fig. 3.6(a), 3.6(b) and 3.6(d), the single bundle types of spirally twisted litz PCB
are designed with different strand numbers. Also, in Fig. 3.6(c), 5 bundles of strands are twisted
respectively and connected in parallel as a whole in which each bundle has 8 strands. The AC
losses and resistance factors of the four structures are listed in Table 3.3 and Fig. 3.7(a) to analyze
the skin/proximity effects on the proposed litz PCB. From the illustrated results, the (4×10 Strands,
8 mils) litz routing structure has the smallest resistance factor which is more suitable for the high
frequency application especially when stacking multiple PCB boards to form a specific number of
turns for inductor winding.
The via to be applied in the litz PCB winding design is hollow type with outer and inner
diameters of 12mil and 6mil, respectively. The high frequency loss model of the via is also built
with ANSYS to analyze the impact of via on losses. The loss per via at 500kHz, 25A current is
25.63𝜇W. For a piece of litz winding, there are totally 54 vias including 10, 8 on the two shorter
sides, 18 on both longer sides. They are connected in parallel within each side and in series among
the four sides. Thus, the total losses induced by the via is 8.61𝜇W which is 0.005% of the litz PCB
AC losses and can be neglected.

Litz PCB vs. solid PCB

Considering the final inductor prototype, multiple turns of coil requires the litz PCB to be
stacked for multiple layers. Thus the proximity effect will dominate the copper losses and the
resistance factor will be increased with the stacked layer number. In this subsection, the litz PCB
is compared with solid PCB coil in the aspects of copper losses and resistance factor at different
frequency. Also, the number of stacked PCB layers are taken into account for the AC resistance
analysis. Based on the results in Fig. 3.7(a), (4×10 Strands, 8 mils) litz routing structure is chosen
as the optimal litz winding solution for the core of E42/21/20 due to the least resistance factor.
Also, a solid PCB winding layer with the same 3D sizes as the litz PCB layer is selected for

57
 Figure 3.8: 3D view of a four layer, 40 strand litz PCB design.

comparison. To analyze the resistance factor performance of different number of stacked solid
or litz PCB layers, 4, 8, 12 and 16 layers of litz and solid PCB windings are simulated with the
same current excitation under different frequencies. The resistance factors of the 8 types of PCB
winding cases are plotted in Fig. 3.7(b) with frequency ranged from 100 kHz to 1 MHz. The results
show that the designed litz PCB winding structure has 2 to 3 times lower resistance factor than the
solid PCB at the same number of stacked layers. Thus, the AC copper losses of the litz PCB is
lower than the solid PCB proportionally. For the E core setup, the 3D view of the proposed 4
layer litz PCB winding and the top views of each layer are shown in Fig. 3.8 and 3.9, respectively.
What is noteworthy is that the four right angle corners of the litz PCB layout are designed as solid
structure because the principle of litz routing requires the length of each strand to be equivalent
to avoid uneven magnetic field. The solid design of winding corners guarantees that all the traces
between two solid corners have the same length despite the diagonal lines may reach the edges.
Since whenever a trace reaches the edge, the via will help the trace switch the layer and go towards
another symmetric diagonal direction. For the terminal of the traces in Fig. 3.8 and Fig. 3.9, solid
terminal pads and castellated holes are designed to connect among PCB winding boards. These
castellated holes help to mount one PCB windng board on top of another during assembly. Such
holes provide proper alignment between the winding boards while soldering. Thus, the terminal
pads and castellated holes contribute to the balancing of winding length for every turn.

58
 (a) (b)

(c) (d)

Figure 3.9: (a) Top layer (b) second layer (c) third layer and (d) bottom layer of litz PCB design in
top view.

3.2.2 Core Structure Design

This section discusses the core structure design based on the E core topology which is con-
venient for combined fabrication with PCB winding. A commercially available E core cell of
E42/21/20 is used for the core structure design which is consistent with the theoretical design of
core selection. Four types of core structures are developed based on the emphasis of different mer-
its among the trade-offs of volume, cost and losses. The four core structures are: EE, EI, II and EA
cores which have been shown in Fig. 3.10. Specifically, EE, EI, II are composed of two E cores,
one E core and one I core, two I cores, respectively. The air gap of these three core structures could
be adjusted by inserting different height of resin in the middle of the three legs. For the EA (E-Air)
core, the airgap is not flexible and is mainly determined by the window width since the structure is

59
 (a) (b)

(c) (d)

Figure 3.10: Four types of core structures: (a) EE core (b) EI core (c) II core and (d) EA core.

open on top side without close loop flux path of magnetic material above the E core.

Core structure design based on window/airgap space and winding parallelization

The high resolution design is implemented in ANSYS for validating the proposed four core
structures. For each structure, different airgap values or winding heights are simulated with differ-
ent number of turns to derive the suitable inductance for critical soft switching with optimal core
losses and peak flux density. Based on the soft switching requirements of inductance and current
ripple in equations (3.4) and (3.5), the targeted inductance is 4𝜇H. The simulated results of the four
types of cores are shown in table 3.4. In each type of the EE, EI and II core structure, different turn

60
 Figure 3.11: The analysis of magnetic flux paths for different core structures.

numbers are constructed and swept with different airgap values to derive the optimal inductance,
core losses and peak flux density. For the EA core, since the airgap is not adjustable, the total
winding height is tuned for the adjustment of inductance. Specifically, table 3.4 shows the derived
optimal setup parameters of four core structures and the flux density distributions after simulating
different airgaps/winding heights and turn numbers for each type of the core based on the same
current excitation of 50A peak-peak and frequency of 500kHz and 1MHz.

Table 3.4: Four core structures design results by sweeping the air gap or winding height and turn
number
Core type EE EE EE EI EA II
Turn number 10 6 4 4 5 8
Air gap (mm) 14 3 1 1.2 - 8
Winding height (mm) - - - - 5.8 -
𝑃𝑐𝑜𝑟𝑒 (W) @0.5MHz 1.9 4.6 11.6 7.2 2.7 0.4
𝑃𝑐𝑜𝑟𝑒 (W) @1MHz 9.7 23.6 49.4 28.5 13.8 2
Inductance(𝜇H) 4.3 4.2 4.1 4.1 4.2 4.1
𝐵 𝑝𝑘 (T) 0.37 0.36 0.38 0.34 0.48 0.08

61
Core structure trade off analysis

The four types of core structures are designed considering different emphasis of merit trade-
offs. The EE core costs more on the core material and has the largest volume. But the window
height is the biggest which means more winding could be stacked in parallel to decrease the coil
resistance and copper losses. II core has the smallest volume but the airgap is limited by the
height of the winding coil which means the airgap needs to be no less than the coil height. Thus,
the number of turns and airgap need to be carefully designed to support the desired inductance
especially when considering to parallel winding coil for the reduction of copper losses. The EI
core is a trade-off between the EE and II cores in the aspect of volume cost and copper losses.
Lastly, for the EA core, the airgap is restricted by the open area on top of the E core. Specifically,
the flux path can only go through the window width on top to finish the flux loop. Thus, the
winding coil could not exceed the window upper side and the airgap is not as flexible as the other
three structures. However, EA core saves half of the magnetic material which means the cost is the
least. To better illustrate the flux paths of the four core structures with different airgap formations,
the magnetic flux paths are shown in Fig. 3.11. The green solid arrows are the flux paths in
the core and the red dotted arrows represent the flux paths in the airgap. Thus, the flexibility of
adjusting airgap between EE, EI, II and EA could be seen perceptually in which the EA core has
an approximately constant airgap of the window width.
For the influences of different core structures and the fringing effect on the inductor perfor-
mance, three cases of inductor structure are simulated in ANSYS (under same turn number, airgap,
current excitation) for validation: (1) EE core; (2) EI core with winding evenly distributed in the
window; (3) EI core with winding distributed away from the airgap. The flux density and current
density distributions of the three inductor cases are plotted in Fig. 3.12. The inductance, core
losses are simulated as follows: case (1) Core Loss@500kHz: 4.6W, Core Loss@1MHz: 14W,
L=4.4uH; case (2) Core Loss@500kHz: 4.7W, Core Loss@1MHz: 17W, L=4.6uH case (3) Core
Loss@500kHz: 5.3W, Core Loss@1MHz: 19W, L=4.9uH. Thus, from the ANSYS comparison of
cases (1) and (2), the EE or EI core difference does not influence too much of the inductor con-

62
figuration. From the ANSYS comparison of cases (2) and (3), the fringing effect caused by the
distance between the winding and airgap does not have obvious effect on the inductor behavior.

EE core Evenly winding EI core Unevenly winding EI core

Figure 3.12: Analysis of EE/EI core inductor performances with different winding distributions.

(a)

(b)

Figure 3.13: Four-layer neural network model for resistance factor of the proposed (a) litz and (b)
solid PCB winding.

63
3.2.3 Neural Network Modeling of Litz/Solid PCB Structure

Neural network design

For the analytical modeling of AC losses in the litz/solid PCB winding, two 4-layer neural
network models are built to analyze the resistance factors of the proposed litz/solid PCB winding
under different design parameters. For the structure of the neural network, the 4-layer model
consists of input layer, two hidden layers and output layer as is shown in Fig. 3.13.
Firstly, for the input layer, the key factors that could affect the resistance factor of litz PCB
winding are strand number, 𝑁 𝑠 , trace width, 𝑊𝑠 , trace thickness, 𝑡 𝑃𝐶 𝐵 , layer number, 𝑁𝑙 , and
frequency, 𝑓𝑠𝑤 . The trace thickness could be determined by equation (3.27) to minimize the skin
effect. Thus, 4 variables are configured as the input of the litz PCB neural network model including
strand number, trace width, layer number and frequency. For the solid PCB winding, only trace
width, layer number and frequency are needed for the input variables. Secondly, two hidden layers
are designed to approximate smooth mapping for high accuracy. Different number of neurons are
configured to optimize the training and testing losses. Table 3.5 shows the testing losses of the 4-
layer neural network with different combinations of neuron number from 2 to 6 in the two hidden

102
Train Train
Validation Validation
0
Mean Squared Error (mse)
Mean Squared Error (mse)

10 Test Test
Best Best
100

10-2
10-2

10-4 10-4

0 5 10 15 0 50 100 150
Epochs Epochs

(a) (b)

Figure 3.14: Training and testing losses of the (a) litz and (b) solid PCB winding neural network
model.

64
layers where the losses are defined by Mean Squared Error (MSE) to assess the performance of the
model. Based on the size of training data and input/output variables, (4, 4) and (4, 2) of neuron
number combinations in the two hidden layers can achieve minimum losses of 1.2e-4 and 4.6e-4
for litz PCB and solid PCB models, respectively. Lastly, for the output layer, the resistance factor
is the output of the neural network model for the analysis of litz/solid PCB winding AC losses.
The formulation of the neural network consists of the following five parts: (1) input values,
𝑥(𝑘) (𝑘=1,...,𝑁1 , 𝑁1 =3 for three input variables of solid PCB model, 𝑁1 =4 for 4 input variables of
litz PCB model); (2) hidden layer values, ℎ1 (𝑘) (hidden layer 1 neurons, 𝑘=1,...,𝑁2 , 𝑘 denotes 𝑘-th
hidden layer 1 neuron), ℎ2 (𝑘) (hidden layer 2 neurons, 𝑘=1,...,𝑁3 , 𝑘 denotes 𝑘-th hidden layer 2
neuron); (3) output value, 𝑦(𝑘) (𝑘=1,...,𝑁4 , 𝑘 denotes 𝑘-th output layer neuron); (4) weight, 𝑊2𝑚𝑛
(weight from 𝑚-th input neuron to 𝑛-th hidden layer 1 neuron), 𝑊3𝑚𝑛 (weight from 𝑚-th hidden
layer 1 neuron to 𝑛-th hidden layer 2 neuron), 𝑊4𝑚𝑛 (weight from 𝑚-th hidden layer 2 neuron to
𝑛-th output layer neuron); (5) bias, 𝐵2 𝑘 (bias of 𝑘-th hidden layer 1 neuron), 𝐵3 𝑘 (bias of 𝑘-th
hidden layer 2 neuron), 𝐵4 𝑘 (bias of 𝑘-th output layer neuron).
The input values, 𝑥(𝑘), can be imported as [𝑁 𝑠 ; 𝑊𝑠 ; 𝑁𝑙 ; 𝑓𝑠𝑤 ] for litz PCB model and [𝑊𝑠 ; 𝑁𝑙 ;
𝑓𝑠𝑤 ] for solid PCB model.
The hidden layer values, ℎ1 (𝑘) and ℎ2 (𝑘), can be expressed as

𝑁2
∑︁
ℎ1 (𝑘) = 𝑊2𝑚𝑛 𝑥(𝑘) + 𝐵2 𝑘 , 𝑚 = 1, ..., 𝑁1 , 𝑛 = 1, ..., 𝑁2 (3.29a)
𝑘=1
𝑁3
∑︁
ℎ2 (𝑘) = 𝑊3𝑚𝑛 𝑥(𝑘) + 𝐵3 𝑘 , 𝑚 = 1, ..., 𝑁2 , 𝑛 = 1, ..., 𝑁3 . (3.29b)
𝑘=1

The output layer values, 𝑦(𝑘), can be expressed as

𝑁2
∑︁
𝑦(𝑘) = 𝑊4𝑚𝑛 𝑥(𝑘) + 𝐵4 𝑘 , 𝑚 = 1, ..., 𝑁3 , 𝑛 = 1, ..., 𝑁4 . (3.30)
𝑘=1

65
Data training and testing

High resolution and accuracy ANSYS models for different litz PCB parameter combinations
of (𝑁 𝑠 , 𝑊𝑠 , 𝑁𝑙 , 𝑓𝑠𝑤 ) and solid PCB parameter combinations of (𝑊𝑠 , 𝑁𝑙 , 𝑓𝑠𝑤 ) are imported for
the training data. The Levenberg-Marquardt feed-forward backpropagation algorithm is applied
for the training function to achieve a fast and accurate converging process. Fig. 3.14(a) and Fig.
3.14(b) show that the minimum testing losses of 1.2e-4 and 4.6e-4 are achieved with certain epochs
of iteration for the litz PCB (4, 4) and solid PCB (4, 2) hidden layers neuron number combinations,
respectively.

Inductor loss optimization leveraging neural network

The inductor loss optimization can be implemented leveraging the analytical neural network
models of AC resistance factor for the proposed litz/solid PCB winding. The main difference
between the neural network-based PCB-type inductor loss optimization and the normal inductor
design process of Fig. 3.4 is that number of turns, 𝑛𝑡 , the number of paralleled PCB per turn, 𝑛 𝑝 ,
the strand number, 𝑁 𝑠 , and the trace width, 𝑊𝑠 , for litz/solid PCB winding need to be swept and
optimized.
The constraints for the optimization are:
(1) the multiplication of 𝑛𝑡 𝑛 𝑝 should be less than the maximum allowable number of stacked PCB,
𝑁𝑚𝑎𝑥,𝑃𝐶 𝐵 (in a core window height of 𝑤 ℎ ):

𝑤ℎ
𝑛𝑡 𝑛 𝑝 ≤ 𝑁𝑚𝑎𝑥,𝑃𝐶 𝐵 = . (3.31)
𝑡 𝑃𝐶 𝐵

(2) the multiplication of 𝑁 𝑠 𝑊𝑠 should be less than the core window width, 𝑤 𝑤 :

𝑁 𝑠 𝑊𝑠 ≤ 𝑤 𝑤 . (3.32)

Thus, the neural network-based litz/solid PCB inductor design process can be illustrated in
algorithm 1. By importing the required parameters of voltage, RMS current and ripple current,

66
the optimal number of turns, 𝑛𝑡 , number of paralleled PCB per turn, 𝑛 𝑝 , strand number, 𝑁 𝑠 , trace
width, 𝑊𝑠 , and air-gap, 𝑙 𝑔 for litz/solid PCB inductor can be derived with minimum power losses
at desired switching frequency.

Table 3.5: Loss comparison of the four-layer neural network with different neuron number combi-
nations in two hidden layers.
Neuron number in (hidden layer1, hidden layer2) (2, 2) (2, 4) (4, 2) (2, 6) (6, 2) (4, 4) (4, 6) (6, 4) (6, 6)
Losses of litz PCB neural network model 1.5e-3 2.2e-3 5.2e-3 6.8e-3 7.2e-3 1.2e-4 3.9e-4 5.7e-4 6.2e-3
Losses of solid PCB neural network model 1.6e-2 7.7e-2 4.6e-4 9.1e-3 2.5e-2 2.8e-3 1.4e-3 9.9e-4 4.9e-3

(a) (b)

Figure 3.15: (a) Litz PCB and (b) solid PCB winding prototypes.

3.3 Prototyping Results

The designed inductors are prototyped in this section for the loss, volume and cost comparison.
Based on the theoretical and practical core/winding design, 10 prototypes of EE/EI/EA/II core
structures combined with litz wire/litz PCB/solid PCB windings are built for a comprehensive
analysis.

3.3.1 Prototype Finalization

Firstly, the litz and solid PCB windings are fabricated as is shown in Fig. 3.15. Based on the
resistance factor comparison in Fig. 3.7(a), the (4×10 Strands, 8 mils) litz routing structure has

67
Algorithm 1 PCB Winding Intuctor Design Optimization
1: Initialize the parameters for 𝑉𝑑𝑐 , 𝐼𝑟𝑚𝑠 , Δ𝑖 𝐿 ;
2: for 𝑓𝑠𝑤 =100kHz:10kHz:1MHz do
3: calculate 𝐿 by (3.4) or (3.5);
4: check 𝐴𝑃 by solving (3.12);
5: calculate 𝑁𝑚𝑎𝑥,𝑃𝐶 𝐵 by (3.31);
6: calculate air-gap by (3.8);
7: calculate peak flux density by (3.12);
8: check if 𝐵 𝑝𝑘 ≤ 𝐵𝑚𝑎𝑥 ;
9: 𝑛𝑡 ← 1, 𝑛 𝑝 ← 1, 𝑁 𝑠 ← 1, 𝑊𝑠 ← 4𝑚𝑖𝑙;
10: while 𝑛𝑡 ≤ 𝑁𝑚𝑎𝑥,𝑃𝐶 𝐵 do
11: while 𝑛𝑡 𝑛 𝑝 ≤ 𝑁𝑚𝑎𝑥,𝑃𝐶 𝐵 do
12: for 𝑁 𝑠 =1:4:80 do
13: while 𝑁 𝑠 𝑊𝑠 ≤ 𝑤 𝑤 do
14: calculate core losses by (3.11);
15: calculate copper losses by (3.29), (3.30);
16: calculate air-gap by (3.8);
17: calculate peak flux density by (3.12);
18: check if 𝐵 𝑝𝑘 ≤ 𝐵𝑚𝑎𝑥 ;
19: 𝑊𝑠 = 𝑊𝑠 + 4𝑚𝑖𝑙;
20: end while
21: 𝑊𝑠 ← 4𝑚𝑖𝑙;
22: end for
23: 𝑛 𝑝 = 𝑛 𝑝 + 1;
24: end while
25: 𝑛 𝑝 ← 1;
26: 𝑛𝑡 = 𝑛𝑡 + 1;
27: end while
28: find optimal 𝑛𝑡 , 𝑛 𝑝 , 𝑁 𝑠 , 𝑊𝑠 , 𝑙 𝑔 with minimum losses;
29: end for

68
 Resistance Factor Measurements of PCB and Round Windings
25
Rope wire

20 Solid 4x4 layers

Resistance Factor
15
Solid 4x3 layers

10
Solid 4x2 layers Litz 4x3 layers
Solid 4x1 layers
Litz 4x4 layers
5 Litz wire

Litz 4x2 layers

0 Litz 4x1 layers

0 200 400 600 800 1000
Frequency(kHz)
Litz 4x1 layers Litz 4x2 layers Litz 4x3 layers Litz 4x4 layers
Solid 4x1 layers Solid 4x2 layers Solid 4x3 layers Solid 4x4 layers
Solid wire Litz wire

Figure 3.16: Resistance factor measurements of different layers of litz/solid PCB windings and
round normal/litz wires with different frequencies.

(a) (b) (c) (d) (e)

(f) (g) (h) (i) (j)

Figure 3.17: Proposed inductor prototypes: (a) EE, 10 turns, litz wire (b) EE, 6 turns, litz wire (c)
EE, 4 turns, litz PCB (d) EE, 4 turns, solid PCB (e) EA, 5 turns, litz PCB (f) EA, 5 turns, solid
PCB (g) EI, 4 turns, litz PCB (h) EI, 4 turns, Solid PCB (i) II, 8 turns, Litz PCB (j) II, 8 turns,
Solid PCB.

69
the smallest resistance factor and is selected as the litz PCB winding prototype. The resistance
factor of the prototyped litz/solid PCB winding is measured with LCR meter by stacking different
layers as is shown in Fig. 3.16. The measured RF is consistent with the ANSYS analysis in Fig.
3.7(b). Litz PCB has smaller RF than solid PCB and the advantage of RF is more remarkable with
increased stacked number of layers. Also, a type of AWG 8 litz wire is applied for the litz wire
winding. 10 prototypes are built and shown in Fig. 3.17. From Fig. 3.17(a) to 3.17(j), the inductor
prototypes are designed as: EE core, 10 turns litz wire; EE core, 6 turns litz wire; EE core, 4 turns
litz PCB; EE core, 4 turns solid PCB; EA core, 5 turns litz PCB; EA core, 5 turns solid PCB;
EI core, 4 turns litz PCB; EI core, 4 turns solid PCB; II core, 8 turns litz PCB; II core, 8 turns
solid PCB, respectively. The prototypes are designed and fabricated based on the parameters in
table 3.1. Considering the high frequency ranged from 100kHz to 1MHz and high current ripple
of 50A for critical soft switching operation, the desired inductance, turn number and air-gap are
following the theoretical design and core structure design with ANSYS validation in section II and
III, respectively. Because the thickness of litz wire is higher than PCB winding, litz wire is only
suitable for EE core with more window height as is shown in Fig. 3.17(a) and 3.17(b). On the other
hand, the PCB winding is thin enough to be flexibly fit into any of the core structure’s window area.
To fully utilize the window area of the cores for reducing the winding resistance, the PCB winding
are stacked 8 and 4 layers in parallel per turn in EE of Fig. 3.17(c), 3.17(d) and EI core of Fig.
3.17(g), 3.17(h), respectively. Due to the limited window area of EA and II cores, the number of
stacked PCB per turn is one for the EA prototypes of Fig. 3.17(e), 3.17(f) and II prototypes of Fig.
3.17(i), 3.17(j), respectively. For the EA core, the airgap is nonadjustable and determined by the
width of the window area. For the II core, the airgap is limited by the total thickness of the PCB
winding. Thus, EA/II inductors are designed by sweeping turn number in ANSYS to derive the
desired configurations which are shown in the following section.

70
 Figure 3.18: Testbench for inductor loss measurement.

3.3.2 Experimental Validation

The inductor prototypes are tested with a buck converter at fixed duty cycle of 0.5 to de-
liver 50A current ripple at different switching frequency ranged from 100kHz to 1MHz. The
testbench is shown in Fig. 3.18 including three-phase type of switch board on the right, con-
troller board in the middle and sensing board on the left. The switch board is composed of SiC
MOSFET (C2M0025120D)×6, gate driver (CRD-001)×6, DC bus capacitors (B32774D8505K,
5𝜇F)×9 and DC voltage sensor (RP1215D). The sensing board includes three phase capacitors
(B32774D8126K000, 12𝜇F)×9, voltage sensor (RP1215D)×3, current sensor (CKSR 25-NP)×3,

(a) (b)

Figure 3.19: (a) Inductor voltage, inductor current and output voltage and (b) the zoomed wave-
forms at 500kHz switching frequency, 500V input voltage and 0.5 duty cycle.

71
power relay (T9SV1K15-12)×3. Typical inductor voltage, inductor current and output voltage
waveforms at 500kHz are shown in Fig. 3.19 with zoomed views. The PCB winding width and
thickness are designed for a temperature rise of less than 40 ◦ C under the desired current rating.
The thermal behaviors of designed inductors are compared with the commercial ones in Fig. 3.20.
The proposed inductors have temperature rise only up to 50-60◦ C which are 60-70◦ C lower than
the commercial ones. For a solid winding, the AC resistance will be increased by a factor of more
than 10 when the switching frequency is reaching 500kHz as is shown in Fig. 3.16. If the winding

(a) (b) (c)

(d) (e) (f)

(g) (h) (i)

Figure 3.20: Thermal behaviors of the designed and commercial inductors at 500kHz, 50A peak
current: (a) EE core, litz PCB (b) EA core, solid PCB (c) SER inductor (d) AGM inductor (e)
AGP-332 inductor (f) AGP-562 inductor (g) WE-0068 inductor (h) WE-1022 inductor (i) DMT2-
20 inductor.

72
of commercial inductors are not specially designed, the AC losses will be increased proportionally.
Thus, high temperature rise will occur if no active cooling system is added.
The loss, volume and cost of the 10 proposed prototypes and two typical commercial inductors
are compared in Fig. 3.21 and Fig. 3.22. Specifically, Fig. 3.21(a) shows the comparison of
volume and loss at 500kHz. It can be derived that the EE core litz wire inductors have the lowest
losses but higher volume. II and EA core PCB inductors have the smallest volume and higher
losses. EE core PCB inductors have the medium volume and losses. The miminum losses are
achieved with EE core 6 and 10 turns litz wire inductors which are 13.1W and 6.5W, respectively.
The least volumes are achieved with II core 8 turns and EA core 5 turns PCB inductors which are
29.5 𝑐𝑚 3 and 32.6 𝑐𝑚 3 , respectively. The commercial inductor of AGM and SER have significant
losses compared with the proposed inductors despite of their small volumes. Also, the loss and
cost among the inductors are compared in Fig. 3.21(b). For a mass production, the cost of the PCB
winding inductor is less than the litz wire inductor and the commercial ones. The EA core inductor
has the least cost since it needs only one core for fabrication. The circled points in the two figures
are the desired solutions for the prototype if putting different weighing factors on the loss, volume
or cost. Finally, the break down of core and copper losses for the 10 designed inductors and 2
commercial inductors are listed in Fig. 3.22 with frequencies of 100kHz, 500kHz and 1MHz. The
caption of each prototype from (a) to (j) are consistent in Fig. 3.17 and Fig. 3.22. Compared with
the commercial ones, the designed inductors reduced the core and copper losses significantly by a
factor of 5-10.

3.3.3 Observations

The following observations are derived from the conducted research:

1. The critical soft switching power converter at high power (≥ 11𝑘𝑊) and high frequency
(100kHz-1MHz) requires a large current ripple (≥ 50𝐴). The commercial inductors could
not handle this high ripple high frequency current due to the high power losses and temperature
rise (≥ 125◦𝐶).

73
 Inductor Losses and Volume Comparison
100 Inductor Losses and Cost Comparison
AGM222
2-512ME 100
90 AGM222
AGP4233- 90 2-512ME
80 562ME AGP4233
80 -562ME
70
Inductor Losses (W)

SER291 70
SER2915

Inductor Losses (W)

60 5H-472 AGP4233 H-472
-332ME 60 AGP4233
50 -332ME
EA, 5 turns, EI, 4 turns, 50 EA, 5 turns, EI, 4 turns,
litz PCB litz PCB
40 litz PCB litz PCB
40
II, 8 turns, EE, 4 turns,
30 EI, 4 turns, II, 8 turns, EI, 4 turns,
litz PCB solid PCB 30 EE, 4 turns,
EA, 5 turns, solid PCB EA, 5 turns,
litz PCB solid PCB
solid PCB
II, 8 turns, EE, 4 turns, EE, 6 turns,
20 solid PCB
solid PCB litz PCB 20 solid PCB II, 8 turns, EE, 4 turns,
litz wire
solid PCB litz PCB EE, 10 turns,
10 10 litz wire
EE, 6 turns,
EE, 10 turns, litz wire
0 litz wire 0
10 30 50 70 90 0 20 40 60 80
Volume (cm3) Cost ($)

(a) (b)

Figure 3.21: Comparisons of Power losses with volume and cost among the proposed prototypes
and commercial products: (a) Losses and volume comparison (b) Losses and cost comparison.

Inductor Losses Break Down @100kHz

20
Inductor Losses (W)

15
10
5
0
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) AGM SER 332 562

Core Loss Copper Loss

Inductor Losses Break Down @500kHz
80
Inductor Losses (W)

60
40
20
0
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) AGM SER 332 562

Core Loss Copper Loss

Inductor Losses Break Down @1MHz
300
Inductor Losses (W)

250
200
150
100
50
0
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) AGM SER 332 562

Core Loss Copper Loss

Figure 3.22: Comparison of inductor core and copper losses break down at 100kHz, 500kHz and
1MHz.

2. The conducted research provides the specially designed critical soft switching inductors to
handle high frequency large current ripple working conditions by reducing the overall losses

74
 by a factor of 5-10 and temperature rise by a factor of 2-3.

3. The AC winding losses can be reduced by introducing litz wire with large number of strand.
But the cost and volume of litz wire are high due to the thick outer insulation jacket and manu-
facturing process.

4. Careful design of PCB litz/solid windings can be a substitute for the litz wire in the reduction of
high frequency AC copper losses. On one hand, the thickness of PCB copper could be flexibly
adjusted to reduce the high frequency AC losses caused by the skin effect. On the other hand,
multiple pieces of PCB could be stacked in parallel per turn to fit into the core area for the
reduction of the equivalent DC resistance.

5. The litz PCB 3D layout method could largely emulate the litz wire capability for attenuating
the AC losses of skin and proximity effects by performing a small resistance factor.

6. The four core structures have advantages in different aspects. EE and EI core have more win-
dow area for paralleling more PCB to reduce the DC resistance. EA and II cores have less
volume and cost. The flexibility of adjusting the stacked number of PCB for EE and EI cores
Rating of Performance
Loss Benefit
Losses
10
9
8
7
6
5
4
Weight Volume
Weight 3 Volume
Benefit Benefit

II core, solid PCB

EA core, solid PCB
EE core, litz PCB
EE core, litz wire
CostCost
Benefit
EE core, solid PCB

Figure 3.23: Ratings of performance for four of the desired inductor prototypes.

75
 are better than EA and II cores.

7. For the selection of inductor among the designed prototypes, if volume and cost are the two
primary considerations, II 8 turns inductor and EA 5 turns inductor can be the preferences
which reduce 50% of the volume and 75% of the cost compared to EE inductors. On the other
hand, if the losses are the primary considerations, EE 10 turns litz wire inductor and EE 4
turn litz PCB inductor can be the preferences which reduce 40-60% of the losses compared
to the II or EA inductors. Specifically for the core structure selection, the EE core has more
window area for winding and is suitable for round litz wire (high diameter) and high inductance
applications (more turn number). II core window area is restricted by the air-gap. Thus it is
suitable for PCB winding (low thickness) and low inductance applications (less turn number).

8. For the selection of litz or solid PCB windings, the AC resistance can be calculated to guide for
selection which are based on the DC resistance of two PCB windings, 𝑅 𝐷𝐶,𝑙𝑖𝑡𝑧 and 𝑅 𝐷𝐶,𝑠𝑜𝑙𝑖𝑑 ,
in Fig. 3.15, number of turns, 𝑛𝑡 , and number of paralleled PCB per turn, 𝑛 𝑝 , resistance factor
at a stacked PCB number of 𝑛 𝑝 × 𝑛𝑡 , 𝑅𝐹𝑛 𝑝 ×𝑛𝑡 . The total AC resistance of an inductor, 𝑅 𝐴𝐶,𝑙𝑖𝑡𝑧
or 𝑅 𝐴𝐶,𝑠𝑜𝑙𝑖𝑑 , can be expressed as

𝑅 𝐷𝐶,𝑙𝑖𝑡𝑧 𝑛𝑡
𝑅 𝐴𝐶,𝑙𝑖𝑡𝑧 = 𝑅𝐹𝑙𝑖𝑡𝑧,𝑛 𝑝 ×𝑛𝑡 (3.33)
𝑛𝑝

𝑅 𝐷𝐶,𝑠𝑜𝑙𝑖𝑑 𝑛𝑡
𝑅 𝐴𝐶,𝑠𝑜𝑙𝑖𝑑 = 𝑅𝐹𝑠𝑜𝑙𝑖𝑑,𝑛 𝑝 ×𝑛𝑡 . (3.34)
𝑛𝑝

Thus, at a certain stacked PCB number of 𝑛 𝑝 × 𝑛𝑡 inductor prototype, if 𝑅 𝐴𝐶,𝑙𝑖𝑡𝑧 is less than
𝑅 𝐴𝐶,𝑠𝑜𝑙𝑖𝑑 which means litz PCB has less copper losses, litz PCB winding can be chosen as
preference. On the other hand, solid PCB can be the option. Based on the calculation in (3.33)
and (3.34) and data in Fig. 3.7 and 3.16, in less stacked PCB number of 𝑛 𝑝 × 𝑛𝑡 prototypes
of EA and II core inductors, the solid PCB has less copper losses than litz PCB because the
DC resistance dominates the copper losses more than the resistance factor. However, when the

76
 total stacked number of PCB is larger than 20 layers in EE core inductor, the litz PCB will
prevail due to the litz layout’s more capability than solid PCB at reducing the resistance factor
at higher stacked number of PCB setups.

9. For the inductor optimization design methods that are developed in this chapter, the round wire
type of litz winding inductors are designed based on the analytical litz wire AC loss equa-
tions. The PCB type of litz/solid winding inductors are designed based on the proposed neural
network model for the derivation of optimal PCB winding structures.

To summarize for the prototyping designs, the desired inductor setups are labeled with red cir-
cles in Fig. 3.21(a) and Fig. 3.21(b), respectively by considering different weighing factors on
loss, volume or cost. EE litz wire inductor has low losses, higher cost and volume. EE litz PCB
inductor has lower volume, higher losses and lower cost. II and EA core inductors have low vol-
ume, low cost and higher losses. All the designs are based on the critical soft switching conditions
of high frequency (100kHz-1MHz), high current ripple (50A) which could not be handled by the
benchmarked commercial inductors due to the high loss and temperature rise. Also a performance
rating comparison radar chart of five desired prototypes scored from 6 to 10 is shown in Fig. 3.23
to address the advantages of different designs in the aspects of losses, volume, cost and weight.
For each comparative item, the five prototypes are ordered and scored from 6 to 10 to show their
strength in a unified radar chart system.

Table 3.6: Overall Comparisons of the proposed prototypes, commercial inductors and theoretical
design
(a) (b) (c) (d) (e) (f) (g) (h) (i) (j) SER AGM 332 562 Calculation
Loss (W) @100kHz 0.9 0.5 4.8 5.5 8.4 11.7 14.8 11.6 11.4 9.8 17.6 20.6 10.4 14.7 6.3
Loss (W) @500kHz 6.2 6.5 15.3 15.6 39.9 28.1 39.6 28.1 30.5 21.9 97.2 42.8 57.5 81 19.2
Loss (W) @1MHz 53.2 36.4 55.6 56.4 85.6 77.8 85.7 65.1 63.7 29.4 359.4 137 212.6 299.5 39.5
Volume (𝑐𝑚 3 ) 89.3 71.8 66.8 66.8 32.6 32.6 43.5 43.5 29.5 29.5 10.7 12 44.5 44.5 75
Cost ($) 72 48 44.4 44.4 9 9 25.2 25.2 12.6 12.6 32 9.6 13 13 32
Weight (𝑔) 142 130 144 176 61 66 95 111 54 62 51 35.7 135 135 122

77
3.4 Summary

This chapter develops a theoretical design method for high frequency and high efficiency in-
ductor especially for critical soft switching in high current ripple application. The optimal design
parameters are derived with the minimization of inductor losses. Also, the topological design of
core and coil structures are proposed. Specifically, for the coil, a 3D litz PCB routing method
and designing procedures are developed to reduce the AC losses. For the core, four types of core
structures, EE, EI, II, EA, are developed for different merits of trade-off including core losses,
volume and cost. A neural network-based litz/solid PCB winding AC loss modeling method is
developed to analytically optimize the losses of the PCB inductor design. Finally, a comprehen-
sive analysis and comparison of the proposed designs with typical commercial inductors shows
the advantages of the proposed inductors in the aspect of high frequency high ripple losses and
cost. Power losses, temperature rise and cost are reduced by factors of 10, 2.5 and 3, respectively,
with the proposed core and coil structures for the high frequency high current ripple critical soft
switching applications.

78
 Chapter 4: Model Predictive Control for Modular Power Converters

Model predictive control (MPC) is an advanced control technique that is gaining more attention
with the increasing demand of better system dynamic performace in power electronics. Different
from the conventional proportional-integral (PI) control, the MPC has a better transient perfor-
mance in the aspects of rising-time, steady-state error, overshoot and disturbance rejection. Espe-
cially in high-order filtered power converter system, such as 𝐿𝐶 𝐿 filtered converter, there exists an
intrinsic resonance frequency that can cause oscillation or instability issues with a conventional PI
controller [68]. The resonance cannot be naturally attenuated by PI control.
Passive/active damping resistors can be added in the physical/control loops to compensate for
the resonance [69]. However, on one hand, a passive resistor in the main physical loop will in-
troduce extra power losses [70]. On the other hand, the active damping method requires extra
voltage/current sensors that brings more system cost [71], [72]. Besides the hardware solutions of
passive/active damping methods with extra physical resistors/sensors, another option to attenuate
the resonance is notch filter from the software perspective [73]. The notch filter can be added at the
resonant frequency of the 𝐿𝐶 𝐿 filter to compensate for the resonant spikes. However, the inserted
notch filter will also reduce the control bandwidth and slow down the reference tracking. Notch
filter is a desired solution to reduce the high frequency EMI noise [74]. But at the same time, the
system dynamic performance might be deteriorated.
MPC is capable of increasing the control bandwidth to achieve a high reference tracking speed
[75], [76]. Based on this characteristic of MPC, the resonant frequency of an 𝐿𝐶 𝐿 filtered con-
verter can be shifted to a higher range by down-sizing the filter values and increasing the switch-
ing frequency [77], [78]. With the advantageous dynamic performance of MPC, the volume and
weight of 𝐿𝐶 𝐿 filter can be reduced. Thus, the system cost will be saved. Another intrinsic func-
tion of MPC is active damping for 𝐿𝐶 𝐿 resonance which has not been studied in detail [79]. The

79
MPC can be functioned as an active damping control block that compensates the system resonance
especially in a cascaded PI+MPC control architecture. Thus, the stability of the system can be im-
proved which makes it possible to enlarge the proportional gain and increase the control bandwidth
without exciting oscillation [80].
This chapter designs a cascaded modular model predictive control architecture for a modified
non-isolated 𝐿𝐶 𝐿 filtered grid-connected inverter. The proposed method is configured as continu-
ous control set model predictive control (CCS-MPC) for the implementation. The designed MMPC
includes an upper level grid side inductor current PI control and lower level per phase switch side
inductor, output capacitor (𝐿𝐶) filter MPC control. The inner loop MPC can be functioned as an
active damping term to attenuate the resonance and improve the system stability. Thus, the control
bandwidth can be increased by enlarging the outer loop gain without exciting oscillations. Also,
since only the switch side 𝐿𝐶 parameters are leveraged for the MPC state space model and the
grid side inductor current is controlled by the PI, the uncertainty of grid side inductance will not
influence the control performance. This chapter is organized as follows. Firstly, the modified non-
isolated 𝐿𝐶 𝐿 filtered inverter is introduced with the system modeling in 𝑎𝑏𝑐 and 𝑑𝑞0 reference
frames. The modified topology is capable of bypassing the leakage current from flowing into the
grid. Secondly, three control structures are designed for the modified non-isolated converter with
zero-sequence stabilization capabilities to attenuate the leakage current which include PI control,
PI control+notch filter, PI control cascaded with MMPC. Thirdly, three control architectures are
compared and analyzed with transfer functions to study the resonance rejection capabilities. The
cascaded MMPC method attenuates most of the resonance and achieves the highest control band-
width with the help of intrinsic active damping capability. An optimal control design method is
developed for the cascaded MMPC to achieve better dynamic performance. Finally, the active
damping analysis and proposed control design method are validated experimentally.

80
 Figure 4.1: Non-isolated 𝐿𝐶 𝐿 inverter with low leakage current.

Figure 4.2: Equivalent 𝐿𝐶 𝐿 circuit with consideration of ESR.

Figure 4.3: 𝐿𝐶 𝐿 plant model with consideration of ESR.

4.1 𝐿𝐶 𝐿 System Modeling

The 𝐿𝐶 𝐿 system modeling is based on a modified non-isolated three-phase DC/AC converter

which has been shown in Fig. 4.1. Several methods have been proposed to improve the com-
mon mode performance of the traditional DC/AC converters. [81] connected the grid neutral to
the three-phase output capacitors common point for the compensation of unbalanced three-phase
power system. [82] inserted a grounding capacitor between the three-phase output capacitors com-
mon point and the ground to create a zero sequence bypassing path to reduce the leakage current.
[83] introduced a fourth leg to be connected between the common point of three-phase output ca-

81
 Figure 4.4: 𝐿𝐶 𝐿 plant model transfer function bode plots with consideration of ESR.

pacitors and DC bus neutral to attenuate the common mode voltage. [84] directly connected the
fourth leg to the three-ph ase output capacitors common point with an extra 𝐿𝐶 circuit to stabilize
the common mode voltage. Most of the them cost extra switches to attenuate the common mode
voltage. Different from the traditional two-level three-phase DC/AC converter, the common point
of three-phase capacitors is connected to the DC bus positive/negative terminals to create a by-
passing path for zero-sequence capacitor voltage and zero-sequence switch side inductor current
control. By leveraging the topological modification and zero-sequence control methods, the com-
mon mode voltage can be stabilized to reduce the leakage current. From the perspective of system
dynamic performance, the state space equations and transfer functions of the 𝐿𝐶 𝐿 plant model are
derived for optimal design.

4.1.1 DC/AC 𝐿𝐶 𝐿 Plant Modeling

For a precise modeling of the 𝐿𝐶 𝐿 filtered converter system, the equivalent series resistors
(ESR) of the switch side and grid side inductors are both taken into considerations [85], [86]. For
per phase switch side inductor current, 𝑖 𝐿 𝑓 𝑠 , capacitor voltage, 𝑣 𝐶 𝑓 , grid side inductor current, 𝑖 𝐿 𝑓 𝑔 ,
grid voltage, 𝑣 𝑔 and phase leg output voltage, 𝑣 𝑥 , the equivalent 𝐿𝐶 𝐿 circuit with ESR has been

82
shown in Fig. 4.2. The corresponding state space equations can be expressed as:

𝑑𝑖 𝐿 𝑓 𝑠
𝐿𝑓𝑠 = −𝑣 𝐶 𝑓 − 𝑅 𝐿 𝑓 𝑠 𝑖 𝐿 𝑓 𝑠 + 𝑣 𝑥 (4.1a)
𝑑𝑡
𝑑𝑣 𝐶 𝑓
𝐶𝑓 = 𝑖𝐿 𝑓 𝑠 − 𝑖𝐿 𝑓 𝑔 (4.1b)
𝑑𝑡
𝑑𝑖 𝐿 𝑓 𝑔
𝐿 𝑓𝑔 = 𝑣𝐶 𝑓 − 𝑅 𝐿 𝑓 𝑔 𝑖 𝐿 𝑓 𝑔 − 𝑣 𝑔 (4.1c)
𝑑𝑡

where 𝐿 𝑓 𝑠 , 𝐶 𝑓 and 𝐿 𝑓 𝑔 are the switch side inductor, output capacitor and grid side inductor, respec-
tively. 𝑅 𝐿 𝑓 𝑠 and 𝑅 𝐿 𝑓 𝑔 are the ESR of the switch side inductor and grid side inductor, respectively.
To further derive the standardized format for transfer function, the state space equations can be
expressed as matrix format [87]:

𝑑X
= AX + Bc 𝑣 𝑥 + Bg 𝑣 𝑔 (4.2a)
𝑑𝑡
𝑖 𝐿 𝑓 𝑠 = Cc X (4.2b)

𝑖 𝐿 𝑓 𝑔 = Cg X (4.2c)

where X is the state variable matrix and can be illustrated as:

 
 𝑖𝐿 𝑓 𝑠 
 
 
X =  𝑣 𝐶 𝑓 .
 (4.3)
 
 
 𝑖𝐿 𝑓 𝑔 
 
A, Bc , Bg , Cc , Cg are the system matrices and can be expressed as:

83
  −𝑅 𝐿 𝑓 𝑠 −1


 𝐿𝑓𝑠 𝐿𝑓𝑠 0 

 
A =  1 −1 (4.4a)
𝐶𝑓 1 𝐶𝑓


 
1 −𝑅 𝐿 𝑓 𝑔
0
 
 𝐿 𝑓𝑔 𝐿 𝑓𝑔 
 
1
   

 𝐿𝑓𝑠



 0 
   
Bc =  0  , Bg =  0  (4.4b)
   
−1 
0 
  
  𝐿 𝑓 𝑠 
  
   

 1  
 0 
   
Cc =  0  , Cg =  0  (4.4c)
   
0  1 
   
 
   

Based on the state space matrix equations, the transfer functions can be derived accordingly to
illustrate the 𝐿𝐶 𝐿 plant model. Specifically, the transfer function from phase leg output voltage,
𝑣 𝑥 , to switch side inductor current, 𝑖 𝐿 𝑓 𝑠 , can be expressed as:

𝑖 𝐿 𝑓 𝑠 (𝑠)
𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝐿 (𝑠) = = Cc (𝑠I − A) −1 Bc , (4.5)
𝑣 𝑥 (𝑠)

where I is the 3×3 identity matrix. The transfer function from phase leg output voltage, 𝑣 𝑥 , to grid
side inductor current, 𝑖 𝐿 𝑓 𝑔 , can be expressed as:

𝑖 𝐿 𝑓 𝑔 (𝑠)
𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝑔 (𝑠) = = Cg (𝑠I − A) −1 Bc . (4.6)
𝑣 𝑥 (𝑠)

For the illustration of the resonance issue in 𝐿𝐶 𝐿 filter system to control the grid current and
consider the ESR, the equation (4.6) can be expanded as:

𝑖 𝐿 𝑓 𝑔 (𝑠) 𝑉𝑑𝑐
𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝐿 𝑓 𝑔 (𝑠) = = . (4.7)
𝑣 𝑥 (𝑠) (𝑠𝐿 𝑓 𝑠 + 𝑅 𝐿 𝑓 𝑠 )(𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 )𝑠𝐶 𝑓 + (𝐿 𝑓 𝑠 + 𝐿 𝑓 𝑔 )𝑠 + (𝑅 𝐿 𝑓 𝑠 + 𝑅 𝐿 𝑓 𝑔 )

84
In the plant model transfer function, the quadratic term coefficient of the denominator is multiplied
by the ESR of switch and grid side inductors, 𝑅 𝐿 𝑓 𝑠 and 𝑅 𝐿 𝑓 𝑔 . These two ESR values are ranged at
a level of milliohms which are not enough to damp the resonance because of a too small portion of
quadratic term coefficient [88]. The bode plots of equations (4.5) and (4.6) has been shown in Fig.
4.4. In the resonant frequency of

√︄
𝐿 𝑓𝑠 + 𝐿 𝑓𝑔
𝜔𝑟𝑒𝑠 = , (4.8)
𝐿 𝑓 𝑠 𝐿 𝑓 𝑔𝐶 𝑓

there exists a convex magnitude spike which could cause system stability issue.

4.1.2 Zero-Sequence Modeling

In a traditional transformerless three-phase grid-connected inverter, a leakage current path

could be excited by the high frequency fluctuation of common mode voltage [89], [90]. In a
𝑑𝑞0 reference frame system, the common mode voltage is represented as the zero-sequence com-
ponent. Thus, a high frequency oscillation of zero-sequence voltage can cause high leakage current
in the parasitic paths [91]. The value of leakage current, 𝑖 𝑙 𝑘𝑔 , is mainly determined by the parasitic
capacitance, 𝐶 𝑝𝑎𝑟𝑎 , and the change rate of zero-sequence voltage, 𝑣 𝐶 𝑓 ,0 , [72]:

𝑑𝑣 𝐶 𝑓 ,0
𝑖 𝑙 𝑘𝑔 = 𝐶 𝑝𝑎𝑟𝑎 (4.9)
𝑑𝑡

where 𝑣 𝐶 𝑓 ,0 is the mean value of three-phase output capacitor voltages, 𝑣 𝐶 𝑓 ,𝑎 , 𝑣 𝐶 𝑓 ,𝑏 , 𝑣 𝐶 𝑓 ,𝑐 . In a

conventional 𝐿𝐶 𝐿 filtered grid-tied inverter, the zero-sequence voltage always fluctuates in high
frequency:

𝑣 𝐶 𝑓 ,𝑎 + 𝑣 𝐶 𝑓 ,𝑏 + 𝑣 𝐶 𝑓 ,𝑐
𝑣 𝐶 𝑓 ,0 = . (4.10)
3

However, with the modified non-isolated converter topology in Fig. 4.1, the zero-sequence
voltage can be stabilized as half of DC bus voltage, 𝑉𝑑𝑐 /2. And the connections of three-phase
output capacitors common points to the positive/negative DC bus terminals enables the grid side

85
 Figure 4.5: Leakage current bypassing paths with the modified non-isolated topology.

Figure 4.6: Equivalent common mode circuit of the modified non-isolated topology.

leakage current to be bypassed and attenuated as is shown in Fig. 4.5. With the improved topol-
ogy, the zero-sequence current only flows through the switch side inductors and output capacitors
instead of further injecting into the grid. Leveraging the zero-sequence voltage/current control
methods, the leakage current can be limited within the standard requirements of less than 30mA in
a EV system by IEC 62955:2018 and IET Wiring Regulation 18th Edition (BS 7671:2018) Section
722.531.2.101 [92].

4.2 Control Structures Analysis

The control strategies of the modified 𝐿𝐶 𝐿 filtered inverter are analyzed in this section. Dif-
ferent from the conventional control methods of grid-connected inverters [93], the zero-sequence
components of output capacitor voltage and switch side inductor current are stabilized with specific
controllers. To analyze the dynamic performances and resonance behaviors of different control
strategies in 𝐿𝐶 𝐿 filter system, four control structures are studied including PI control, PI control
with notch filter, cascaded PI and cascaded modular model predictive control methods.

86
 (a) (b)

(c) (d)

Figure 4.7: Control diagrams of the (a) PI (b) notch filtered PI (c) cascaded PI and (d) active-
damping MPC for the transformerless 𝐿𝐶 𝐿 inverter.

4.2.1 PI Control

The PI method of control diagram is shown in Fig. 4.7(a). The grid current is transformed
from 𝑎𝑏𝑐 to 𝑑𝑞0 reference frame based on Park and Clarke transformations. Then, the 𝑑, 𝑞 and
0 sequences of the grid current are controlled by PI in DC frame for a better dynamic tracking
performance. 𝑑, 𝑞 and 0 are corresponding to active power, reactive power and common mode
components, respectively. The output of the grid current controller will be transformed from 𝑑𝑞0
back to 𝑎𝑏𝑐 reference frame for duty cycle of PWM modulation. With the zero-sequence controller
to minimize the zero-sequence grid current with a tracking reference of 0A, the common mode
leakage current on the grid side can be attenuated to a low level.
The transfer functions of 𝑑𝑞0 grid current controllers can be expressed as:

87
 𝐾𝑖,𝑖𝐿 𝑓 𝑔𝑑
𝐺 𝑖𝐿 𝑓 𝑔𝑑,𝑃𝐼 (𝑠) = 𝐾 𝑝,𝑖𝐿 𝑓 𝑔𝑑 + (4.11a)
𝑠
𝐾𝑖,𝑖𝐿 𝑓 𝑔𝑞
𝐺 𝑖𝐿 𝑓 𝑔𝑞,𝑃𝐼 (𝑠) = 𝐾 𝑝,𝑖𝐿 𝑓 𝑔𝑞 + (4.11b)
𝑠
𝐾𝑖,𝑖𝐿 𝑓 𝑔0
𝐺 𝑖𝐿 𝑓 𝑔0,𝑃𝐼 (𝑠) = 𝐾 𝑝,𝑖𝐿 𝑓 𝑔0 + . (4.11c)
𝑠

With the PI control strategy, the resonance of 𝐿𝐶 𝐿 filter in Fig. 4.4 still exists at the resonant
frequency point.

4.2.2 PI Control with Notch Filter

To attenuate the resonance of 𝐿𝐶 𝐿 system, a notch filter can be added after the output of grid
current controllers as is shown in Fig. 4.7(b). The principle of notch filter is to flatten the spike
within a certain range centered at resonant frequency point. The notch filter can be designed in
continuous-time as

𝑠2 + 𝜔𝑟𝑒𝑠 2
𝐺 𝑁𝑜𝑡𝑐ℎ (𝑠) = 2
(4.12)
𝑠2 + 𝜔𝑄𝑟 𝑒𝑠 𝑠 + 𝜔𝑟𝑒𝑠

and implemented in discrete-time as difference equations. The variable 𝑄 represents the quality
factor and is configured to adjust the frequency range of notch filter.
With the help of notch filter, the resonance of the peak spike from the 𝐿𝐶 𝐿 system can be
attenuated. However, on one hand, another concave spike may be excited because of the notch
filter. On the other hand, the added notch filter reduces the control bandwidth and slows down the
dynamic performance.

4.2.3 Cascaded PI Control

To make a comprehensive comparison of resonance damping and dynamic performance before

introducing the proposed cascaded modular model predictive control method, the cascaded PI con-
trol is analyzed as is shown in Fig. 4.7(c). The cascaded PI control diagram for the 𝐿𝐶 𝐿 filtered

88
inverter includes the the outer loop of grid side inductor current control and inner loop capacitor
voltage control. The references for the inner loop capacitor voltage control are derived from the
output of the outer loop grid side inductor current control.
The transfer functions of capacitor voltage controller can be expressed as:

𝐾𝑖,𝑣𝐶 𝑓
𝐺 𝑣𝐶 𝑓 ,𝑃𝐼 (𝑠) = 𝐾 𝑝,𝑣𝐶 𝑓 + (4.13)
𝑠

The output of the capacitor voltage controller will be transformed to the duty cycle for PWM
modulation.

4.2.4 Cascaded Modular Model Predictive Control

To increase the control speed and solve the concave spike of PI+notch filter method and atten-
uate the resonance spike issue of PI control method, a cascaded modular model predictive control
method is developed in this section. The control diagram of the cascaded MMPC is shown in Fig.
4.7(d). It includes two cascaded control layers: (1) the outer loop of grid side inductor current
PI control in 𝑑𝑞0 reference frame; (2) the inner loop of per phase switch side 𝐿𝐶 filter inductor
current/capacitor voltage MPC control in 𝑎𝑏𝑐 reference frame and zero-sequence output capacitor
voltage MPC control. The reasons for implementing the grid side inductor current PI control in
𝑑𝑞0 and per phase switch side 𝐿𝐶 current/voltage MPC control in 𝑎𝑏𝑐 reference frames, respec-
tively, can be concluded in two aspects: (1) the MPC has better tracking performance and transient
behavior on time-varying AC reference signals than PI; (2) the outer loop grid side 𝑑 and 𝑞 current
are corresponding to the active and reactive power, respectively. Thus, instead of configuring AC
references for grid side 𝑎𝑏𝑐 phase current, 𝑑𝑞 grid current references can be directly linked to the
active/reactive power control when grid services are required.

Outer loop grid current PI control

For the outer loop control, the grid side inductor current is firstly transformed from 𝑎𝑏𝑐 to 𝑑𝑞
reference frame with Clarke and Park transformations. Then, two PI controllers are configured to

89
regulate the 𝑑𝑞 sequence of grid currents, 𝑖 𝐿 𝑓 𝑔,𝑑 and 𝑖 𝐿 𝑓 𝑔,𝑞 , respectively. The 𝑑 and 𝑞 components
of grid current references, 𝑖 ∗𝐿 𝑓 𝑔,𝑑 and 𝑖 ∗𝐿 𝑓 𝑔,𝑑 , represent the active and reactive power, respectively.
Then, the outputs of grid current controller are configured as the references for 𝑑𝑞 sequence out-
put capacitor voltages, 𝑣 𝐶∗ 𝑓 ,𝑑 and 𝑣 𝐶∗ 𝑓 ,𝑞 , which will be transformed to 𝑎𝑏𝑐 reference frame and
configured as the references of inner loop per phase 𝐿𝐶 capacitor voltage MPC.

Zero-sequence capacitor voltage MPC

For the stabilization of common mode voltage to bypass the grid side leakage current, the
zero sequence component of output capacitor voltages is independently controlled through MPC
as half of DC bus voltage. Thus, half of DC bus voltage measurement, 𝑉𝑑𝑐 , is configured as the
reference of per phase zero sequence voltage MPC. With the zero sequence voltage MPC, the grid
side leakage current can be attenuated to be lower than the standard requirement.

Inner loop per phase 𝐿𝐶 MPC

An explicit MPC method is designed for the switch side capacitor voltage and inductor current
control. As is shown in Fig. 4.7(d) of the control diagram, the three-phase capacitor voltages are
controlled in 𝑎𝑏𝑐 frame to follow the references from the cascaded grid current controller’s outputs.
The switch side inductor currents are also regulated with the MPC by adjusting the weighing
factor between 𝑖 𝐿 𝑓 𝑠,𝑎𝑏𝑐 and 𝑢𝐶 𝑓 ,𝑎𝑏𝑐 . The benefits to configure the MPC per phase in 𝑎𝑏𝑐 frame
can be concluded as: (1) the state space matrix of LC per phase is simpler than 𝑑𝑞 system to
implement the offline piecewise affine optimization code in a less costly DSP controller; (2) The
time-varying angular speed term, 𝜔, can be omitted in the explicit MPC state space matrix for the
offline optimization calculation; (3) Per phase MPC for LC is more flexible for a modular design
perspective to extend the paralleled phase number and other topologies, e.g., DC/DC, single-phase
DC/AC converters.
For the MPC implementation, in every control period, the MPC controller receives the mea-
sured switch side inductor current, 𝑖 𝐿 𝑓 𝑠,𝑎𝑏𝑐 , output capacitor voltage, 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 , grid side inductor

90
current, 𝑖 𝐿 𝑓 𝑔,𝑎𝑏𝑐 , from ADC and output capacitor voltage references, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 from the outer loop
grid side inductor current PI controller. An offline generated piecewise affine search tree is applied
to derive the optimal duty cycle for the explicit MPC. The state equations of switch side LC filter
can be expressed as

𝑇𝑠 𝑉𝑑𝑐𝑇𝑠
𝑖 𝐿 𝑓 𝑠 (𝑘 + 1) = 𝑖 𝐿 𝑓 𝑠 (𝑘) − 𝑣 𝐶 𝑓 (𝑘) + 𝑑 (𝑘) (4.14a)
𝐿𝑓𝑠 𝐿𝑓𝑠
𝑇𝑠 𝑇𝑠
𝑣 𝐶 𝑓 (𝑘 + 1) = 𝑖 𝐿 𝑓 𝑠 (𝑘) + 𝑣 𝐶 𝑓 (𝑘) − 𝑖 𝐿 𝑓 𝑔 (𝑘). (4.14b)
𝐶𝑓 𝐶𝑓

For the flexibility of implementing the explicit MPC and the convenience of experimentally
adjusting the DC bus voltage during test, the last term of (4.14), 𝑉𝑑𝑐 𝑑 (𝑘), can be replaced by the
phase leg output voltage, 𝑣 𝑥 (𝑘). The state-space model can be expressed in standard matrix format
of

𝑋 𝑘+1 = 𝐴𝑋 𝑘 + 𝐵𝑢 𝑘 + 𝐸𝑒 𝑘 (4.15)

where the variables and matrices represent

   𝑇   
 1 − 𝑅 𝐿 𝑓 𝑠 − 𝑇𝑠   𝑠   0 
𝐿𝑓𝑠 𝐿𝑓𝑠  𝐿𝑓𝑠 
𝐴= ,𝐵 = ,𝐸 =  (4.16a)
   
 ,
𝑇𝑠  − 𝑇𝑠

 𝐶𝑓 1 

 0 
   𝐶𝑓


     
 
 𝑖 𝐿 𝑓 𝑠 (𝑘)  h i h i
𝑋𝑘 =   ,𝑢 = , 𝑒𝑘 = (4.16b)
 
𝑉𝑑𝑐 𝑑 (𝑘) 𝑖 𝐿 𝑓 𝑔 (𝑘) .
 𝑣 (𝑘)  𝑘
 𝐶𝑓 
 

In the MPC formulation, the inductor current/capacitor voltage references can be defined as 𝑋¯
and the tracking errors between the measurement and the references are expressed as 𝑋˜ which are

91
composed of
   
 𝑖 𝐿 𝑓 𝑠,𝑟𝑒 𝑓 (𝑘)   𝑖 𝐿 𝑓 𝑠,𝑟𝑒 𝑓 (𝑘) − 𝑖 𝐿 𝑓 𝑠 (𝑘) 
𝑋¯ 𝑘 = 
 ˜
= (4.17)
  
, 𝑋
 𝑘  .
 𝐶 𝑓 ,𝑟𝑒 𝑓 (𝑘)  𝐶 𝑓 ,𝑟𝑒 𝑓 (𝑘) − 𝑣 𝐶 𝑓 (𝑘)
 𝑣   𝑣 
 
   
Thus, the cost function includes two terms

𝑁𝑐
∑︁ 𝑝 −1
𝑁∑︁
𝑚𝑖𝑛 𝑋˜ 𝑘𝑇 𝑄 𝑋˜ 𝑘 + △𝑢𝑇𝑘 𝑅△𝑢 𝑘 . (4.18)
𝑘=0 𝑘=0

For the penalties of the cost function, 𝑄 and 𝑅 represent the weighing factor matrices that are
implemented on the state values and input values, respectively.
The constraints of the MPC controller can be expressed as

𝑋˜ 𝑘+1 = 𝐴 𝑋˜ 𝑘 + 𝐵𝑢 𝑘 + 𝐸𝑒 𝑘 ∈ X (4.19)

△𝑢 𝑘 = 𝑢 𝑘 − 𝑢 𝑘−1 ∈ U (4.20)
   
 −𝐼 𝐿 𝑓 𝑠,𝑚𝑎𝑥   𝐼 𝐿 𝑓 𝑠,𝑚𝑎𝑥 
 ≤ 𝑋𝑘 ≤  (4.21)
   
 

 0 

 𝑉
 𝑑𝑐


   
h i h i
0 ≤ 𝑢 𝑘 ≤ 𝑉𝑑𝑐 (4.22)
h i h i
−𝐼 𝐿 𝑓 𝑔,𝑚𝑎𝑥 ≤ 𝑒𝑘 ≤ 𝐼 𝐿 𝑓 𝑔,𝑚𝑎𝑥 . (4.23)

For the implementation of MPC algorithm in every control period [43], the cost function in
(4.18) will be solved to predict the future steps of optimal input variable, 𝑢 𝑘 . And the first step of
the input value will be implemented as the MPC output for the PWM modulation. Different from
the PI control process, the MPC algorithm derives the optimal duty cycle by processing the state
variable, 𝑋 𝑘 , and tracking error, 𝑋˜ 𝑘 , in a linear way with specific coefficients. Since no integration
procedure is needed in MPC, the dynamic performance of MPC is better than PI with less overshoot
and higher tracking speed. Also, the inner loop MPC has higher control bandwidth which can be
functioned as an active damping term to solve the 𝐿𝐶 𝐿 resonance. Due to the active damping and

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high bandwidth of the inner loop MPC, the outer loop PI gains can be largely increased to speed
up the dynamic reference tracking performance without causing extra resonance issue.
For the cascaded model predictive control of 𝐿𝐶 𝐿 filter system, a state estimator is designed to
reduce the sensor count. One of the three variables, 𝑖 𝐿 𝑓 𝑠 , 𝑣 𝐶 𝑓 , 𝑖 𝐿 𝑓 𝑔 , can be estimated by the other
two. The merits of the estimator include the anti-noise capability for better control performance
and the reduction of sensor cost.
Specifically, the Luenberger observer can be designed to estimate the switch side inductor
current, 𝑖ˆ𝐿 𝑓 𝑠 , capacitor voltage, 𝑣ˆ 𝐶 𝑓 , and grid side inductor current, 𝑖ˆ𝐿 𝑓 𝑔 , with the samplings of
capacitor voltage, 𝑣 𝐶 𝑓 , and grid side inductor current, 𝑖 𝐿 𝑓 𝑔 . The detailed implementation of the
state estimator is introduced in Chapter 6 of the grid-tied inverter design case.

4.3 Optimal Control Design for Resonance Damping and Dynamic Performance

The optimal control design for resonance damping and dynamic performance of 𝐿𝐶 𝐿 filtered
grid-connected inverter is analyzed in this section. Four control strategies in Fig. 4.7 are compared
with transfer functions, bode plots, step responses and root locus to illustrate the active damping
and dynamic performance improvement capabilities of the cascaded MMPC method [94].

4.3.1 Control Plant Model Analysis

The integrated plant models of the three control strategies including 𝐿𝐶 𝐿 filter and control
blocks are derived in Fig. 4.8. The former stages are the three types of control blocks with the
input variable of grid side inductor current and output variable of duty cycle. The latter stage is the
𝐿𝐶 𝐿 filter plant model which has been derived in Fig. 4.3. Thus, the complete transfer functions
can be expressed based on different control strategies.

PI control transfer function

For the first control strategy of PI method in Fig. 4.7(a), the corresponding system plant model
has been shown in Fig. 4.8(a). Based on the derivations in (4.7) and (4.11), the transfer func-

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 (a)

(b)

(c)

(d)

Figure 4.8: Plant models of the (a) PI (b) notch filtered PI (c) cascaded PI and (d) active-damping
MPC for the transformerless 𝐿𝐶 𝐿 inverter.

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 Figure 4.9: Typical LQR control diagram with delay compensation.

(a) (b)

Figure 4.10: Comparison of bode plots for three control strategies (a) from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 and (b)
from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑣 𝐶 𝑓 .

tion from tracking error, 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 , to the measurement, 𝑖 𝐿 𝑓 𝑔 , of grid side inductor current can be
expressed as:

𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝑃𝐼 (𝑠) = 𝐺 𝑖𝐿 𝑓 𝑔,𝑃𝐼 (𝑠) · 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝐿 𝑓 𝑔 (𝑠). (4.24)

Notch filtered PI control transfer function

For the second control strategy of adding a notch filter after the PI controller to attenuate the
resonance spike in Fig. 4.7(b), the corresponding system plant model has been shown in Fig.

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 (a) (b)

Figure 4.11: Bode plots for cascaded PI control from (a) 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 and (b) 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑣 𝐶 𝑓 with
the inner loop 𝐾 𝑝,𝑣𝐶 𝑓 gain swept from 1 to 625.

4.8(b). Based on the derivation of notch filter design in (4.12), the transfer function from tracking
error, 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 , to the measurement, 𝑖 𝐿 𝑓 𝑔 , of grid side inductor current can be expressed as:

𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑖𝐿𝑔,𝑁𝑜𝑡𝑐ℎ𝑃𝐼 (𝑠) = 𝐺 𝑖𝐿 𝑓 𝑔,𝑃𝐼 (𝑠) · 𝐺 𝑁𝑜𝑡𝑐ℎ (𝑠) · 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝐿 𝑓 𝑔 (𝑠). (4.25)

Cascaded PI control transfer function

For the third control strategy of cascaded PI controller in Fig. 4.7(c), the corresponding system
plant model has been shown in Fig. 4.8(c). Based on the derivations in (4.7) and (4.13), the transfer
function from tracking error of output capacitor voltage, 𝑣 𝐶 𝑓 ,𝑒𝑟𝑟 , to the measurement of grid side
inductor current, 𝑖 𝐿 𝑓 𝑔 , can be derived as:

𝐺 𝑣𝐶 𝑓 𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) = 𝐺 𝑣𝐶 𝑓 ,𝑃𝐼 (𝑠) · 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝐿 𝑓 𝑔 (𝑠). (4.26)

Then, the transfer function from the reference of output capacitor voltage, 𝑣 𝐶 𝑓 ,𝑟𝑒 𝑓 , to the mea-
surement of grid side inductor current, 𝑖 𝐿 𝑓 𝑔 , can be expressed as:

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 Figure 4.12: The cascaded MMPC control parameter design flow chart.

𝐺 𝑣𝐶 𝑓 𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠)

𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) = . (4.27)
1 + 𝐺 𝑣𝐶 𝑓 𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠)

Furthermore, adding the outer loop grid side inductor current PI control, the transfer function

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 (a) (b)

Figure 4.13: The bode plots of the PI control, notch filtered PI control and cascaded MMPC
methods transfer functions from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 with the cascaded MMPC (a) weighing factor Q/R
swept from 100 to 800 at the 𝐾 𝑝 gain of 10 and (b) 𝐾 𝑝 gain swept from 10 to 40 at the Q/R of 400.

(a) (b)

Figure 4.14: The step responses of the cascaded MMPC close loop transfer function from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟
to 𝑖 𝐿 𝑓 𝑔 with (a) weighing factor Q/R swept from 100 to 800 and (b) 𝐾 𝑝 gain swept from 10 to 40.

from the tracking error, 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 , to the measurement, 𝑖 𝐿 𝑓 𝑔 , of grid side inductor current can be
expressed as:

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 (a) (b)

Figure 4.15: The zeros and poles plots of the cascaded MMPC from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 with (a)
weighing factor Q/R swept from 100 to 800 and (b) 𝐾 𝑝 gain swept from 10 to 40.

𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) = 𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) · 𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠). (4.28)

Then, the transfer function from the reference, 𝑖 𝐿 𝑓 𝑔,𝑟𝑒 𝑓 , to the measurement, 𝑖 𝐿 𝑓 𝑔 , of grid side
inductor current can be derived as:

𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠)

𝐺 𝑖𝐿 𝑓 𝑔𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) = . (4.29)
1 + 𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠)

And, based on equation (4.29) and the 𝐿𝐶 𝐿 plant model in Fig. 4.3, the transfer function
from the reference of switch side inductor current, 𝑖 𝐿 𝑓 𝑔,𝑟𝑒 𝑓 , to the measurement of output capacitor
voltage, 𝑣 𝐶 𝑓 , can be derived as

𝐺 𝑖𝐿 𝑓 𝑔𝑟𝑒 𝑓 2𝑣𝐶 𝑓 ,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) = 𝐺 𝑖𝐿 𝑓 𝑔𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝐶𝑎𝑠𝑐𝑎𝑑𝑒𝑑𝑃𝐼 (𝑠) · (𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 ). (4.30)

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Cascaded MMPC control transfer function

For the fourth control strategy of cascaded MMPC in Fig. 4.7(d), the corresponding system
plant model has been shown in Fig. 4.8(d). The inner loop per phase switch side 𝐿𝐶 MMPC is
cascaded with the outer loop of grid side inductor current control. A linear-quadratic regulator
(LQR) can be applied to derive the transfer function for the MPC algorithm part in the control
plant model of Fig. 4.8(d) to solve the cost function of (4.18).
A typical LQR control diagram integrated with a dynamic system is shown in Fig. 4.9 where
𝑥, 𝑦, 𝑢, 𝑟 represent the state variable, [𝑖 𝐿 𝑓 𝑠 ; 𝑣 𝐶 𝑓 ], output variable, 𝑖 𝐿 𝑓 𝑠 , input variable of duty cycle,
𝑑, and tracking reference, 𝑖 𝐿 𝑓 𝑠,𝑟𝑒 𝑓 , respectively. The middle block of Fig. 4.9 is the core algorithm
of MPC to calculate the optimal duty cycle which is a linear coefficient matrix, -K. And the MPC
equation to calculate the optimal duty cycle based on the tracking error and state variable can be
expressed as:

   
 𝑖𝐿 𝑓 𝑠   𝑖𝐿 𝑓 𝑠 
   
   
𝑑 = −K  𝑣 𝐶 𝑓  = −[𝐾11 , 𝐾12 , 𝐾13 ]

 𝑣
 𝐶𝑓

 (4.31)
   
   
 𝑣 𝐶 𝑓 ,𝑒𝑟𝑟   𝑣 𝐶 𝑓 ,𝑒𝑟𝑟 
   
where 𝑣 𝐶 𝑓 ,𝑒𝑟𝑟 is the tracking error of the MPC calculated as 𝑣 𝐶 𝑓 ,𝑟𝑒 𝑓 − 𝑣 𝐶 𝑓 .
Thus, the inner loop of MPC can be expressed in the transfer function as Fig. 4.8(d). The
transfer function from tracking error, 𝑣 𝐶 𝑓 ,𝑒𝑟𝑟 , to the measurement, 𝑣 𝐶 𝑓 , of output capacitor voltage
can be expressed as:

−𝐾13 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝑔 (𝑠)(𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 )(𝑠𝐿 𝑓 𝑠 + 𝑅 𝐿 𝑓 𝑠 )/𝑉𝑑𝑐

𝐺 𝑣𝐶 𝑓 𝑒𝑟𝑟2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠) =
{(𝑠𝐿 𝑓 𝑠 + 𝑅 𝐿 𝑓 𝑠 ) + 𝐾11 [𝑉𝑑𝑐 − 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝑔 (𝑠)(𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 )]/𝑉𝑑𝑐 +

𝐾12 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝑔 (𝑠)(𝑠𝐿 𝑓 𝑠 + 𝑅 𝐿 𝑓 𝑠 )(𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 )/𝑉𝑑𝑐 − (4.32)

𝐾13 𝐺 𝐿𝐶 𝐿,𝑣𝑥2𝑖𝑔 (𝑠)(𝑠𝐿 𝑓 𝑠 + 𝑅 𝐿 𝑓 𝑠 )(𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 )/𝑉𝑑𝑐 }.

Furthermore, the transfer function from the reference, 𝑣 𝐶 𝑓 ,𝑟𝑒 𝑓 , to the measurement, 𝑣 𝐶 𝑓 , of

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output capacitor voltage can be expressed as:

𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠) = 𝐺 𝑣𝐶 𝑓 𝑒𝑟𝑟2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠)/[1 + 𝐺 𝑣𝐶 𝑓 𝑒𝑟𝑟2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠)]. (4.33)

Based on equation (4.33) and the 𝐿𝐶 𝐿 plant model in Fig. 4.3, the transfer function from the
reference of output capacitor voltage, 𝑣 𝐶 𝑓 ,𝑟𝑒 𝑓 , to the measurement of grid side inductor current,
𝑖 𝐿 𝑓 𝑔 , can be derived as:

𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝑀 𝑃𝐶 (𝑠) = 𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠)/(𝑠𝐿 𝑓 𝑔 + 𝑅 𝐿 𝑓 𝑔 ). (4.34)

Then, taking the outer loop grid side inductor current PI control into consideration, the cascaded
MMPC transfer function from tracking error, 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 , to the measurement, 𝑖 𝐿 𝑓 𝑔 , of grid side induc-
tor current can be expressed as:

𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑖𝐿 𝑓 𝑔,𝑀 𝑃𝐶 (𝑠) = 𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑖𝐿 𝑓 𝑔,𝑀 𝑃𝐶 (𝑠) · 𝐺 𝑖𝐿 𝑓 𝑔,𝑃𝐼 (𝑠). (4.35)

The cascaded MMPC transfer function from tracking error of grid side inductor, 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 , to the
measurement of output capacitor voltage, 𝑣 𝐶 𝑓 , can be expressed as:

𝐺 𝑖𝐿 𝑓 𝑔𝑒𝑟𝑟2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠) = 𝐺 𝑣𝐶 𝑓 𝑟𝑒 𝑓 2𝑣𝐶 𝑓 ,𝑀 𝑃𝐶 (𝑠) · 𝐺 𝑖𝐿 𝑓 𝑔,𝑃𝐼 (𝑠). (4.36)

4.3.2 Mechanism of Inner-loop MMPC for Active Damping

The resonance behavior and dynamic performance of the four control strategies for 𝐿𝐶 𝐿 fil-
tered grid-connected inverter are analyzed based on the derived transfer functions. Fig. 4.10(a),
4.11(a) and Fig. 4.10(b), 4.11(b) show the bode plots comparison of transfer functions from the
tracking error to the measurement of grid side inductor current and from the tracking error of grid
side inductor current to the measurement of output capacitor voltage, respectively. The magnitude
plots manifest that the PI control in Fig. 4.8(a) has a convex spike at the resonant frequency point.
The notch filtered PI control in Fig. 4.8(b) has a concave spike at the resonant frequency point.

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The cascaded PI control in Fig. 4.8(c) has a narrow bandwidth at high frequency range. The cas-
caded MMPC in Fig. 4.8(d) attenuates the spike at the resonant frequency point and the control
bandwidth is wider than the conventional PI, notch filtered PI and cascaded PI methods.
Thus, the inner loop MPC of the cascaded MMPC is functioned as an active damping term to
mitigate the resonance in 𝐿𝐶 𝐿 system. This active damping term contributes to the improvement of
stability and control bandwidth. Furthermore, the fast response and active damping characteristics
of the inner loop MPC permits a wider control bandwidth for the outer loop PI control. Instead
of concerning about instability of resonance in the PI control method of Fig. 4.8(a), the gains of
the outer loop grid side inductor PI controller can be largely increased to improve the dynamic
performance. So, by carefully designing the outer loop PI control gain, 𝐾 𝑝 , and the inner loop
MPC weighing factor of the cascaded MMPC, 𝑊 𝐹 = 𝑄/𝑅, the 𝐿𝐶 𝐿 system dynamic performance
can be further improved.

4.3.3 Cascaded Control Design for Dynamic Performance

The control design of the proposed cascaded MMPC is analyzed in this section. Two key
parameters of outer loop PI control gain, 𝐾 𝑝 , and the inner loop MPC weighing factor, 𝑊 𝐹, need
to be designed. The bode plots of open loop transfer functions, closed loop step responses and
zero-pole maps are evaluated for the design procedure.
The optimal cascaded control design flowchart is shown in Fig. 4.12 which includes inner loop
MPC weighing factor, 𝑊 𝐹, design and outer loop grid side inductor current PI gain, 𝐾 𝑝 , design.
Since the inner loop MPC can attenuate the resonance spike by functioning as an active damping
term, the outer loop PI gain is permitted with a larger tuning range without losing stability. The
control parameter design starts from the inner loop.
Firstly, the design parameters should be initialized based on the bandwidths of inner and outer
loop controllers. Typically, the PI control bandwidth, 𝐵𝑊𝑃𝐼 , is configured to be 5-10 times slower
than the inner loop MPC bandwidth, 𝐵𝑊 𝑀 𝑃𝐶 [95]:

102
 5𝐵𝑊𝑃𝐼 ≤ 𝐵𝑊 𝑀 𝑃𝐶 ≤ 10𝐵𝑊𝑃𝐼 . (4.37)

And the PI control cutoff frequency, 𝜔𝑐 , should be set below 30% of the 𝐿𝐶 𝐿 resonant frequency,
𝜔𝑟𝑒𝑠 :

𝜔𝑐 ≤ 30%𝜔𝑟𝑒𝑠 . (4.38)

The initial values for optimal PI gains design flow chart can follow the equations below [79]:

(𝐿 𝑓 𝑠 + 𝐿 𝑓 𝑔 ) 𝑓𝑠𝑤
𝐾 𝑝,𝑖𝐿 𝑓 𝑔 = (4.39a)
3
𝐿 𝑓𝑠 + 𝐿 𝑓𝑔
𝜏𝑖,𝑖𝐿 𝑓 𝑔 = (4.39b)
𝑅𝑓𝑠 + 𝑅𝑓𝑔

where 𝑓𝑠𝑤 and 𝜏𝑖,𝑖𝐿 𝑓 𝑔 are the switching frequency and integral time constant, respectively. The
initial value for weighing factor can start from a typical range of 800-1000.
Secondly, based on the initial 𝑊 𝐹 and 𝐾 𝑝 , the inner loop weighing factor is swept from 100
to 800. During the sweeping period, the bode plots of open loop transfer functions from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟
to 𝑖 𝐿 𝑓 𝑔 are derived in Fig. 4.13(a). Also, the step responses and zero-pole map of closed loop
transfer functions from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 are derived in Fig. 4.14(a) and Fig. 4.15(a), respectively.
With the reduction of weighing factor, the control bandwidth is increased in Fig. 4.13(a). And
the response time is decreased with more overshoot in the transient period as is shown in Fig.
4.14(a). The sweeping check conditions of inner loop MPC weighing factor are the overshoot
percentage, response time and poles magnitude. Since the outer loop 𝐾 𝑝 gain is kept in low level
and has not been tuned yet, the overshoot is not a big issue in the sweeping process of inner loop
weighing factor. And the response time is largely determined by the outer loop 𝐾 𝑝 gain and has
not been shortened yet in the inner loop sweeping process. Thus, for the sweeping procedure of
weighing factor, the overshoot check condition threshold can be configured smaller than the outer

103
loop sweeping process. And the response time check condition threshold can be configured larger
than the outer loop sweeping process. If the overshoot is larger than 5%, response time is smaller
than 5ms or poles are outside of the unit circle, the weighing factor sweeping is stopped to entering
the outer loop PI gain sweeping procedure.
Thirdly, the outer loop PI gain is swept from 10 to 40. During the sweeping period, the bode
plots of open loop transfer functions from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 are also derived in Fig. 4.13(b). Also,
the step responses and zero-pole map of closed loop transfer functions from 𝑖 𝐿 𝑓 𝑔,𝑒𝑟𝑟 to 𝑖 𝐿 𝑓 𝑔 are
derived in Fig. 4.14(b) and Fig. 4.15(b), respectively. With the increment of gain, the control
bandwidth is increased in Fig. 4.13(b). And the response time is decreased with more overshoot
in the transient period as is shown in Fig. 4.14(b). Same sweeping check items of outer loop PI
gain are configured as the overshoot percentage, response time and poles magnitude with different
thresholds. Compared with the inner loop weighing factor sweeping, the outer loop gain sweeping
procedure addresses more on the tracking speed and less on overshoot issue, since the inner loop
MPC has been proved to guarantee an active damping function for the whole 𝐿𝐶 𝐿 system stability
to attenuate the resonance. If the overshoot is larger than 10%, response time is smaller than 1ms
or poles are outside of the unit circle, the weighing factor sweeping is stopped to finalize the outer
loop PI gain sweeping procedure.

Table 4.1: System Parameter Configurations

Parameter Value
Grid voltage, 𝑉𝑔𝑟𝑖𝑑,𝐿−𝑁 110V-120V
DC voltage, 𝑉𝑑𝑐 400V-450V
Switching frequency 80kHz
Switch side inductor, 𝐿 𝑓 𝑠 45𝜇H
Grid side inductor, 𝐿 𝑓 𝑔 450𝜇H
Output Capacitor, 𝐶 𝑓 12𝜇F
MOSFET C3M0021120K
Controller LAUNCHXL-F28379D
Leakage current ≤ 15mA

104
 (a) (b)

(c)

Figure 4.16: Comparison of the experimentally captured estimation and measurement of (a) switch
side inductor current (b) output capacitor voltage and (c) grid side inductor current.

Figure 4.17: Steady state waveforms of switch side inductor current, output capacitor voltage, grid
side inductor current and DC bus voltage.

Table 4.2: Control Parameters of Different Methods

Q/R 𝐾𝑝
PI n/a 2, 20
Notch filtered PI n/a 20
MMPC 400 10, 20, 30, 40

105
Figure 4.18: Steady state waveforms of three-phase grid voltage, leakage current, DC bus voltage
and zero-sequence grid voltage.

(a) (b)

Figure 4.19: (a) Transient and (b) zoomed transient waveforms of switch side inductor current,
output capacitor voltage, grid side inductor current and DC bus voltage with 𝑖 𝐿 𝑓 𝑔,𝑞 from 3A to
10A.

(a) (b)

Figure 4.20: Cascaded MMPC transient captured ADC readings of grid side inductor current 𝑞
component (a) from 2A to 8A and (b) from 8A to 2A with 𝐾 𝑝 gain of 10, 20, 30 and 40.

106
 (a) (b)

Figure 4.21: Comparison of PI, notch filtered PI and MMPC transient captured ADC readings of
(a) grid side inductor current 𝑞 component from 2A to 8A and (b) zoomed waveforms.

(a) (b)

Figure 4.22: Comparison of PI and MMPC transient captured ADC readings of (a) grid side in-
ductor current 𝑞 component from 8A to 2A and (b) zoomed waveforms.

4.4 Results

The proposed optimal control design method for resonance damping and dynamic perfor-
mance improvement is validated experimentally on the modified non-isolated three-phase con-
verter with grid simulator. The testing parameters are 400-450𝑉𝑑𝑐 to 110-120𝑉𝐿−𝑁 with switching
frequency of 80kHz. The 𝐿𝐶 𝐿 filter parameters are 45𝜇H for 𝐿 𝑓 𝑠 , 12𝜇F for 𝐶 𝑓 and 450𝜇H for

107
 (a) (b)

(c) (d)

(e)

Figure 4.23: Waveforms comparison of inductor current, output capacitor voltage, grid current and
DC bus voltage for (a) PI control with 𝐾 𝑝 of 20 (b) notch filtered PI control with 𝐾 𝑝 of 20 (c) PI
control with 𝐾 𝑝 of 2 (d) MMPC control with 𝐾 𝑝 of 20 and (e) cascaded PI control with 𝐾 𝑝 of 2.

𝐿 𝑓 𝑔 . C3M0021120K SiC from Cree and TMS320F28379D from TI are applied for switches and
controller, respectively.

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4.4.1 State Estimation Test

The state estimator combined with the MPC has been tested experimentally for the reduction
of sensor count. Fig. 4.16(a), 4.16(b) and 4.16(c) show the captured ADC readings of estimation
and measurement for switch side inductor current, output capacitor voltage and grid side inductor
current, respectively. The switch side inductor current can be accurately estimated for MPC control
purpose based on the measurement of output capacitor voltage and grid side inductor current.

4.4.2 Steady State Common Mode Test

The steady state performance of the cascaded MMPC is tested experimentally to show the
stabilized zero-sequence grid voltage and reduced leakage current. Fig. 4.17 shows the switch
side inductor current, output capacitor voltage, grid side inductor current and DC bus voltage in
steady state. The leakage current and zero-sequence grid voltage performances are shown in Fig.
4.18 with 450V DC bus. It can be seen from the bottom waveform that the zero-sequence grid
voltage has been stabilized to be constant at half of DC bus, 225V. And the leakage current has
been attenuated to be less than 15mA. Thus, the developed zero-sequence voltage MPC method
is capable of reducing leakage current in the modified non-isolated 𝐿𝐶 𝐿 inverter. The standard
requirements of leakage current in IEC and IET are also satisfied.

4.4.3 Dynamic and Stability Performance Test

The dynamic performance of the developed optimal control design method for cascaded MMPC
is validated with step transient testing. Fig. 4.19 shows the transient waveforms of switch side in-
ductor current, output capacitor voltage, grid side inductor current and DC bus voltage with a
current step of 7A. The transient performance of control methods are evaluated by capturing the
experimental ADC readings with current steps. Fig. 4.20(a) and Fig. 4.20(b) show the 𝑖 𝐿 𝑓 𝑔,𝑞 steps
from 2A to 8A and 8A to 2A with different outer loop grid side inductor current control gains
of 10, 20, 30 and 40, respectively. Thus, the optimal gain is selected as 20 based on the control
parameter design flow chart. For the dynamic performance comparison of PI control, notch filtered

109
PI control, cascaded MMPC and cascaded PI methods, Fig. 4.21 and Fig. 4.22 show the 𝑖 𝐿 𝑓 𝑔,𝑞
steps and zoomed waveforms from 2A to 8A and 8A to 2A under five testing cases: (1) PI control
with 𝐾 𝑝 gain of 20; (2) notch filtered PI control with 𝐾 𝑝 gain of 20; (3) PI control with 𝐾 𝑝 gain of
2; (4) MMPC control with 𝐾 𝑝 gain of 20; (5) cascaded PI control with 𝐾 𝑝 gain of 2. It can be seen
that the the MMPC behaves more stable than either PI control or notch filtered PI control at high
𝐾 𝑝 gain of 20 with less overshoot and oscillation. Even though the PI and cascaded PI methods can
act stably with a smaller 𝐾 𝑝 gain of 2, the response time is much longer than MMPC. For a more
intuitional comparison, the inductor current, output capacitor voltage, grid current and DC bus
voltage waveforms of these five testing cases are shown in Fig. 4.23(a), 4.23(b), 4.23(c), 4.23(d)
and 4.23(e), respectively. The PI control has more oscillation than MMPC method at the same high
𝐾 𝑝 gain condition of 20. Even with the notch filter, a high 𝐾 𝑝 gain of 20 could also oscillate the
waveforms with slightly less ripple than pure PI. The cascaded PI has more oscillation than PI at
a low 𝐾 𝑝 of 2. The cascaded PI will diverge faster than PI method at higher 𝐾 𝑝 gain. The MMPC
can operate at a 𝐾 𝑝 of 20 without oscillation and shorten the response time without the need of
reducing the 𝐾 𝑝 gain as pure PI method. Thus, the experimental comparison of PI, notch filtered
PI, MMPC and cascaded PI verifies that the optimal control design method for cascaded MMPC
improves the dynamic performance with shorter response time, less overshoot and less oscillation.
Based on the theoretical analysis in this chapter, the improvements of MMPC is resulted from the
inner loop MPC which has the function of active damping and attenuation of resonance in 𝐿𝐶 𝐿
filtered grid-connected inverter. The corresponding control parameters for the experiments have
been summarized in table 4.2.

4.4.4 Comparison with the State of Art

The proposed active damping MMPC is compared with the state of art for the grid-connected
𝐿𝐶 𝐿 inverter MPC control methods in this section. [96] proposed an observations-based FCS-
MPC method with grid side inductor current sensors for balanced and unbalanced grid voltage
conditions. [97] proposed two implementations of FCS-MPC methods to eliminate the low-order

110
grid current harmonics and decrease the sensitivity to grid voltage distortion. [98] and [99] pro-
posed also FCS-MPC methods to deal with the dynamic performance of grid-connected 𝐿𝐶 𝐿 in-
verter in 𝛼𝛽 reference frame. The advantages of the proposed MMPC can be concluded in three
aspects: (1) The computation burden is low to be implemented explicitly on a low cost DSP instead
of the expensive FPGA for the above mentioned references. The proposed MMPC is implemented
in per phase switch side 𝐿𝐶 of 𝑎𝑏𝑐 reference frame instead of 𝑑𝑞 or 𝛼𝛽. Thus, the variable of grid
angular speed is not required in the state space matrix and the order of the per phase 𝐿𝐶 state space
matrix is lower. The execution time for MMPC is within 4𝜇s at each control interrupt. (2) The
proposed MMPC is combined with the modified inverter topology to stabilized the zero-sequence
voltage and attenuate the leakage current. This function enables the non-isolated converter ap-
plications to satisfy the grid-connection standard requirements for common mode behavior. (3)
The size of offline generated piecewise affine function C code file is small to be fit into the DSP
controller. Since the MMPC is implemented for per phase 𝐿𝐶 in 𝑎𝑏𝑐 reference frame, the explicit
solver function is largely simplified and the C file is within 5KB. This size could be easily fit into
the DSP memory.

4.5 Summary

This chapter develops an optimal control design method for resonance damping and dynamic
performance improvement of cascaded modular model predictive control for a modified grid-
connected 𝐿𝐶 𝐿 inverter. The 𝐿𝐶 𝐿 system is modeled to show the intrinsic resonance issue. Also,
the common mode circuit is analyzed for the modified non-isolated grid-connected inverter to
manifest the leakage current bypassing and zero-sequence voltage stabilization functions. Three
control strategies, including PI control, notch filtered PI control and cascaded MMPC, are studied
with zero-sequence stabilization capabilities to explore the dynamic and stability performance. The
cascaded MMPC is validated to have the active damping function by inserting an inner loop MPC
cascaded with outer loop PI control. This cascaded control structure is capable of damping the
resonance and increasing the control bandwidth to improve the system dynamic performance. A

111
control parameter design method is finally proposed for the cascaded MMPC to derive the optimal
weighing factor and gain. The experiments have validated the proposed method.

112
 Chapter 5: Hierarchical Software-Defined Control Architecture with

MPC-Based Power Module

In practice, high performance power conversion systems require specialized design to satisfy
the demands from various loads or sources. Based on the features of different interfaced applica-
tions, the corresponding power control algorithms, parametric modeling and operating robustness
design might be varying. Also, the hardware circuitry topologies need specific design procedures.
The repetitive power electronics design routines increase the cost both from software algorithm and
hardware circuit perspectives. Firstly, an option to provide more generalized power electronics de-
sign is to introduce the modular concept. For the power conversion system with various possible
interfaced applications, the basic power module can be designed to formulate different convert-
ers to meet the various demands. However, the existing modular power electronics either focus
on micro-grid system level to redistribute the energy among different interfaced power sources
or hardware device level to reconstruct different circuits within a certain application case [100,
101, 102]. Thus, the specific converter design is necessary for each of the application. Secondly,
to manipulate the power modules, multi-layer control is typically applied for the digital control
system. Similarly, the commonly used multi-layer control techniques are concentrating on either
the whole micro-grid system level to manage among the distributed energy resources (DER) or
individual converter level with cascaded power control methods [103, 104, 105, 106, 107, 108].
Thirdly, the generalized power module needs a robust and stable control technique to satisfy dif-
ferent application requirements. Conventional PI method is simple to implement. But the dynamic
performance and resonant oscillation could cause operating issues under various types of energy
interfaces. MPC is an advanced control technique which has better dynamic performance and
higher robustness [75, 76, 77, 78, 43, 109].

113
 Figure 5.1: Hirarchical control architecture with MPC-based power module.

This chapter proposes a hierarchical software-defined control architecture with MPC-based

power modules to improve the performance of energy conversion system with reconfigurability
for different applications including single/three-phase grid, motor, battery, etc. Firstly, the control
architecture is introduced with the system modeling of local MPC-based power module and three
types of interfaced applications. Secondly, the three-layer hierarchical control architecture is illus-
trated in details including central control layer, local module control layer and application layer.
Thirdly, the merits of the developed control architecture are summarized with the corresponding
experimental validations.

114
 Local Power Control Module
io iL Vc* Vc Vdc
M1 Cf,up

Local MPC Controller

Gate
Driver
iL io
PWM,up

duty Lfs +
PWM,lo
Vc
Gate Cf,lo _
Driver M2

Figure 5.2: Local MPC-based power module.

5.1 System Modeling

The proposed hierarchical control architecture is shown in Fig. 5.1. The architecture is com-
posed of three layers which make the system reconfigurable for different types of load/source and
power converter topologies. From top to bottom of Fig. 5.1, the multi-layer control architecture is
constituted by central control layer, local module control layer and application layer. Specifically,
the central control layer includes software-defined functions that are responsible for the recog-
nition of different types of interfaced load/source, reconstruction of power converter, high level
current/voltage/power control and generate references for local power module control. The local
module control layer is composed of desired number of MPC-based power module unit as is shown
in Fig. 5.2. The local power module is configured with MPC to improve the dynamic performance
and attenuate the common-mode noise. The application layer defines the interface with different
types of load/source including single/three-phase grid, battery, motor, etc. This section analyzes
the system modeling of the key basic component (local power module) and the correspondingly
formulated different applications of the proposed hierarchical control architecture.

5.1.1 Local Power Module Modeling

As is shown in Fig. 5.2, the local power module consists of the upper/lower switches, switch
side inductor, upper/lower output capacitors and the high-resolution MPC controller for the per
module 𝐿𝐶 control. The differential equations for the local power module 𝐿𝐶 filter can be ex-

115
pressed as:

1 𝑣 𝑑𝑐
𝑖¤𝐿 𝑓 𝑠 (𝑡) = − 𝑢𝐶 𝑓 (𝑡) + 𝑑 (𝑡) (5.1a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑢¤ 𝐶 𝑓 (𝑡) = 𝑖 𝐿 𝑓 (𝑡) − 𝑖 𝐿 𝑓 𝑜 (𝑡). (5.1b)
𝐶𝑓 𝐶𝑓

where 𝐿 𝑓 𝑠 and 𝐶 𝑓 are the switch side inductor and capacitor, respectively. 𝑖 𝐿 𝑓 𝑠 , 𝑣 𝐶 𝑓 and 𝑖 𝐿 𝑓 𝑜 are
the switch side inductor current, capacitor voltage and output side current. The local MPC control
algorithm is designed based on the per phase 𝐿𝐶 filter to track the reference commands from the
central control layer.

5.1.2 Application Modeling

With the recognition and reconstruction of different types of load/source interfaces from the
central control layer, different number of local power modules are connected with the correspond-
ing system models to perform the specific power control algorithms. The various types of applica-
tions include single/three-phase grid connection, motor traction and battery.

Single-Phase Grid

Firstly, two local power modules can be connected in parallel to formulate a single-phase full-
bridge transformerless grid-connected inverter as is shown in Fig. 5.3(a). The state space equations
in 𝑎𝑏 reference frame can be expressed as:

1 1
𝑖¤𝐿 𝑓 𝑠,𝑎𝑏 = I1𝜙 𝑣 𝑥,𝑎𝑏 − I1𝜙 𝑣 𝐶 𝑓 ,𝑎𝑏 (5.2a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑣¤ 𝐶 𝑓 ,𝑎𝑏 = I1𝜙 𝑖 𝐿 𝑓 𝑠,𝑎𝑏 − I1𝜙 𝑖 𝐿 𝑓 𝑔,𝑎𝑏 (5.2b)
𝐶𝑓 𝐶𝑓
1 1
𝑖¤𝐿 𝑓 𝑔,𝑎𝑏 = I1𝜙 𝑣 𝐶 𝑓 ,𝑎𝑏 − I1𝜙 𝑣 𝑔,𝑎𝑏 , (5.2c)
𝐿 𝑓𝑔 𝐿 𝑓𝑔

where 𝐿 𝑓 𝑠 , 𝐶 𝑓 and 𝐿 𝑓 𝑔 are the switch side inductor, capacitor and grid side inductor, respectively,

116
for the 𝐿𝐶 𝐿 filter. 𝑖 𝐿 𝑓 𝑠,𝑎𝑏 , 𝑣 𝐶 𝑓 ,𝑎𝑏 , 𝑖 𝐿 𝑓 𝑔,𝑎𝑏 and 𝑣 𝑥,𝑎𝑏 are the switch side inductor current, capacitor
voltage, grid side current and grid voltage for the single-phase grid-connected system, respectively.
I1𝜙 ∈ R2×2 is the identity matrix for single-phase grid connection system.
Leveraging the Park and Clarke transformations, the state space equations can be converted to
the 𝑑𝑞0 reference frame for the central level control:

1 1
𝑖¤𝐿 𝑓 𝑠,𝑑𝑞0 = I𝑑𝑞0 𝑣 𝑥,𝑑𝑞0 − I𝑑𝑞0 𝑣 𝐶 𝑓 ,𝑑𝑞0 − 𝜔S𝑖 𝐿 𝑓 𝑠,𝑑𝑞0 (5.3a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑣¤ 𝐶 𝑓 ,𝑑𝑞0 = I𝑑𝑞0𝑖 𝐿 𝑓 𝑠,𝑑𝑞0 − I𝑑𝑞0𝑖 𝐿 𝑓 𝑔,𝑑𝑞0 − 𝜔S𝑣 𝐶 𝑓 ,𝑑𝑞0 (5.3b)
𝐶𝑓 𝐶𝑓
1 1
𝑖¤𝐿 𝑓 𝑔,𝑑𝑞0 = I𝑑𝑞0 𝑣 𝐶 𝑓 ,𝑑𝑞0 − I𝑑𝑞0 𝑣 𝑔,𝑑𝑞0 − 𝜔S𝑖 𝐿 𝑓 𝑔,𝑑𝑞0 (5.3c)
𝐿 𝑓𝑔 𝐿 𝑓𝑔

where 𝜔 is the angular velocity of the grid in rad/s. S is the matrix, [0, -1, 0; 1, 0, 0; 0, 0, 0], for
the coupling terms of single-phase grid-connection model. I𝑑𝑞0 ∈ R3×3 is the identity matrix for
𝑑𝑞0 grid connection system.
Different from the conventional inverter topologies, the upper/lower output capacitors of the
local MPC-based power module provide common-mode leakage current bypassing paths for the
formulated single-phase grid-connected inverter as is shown in Fig. 5.4(a). The common-mode
voltage of the single-phase topology can be derived as:

𝑣 𝐶 𝑓 ,𝑎 + 𝑣 𝐶 𝑓 ,𝑏
𝑣 𝑐𝑚,1𝜙 = 𝑣 𝐶 𝑓 0,1𝜙 = . (5.4)
2

The leakage leakage current is typically excited by the high frequency fluctuation of the common-
mode voltage to be injected into the grid through a parasitic capacitor, 𝐶 𝑝𝑎𝑟𝑎 . The leakage current
is defined as:

𝑑𝑣 𝐶 𝑓 0,1𝜙
𝑖𝑙𝑘𝑔,1𝜙 = 𝑖 𝐿 𝑓 𝑔0,1𝜙 = 𝐶 𝑝𝑎𝑟 𝑎 . (5.5)
𝑑𝑡

With two MPC-based power modules connected in parallel for single-phase grid-connected
inverter in Fig. 5.3(a), the equivalent common-mode circuit in Fig. 5.4(a) demonstrates that the

117
leakage current can be bypassed by the upper/lower output capacitors with the zero-sequence volt-
age MPC control. From the control perspective, the embedded local power module zero-sequence
voltage MPC can stabilize the common-mode voltage, 𝑣 𝐶 𝑓 0,1𝜙 , to be constant as half of DC bus
voltage. Then, according to (5.5), the leakage current flowing to the grid will be largely attenuated.

Three-Phase Grid

Secondly, three local power modules can be connected in parallel to formulate a three-phase
transformerless grid-connected inverter as is shown in Fig. 5.3(b). The state space equations in
𝑎𝑏𝑐 reference frame is similar with equation (5.2) by substituting 𝑖 𝐿 𝑓 𝑠,𝑎𝑏 , 𝑣 𝐶 𝑓 ,𝑎𝑏 , 𝑖 𝐿 𝑓 𝑔,𝑎𝑏 , 𝑣 𝑥,𝑎𝑏 and
I1𝜙 ∈ R2×2 with 𝑖 𝐿 𝑓 𝑠,𝑎𝑏𝑐 , 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 , 𝑖 𝐿 𝑓 𝑔,𝑎𝑏𝑐 and 𝑣 𝑥,𝑎𝑏𝑐 and I3𝜙 ∈ R3×3 for the three-phase system.
Leveraging the Park and Clarke transformations, the state space equations of three-phase sys-
tem can be converted to the 𝑑𝑞0 reference frame for the central level control which are similar with
equation (5.3) in the single-phase system.
Different from the conventional three-phase inverter topologies, the upper/lower output capac-
itors of the local MPC-based power module provide common-mode leakage current bypassing
paths for the formulated three-phase grid-connected inverter as is shown in Fig. 5.4(b). The
common-mode voltage and leakage current expressions are similar to equations (5.4) and (5.5)
by transferring single-phase variables into three-phase system.
With three MPC-based power modules connected in parallel for three-phase grid-connected
inverter in Fig. 5.3(b), the equivalent common-mode circuit in Fig. 5.4(b) demonstrates that the
leakage current can be bypassed by the upper/lower output capacitors with the zero-sequence volt-
age MPC control. From the control perspective, the embedded local power module zero-sequence
voltage MPC can stabilize the common-mode voltage, 𝑣 𝐶 𝑓 0,3𝜙 , to be constant as half of DC bus
voltage. Then, the leakage current flowing to the grid will also be largely attenuated.

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Motor Drive

Thirdly, three local power modules can also be connected in parallel to formulate a three-
phase transformerless motor traction inverter as is shown in Fig. 5.3(c). Different from the grid-
connected inverter applications, the motor drive interface does not require the grid side inductors,
𝐿 𝑓 𝑔 . Three power modules can be directly connected to the motor. Thus, the motor drive modeling
can be separated into switch side 𝐿𝐶 filter modeling and PMSM modeling.
For the switch side 𝐿𝐶 filter modeling, the state space equations in 𝑎𝑏𝑐 reference frame can be
derived as:

1 1
𝑖¤𝐿 𝑓 𝑠,𝑎𝑏𝑐 = I3𝜙 𝑣 𝑥,𝑎𝑏𝑐 − I3𝜙 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 (5.6a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑣¤ 𝐶 𝑓 ,𝑎𝑏𝑐 = I3𝜙 𝑖 𝐿 𝑓 𝑠,𝑎𝑏𝑐 − I3𝜙 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑎𝑏𝑐 (5.6b)
𝐶𝑓 𝐶𝑓

where 𝑖 𝑚𝑜𝑡𝑜𝑟,𝑎𝑏𝑐 is the current flowing into the motor winding. Leveraging the Park and Clarke
transformations, the state space equations can be converted to the 𝑑𝑞0 reference frame for the
central level control:

1 1
𝑖¤𝐿 𝑓 𝑠,𝑑𝑞0 = I𝑑𝑞0 𝑣 𝑥,𝑑𝑞0 − I𝑑𝑞0 𝑣 𝐶 𝑓 ,𝑑𝑞0 − 𝜔M𝑖 𝐿 𝑓 𝑠,𝑑𝑞0 (5.7a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑣¤ 𝐶 𝑓 ,𝑑𝑞0 = I𝑑𝑞0𝑖 𝐿 𝑓 𝑠,𝑑𝑞0 − I𝑑𝑞0𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑑𝑞0 − 𝜔M𝑣 𝐶 𝑓 ,𝑑𝑞0 (5.7b)
𝐶𝑓 𝐶𝑓

where M is the matrix, [0, -1, 0; 1, 0, 0; 0, 0, 0], for the coupling terms of motor drive model.
For the motor side modeling, a typical PMSM is analyzed in this section [110]. Different from
the grid side inductor current, 𝑖 𝐿 𝑓 𝑔,𝑑𝑞0 , the motor windng current, 𝑖 𝑚𝑜𝑡𝑜𝑟,𝑑𝑞0 , can be modeled as:

119
 1
𝑖¤𝑚𝑜𝑡𝑜𝑟 ,𝑑 =


𝑣 𝐶 𝑓 ,𝑑 − 𝑅𝑠 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑑 + 𝜔𝑒 𝐿 𝑞 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑞 (5.8a)
𝐿𝑑
1
𝑖¤𝑚𝑜𝑡𝑜𝑟 ,𝑞 =



𝑣 𝐶 𝑓 ,𝑞 − 𝑅𝑠 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑞 − 𝜔𝑒 𝐿 𝑑 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑑 + 𝜓 (5.8b)
𝐿𝑞
3


𝑇𝑒 = 𝑝 𝜆𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑞 + 𝐿 𝑑 − 𝐿 𝑞 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑑 𝑖 𝑚𝑜𝑡𝑜𝑟 ,𝑞 (5.8c)
2
1
𝜔¤ 𝑒 = (−𝐵𝜔𝑒 + 𝑝𝑇𝑒 − 𝑝𝑇𝑙 ) (5.8d)
𝐽

where 𝐿 𝑑 , 𝐿 𝑞 represent the 𝑑𝑞 component inductance of the motor, respectively; 𝑅𝑠 is the stator
winding resistance. 𝜓 is the flux of the permanent magnets. 𝜔 𝑒 is the electrical angular velocity
of the rotor which is related to the mechanical angular velocity 𝜔𝑚 by the pole pairs 𝑝 𝑝 by 𝜔 𝑒 =
𝑝 𝑝 𝜔𝑚 . 𝑇𝑒 and 𝑇𝑙 are the electrical and load torques, respectively. 𝐵 and 𝐽 are the friction and
inertia coefficients, respectively.
The motor bearing current and shaft voltage caused by the switching pulsation of the traction
inverter is a key factor that could result in electric motor failure. The upper/lower output capacitors
of the local MPC-based power module can provide common-mode leakage current bypassing paths
for the formulated motor traction inverter as is shown in Fig. 5.4(c). The common-mode voltage
of the motor traction inverter topology which is highly related to the shaft voltage of the motor can
be derived as:

𝑣 𝐶 𝑓 ,𝑎 + 𝑣 𝐶 𝑓 ,𝑏 + 𝑣 𝐶 𝑓 ,𝑐
𝑣 𝑐𝑚,𝑚𝑜𝑡𝑜𝑟 = 𝑣 𝐶 𝑓 0,𝑚𝑜𝑡𝑜𝑟 = . (5.9)
3

For the motor system, the leakage current is also typically generated by the high frequency fluc-
tuation of the common-mode voltage to be injected into the motor bearing through the parasitic
capacitor, 𝐶 𝑝𝑎𝑟𝑎 . The equivalent parasitic circuit model for the motor system has been displayed
in Fig. 5.4(c) which consists of two paths. The first parasitic path is from the stator windings to
the frame of the motor, 𝐶𝑤2 𝑓 . The second path includes two cascaded sections which are from the
stator windings to the rotor, 𝐶𝑤2𝑟 , and then from the rotor to the frame, 𝐶𝑟2 𝑓 , 𝐶𝑏,𝑁 𝐷𝐸 , 𝐶𝑏,𝐷𝐸 . The
leakage current, 𝑖 𝑙 𝑘𝑔,𝑚𝑜𝑡𝑜𝑟 , generated by the high frequency fluctuation of the common mode volt-

120
age mainly flows through the first path of stator windings to the frame capacitor, 𝐶𝑤2 𝑓 , because of
its low impedance. And the second path of leakage current is mostly relevant to the bearing current
and bearing voltage which are also generated by the high frequency fluctuation of common mode
voltage. Specifically, 𝐶𝑤2𝑟 , 𝐶𝑟2 𝑓 , 𝐶𝑏,𝑁 𝐷𝐸 and 𝐶𝑏,𝐷𝐸 are the stator windings to rotor capacitor,
rotor to frame capacitor, non-drive end and drive end capacitors, respectively. So, the equivalent
parasitic capacitance can be derived as:

(𝐶𝑟2 𝑓 + 𝐶𝑏, 𝑁 𝐷𝐸 + 𝐶𝑏,𝐷𝐸 )𝐶𝑤2𝑟

𝐶 𝑝𝑎𝑟 𝑎 = + 𝐶𝑤2 𝑓 . (5.10)
(𝐶𝑟2 𝑓 + 𝐶𝑏, 𝑁 𝐷𝐸 + 𝐶𝑏,𝐷𝐸 ) + 𝐶𝑤2𝑟

Thus, the leakage current also regarded as the bearing current is defined as:

𝑑𝑣 𝐶 𝑓 0,𝑚𝑜𝑡𝑜𝑟
𝑖𝑙𝑘𝑔,𝑚𝑜𝑡𝑜𝑟 = 𝑖0,𝑚𝑜𝑡𝑜𝑟 = 𝐶 𝑝𝑎𝑟 𝑎 . (5.11)
𝑑𝑡

With three MPC-based power modules connected in parallel for the modified motor traction
inverter in Fig. 5.3(c), the equivalent common-mode circuit in Fig. 5.4(c) demonstrates that the
leakage current can be bypassed by the upper/lower output capacitors with the zero-sequence volt-
age MPC control. From the control perspective, the embedded local power module zero-sequence
voltage MPC can stabilize the motor common-mode voltage, 𝑣 𝐶 𝑓 0,𝑚𝑜𝑡𝑜𝑟 , to be constant as half of
DC bus voltage. Then, according to (5.11), the leakage current flowing to the motor bearing will
also be largely attenuated.

5.2 Hierarchical Control Structure

The proposed hierarchical control structure is illustrated in this section. As is demonstrated in

Fig. 5.1, the hierarchical control structure consists of three layers: (1) Central control layer for
recognition of different types of load/source, reconfiguration of power converter topologies with
desired number of power modules, high level current/voltage/power control and generate refer-
ences for local MPC-based power module control; (2) Local module control layer for implement-
ing the MPC algorithm to track the references from the central controller with improved dynamic
performance, stabilizing the common-mode voltage, collecting ADC samplings and generating

121
 (a) (b)

(c)

Figure 5.3: (a) Single-phase grid (b) three-phase grid and (c) three-phase motor traction topological
applications of the multi-layer control architecture.

(a) (b)

(c)

Figure 5.4: Equivalent common-mode circuit of the formulated (a) Single-phase grid (b) three-
phase grid and (c) three-phase motor inverters.

122
 Kp,PLL Kp,PLL
vq*=0 + ω θ θ* vq*=0 + ω θ θ*
∫ ωtdt floor(θ/2π) floor(θ/2π)
+
_ + + +
∫ ωtdt
Ki,PLL/s _
Ki,PLL/s

θ* θ*
vα
vq αβ vq vα va
va αβ abc vb
vd dq delay π/4 vd dq αβ
vβ vβ vc

(a) (b)

Figure 5.5: (a) Single-phase and (b) three-phase PLL control blocks.

PWM signals for local power switches; (3) Application layer for the interface with different types
of load/source including single/three-phase grid, battery, motor drive and so on.

5.2.1 Single-Phase Grid Interface Control

Fig. 5.6 displays the control architecture for the application of single-phase grid interface. The
corresponding power converter topology is shown in Fig. 5.3(a).

Central Control Layer

The central control layer is functioned to recognize the single-phase grid interface and recon-
figure the power converter topology with two local power modules in parallel as is shown in Fig.
5.3(a). The specific functions of single-phase grid interface central control layer are illustrated as
follows.
Firstly, the single-phase grid side inductor current, 𝑖 𝐿 𝑓 𝑔,𝑎𝑏 , and output capacitor voltage, 𝑣 𝐶 𝑓 ,𝑎𝑏 ,
are received from the local power modules and transformed into 𝑑𝑞0 reference frame as 𝑖 𝐿 𝑓 𝑔,𝑑𝑞0
and 𝑣 𝐶 𝑓 ,𝑑𝑞0 , respectively, for the high level control purpose.
Secondly, the single-phase phase-lock loop (PLL) is designed in the central control layer as is
shown in Fig. 5.5(a). The virtual 𝛼𝛽 components of output capacitor voltage are constructed and
transformed to 𝑑𝑞 axis to control the 𝑞 component to be zero for the generation of accurate grid
angular speed, 𝜔, and phase angle, 𝜃.
Thirdly, the grid service control functions are configured to provide active/reactive power com-

123
 Figure 5.6: Single-phase grid application of the hierarchical architecture.

pensations based on the grid frequency/voltage abnormal conditions. The grid service control
blocks are detailed in Fig. 5.9 by following the standardized principles of IEEE 1547 [111]. The
general implementing methodology is to output the certain amount of active/reactive power for
the distributed energy resources (DER) by following the prescribed linear curve functions. The
linear functions in the grid service standards regulate the output active/reactive power based on the
variations of grid voltage/frequency and output active power to compensate for the abnormal grid

124
 Figure 5.7: Three-phase grid application of the hierarchical architecture.

conditions. Six typical working modes of the grid services have been shown in Fig. 5.9 including
constant reactive power mode (Const-Var), constant power factor mode (Const-PF), grid voltage
and reactive power mode (Volt-Var), active power and reactive power mode (P-Q), grid frequency
and active power mode (Freq-Watt), grid voltage and active power mode (Volt-Watt). Thus, the
grid service controller in the central control layer receives the measured grid voltage/frequency and
active power of DER to generate the desired active/reactive power references, 𝑃∗ and 𝑄 ∗ , for the
active/reactive power controllers. The active/reactive power controllers derive the 𝑑𝑞 components
of grid side inductor current references, 𝑖 ∗𝐿 𝑓 𝑔,𝑑𝑞 for the following grid current 𝑑𝑞 controllers.
Fourthly, the grid side inductor current 𝑑𝑞 components, 𝑖 𝐿 𝑓 𝑔,𝑑𝑞 , are controlled separately with

125
 Figure 5.8: Motor drive application of the hierarchical architecture.

two PI controllers to generate 𝑑𝑞 output capacitor voltage references, 𝑣 𝐶∗ 𝑓 ,𝑑𝑞 . And the zero-
sequence output capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,0 , is configured as half of DC bus voltage, 𝑣 𝑑𝑐 ,
to stabilize the common mode voltage. Combining the zero-sequence voltage control with the
modified topology in Fig. 5.3(a), the leakage current can be attenuated from flowing into the grid.
Then, the 𝑑𝑞0 components of output capacitor voltage references are transformed into 𝑎𝑏 refer-
ence frame with the reversed Park and Clarke functions as, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏 . The generated 𝑣 𝐶∗ 𝑓 ,𝑎𝑏 then will
be distributed to the per phase local module control layer as the tracking references of local MPC
control.

126
Figure 5.9: Grid service control blocks in the central control for single/three-phase grid interfaced
renewable energy applications.

Local Module Control Layer

The local module control layer of the single-phase grid interfaced system consists of two MPC-
based power modules. Each of the power module is implementing the same MPC algorithm for
the switch side 𝐿𝐶 filter to track the output capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏 , received from the
central control layer.
For the MPC implementation, in every control period, the MPC controller receives the mea-
sured switch side inductor current, 𝑖 𝐿,𝑎𝑏𝑐 , capacitor voltage, 𝑣 𝑐,𝑎𝑏𝑐 , grid current, 𝑖 𝑔,𝑎𝑏𝑐 , from ADC
and capacitor voltage reference, 𝑣 ∗𝑐,𝑎𝑏𝑐 from the grid current controller. An offline generated piece-
wise affine search tree is applied to derive the optimal duty cycle for the explicit MPC. The discrete
state equations of switch side LC filter can be derived from the continuous equations in (5.1) as:

127
 𝑇𝑠 𝑣 𝑑𝑐 𝑇𝑠
𝑖 𝐿 𝑓 𝑠 (𝑘 + 1) = 𝑖 𝐿 𝑓 𝑠 (𝑘) − 𝑣 𝐶 𝑓 (𝑘) + 𝑑 (𝑘) (5.12a)
𝐿𝑓𝑠 𝐿𝑓𝑠
𝑇𝑠 𝑇𝑠
𝑣 𝐶 𝑓 (𝑘 + 1) = 𝑖 𝐿 𝑓 𝑠 (𝑘) + 𝑣 𝐶 𝑓 (𝑘) − 𝑖 𝐿 𝑓 𝑔 (𝑘). (5.12b)
𝐶𝑓 𝐶𝑓

For the flexibility of implementing the explicit MPC and the convenience of experimentally
adjusting the DC bus voltage during test, the last term of (5.12), 𝑣 𝑑𝑐 𝑑 (𝑘), can be replaced by the
phase leg output voltage, 𝑣 𝑥 (𝑘). The state-space model for MPC can be expressed in standard
matrix format of

𝑋 𝑘+1 = 𝐴𝐶 𝑋 𝑘 + 𝐵𝐶 𝑢 𝑘 + 𝐸𝐶 𝑒 𝑘 (5.13)

where the variables and matrices for MPC control represent

   𝑇   
 1 − 𝑇𝑠   𝑠   0 
𝐿𝑓𝑠   𝐿𝑓𝑠 
𝐴𝐶 =   , 𝐵𝐶 =   , 𝐸𝐶 =  (5.14a)
  
,
 𝑇𝑠  𝑇𝑠 
1   0   −𝐶𝑓 
  
 𝐶𝑓
     
 
 𝑖 𝐿 𝑓 𝑠 (𝑘)     
𝑋𝑘 =   , 𝑢 𝑘 = 𝑣 𝑑𝑐 𝑑 (𝑘) , 𝑒 𝑘 = 𝑖 𝐿 𝑓 𝑔 (𝑘) . (5.14b)
 
(𝑘)
 
𝑣
 𝐶𝑓 
 

In the MPC formulation, the inductor current/capacitor voltage references can be defined as 𝑋¯
and the tracking errors between the measurement and the references are expressed as 𝑋˜ which are
composed of

   
 𝑖 𝐿 𝑓 𝑠,𝑟 𝑒 𝑓 (𝑘)   𝑖 𝐿 𝑓 𝑠,𝑟 𝑒 𝑓 (𝑘) − 𝑖 𝐿 𝑓 𝑠 (𝑘) 
𝑋¯ 𝑘 = 
 ˜
 , 𝑋𝑘 =  (5.15)
  
.
 𝑣 𝐶 𝑓 ,𝑟 𝑒 𝑓 (𝑘)  𝑣 𝐶 𝑓 ,𝑟 𝑒 𝑓 (𝑘) − 𝑣 𝐶 𝑓 (𝑘)
   
 
   
Thus, the cost function includes two terms

𝑁𝑐
∑︁ 𝑝 −1
𝑁∑︁
𝑚𝑖𝑛 𝑋˜ 𝑘𝑇 𝑄 𝐶 𝑋˜ 𝑘 + △𝑢𝑇𝑘 𝑅𝐶 △𝑢 𝑘 . (5.16)
𝑘=0 𝑘=0

128
For the penalties of the MPC cost function, 𝑄 𝐶 and 𝑅𝐶 represent the weighing factor matrices that
are implemented on the state values and input values, respectively.

Application Layer

For the application layer, the interface between the local power modules and the single-phase
grid are two grid side inductors, 𝐿 𝑓 𝑔 .

5.2.2 Three-Phase Grid Interface Control

Fig. 5.7 displays the control architecture for the application of three-phase grid interface. The
corresponding power converter topology is shown in Fig. 5.3(b).

Central Control Layer

The central control layer is functioned to recognize the three-phase grid interface and recon-
figure the power converter topology with three local power modules in parallel as is shown in Fig.
5.3(b). The specific functions of three-phase grid interface central control layer are illustrated as
follows.
Firstly, the three-phase grid side inductor current, 𝑖 𝐿 𝑓 𝑔,𝑎𝑏𝑐 , and output capacitor voltage, 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 ,
are received from the local power modules and transformed into 𝑑𝑞0 reference frame as 𝑖 𝐿 𝑓 𝑔,𝑑𝑞0
and 𝑣 𝐶 𝑓 ,𝑑𝑞0 , respectively, for the high level control purpose.
Secondly, the three-phase PLL is designed in the central control layer as is shown in Fig.
5.5(b). The 𝑎𝑏𝑐 components of output capacitor voltage are received from local power modules
and transformed to 𝑑𝑞 axis to control the 𝑞 component to be zero for the generation of accurate
grid angular speed, 𝜔, and phase angle, 𝜃.
Thirdly, the grid service control functions are configured to provide active/reactive power com-
pensations based on the grid frequency/voltage abnormal conditions. The grid service control
blocks are also following the working modes in Fig. 5.9 to generate the desired active/reactive
power references, 𝑃∗ and 𝑄 ∗ , for the active/reactive power controllers. The active/reactive power

129
controllers derive the 𝑑𝑞 components of grid side inductor current references, 𝑖 ∗𝐿 𝑓 𝑔,𝑑𝑞 for the fol-
lowing grid current 𝑑𝑞 controllers.
Fourthly, the grid side inductor current 𝑑𝑞 components, 𝑖 𝐿 𝑓 𝑔,𝑑𝑞0 , are controlled separately
with two PI controllers to generate 𝑑𝑞 output capacitor voltage references, 𝑣 𝐶∗ 𝑓 ,𝑑𝑞 . And the zero-
sequence output capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,0 , is configured as half of DC bus voltage, 𝑣 𝑑𝑐 ,
to stabilize the common mode voltage. Combining the zero-sequence voltage control with the
modified topology in Fig. 5.3(b), the leakage current can be attenuated from flowing into the grid.
Then, the 𝑑𝑞0 components of output capacitor voltage references are transformed into 𝑎𝑏𝑐 refer-
ence frame with the reversed Park and Clarke functions as, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 . The generated 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 then
will be distributed to the per phase local module control layer as the tracking references of local
MPC control.

Local Module Control Layer

The local module control layer of the three-phase grid interfaced system consists of three MPC-
based power modules. Each of the power module is implementing the same MPC algorithm for
the switch side 𝐿𝐶 filter to track the output capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 , received from the
central control layer.

Application Layer

For the application layer, the interface between the local power modules and the three-phase
grid are three grid side inductors, 𝐿 𝑓 𝑔 .

5.2.3 Motor Drive Interface Control

Fig. 5.8 illustrates the control architecture for the application of motor drive. The correspond-
ing motor traction inverter topology is shown in Fig. 5.3(c). A permanent magnet synchronous
motor (PMSM) is connected directly to the three local MPC-based power modules for the valida-
tion.

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Central Control Layer

The central control layer is functioned to recognize the motor interface and reconfigure the
power converter topology with three local power modules in parallel as is shown in Fig. 5.3(c).
The specific functions of motor interface central control layer are illustrated as follows.
Firstly, the rotor position is measured with a encoder board. And a speed controller is designed
to control the rotor speed. The output of the speed controller is configured as the 𝑞 component mo-
∗
tor winding current reference, 𝑖 𝑚𝑜𝑡𝑜𝑟,𝑞 to be cascaded with the following motor current controllers.
Secondly, the three-phase motor winding current, 𝑖 𝑚𝑜𝑡𝑜𝑟,𝑎𝑏𝑐 , and output capacitor voltage,
𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 , are received from the local power modules and transformed into 𝑑𝑞0 reference frame
as 𝑖 𝑚𝑜𝑡𝑜𝑟,𝑑𝑞0 and 𝑣 𝐶 𝑓 ,𝑑𝑞0 , respectively, for the high level control purpose.
Thirdly, the motor winding current 𝑑𝑞 components, 𝑖 𝑚𝑜𝑡𝑜𝑟,𝑑𝑞 , are controlled separately with two
PI controllers to generate 𝑑𝑞 output capacitor voltage references, 𝑣 𝐶∗ 𝑓 ,𝑑𝑞 . And the zero-sequence
output capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,0 , is configured as half of DC bus voltage, 𝑣 𝑑𝑐 . Then,
the 𝑑𝑞0 components of output capacitor voltage references are transformed into 𝑎𝑏𝑐 reference
frame with the reversed Park and Clarke functions as, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 . The generated 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 then will
be distributed to the per phase local module control layer as the tracking references of local MPC
control.

Local Module Control Layer

The local module control layer of the motor interfaced system consists of three MPC-based
power modules. Each of the power module is implementing the same MPC algorithm for the
switch side 𝐿𝐶 filter to track the output capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 , received from the
central control layer.

Application Layer

For the application layer, the three local power modules are directly interfaced with the PMSM.

131
 Figure 5.10: Prototype of the hierarchical control structure.

5.3 Merits and Validations

The proposed hierarchical software-defined control architecture is validated experimentally on

the MPC-based power module test bench with C3M0021120K MOSFETs and TMS320F280049
control card configured with CAN communication as is shown in Fig. 5.10. The merits of the
designed architecture can be concluded in the following four aspects.

5.3.1 Reconfigurability with Unified Power Modules

Firstly, one of the major merits for the proposed hierarchical control architecture is the recon-
figurability to be applied to different applications with the unified MPC-based power modules. As
is shown in Fig. 5.1 and 5.10, different number of MPC-based power modules can be connected
to formalize the desired circuitry topology and interfaced application. Fig. 5.11(a) and 5.11(b)
show the single- and three-phase grid interfaced applications of the grid current, capacitor voltage,
inductor current and DC voltage waveforms, respectively. The testing results of motor application
are shown in Fig. 5.12(a) and 5.12(b) with speed step of 730 rpm and torque step of 26 Nm, respec-

132
 (a) (b)

Figure 5.11: (a) Single-phase and (b) Three-phase grid interfaces grid current, capacitor voltage,
inductor current and DC voltage steady state waveforms.

(a) (b)

Figure 5.12: Captured ADC readings of motor (a) speed step from 0 to 470 rpm and (b) torque
step from 5 to -5 Nm.

tively. The three applications, single/three-phase grid and motor, are all following the hierarchical
control architectures illustrated in Fig. 5.6, 5.7 and 5.8, respectively.

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 (a) (b)

Figure 5.13: (a) Single-phase and (b) Three-phase grid interfaces grid current, capacitor voltage,
inductor current and DC voltage transient waveforms.

(a) (b)

Figure 5.14: Captured ADC readings of grid current steps from (a) 2A to 8A and (b) 8A to 2A for
the proposed MPC and conventional PI methods.

5.3.2 Improved Dynamic Performance with MPC-Based Local Layer Power Module

Secondly, the local level MPC control improves the dynamic performance by actively damping
the resonance of the 𝐿𝐶 𝐿 filter and enabling a high control bandwidth. By inserting am MPC loop
between the central level output current PI and PWM modulation, the control gain is capable of
being largely increased without inducing too much resonant oscillation. Fig. 5.13(a) and 5.11(b)
shows the single- and three-phase grid interfaced applications of the grid current, capacitor voltage,
inductor current and DC voltage waveforms, respectively, with current step from 2A to 6A. Also,

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 (a) (b)

(c)

Figure 5.15: The comparison of leakage current and common mode voltage for the (a) proposed
grid connected topology with zero-sequence voltage control (c) proposed three-phase grid con-
nected topology without zero-sequence voltage control and (d) traditional topology without zero-
sequence voltage control.

(a) (b)

Figure 5.16: The comparison of leakage current, shaft voltage and common mode voltage for
the (a) conventional motor connected topology (b) proposed motor connected topology with zero-
sequence voltage control.

for a better comparison with the conventional PI control, three testing cases of the captured ADC
readings for grid current from 2A to 8A and 8A to 2A are shown in Fig. 5.14(a) and 5.14(b),
respectively. Compared with low 𝐾 𝑝 of the traditional PI, the proposed MPC control can track
the reference 5 times faster without overshoot. Compared with high 𝐾 𝑝 of the traditional PI, the
proposed MPC control performs more steadily without oscillation.

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5.3.3 Non-Isolated Applications with Central Layer Zero-Sequence Control

Thirdly, the central layer manages a zero-sequence voltage control to be distributed to the local
MPC power modules. With the zero-sequence controller combined with the modified topologies
in Fig. 5.4(a), 5.4(b) and 5.4(c), the leakage current/common mode voltage of single/three-phase
grid and shaft voltage/bearing current of motor can be attenuated. Thus, the non-isolated topol-
ogy can save the cost of bulky transformer. Specifically, Fig. 5.15(a)-5.15(c) compare the leakage
current and common mode voltage for the modified grid-connected topology with zero-sequence
controller, the modified grid-connected topology without zero-sequence controller and conven-
tional grid-connected topology without zero-sequence controller, respectively. Only leveraging
the modified topologies can reduce 2-3 times leakage current. However, combining the modified
topologies with zero-sequence controller can reduce 10-15 times leakage current. Also, the com-
parison of leakage current, shaft voltage and common mode voltage for the conventional motor
connected topology and proposed motor connected topology with zero-sequence voltage control
in Fig. 5.16 demonstrates that the leakage current and shaft voltage on the motor can be attenuated
by 10-20 times.

5.3.4 Robust MPC Free of Application Model Parameters Influence

Lastly, for the proposed hierarchical control architecture, the control accuracy and robustness
are guaranteed by the cascaded multi-layer control structure. As are shown in Fig. 5.6, 5.7 and
5.8 of the three applications, the output side inductor current is directly managed by the central
layer controller and the corresponding output side inductance is free from the local MPC paramet-
ric modeling. Thus, the uncertainties of the equivalent output parameters caused by the various
interfaced grid or motor will not influence the accuracy of the local MPC parametric modeling.

136
5.4 Summary

This chapter develops a hierarchical software-defined control architecture with MPC-based

power module to improve the performance of energy conversion system. The multi-layer control
structure includes central control layer for high-level power control, local MPC control layer for
each power module and application layer for different interfaces. Different applications have been
demonstrated to be applied in the generalized control architecture such as single/three-phase grid
and motor. The developed structure has the advantages of reconfigurability for various applica-
tion requirements, better transient performance improved by the local MPC modules, non-isolated
topologies enabled by the central level zero-sequence control and high accuracy free from the
parameter uncertainties of different interfaces.

137
 Chapter 6: Design Case of Three-Phase Grid-Tied Inverter with High

Efficiency and Power Density

With the increasing demands of high efficiency, high power density and better dynamic/steady
state performance in the application of power electronics, more advanced control techniques and
circuitry topologies have been studied to improve the performance of power converters. To achieve
high power density with low volume, the size of passive magnetic components needs to be reduced.
Thus, it is necessary to increase the switching frequency for maintaining reasonable current/voltage
ripples on the inductor/capacitor [112], [113]. However, higher switching frequency brings more
switching losses and inductor losses which could influence the efficiency of the power conversion
system. Thus, there exists a typical trade-off between efficiency and power density for balancing
[114]. For the dynamic performance of power converters, besides a careful hardware design, more
advanced control techniques can contribute to the transient behavior. Model predictive control
(MPC) has been studied to have better dynamic performance than the traditional method of PI
control [75].
Firstly, for the trade-off between high efficiency and high power density, soft switching tech-
niques can be applied to achieve both targets with less compromise [115]. The switching losses
are mainly caused by the overlapping of voltage and current across the switch during turn-on and
turn-off transients. Soft switching techniques are generally aimed at minimizing the overlapping
area of switch voltage and current in transients. Zero-voltage switching (ZVS) and zero-current
switching (ZCS) are the two main soft switching methods [116], [117]. ZVS focuses on reducing
the voltage across the switch and ZCS can minimize the current flowing through the switch during
the turn-on or turn-off transients [118], [119]. The soft switching can be achieved by adding aux-
iliary circuit. Typically, extra inductor, capacitor and switch are needed to form the buffer circuit

138
for the implementation of soft switching [120], [121]. This will bring extra cost and control com-
plexity. Another method to achieve ZVS is by replacing the higher turn-on loss with lower turn-off
loss. This strategy can be realized by controlling the switch side inductor current ripple to be bidi-
rectional during switching transients [122]. To control the peak/valley inductor current for ZVS,
the simplest way is varying the switching frequency for the adjustment of inductor current ripple
[123]. A variable frequency soft switching method is proposed in this chapter in combination with
MPC and state estimator to reduce the switching losses without introducing auxiliary circuit.
Secondly, for the improvement of dynamic performance, advanced control techniques can be
applied. Different from the conventional proportional and integral (PI) control method, model pre-
dictive control (MPC) has the advantages in the aspects of rising time, overshoot and disturbance
rejection [76]. The MPC is typically implemented by optimizing the tracking error between the
measurement and reference in the desired future steps to predict the duty cycle for the modulation
[77]. Some recent MPC techniques has been published to improve the performance of inverter
control [124, 125, 126, 127]. Specifically, [124] leveraged joint voltage vector for the Quazi-Z-
Source inverter MPC control to suppress the current ripple. [125] developed the constrained MPC
algorithm based on large-signal model for microgrid inverter. [126] proposed a voltage-sensorless
MPC for grid-conneceted inverter. And [127] enabled the MPC control with inductance online
identification capability and improved phase-locked loop. The MPC can perform a high track-
ing speed with less transient oscillation especially during load or reference variations [43]. This
characteristic can be combined with the variable frequency soft switching technique to reduce the
oscillation caused by the switching frequency variation. The design case in this chapter lever-
ages the advantages of MPC in dynamic performance to mitigate the oscillation and stability issue
caused by the variable frequency soft switching operation.
Thirdly, for the accuracy of state parameter acquisition, the state estimation techniques have
been developed to improve the quality of sampling information and reduce the sensor cost. The
recent publications are introduced as follows. Specifically, in the power electronics field, [128]
developed a state and disturbance observer for grid-connected inverter under non-ideal conditions.

139
[129] proposed a robust observer algorithm for Voltage and frequency control of a doubly fed
induction generator. [130] applied an extended-state observer estimation method for 𝐿𝐶 𝐿 inverter
to improve the observation dynamics. [131] studied the resonant extended state observer for grid
voltage estimation of 𝐿𝐶 𝐿 inverter.
The contributions of this chapter can be concluded in four main aspects. Firstly, the combi-
nation of MPC with variable-frequency critical-soft-switching control improves the efficiency of
grid-connected inverter. The unexpected hard switching power loss from the oscillation caused by
the time-varying switching frequency is attenuated by the MPC due to the robust transient perfor-
mance. Secondly, two variable-frequency techniques, VCF-CSS and VDF-CSS, are proposed to
achieve the full grid period soft switching. A Luenberger Observer is designed to be integrated
with VCF-CSS for a more accurate inductor current estimation and soft switching boundary calcu-
lation. Both VCF-CSS and VDF-CSS do not need extra sensor circuits, e.g., [132], to sample the
averaged inductor current for soft switching. Thirdly, the zero-sequence voltage control method
combined with the modified inverter topology enables the non-isolated circuitry application with
low leakage current. Fourthly, compared with the typical prototypes, the designed inverter achieves
the Pareto Optimal Points in the parameters of Frequency-Power and Efficiency-Power density.
This chapter is organized as follows. Firstly, a modified non-isolated grid connected inverter
topology is introduced. The modified topology is composed based on a fundamental power module
for each phase. The power module includes uppper/lower switches, switch side inductor and two
output capacitors to be connected to the upper/lower DC bus terminals. Three power modules can
be connected to form a modified three phase non-isolated inverter with the capability to stabilize
the zero-sequence voltage and attenuate the leakage current. Then, based on the power module,
a critical soft switching technique is introduced to reduce the large turn-on loss with small turn-
off loss for the improvement of efficiency. Thirdly, the control strategies are proposed including
three parts: (1) central level of grid current control/zero-sequence voltage control cascaded with
local level of per phase power module modular model predictive control; (2) two types of variable-
frequency critical-soft-switching controllers including variable-continuous-frequency critical-soft-

140
 (a) (b)

Figure 6.1: Conventional (a) 𝐿 and (b) 𝐿𝐶 𝐿 types of non-isolated inverters.

Figure 6.2: Proposed modified non-isolated inverter composed of per phase power modules.

switching (VCF-CSS) and variable-discrete-frequency critical-soft-switching controllers (VDF-

CSS) to achieve highly efficient critical soft switching operation by adjusting switching frequency
and inductor current ripple; (3) state estimator for per power module to estimate the switch side
inductor current, output capacitor voltage and grid side inductor current with the sampling values
of output capacitor voltage and grid side inductor current. The combination of MPC and VF-CSS
guarantees a complete critical soft switching operation at full period range of varying frequency
and especially during transient. The estimator provides noise rejection and accurate switch side
inductor current estimations for MPC and VF-CSS. Three controllers can be combined to achieve
a high efficiency, good dynamic/steady state performance non-isolated grid-tied inverter with low
leakage current. Finally, two cases of prototype are built with medium frequency/medium induc-
tance (>200kHz, 45𝜇H) and high frequency/small inductance (>1MHz, 4.5𝜇H) to validate the
effectiveness of the proposed methods. The efficiency is above 99% at a rated power of 15kW. A
power density of more than 10.4kW/L is achieved.

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6.1 Non-Isolated System and Critical Soft Switching

6.1.1 Non-isolated System

The proposed control methods are based on a modified non-isolated grid-tied 𝐿𝐶 𝐿 inverter.
Different from the conventional 𝐿 and 𝐿𝐶 𝐿 types of non-isolated inverters in Fig. 6.1, the pro-
posed topology is shown in Fig. 6.2 which consists of three power module units and three grid
side inductors, 𝐿 𝑓 𝑔 . The per phase power module unit is composed of upper/lower switches, 𝑀1
and 𝑀2 , switch side inductor, 𝐿 𝑓 𝑠 , and two output capacitors connected to the upper/lower DC
bus terminals, 𝐶 𝑓 ,𝑢 𝑝 and 𝐶 𝑓 ,𝑙𝑜 . The modification of non-isolated topology contributes to the sta-
bilization of common mode voltage leveraging the proposed control methods and the proposed
variable-frequency critical-soft-switching methods, VCF-CSS and VDF-CSS, are based on the per
phase power module unit. As is shown in Fig. 6.2, the local level control is implemented at each
of the power module independently for MPC, estimator and VF-CSS to improve the efficiency and
dynamic/steady state performance.
The modified non-isolated topology is composed of three power modules (upper/lower switches,
switch side inductor, upper/lower capacitors), grid side inductors and DC bus capacitor as is shown
in Fig. 6.2. With the help of the power module units labeled in colored blocks in Fig. 6.2, the up-
per/lower common points of three-phase output capacitors are connected to the positive/negative
DC bus terminals, respectively. This topological modification allows the zero-sequence capacitor
voltage to be stabilized as constant and the leakage current to be bypassed from flowing into the
grid.

6.1.2 Critical Soft Switching Analysis

To reduce the switching losses of the power module, a critical soft switching method is intro-
duced in this section. The critical soft switching technique is aimed at improving the power density
and efficiency at the same time. It permits to increase the switching frequency by a factor of 3-5
and reduce the required inductance by a factor of 10-20. As is shown in Fig. 6.3, three sets of

142
Figure 6.3: Three inductor size comparison for implementing low, medium and high frequency
converters.

Figure 6.4: Critical soft switching working principles for DC and AC current modes.

inductors are compared in size and volume with the inductance of 450𝜇H, 45𝜇H and 4.5𝜇H, re-
spectively. From left to right of the three inductors, the inductance are decreased by a factor of 10
in sequence, the volume is decreased by the factors of 5.5 and 4.1 in sequence, respectively. For the
inductor design perspective considering the area product (AP), losses and current ripple saturation,
the desired operating frequencies are increased by a factor of 3-5 from left to right in sequence.
Thus, instead of using a bulky 450𝜇H inductor on the left side of Fig. 6.3 for hard switching, the
critical soft switching technique enables smaller inductors on the middle and right sides of Fig. 6.3
with lower inductance/switching losses and higher switching frequency/power density.

143
 Figure 6.5: Turn-on and turn-off loss comparison of typical SiC MOSFET C3M0021120K.

The working principle diagram of critical soft switching is shown in Fig. 6.4 with DC and AC
current modes for each of the proposed power module. The core idea of critical soft switching
method is to replace the large turn-on loss of the upper switch with small turn-off loss of the lower
switch in the power module. For a typical SiC MOSFET, C3M0021120K, at a certain DC voltage
of 800V, the turn-on, turn-off and total switching losses of energy have been plotted in Fig. 6.5
with the drain-source current which shows that the turn-on loss is 4 times larger than the turn-off
loss. The methodology of critical soft switching is to ensure that the peak point and valley point
of the switch side inductor current should be positive and negative, respectively. And the absolute
values of positive peak point and negative valley point should be above a threshold current level
to ensure the complete soft switching. The threshold current and dead time define the boundary

Figure 6.6: The critical soft switching operation regions for different devices.

144
condition of critical soft switching. As is shown in Fig. 6.4, in the turn-on transient of upper
switch, a negative inductor current can discharge the upper switch output capacitor, 𝐶𝑜𝑠𝑠,𝑀1 . The
zero-voltage turn-on of upper switch will be achieved if 𝐶𝑜𝑠𝑠,𝑀1 is fully discharged before it turns
on. Similarly, a positive inductor current is needed to fully discharge the lower switch output
capacitor, 𝐶𝑜𝑠𝑠,𝑀2 , before it turns on. The critical soft switching deals with the boundary condition
of zero-voltage soft turn-on for the required threshold current and dead time to fully discharge the
output capacitors of upper and lower switches before they turn on. The DC and AC current modes
of switch side inductor current waveforms have been shown at the bottom of Fig. 6.4 where the
dashed lines of current ripple envelope demonstrate the required threshold current for critical soft
switching operation at certain dead time.
The switch side inductor current peak/valley point values, 𝑖 𝐿 𝑓 𝑠,𝑚𝑎𝑥/𝑚𝑖𝑛 , for critical soft switch-
ing operation can be expressed by the drain-source current through the upper and lower switches,
𝑖 𝐷𝑆,𝑀1 and 𝑖 𝐷𝑆,𝑀2 , and the current through the upper and lower switch output capacitance, 𝑖𝐶𝐷𝑆,𝑀1
and 𝑖𝐶𝐷𝑆,𝑀2 . And the 𝑖𝐶𝐷𝑆,𝑀1 and 𝑖𝐶𝐷𝑆,𝑀2 are the derivative functions of upper/lower switch out-
put capacitors, 𝐶𝐷𝑆,𝑀1 and 𝐶𝐷𝑆,𝑀2 , and drain-source voltages, 𝑣 𝐷𝑆,𝑀1 and 𝑣 𝐷𝑆,𝑀2 . Then, with
the integral calculation in each switching dead time period, 𝑡 𝑑 , the required 𝑖 𝐿 𝑓 𝑠,𝑚𝑎𝑥/𝑚𝑖𝑛 at specific
dead time can be further expressed by the discharge, 𝑄 𝑚𝑖𝑛 and 𝑄 𝑚𝑎𝑥 , of upper/lower switch output
capacitors which have been provided by the MOSFET manuals:

1
2 𝑖 𝐿 𝑓 𝑠,𝑚𝑖𝑛 𝑡 𝑑 ≤ 𝑄 𝑚𝑖𝑛 ≤ 0 (6.1a)
1
2 𝑖 𝐿 𝑓 𝑠,𝑚𝑎𝑥 𝑡 𝑑 ≥ 𝑄 𝑚𝑎𝑥 ≥ 0. (6.1b)

Then, the model of critical soft switching method can be expressed with the function image
in Fig. 6.6 where the light green regions are the feasible soft switching range based on (6.1) and
the peak/valley inductor current can be controlled with the developed methods in the following
sections.

145
 Figure 6.7: Proposed control diagram.

6.2 Control

The proposed control strategies of the modified non-isolated converter include two layers of
control: (1) Central level grid side inductor current control and zero-sequence voltage MPC control
to generate the references for the per phase power module local control; (2) Local level per power
module model predictive control, state estimator and variable-frequency critical-soft-switching
control. The combination of MPC and VF-CSS guarantees a complete critical soft switching op-
eration at varying frequency and even transient. The state estimator provides noise rejection and
more accurate switch side inductor current estimations for MPC and VF-CSS.

6.2.1 Central Level Grid Current/Zero-Sequence Voltage Control

As is shown in the left block of Fig. 6.7, the central level control layer is composed of phase-
lock-loop (PLL), Park/Clarke transformations, grid current control and zero-sequence voltage con-
trol. Two main targets are achieved with central level grid current and zero-sequence voltage con-
trol: (1) provide the three-phase capacitor voltage references for local level power module MPC
control; (2) stabilize the zero-sequence voltage and attenuate the leakage current for the modified

146
non-isolated topology.

Grid side inductor current control

The three-phase grid side inductor currents are transformed from 𝑎𝑏𝑐 to 𝑑𝑞0 reference frame
with PLL and Clarke/Park transformations. Two PI controllers are designed to regulate the 𝑑
and 𝑞 components of grid current, 𝑖 𝐿 𝑓 𝑔,𝑑 and 𝑖 𝐿 𝑓 𝑔,𝑞 , respectively. The outputs of 𝑑𝑞 grid current
∗ and 𝑉 ∗ , respectively.
controllers are configured as the 𝑑𝑞 output capacitor voltage references, 𝑉𝑐,𝑑 𝑐,𝑞
∗ and 𝑉 ∗ are transformed to 𝑎𝑏𝑐 reference frame as 𝑉 ∗ , 𝑉 ∗ and 𝑉 ∗ , for the tracking
Then 𝑉𝑐,𝑑 𝑐,𝑞 𝑐,𝑎 𝑐,𝑏 𝑐,𝑐

purpose of per phase local power module MPC control.

Zero-sequence voltage control

Based on the proposed topological modification in Fig. 6.2 to connect three-phase output
capacitors common points with positive/negative DC bus terminals, the zero-sequence capacitor
voltage is controlled to be half of DC bus voltage as is shown in Fig. 6.7. In central level con-
trol layer, the zero-sequence output capacitor voltage reference is configured to be half of DC bus
voltage and allocated to the local level per phase MPC controller. Thus, the local MPC can sta-
bilize the zero-sequence capacitor voltage to attenuate the leakage current. Since the controlled
three-phase output capacitor voltages, 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 , are measured with respect to the DC bus negative
terminal and the upper/lower capacitors are connected to the DC bus positive/negative terminals,
the output capacitor voltage waveforms will be ranged within 0-𝑉𝑑𝑐 and centered at 𝑉𝑑𝑐 /2. Thus,
the reference of zero-sequence voltage controller is configured as 𝑉𝑑𝑐 /2 for the common mode
voltage stabilization.
In the conventional topologies, the zero-sequence capacitor voltage is not controlled to be con-
stant which causes the leakage current to be flowing into the grid. However, in the proposed
modified circuit, the zero-sequence capacitor voltage is stabilized by MPC to be half of DC bus.
Thus, the zero-sequence current will be bypassed to be only flowing through the switch side induc-
tors. The leakage current will be prevented from injecting into the grid. The definition of leakage

147
 Figure 6.8: Equivalent circuit for state space equation.

Figure 6.9: MPC optimization search tree implementing process.

current to the grid can be expressed as:

𝑑𝑣 𝑐,0
𝑖 𝐿 𝑓 𝑔,0 = 𝐶 𝑝 . (6.2)
𝑑𝑡

Thus, the zero-sequence capacitor voltage stabilization by MPC can attenuate the grid side leakage
current.

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6.2.2 Local Level Model Predictive Control

For the purpose of improving the dynamic performance especially when the controller is com-
bined with variable-frequency operations, an explicit MPC method is designed for the per phase
switch side capacitor voltage and inductor current control by solving the Constrained Finite Time
Optimal Control (CFTOC) problem. As is shown in Fig. 6.7 of the control diagram, the three-
phase capacitor voltages are controlled in 𝑎𝑏𝑐 frame to follow the references from the cascaded
grid current controller’s outputs. The switch side inductor currents are also regulated with the MPC
by adjusting the weighing factor between 𝑖 𝐿 𝑓 𝑠,𝑎𝑏𝑐 and 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 . The benefits to configure the MPC
per phase in 𝑎𝑏𝑐 frame can be concluded as: (1) the state space matrix of LC per phase is simpler
than 𝑑𝑞 system to implement the offline piecewise affine optimization code in a less costly DSP
controller; (2) The time-varying angular speed term, 𝜔, in the typical three-phase 𝐿𝐶 𝐿 inverter
state space equations can be omitted in the explicit MPC state space matrix for the offline opti-
mization calculation; (3) Per phase MPC for 𝐿𝐶 is more flexible for a modular design perspective
to extend the paralleled phase number and other topologies, e.g., DC/DC, single-phase DC/AC
converters.
For the MPC implementation, in every control period, the MPC controller receives the mea-
sured switch side inductor current, 𝑖 𝐿 𝑓 𝑠,𝑎𝑏𝑐 , output lower capacitor voltage, 𝑣 𝐶 𝑓 ,𝑎𝑏𝑐 , grid current,
𝑖 𝐿 𝑓 𝑔,𝑎𝑏𝑐 , from ADC and capacitor voltage reference, 𝑣 𝐶∗ 𝑓 ,𝑎𝑏𝑐 from the grid current controller. An
offline generated piecewise affine search tree is applied to derive the optimal duty cycle for the
explicit MPC. The equivalent circuit for each power module is shown in Fig. 6.8 with the variables
to derive the state space equation for MPC. The state equations of switch side LC filter can be
expressed as

𝑇𝑠 𝑣 𝑑𝑐𝑇𝑠
𝑖 𝐿 𝑓 𝑠 (𝑘 + 1) = 𝑖 𝐿 𝑓 𝑠 (𝑘) − 𝑣 𝐶 𝑓 (𝑘) + 𝑑 (𝑘) (6.3a)
𝐿𝑓𝑠 𝐿𝑓𝑠
𝑇𝑠 𝑇𝑠
𝑣 𝐶 𝑓 (𝑘 + 1) = 𝑖 𝐿 𝑓 𝑠 (𝑘) + 𝑣 𝐶 𝑓 (𝑘) − 𝑖 𝐿 𝑓 𝑔 (𝑘). (6.3b)
𝐶𝑓 𝐶𝑓

149
 For the flexibility of implementing the explicit MPC and the convenience of experimentally
adjusting the DC bus voltage during test, the last term of (6.3), 𝑣 𝑑𝑐 𝑑 (𝑘), can be replaced by the
switch leg output voltage, 𝑣 𝑥 (𝑘). The state-space model for MPC can be expressed in standard
matrix format of

𝑋 𝑘+1 = 𝐴𝐶 𝑋 𝑘 + 𝐵𝐶 𝑢 𝑘 + 𝐸𝐶 𝑒 𝑘 (6.4)

where the variables and matrices for MPC control represent

   𝑇   
 1 − 𝑇𝑠   𝑠   0 
𝐿𝑓𝑠   𝐿 
𝐴𝐶 =   , 𝐵𝐶 =  𝑓 𝑠  , 𝐸 𝐶 =  (6.5a)
  
,
 𝑇𝑠 𝑇𝑠 
1   0   −𝐶𝑓 
   
 𝐶𝑓
     
 
 𝑖 𝐿 𝑓 𝑠 (𝑘)  h i h i
𝑋𝑘 =   , 𝑢 = 𝑣 𝑑𝑐 𝑑 (𝑘) , 𝑒 𝑘 = 𝑖 𝐿 𝑓 𝑔 (𝑘) . (6.5b)
 
 𝑣 (𝑘)  𝑘
 𝐶𝑓 
 

In the MPC formulation, the inductor current/capacitor voltage references can be defined as 𝑋¯
and the tracking errors between the measurement and the references are expressed as 𝑋˜ which are
composed of

   
 𝑖 𝐿 𝑓 𝑠,𝑟𝑒 𝑓 (𝑘)   𝑖 𝐿 𝑓 𝑠,𝑟𝑒 𝑓 (𝑘) − 𝑖 𝐿 𝑓 𝑠 (𝑘) 
𝑋¯ 𝑘 = 
 ˜
 , 𝑋𝑘 =  (6.6)
  
.
 𝐶 𝑓 ,𝑟𝑒 𝑓 (𝑘)  𝐶 𝑓 ,𝑟𝑒 𝑓 (𝑘) − 𝑣 𝐶 𝑓 (𝑘)
 𝑣   𝑣 
 
   
Thus, the cost function includes two terms

𝑁𝑐
∑︁ 𝑝 −1
𝑁∑︁
𝑚𝑖𝑛 𝑋˜ 𝑘𝑇 𝑄 𝐶 𝑋˜ 𝑘 + △𝑢𝑇𝑘 𝑅𝐶 △𝑢 𝑘 . (6.7)
𝑘=0 𝑘=0

For the penalties of the MPC cost function, 𝑄 𝐶 and 𝑅𝐶 represent the weighing factor matrices that
are implemented on the state values and input values, respectively.

150
 The constraints of the MPC controller can be expressed as

𝑋˜ 𝑘+1 = 𝐴 𝑋˜ 𝑘 + 𝐵𝑢 𝑘 + 𝐸𝑒 𝑘 ∈ X (6.8)

△𝑢 𝑘 = 𝑢 𝑘 − 𝑢 𝑘−1 ∈ U (6.9)
   
 −𝐼 𝐿 𝑓 𝑠,𝑚𝑎𝑥   𝐼 𝐿 𝑓 𝑠,𝑚𝑎𝑥 
 ≤ 𝑋𝑘 ≤ (6.10)
   
  

 0 

 𝑣
 𝑑𝑐


   
h i h i
0 ≤ 𝑢𝑘 ≤ 𝑣 𝑑𝑐 (6.11)
h i h i
−𝐼 𝐿 𝑓 𝑔,𝑚𝑎𝑥 ≤ 𝑒𝑘 ≤ 𝐼 𝐿 𝑓 𝑔,𝑚𝑎𝑥 . (6.12)

Since the application of the MPC is kelo-to-mega-Hertz switching frequency, the execution
efficiency of the algorithm should be high. Thus, an explicit method is developed to relieve the
online MPC implementation burden. Specifically, based on the state space model, cost function and
the corresponding constraints of the power module, a piecewise affine (PWA) function is derived
with computer and the related C code is configured in the DSP controller memory for the online
implementation. The internal operation principle of the MPC is shown in Fig. 6.9 where the
flowchart of MPC implementing process is demonstrated. The PWA function is reflected on the C
code as 𝑛 sections of active regions, 𝐻𝑛 and 𝐾𝑛 , with the corresponding feedback law, 𝐹𝑛 and 𝐺 𝑛 .
And the colored areas in Fig. 6.9 represent different regions. A binary search tree is configured to
quickly find the active region, 𝑟, and the related feedback law, 𝐹𝑟 and 𝐺 𝑟 , for the derivation of the
optimal duty cycle.
During the control interrupt period, the binary search tree finds the active region, 𝑟, based on the
ADC samplings/estimations of inductor current, capacitor voltage, output current and the tracking
references. Then, the corresponding feedback law, 𝐹𝑟 and 𝐺 𝑟 , will calculate the optimal duty cycle
for PWM modulation. This simplified explicit process avoids the online MPC optimization and is
suitable for the developed high frequency inverter control design.

151
 Figure 6.10: Diagram of the state estimator.

(a) (b)

Figure 6.11: (a) VDF-CSS and (b) VCF-CSS AC current ripple .

6.2.3 Local Level Luenberger Observer

A state estimator is designed for per phase power module to provide more accurate switch
side inductor current estimation and noise rejection as is shown in Fig. 6.10. Since the VF-CSS
controller needs an accurate inductor current sampling for peak/valley ripple current calculations
especially when the current ripple is huge (≥ 200%), a state estimator is desired to predict the
inductor current with capacitor voltage and grid current samplings. The main purposes of the state
estimator are (1) avoid inaccuracy of inductor current sampling with high current ripple for VF-
CSS; (2) improve the anti-noise capability for better control performance; (3) reduce the sensor
cost.
The Luenberger observer is designed to estimate the switch side inductor current, 𝑖ˆ𝐿 𝑓 𝑠 , capaci-

152
tor voltage, 𝑣ˆ 𝐶 𝑓 , and grid side inductor current, 𝑖ˆ𝐿 𝑓 𝑔 , with the samplings of capacitor voltage, 𝑣 𝐶 𝑓 ,
and grid side inductor current, 𝑖 𝐿 𝑓 𝑔 . The state-space equations for the discrete-time state estimator
can be expressed in standard matrix format of

𝑋ˆ 𝑘+1 = 𝐴𝐸 𝑋ˆ 𝑘 + 𝐵 𝐸 𝑢 𝑘 + 𝐿 𝐸 (𝑌𝑘 − 𝑌ˆ𝑘 ) (6.13a)

𝑌ˆ𝑘+1 = 𝐶𝐸 𝑋ˆ 𝑘 + 𝐷 𝐸 𝑢 𝑘 (6.13b)

where the variables and matrices for Luenberger observer represent

− 𝐿1𝑓 𝑠
   1 

 0 0 


 𝐿𝑓𝑠


   
𝐴𝐸 =  1 1 ,𝐵 =  (6.14a)
𝐶𝑓 0 − 𝐶𝑓  𝐸  0
,

   
0 0 0   0
   
 
   
   
 0 1 0   0 
𝐶𝐸 =   , 𝐷𝐸 =   , (6.14b)
  

 0 0 1   0 
 
   
𝑖ˆ𝐿 𝑓 𝑠 (𝑘) 
 
  

   𝑣ˆ 𝐶 𝑓 (𝑘) 
𝑋ˆ 𝑘 =  𝑣ˆ 𝐶 𝑓 (𝑘)  , 𝑌ˆ𝑘 =  (6.14c)
 
.
  ˆ
 𝑖 𝐿 𝑓 𝑔 (𝑘) 
 
𝑖ˆ𝐿 𝑓 𝑔 (𝑘) 
   

 

𝐿 𝐸 is a 3×2 observer gain matrix that can be tuned to achieve minimal estimation errors. The
diagram of the state estimator is shown in Fig. 6.10. The state observer minimizes the estimation
error, 𝑒(𝑘), with a dynamic equation of

𝑒 𝑘+1 = ( 𝐴𝐸 − 𝐿 𝐸 𝐶𝐸 )𝑒 𝑘 . (6.15)

The estimation gain can be derived by

153
 Figure 6.12: Control diagram of power module with VCF-CSS, MPC and estimator.

Figure 6.13: Control diagram of power module with VDF-CSS and MPC.

𝐿𝑇𝐸 = 𝑅𝑀 −1 (6.16)

where 𝑅 is composed of tuning factors and 𝑀 is determined by solving the Sylvester equation

𝐴𝑇𝐸 𝑀 − 𝑀Λ = 𝐶𝐸𝑇 𝑅 (6.17)

in which Λ is a matrix with the desired eigenvalues.

6.2.4 Local Level Variable Frequency Control

For the local level per phase variable-frequency critical-soft-switching control, two control
strategies are proposed including variable-continuous-frequency critical-soft-switching (VCF-CSS)

154
Figure 6.14: The relationship of PWM carriers and fundamental sampling signals for VDF-CSS.

and variable-discrete-frequency critical-soft-switching (VDF-CSS). Two frequency controllers are

implemented to achieve critical soft switching operation for high effciency with different types
of frequency. The VCF-CSS derives a continuous switching frequency based on the critical soft
switching boundary conditions and then directly implements the frequency value to the PWM with
the help of state estimator to collect the switch side inductor current value. On the other hand,
VDF-CSS discretizes the calculated switching frequency with multiple times of the sampling fre-
quency for PWM which does not need the state estimator to derive an accurate switch side inductor
current value. Fig. 6.11(a) and 6.11(b) show the switch side inductor current waveforms for VCF-
CSS and VDF-CSS, respectively. The envelopes of VCF-CSS and VDF-CSS are smooth and
discretized due to the varying types of switching frequency. Both methods can achieve critical soft
switching operation for the improvement of efficiency. Since both the VCF-CSS and VDF-CSS are
combined with MPC to deal with the time-varying switching frequency, the transient performance
is improved by MPC with less oscillation and spikes even for the discretized frequency. And the
corresponding 𝑑𝑖/𝑑𝑡 stress on the switches are low.

VCF-CSS

VCF-CSS is designed to calculate the desired continuous switching frequency based on the
peak/valley switch side inductor current and the critical soft switching boundary conditions in
equation (6.1). The control diagram of the per phase power module with VCF-CSS and MPC has

155
been shown in Fig. 6.12 which includes MPC controller, state estimator and VCF-CSS controller.
For the VCF-CSS controller, the continuously varying switching frequency, 𝑓𝑠,𝑐𝑎𝑙 , is derived based
on the threshold current, 𝐼𝑡ℎ , of critical soft switching boundary conditions in (6.1). Since the
switch side inductor current ripple, Δ𝑖 𝐿 𝑓 𝑠 , can be calculated as

𝑑 (1 − 𝑑)𝑣 𝑑𝑐
Δ𝑖 𝐿 𝑓 𝑠 = . (6.18)
𝑓𝑠 𝐿 𝑓 𝑠

And the critical soft switching boundary conditions require the peak/valley inductor current values
to be higher than 𝐼𝑡ℎ and lower than -𝐼𝑡ℎ , respectively. Thus, the calculation of the continuously
varying switching frequency, 𝑓𝑠,𝑐𝑎𝑙 , can be expressed as

(1 − 𝑑)𝑑𝑣 𝑑𝑐
𝑓𝑠,𝑐𝑎𝑙 = , 𝑖 𝐿 𝑓 𝑠,𝑎𝑣𝑒 ≥ 0 (6.19a)
2(𝑖 𝐿 𝑓 𝑠,𝑎𝑣𝑒 + 𝐼𝑡ℎ )𝐿 𝑓 𝑠
(1 − 𝑑)𝑑𝑣 𝑑𝑐
𝑓𝑠,𝑐𝑎𝑙 = , 𝑖 𝐿 𝑓 𝑠,𝑎𝑣𝑒 ≤ 0 (6.19b)
2(𝐼𝑡ℎ − 𝑖 𝐿 𝑓 𝑠,𝑎𝑣𝑒 )𝐿 𝑓 𝑠

where 𝑖 𝐿 𝑓 𝑠,𝑎𝑣𝑒 is the average value of switch side inductor current without considering the high
current ripple for critical soft switching calculation. The 𝑖 𝐿 𝑓 𝑠,𝑎𝑣𝑒 have also been plotted as the blue
sine waveform lines in Fig. 6.11.
As is shown in Fig. 6.12, the VCF-CSS receives the estimated values of 𝑖 𝐿 𝑓 𝑠,𝑒𝑠𝑡 , 𝑣 𝐶 𝑓 ,𝑒𝑠𝑡 and
𝑖 𝐿 𝑓 𝑔,𝑒𝑠𝑡 from the state estimator and optimal duty cycle value from MPC controller to calculate the
desired switching frequency, 𝑓𝑠,𝑐𝑎𝑙 , and applies to the PWM. The state estimator contributes to pro-
viding a more accurate switch side inductor current value for frequency calculation compared with
the direct sampling value since the sampling frequency and control frequency are both constant.
The varying switching frequency could result in a deviation of sampling from the true averaged
inductor current value especially when the current ripple is large for critical soft switching. This
deviation error can be solved by the state estimator.

156
VDF-CSS

Another frequency controller is designed as VDF-CSS to further discretize the calculated

switching frequency in equations (6.19). The local per phase power module control with VDF-
CSS is shown in Fig. 6.13. The continuously varying switching frequency in equations (6.19)
is further discretized into pre-defined frequency bandwidth sections which is designed as integral
multiple of the fundamental sampling frequency, 𝑓𝑠,𝑏𝑎𝑠𝑒 . Thus, the discretized varying switching
frequency for PWM signals could be 𝑛 times of 𝑓𝑠,𝑏𝑎𝑠𝑒 (𝑛 ∈ Z). To ensure the soft switching op-
eration, the multiple value of 𝑛 is rounded down during the discretization by choosing a relatively
lower switching frequency section. The implementation of the frequency controller is shown in the
left bottom block of Fig. 6.13. The relationship of PWM switching carrier signals and sampling
signals are shown in Fig. 6.14 with a varying switching frequency from 4 𝑓𝑠,𝑏𝑎𝑠𝑒 to 2 𝑓𝑠,𝑏𝑎𝑠𝑒 then to
𝑓𝑠,𝑏𝑎𝑠𝑒 . The process of frequency discretization can be expressed as

𝑓𝑠,𝑐𝑎𝑙
𝑓𝑠,𝑑𝑖𝑠𝑐𝑟𝑒𝑡𝑒 = 𝑛 𝑓𝑠,𝑏𝑎𝑠𝑒 = 𝑓 𝑙𝑜𝑜𝑟 ( ) 𝑓𝑠,𝑏𝑎𝑠𝑒 . (6.20)
𝑓𝑠,𝑏𝑎𝑠𝑒

The discretized frequency may be ringing back and forth by the oscillation of sampling noise
during frequency changing transients. A hysteresis loop is configured after the frequency dis-
cretization process to eliminate the frequency oscillation. Then, the discretized frequency will be
implemented to the PWM for soft switching operation.
Compared with the VCF-CSS, the VDF-CSS discretizes the switching frequency to be multiple
times of the fundamental sampling frequency. Thus, the switch side inductor current will be sam-
pled exactly at the average points of the current ripple without deviation from the accurate values
as is shown in Fig. 6.14. Thus, even without the state estimator for the estimation of 𝑖 𝐿 𝑓 𝑠 , the
inductor current sampling can be accurate for the critical soft switching calculation at high current
ripple.

157
 (a)

(b) (c) (d)

Figure 6.15: Hardware prototypes of (a) integrated prototype (b) power board (c) medium fre-
quency inductor and (d) high frequency inductor.

(a) (b)

Figure 6.16: Switching frequency of VCF-CSS and VDF-CSS for (a) medium frequency and (b)
high frequency applications.

158
 (a) (b)

(c)

Figure 6.17: Captured experimental readings of sampling measurement in blue lines and estimation
in red lines of (a) switch side inductor current (b) capacitor voltage and (c) grid side inductor
current.

(a) (b)

Figure 6.18: Captured experimental readings of switching frequency in blue lines and grid side
inductor current in red lines of (a) VCF-CSS and (b) VDF-CSS at medium frequency of 40kHz-
240kHz with 45𝜇H switch side inductor.

159
 (a) (b)

Figure 6.19: Captured experimental readings of switching frequency in blue lines and grid side
inductor current in red lines of (a) VCF-CSS and (b) VDF-CSS at high frequency of 360kHz-
1.08MHz with 4.5𝜇H switch side inductor.

(a) (b)

Figure 6.20: (a) The inductor current, capacitor voltage, grid current and DC bus voltage with
constant switching frequency and (b) zoomed waveforms.

6.3 Results

The proposed variable-frequency critical-soft-switching model predictive control methods with

state estimator for zero-sequence stabilized non-isolated grid-connected inverter have been vali-

160
 (a) (b)

Figure 6.21: Medium frequency of 40kHz-240kHz with 45𝜇H switch side inductor (a) VCF-CSS
and (b) zoomed steady state waveforms of inductor current, capacitor voltage, grid current and DC
bus voltage.

(a) (b)

Figure 6.22: High frequency of 360kHz-1.08MHz with 4.5𝜇H switch side inductor (a) VCF-CSS
and (b) zoomed steady state waveforms of inductor current, capacitor voltage, grid current and DC
bus voltage.

dated experimentally with carefully designed litz wire inductors and power converter board. The
control strategies and modified topology are applied to both medium frequency of 40kHz-240kHz
with 45𝜇H switch side inductor and high frequency of 360kHz-1.08MHz with 4.5𝜇H switch side
inductor, respectively. The maximum efficiency at rated power of 15kW is reaching 99%. The

161
 (a) (b)

Figure 6.23: Medium frequency of 40kHz-160kHz with 45𝜇H switch side inductor (a) VDF-CSS
and (b) zoomed steady state waveforms of inductor current, capacitor voltage, grid current and DC
bus voltage.

(a) (b)

Figure 6.24: High frequency of 360kHz-1.08MHz with 4.5𝜇H switch side inductor (a) VDF-CSS
and (b) zoomed steady state waveforms of inductor current, capacitor voltage, grid current and DC
bus voltage.

power densities of 8.14kW/L and 10.4kW/L are achieved for medium and high frequencies, respec-
tively. The detailed performances of the proposed control methods on the modified non-isolated
inverter are shown as follows.

162
Figure 6.25: The drain-source voltage and current across the upper switch for soft switching oper-
ation.

(a) (b)

Figure 6.26: (a) VCF-CSS and (b) zoomed transient waveforms of inductor current, capacitor
voltage and DC bus voltage with a current step of 4A.

(a) (b)

Figure 6.27: (a) VDF-CSS and (b) zoomed transient waveforms of inductor current, capacitor
voltage and DC bus voltage with a current step of 4A.

163
Figure 6.28: The efficiency curves comparison of VCF-CSS, VDF-CSS and constant frequency.

Figure 6.29: The loss comparison between the conventional 𝐿𝐶 𝐿 inverter and the developed in-
verter with VF-CSS.

6.3.1 Hardware Setup

The testbench is shown in Fig. 6.15 including the power converter board in Fig. 6.15(b) and
switch side medium inductor in Fig. 6.15(c) and small inductor in Fig. 6.15(d). The DSP control
card, TMS320F28388D, is plugged on side of the power converter board. The Cree SiC MOSFET,

164
 (a) (b)

Figure 6.30: The (a) power-frequency and (b) efficiency-power density diagrams of SiC and GaN
based applications.

C3M0032120K, is chosen for the power switch in the middle area of the power board covered
by the heat sink and cooling fan. For the switch side 𝐿𝐶 𝐿 inductors, two types of inductors with
45𝜇H and 4.5𝜇H are designed at rated power for the medium frequency of 40kHz-240kHz and high
frequency of 360kHz-1.08MHz operations, respectively. The switching frequency as functions of
output power for high/medium frequencies VCF-CSS/VDF-CSS are also shown in Fig. 6.16. The
dead time is configured as 80ns for the safety consideration. Thus, the maximal modulation indexes
for the medium and high frequency inductor applications are calculated as 0.98 for 240kHz and
0.91 for 1.08MHz, respectively.
For the medium inductor in Fig. 6.15(c), air-gaped E-E core is designed with E42/21/20-3F3
from Ferroxcube to be combined with litz wire winding (equivalent gauge 10). For the small
inductor in Fig. 6.15(d), air-gaped E-I core is designed with E42/21/20-3F3 from Ferroxcube to be
combined with litz PCB winding for the purpose of saving window space to reduce the inductor
volume as has been designed in [133].
For the output capacitors, each phase has three 2.5𝜇F upper caps and three 2.5𝜇F lower caps

165
in parallel all from TDK FA10 to be integrated on the power board. The grid side inductor are
composed of two 1𝜇H in series for each each phase on the board.
For the parameters design of output capacitance and grid side inductance, the principles are
based on the minimum output capacitor voltage ripple, 𝑣 𝐶 𝑓 ,𝑟𝑖 𝑝 𝑝𝑙𝑒 and the resonant frequency of the
𝐿𝐶 𝐿 filter, 𝜔𝑟𝑒𝑠 . Specifically, the minimum capacitance is determined by the output voltage ripple
which is expressed as:

1 − 𝑑𝑚𝑖𝑛
𝐶 𝑓 ,𝑚𝑖𝑛 = 2
. (6.21)
8𝐿 𝑓 𝑠 𝑣 𝐶 𝑓 ,𝑟𝑖 𝑝 𝑝𝑙𝑒 [%] 𝑓𝑠𝑤

Then, from the minimum available 𝐶 𝑓 ,𝑚𝑖𝑛 , the value of grid inductance can be adjusted to determine
the resonant frequency of 𝐿𝐶 𝐿 filter system as is shown in

√︄
𝐿 𝑓𝑠 + 𝐿 𝑓𝑔
𝜔𝑟𝑒𝑠 = . (6.22)
𝐿 𝑓 𝑠 𝐿 𝑓 𝑔𝐶 𝑓

6.3.2 State Estimation Results

The state estimation method is validated in the modified non-isolated 𝐿𝐶 𝐿 grid-connected

inverter to be combined with the VCF-CSS and MPC. One purpose of the estimator is to provide
accurate switch side inductor current readings, 𝑖 𝐿 𝑓 𝑠 , for both the calculation of optimal soft switch-
ing frequency and MPC implemention with fixed control frequency at high current ripple. Another
purpose is to reduce the sampling noise from the sensors for a better steady state performance.
The observer estimates the switch side inductor current, 𝑖ˆ𝐿 𝑓 𝑠 , capacitor voltage, 𝑣ˆ 𝐶 𝑓 , and grid
side inductor current, 𝑖ˆ𝐿 𝑓 𝑔 , with the ADC measurements of capacitor voltage, 𝑣 𝐶 𝑓 , and grid side
inductor current, 𝑖 𝐿 𝑓 𝑔 . Fig. 6.17 shows the experimental readings from DSP of the estimated 𝑖ˆ𝐿 𝑓 𝑠 ,
𝑣ˆ 𝐶 𝑓 , 𝑖ˆ𝐿 𝑓 𝑔 in blue lines and the measured 𝑖 𝐿 𝑓 𝑠 , 𝑣 𝐶 𝑓 , 𝑖 𝐿 𝑓 𝑔 in red lines. The observer accurately
estimates the measurements of 𝐿𝐶 𝐿 system. And the sampling noises from the measurements are
reduced with observer to provide cleaner and smoother current/voltage information for VCF-CSS
and MPC.

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6.3.3 Steady State Results

The steady state experimental results of VCF-CSS and VDF-CSS with MPC and estimator
are shown in this section to demonstrate the critical soft switching performance for both medium
frequency (40kHz-240kHz, 45𝜇H) and high frequency (360kHz-1.08MHz, 4.5𝜇H) testing setups.
Fig. 6.18 shows the captured data of switching frequency and the corresponding AC current
with medium frequency ranged at 40kHz-240kHz on the 45𝜇H inductor test bench. Specifically,
Fig. 6.18(a) captures the VCF-CSS data of switching frequency and AC current based on the
control method in Fig. 6.12 and equation (6.19). Fig. 6.18(b) captures the VDF-CSS data of
switching frequency and AC current based on the control method in Fig. 6.13. The variable
discrete frequency is separated into three discretized levels including 40kHz, 80kHz and 160kHz
which are all multiple times of the fixed sampling frequency of 40kHz. Thus, the switch side
inductor current can be sampled more accurately at high current ripple even without estimation.
Fig. 6.19 shows the captured data of switching frequency and the corresponding AC current
with high frequency ranged at 360kHz-1.08MHz on the 4.5𝜇H inductor test bench. Specifically,
Fig. 6.19(a) captures the VCF-CSS data of switching frequency and AC current based on the
control method in Fig. 6.12 and equation (6.19). Fig. 6.19(b) captures the VDF-CSS data of
switching frequency and AC current based on the control method in Fig. 6.13. The variable
discrete frequency is separated into four discretized levels including 360kHz, 600kHz, 840kHz
and 1.08MHz which are all multiple times of the fixed sampling frequency of 120kHz. Thus, the
switch side inductor current can be sampled more accurately at high current ripple even without
estimation.
The experimental waveforms of switch side inductor current, capacitor voltage, grid current
and DC voltage are compared between the hard switching and the proposed VCF-CSS and VDF-
CSS in Fig. 6.20 to Fig. 6.24. Specifically, in Fig. 6.20, a fixed switching frequency of 80kHz
is implemented which results in hard switching at the peak and valley points of the sinusoidal AC
current waveforms. Fig. 6.21 and Fig. 6.22 show the VCF-CSS and zoomed waveforms at medium
and high frequency, respectively. The critical soft switching operations are maintained at the full

167
AC current period. Fig. 6.23 and Fig. 6.24 show the VDF-CSS and zoomed waveforms at medium
and high frequency, respectively. The critical soft switching operations can also be maintained
by the discretized frequency at the full AC current period. Since the main target of VF-CSS is to
achieve soft-switching turn-on of the upper switch, the detailed drain-source voltage and current
waveforms across the upper switch for soft switching are shown in Fig. 6.25 to illustrate the ZVS
operation.

6.3.4 Model Predictive Control Transient Results

The transient experimental results for the proposed MPC controller with state estimator are
shown in this section to demonstrate the improved dynamic performance of the proposed MPC for
the variable frequency operation and during current reference steps.
The transient experimental results and the zoomed waveforms for VCF-CSS-MPC and VDF-
CSS-MPC are shown in Fig. 6.26 and Fig. 6.27 with a current step of 4A, respectively. From
the zoomed switch side inductor current waveforms, the critical soft switching operations are fully
maintained during both the current step transients and switching frequency transition instants.

6.3.5 Efficiency and Power Density Results

The efficiencies of the proposed VCF-CSS and VDF-CSS control strategies have been tested
up to the rated power as is shown in Fig. 6.28. The efficiencies of above 99% are both achieved for
the VCF-CSS and VDC-CSS which are 2% higher than the hard switching operation. Also the loss
breakdown comparison between the developed inverter with VF-CSS and the conventional 𝐿𝐶 𝐿
inverter with hard switching is shown in Fig. 6.29. With the proposed method, the switching loss
is reduced by more than times. And with the high frequency inductor and power board design in
Fig. 6.15, a maximum power density of 10.4kW/L is achieved. Several typical SiC/GaN converter
designs are compared in Fig. 6.30 with the power-frequency and efficiency-power density plots
[134, 135, 136, 137, 138, 139, 140, 141, 142, 143]. The proposed design is labeled in red star and
achieves the Pareto Optimal Points.

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6.4 Summary

This chapter proposes variable-frequency critical-soft-switching model predictive control strate-

gies to improve the efficiency and power density of a modified non-isolated grid-connected inverter.
Also, a state estimator is developed to be combined with the variable frequency model predictive
controller for the improvements of sampling accuracy and noise rejection. The leakage current is
attenuated by the zero-sequence model predictive control and the modified non-isolated topology.
Two types of variable frequency controllers are developed including VCF-CSS and VDF-CSS to
achieve the critical soft switching operation. A Luenberger Observer is developed to be combined
with the VCF-CSS for more accurate inductor current calclation of critical soft switching and noise
rejection. The proposed control methods and modified non-isolated topology have been validated
on medium frequency (>200kHz, 45𝜇H) and high frequency (>1MHz, 4.5𝜇H) test benches, re-
spectively. With the proposed critical soft switching control strategies, the efficiency is above 99%
at the rated power of 15kW and a power density of more than 10.4kW/L is achieved.

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Chapter 7: Design Case of MPC-Based Regulated Third Harmonic Injection

for Zero-Sequence Stabilized 𝐿𝐶 𝐿 Inverter

In the grid-connected power converter applications such as electric vehicle (EV) charger and
photovoltaic (PV), leakage current issue and DC bus utilization are two key factors that influence
the performance. For the leakage current issue, a bulky line frequency transformer is typically
installed to block the leakage path at the point of common coupling (PCC) which increases the
cost, volume and weight of the system. For the DC bus utilization, the DC bus voltage needs to be
stepped up to be at least twice of the grid voltage amplitude to avoid saturation issue which brings
extra switching losses and challenges to the switch voltage tolerance capability. This chapter fo-
cuses on the combination of modular MPC with zero-sequence voltage control and regulated third
harmonic injection (THI) techniques in the modified non-isolated three-phase 𝐿𝐶 𝐿 converter. The
developed software-defined power electronics architecture in Chapter 5 is leveraged to implement
the MPC-based regulated third harmonic injection technique.
For the DC bus utilization of DC/AC inverters, the THI can be implemented to avoid duty cycle
saturation with a relatively low DC voltage [144]. To evaluate the DC bus utilization, a modulation
index can be calculated as the ratio of AC output voltage fundamental component (grid voltage)
peak value to the modulation waveform fundamental component (DC bus voltage) peak value.
Several methods have been studied to improve the DC bus utilization, e.g., third harmonic sinu-
soidal waveform injection for sinusoidal PWM (SPWM), triangular waveform injection for space
vector pulse width modulation (SVPWM) [145]. Among the aforementioned injection methods,
the SPWM-based mechanism is simpler to implement in the DSP [146], [147]. However, if the
third harmonic or triangular waveforms are directly injected in the duty cycle before the modula-
tion, the control stability and robustness will be affected and even the divergence could occur in the

170
PWM modulation. Also, the conventional THI approaches will inject extra harmonics to the grid
which will deteriorate the power quality of the grid voltage and current. Even [146] and [147] have
proposed optimized THI algorithms to minimize the grid distortion of THI, the injected grid har-
monics cannot be fully eliminated. And the optimization look-up table from the published methods
accounts for extra computation resources and brings more control complexity. For the modulation
contribution of this chapter, a simple MPC-based zero-sequence regulated third harmonic injection
method is proposed without the need of introducing optimization algorithm and no extra harmonics
are injected to the grid. The power quality and system stability are improved. Combined with the
proposed topology and MPC-based regulated THI method, the DC bus utilization is improved in a
robust way without injecting harmonics to the grid and the complexity of optimization methods in
[146] and [147] are saved.
This chapter is organized as follows. Firstly, the circuitry model of the proposed non-isolated
three-phase grid-connected converter in Fig. 7.1(b) is analyzed in detail. Compared with the con-
ventional topology in Fig. 7.1(a), the common points of the output capacitors are connected to the
positive/negative terminals of the DC bus to bypass the leakage current and stabilize the common
mode voltage. The common mode circuit with parasitic path is illustrated. Also the equivalent
circuit model in 𝑑𝑞0 reference frame is analyzed. Secondly, the proposed modular MPC control
method is introduced with zero-sequence voltage controller to stabilize the common mode voltage.
The control mechanism includes the central level grid current 𝑑𝑞 control and local level MPC of
zero-sequence voltage control and three-phase capacitor voltage/inductor current control. The lo-
cal MPC module algorithm is designed based on the management of switch side per phase LC filter
inductor current and capacitor voltage. An explicit MPC method is applied for local module to save
the execution time. Thirdly, the regulated third harmonic injection method is proposed based on
the zero-sequence voltage control to improve the DC bus voltage utilization without injecting extra
harmonics to the grid. The advantages of the proposed methods can be concluded as non-isolated
zero-sequence voltage MPC for common mode improvement, per phase explicit modular MPC for
reducing DSP calculation complexity, regulated THI based on zero-sequence voltage control for

171
 (a) (b)

Figure 7.1: (a) Conventional 𝐿𝐶 𝐿 converter with monolithic control and (b) modified non-isolated
three-phase 𝐿𝐶 𝐿 converter with modularized MPC.

a stable and robust implementation of DC bus utilization improvement without extra harmonics
to deteriorate the grid and the inner loop MPC for triansent performance improvement. No grid
side inductance value is needed for the two-layer cascaded control structure which both improves
the dynamic performance from inner MPC loop and avoids the MPC parametric error caused by
the uncertainty of grid side inductance. Also, the modular concept of local MPC module enables
the extensibility for the power converter control with a flexible number of phases. Finally, the
experimental results are shown to validate the proposed control methods.

7.1 System Modeling

The leveraged non-isolated three-phase DC/AC converter has been shown in Fig. 7.1(b). Dif-
ferent from the traditional two-level three-phase DC/AC converter, the common point of three-
phase capacitors is connected to the DC bus positive/negative terminals to create a bypassing path
for zero-sequence voltage model predictive control. By leveraging the topological modification and
zero voltage control, the common mode voltage can be stabilized to reduce the leakage current.

7.1.1 DC/AC 𝐿𝐶 𝐿 Converter Modeling

The DC/AC converter is directly interfaced with the grid. To maintain a constant common
mode voltage, the proposed control method is based on the 𝑑𝑞0 coordinate system to leverage the
zero-sequence voltage component in the proposed topology. Compared with the 𝑎𝑏𝑐 system, the

172
active/reactive power and common mode voltage can be controlled independently with d, q and
0 sequence components in a 𝑑𝑞0 system. The coordinate system model of the proposed DC/AC
converter can be derived from 𝑎𝑏𝑐 reference frame.

abc system

The state space equations in 𝑎𝑏𝑐 system are expressed as:

1 1
𝑖¤𝐿,𝑎𝑏𝑐 = I𝑢 𝑥,𝑎𝑏𝑐 − I𝑢 𝑐,𝑎𝑏𝑐 (7.1a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑢¤ 𝑐,𝑎𝑏𝑐 = I𝑖 𝐿,𝑎𝑏𝑐 − I𝑖 𝑔,𝑎𝑏𝑐 (7.1b)
𝐶𝑓 𝐶𝑓
1 1
𝑖¤𝑔,𝑎𝑏𝑐 = I𝑢 𝑐,𝑎𝑏𝑐 − I𝑢 𝑔,𝑎𝑏𝑐 , (7.1c)
𝐿 𝑓𝑔 𝐿 𝑓𝑔

where 𝐿 𝑓 𝑠 , 𝐶 𝑓 and 𝐿 𝑓 𝑔 are the switch side inductor, capacitor and grid side inductor, respectively,
for the 𝐿𝐶 𝐿 filter. 𝑖 𝐿,𝑎𝑏𝑐 , 𝑢 𝑐,𝑎𝑏𝑐 , 𝑖 𝑔,𝑎𝑏𝑐 and 𝑢 𝑥,𝑎𝑏𝑐 are the switch side inductor current, capacitor
voltage, grid side current and grid voltage, respectively. I ∈ R3×3 is the identity matrix.

dq0 system

Since it is difficult to control the time-varying sinusoidal references in 𝑎𝑏𝑐 system while con-
venient to calculate the active/reactive power and stabilize zero-sequence voltage in 𝑑𝑞0 system,
the state space model is transformed to 𝑑𝑞0 reference frame for control purpose of the proposed
method. Coordinate system transformation has been widely applied in the three-phase AC systems
because the 𝑑𝑞 system can transfer the time-varying sinusoidal waveforms to equivalent constant
DC values [148]. For the implementation of control, the DC values are much easier to be controlled
than AC values. However, the traditional methods mainly utilize the 𝑑𝑞 system without considering
the zero-sequence. The proposed topology connects the common point of AC three-phase capaci-
tors to the DC bus positive/negative terminals which permits to extract the zero-sequence from 𝑎𝑏𝑐
system to 𝑑𝑞0 system and control the zero-sequence voltage to be half of DC bus voltage. Thus,

173
the 𝑢 𝑐𝑚 can be stabilized accordingly.
For the reference frame transformation with zero-sequence components, 𝑎𝑏𝑐 system needs to
be firstly transformed to 𝛼𝛽0 and then to 𝑑𝑞0 system. From 𝑎𝑏𝑐 to 𝛼𝛽0, the Clarke transform is
applied as:

 
 1 −1/2 −1/2 
 
2  √ √ 
𝑥 𝛼𝛽0 = T𝑥 𝑎𝑏𝑐 =  0 3/2 − 3/2  𝑥 𝑎𝑏𝑐 . (7.2)
3 

 1/2 1/2 1/2
 

 
In 𝛼𝛽0 system, the signls are composed of two orthogonal sinusoidal AC waveforms in 𝛼 and
𝛽 frames and a zero-sequence component. A Park transform is implemented secondly to convert
the stationary reference frame of 𝛼𝛽0 to the rotating 𝑑𝑞0 system which is calculated as:

 
 cos𝜃 sin𝜃 0 
 
 
𝑥 𝑑𝑞0 = P(𝜃)𝑥 𝛼𝛽0 =  −sin𝜃 cos𝜃 0  𝑥 𝛼𝛽0 . (7.3)
 
 0 0 1 
 
 
𝜃 is the phase angle of the grid which is tracked with a phase-locked-loop (PLL) controller
by measuring the grid voltage at the point of common coupling (PCC). Thus, the AC sinusoidal
signals in 𝑎𝑏𝑐 are converted to DC values in a rotating 𝑑𝑞0 frame with a time-varying angle of 𝜃.
Considering the control requirements to finally implement the duty cycles in 𝑎𝑏𝑐 format for the
PWM modulation, the inverse Clarke and Park transformations are needed to convert the output of
control signals from 𝑑𝑞0 to 𝑎𝑏𝑐:

𝑥 𝑎𝑏𝑐 = T−1 𝑥 𝛼𝛽0 = T−1 P(𝜃) −1 𝑥 𝑑𝑞0 . (7.4)

Based on equations (7.2) and (7.3) of the coordinate system transformations, the state space
equations of (7.1) can be transformed from 𝑎𝑏𝑐 to 𝑑𝑞0:

174
 1 1
𝑖¤𝐿,𝑑𝑞0 = I𝑢 𝑥,𝑑𝑞0 − I𝑢 𝑐,𝑑𝑞0 − 𝜔G𝑖 𝐿,𝑑𝑞0 (7.5a)
𝐿𝑓𝑠 𝐿𝑓𝑠
1 1
𝑢¤ 𝑐,𝑑𝑞0 = I𝑖 𝐿,𝑑𝑞0 − I𝑖 𝑔,𝑑𝑞0 − 𝜔G𝑢 𝑐,𝑑𝑞0 (7.5b)
𝐶𝑓 𝐶𝑓
1 1
𝑖¤𝑔,𝑑𝑞0 = I𝑢 𝑐,𝑑𝑞0 − I𝑢 𝑔,𝑑𝑞0 − 𝜔G𝑖 𝑔,𝑑𝑞0 (7.5c)
𝐿 𝑓𝑔 𝐿 𝑓𝑔

where 𝜔 is the angular velocity of the grid in rad/s. G is the matrix for the coupling terms resulted
from the transformation:

 
 0 −1 0 
 
 
G =  1 0 0  . (7.6)
 
 0 0 0 
 
 
By leveraging the 𝑑𝑞0 state space equations and the connection of three-phase capacitors com-
mon point with DC bus positive/negative terminals, the zero-sequence voltage can be controlled
explicitly to stabilize the 𝑢 𝑐𝑚 .
The equivalent circuits of the 𝑑𝑞0 system for proposed topology of DC/AC side converter are
shown in Fig. 7.2.

7.1.2 Common Mode Modeling

For a conventional transformerless three-phase grid-connected system as is shown in Fig.

7.1(a), there exist common mode leakage current paths among the grid neutral, chassis of the
power module and DC ground due to the high frequency common mode voltage, 𝑣 𝑐𝑚 , fluctuation
on the switch side and the equivalent parasitic capacitance, 𝐶 𝑝 [149]. The leakage current, 𝑖 𝑙 𝑘𝑔 ,
will flow through the common mode path and can be derived as:

𝑑𝑣 𝑐𝑚
𝑖 𝑙 𝑘𝑔 = 𝐶 𝑝 (7.7)
𝑑𝑡

175
 (a) (b)

(c)

Figure 7.2: (a) 𝑑-axis (b) 𝑞-axis and (c) 0-axis equivalent circuit of the modified topology on
DC/AC side.

(a) (b)

Figure 7.3: Equivalent common mode circuit of the (a) conventional and (b) proposed non-isolated
DC/AC converter.

The level of leakage current is mainly dominated by the fluctuating rate of common mode voltage
and equivalent impedance of parasitic capacitance [150], [151]. The fluctuation of common mode
voltage is induced by the intrinsic high switching frequency of the circuit and can be expressed as
the mean value of three-phase switching legs output voltages, 𝑣 𝑥,𝑎 , 𝑣 𝑥,𝑏 , 𝑣 𝑥,𝑐 :

𝑣 𝑥,𝑎 + 𝑣 𝑥,𝑏 + 𝑣 𝑥,𝑐

𝑣 𝑐𝑚 = . (7.8)
3

176
 Central Level Grid current/Zero-voltage/THI Controllers Local Level Per Phase MPC Control Modules
ig,a M1 ΦA
theta theta PWM,up Cf,up

iL,a Gate
Phase A d,a* Driver L
ig,d* Grid Vc,a* Local MPC
Current Vc,a Controller PWM,lo +
Gate Va,out_
Vg,abc Vg,dq0 ig,d Vd* Vdc
Cf,lo

abc Driver M2

ig,d Control
ig,abc ig,dq0
dq0 Grid dq0 ig,b
PWM,up
M1 Cf,up ΦB

iL,abc iL,dq0
ig,q* Current iL,b Gate
Phase B d,b* Driver L
ig,q Vc,b* Local MPC
Control Vq* Vc,b PWM,lo
+
ig,q Controller Gate Cf,lo
Vb,out
_
Vdc Driver M2

Vg,q*
Vdc/2
Phase theta* Vdc/2 abc ig,c M1 Cf,up ΦC
Lock iL,c
PWM,up
Gate
Vdc/2 Vdc/2 Phase C d,c* L
Loop + V0* Vc,c* Local MPC
Driver

Vg,q Vc,abc* Vc,c PWM,lo

+

V3rd Controller Gate Cf,lo

Vc,out
_
theta Vdc Driver M2

Figure 7.4: Proposed modular MPC control diagram of the non-isolated DC/AC converter.

Fig. 7.3(a) shows the equivalent common mode circuit in a traditional non-isolated DC/AC
converter where the red dotted lines with arrows represent the leakage current. This leakage current
is excited by the high frequency fluctuation of common mode voltage in the parasitic path. So, the
leakage current is mainly determined by two factors: (1) rate of 𝑢 𝑐𝑚 ; (2) parasitic capacitance.
Firstly, according to equation (7.8), the mean value of three-phase switching legs output voltages
is squre waveforms with an amplitude of DC bus voltage at switching frequency level. Thus, the
rate of change, 𝑑𝑢 𝑐𝑚 /𝑑𝑡 is high to amplify the leakage current. Secondly, the parasitic capacitance,
𝐶 𝑝 is another factor to influence the leakage current. The value of 𝐶 𝑝 varies in the solar and EV
charging systems. For a typical photovoltaic system, 𝐶 𝑝 is ranged between 10nF-100nF. However,
in a EV system, 𝐶 𝑝 is between 1nF-10nF [152]. For the safety consideration of the standard
requirements, the leakage current is limited to be no more than 30mA in a EV system by IEC
62955:2018 and IET Wiring Regulation 18th Edition (BS 7671:2018) Section 722.531.2.101.
Fig. 7.3(b) presents the equivalent common mode circuit in the proposed non-isolated DC/AC
converter where the leakage current to the grid can be bypassed with the connection of three-
phase output capacitors common point and DC positive/negative terminals. This leakage current
attenuation capability is achieved by the proposed zero-sequence voltage controller which aims
at stabilizing the zero-sequence capacitor voltage to be a constant value of half DC bus voltage,
𝑢 𝑑𝑐 /2, instead of a high frequency fluctuating square waveform.

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7.2 Control Design

The proposed model predictive control method of non-isolated three-phase 𝐿𝐶 𝐿 converter

with zero-sequence voltage stabilization capability is illustrated in this section. Fig. 7.4 shows
the control diagram which consists of the central level control of 𝑑𝑞 sequences output current PI
control cascaded with the local level control of zero-sequence voltage, three-phase inductor cur-
rent/capacitor voltage model predictive control. The local level modular MPC is implemented for
each phase of LC module. The modularized local MPC enables the extensibility for random phase
number of power converter control and reduces the computational complexity of multi-phase MPC
algorithm as a whole function.

7.2.1 Phase-locked-loop

The transformations between 𝑎𝑏𝑐 and 𝑑𝑞0 needs the real-time phase angle information, 𝜃, of
the grid voltage [153]. An effective way can be implemented with a PI controller by controlling
the 𝑞 component of the grid voltage, 𝑣 𝑔,𝑞 , to be zero to derive the angular velocity, 𝜔, of the phase
angle. Then, the 𝜃 can be calculated with a period of 2𝜋. And based on the active/reactive power
calculation in

     
 𝑃  3  𝑢 𝑔,𝑑 𝑢 𝑔,𝑞   𝑖 𝑔,𝑑 
=  (7.9)
     
   
 𝑄  2 𝑢
 𝑔,𝑞 −𝑢 𝑔,𝑑
  𝑖 
    𝑔,𝑞 
     
the 𝑑-axis and 𝑞-axis represent the active and reactive power, respectively.

7.2.2 Central Level Output Current Control

The output current is transformed from 𝑎𝑏𝑐 to 𝑑𝑞 reference frame with Clarke and Park trans-
formations. Then, two PI controllers are configured to regulate the 𝑑𝑞 sequence output currents,
𝑖 𝑔,𝑑 and 𝑖 𝑔,𝑞 , respectively. Based on the configuration of PLL to control the 𝑞 component of grid
voltage, 𝑣 𝑔,𝑞 , to be zero and the active/reactive equation in (7.9), 𝑖 𝑔,𝑑 and 𝑖 𝑔,𝑞 are linked to the

178
active and reactive power control loops, respectively. The outputs of grid current controller are the
references of 𝑑𝑞 sequence capacitor voltages, 𝑣 ∗𝑑 and 𝑣 ∗𝑑 , which will be transformed back to 𝑎𝑏𝑐
reference frame and configured as the MPC reference of three-phase capacitor voltages.

7.2.3 Zero-sequence Voltage Control

The zero-sequence voltage of the three-phase capacitors are controlled to be half of DC bus
voltage with MPC to block the leakage current from flowing through the grid. As are shown in
Fig. 7.2(c) of the 0-axis equivalent circuit and Fig. 7.3(b) of the 𝑎𝑏𝑐 frame equivalent common
mode circuit, the zero-sequence output current can be attenuated by the stabilization control of
zero-sequence capacitor voltage. Specifically, half of DC bus voltage measurement is configured
as the reference of zero-sequence voltage controller and transformed from 𝑑𝑞0 to 𝑎𝑏𝑐 frame for the
three-phase LC capacitor voltage model predictive control. A third harmonic component extracted
from the central level grid side inductor current controller output after reversed Park transformation
can be added to the zero-sequence voltage reference to improve the DC bus voltage utilization
which will be analyzed in the fourth section.
The working principle of zero sequence voltage control is based on the three phase output ca-
pacitor voltage reference MPC tracking. Specifically, in the central controller, the zero sequence
component of the reference is designed as half of DC bus voltage measurement, 𝑉𝑑𝑐 /2. This ref-
erence is combined with 𝑑𝑞 components references from the output of grid side inductor current
controllers and then transformed into 𝑎𝑏𝑐 reference frame for tracking references of the local three
phase MPC controllers. Each of the reference input for three phase local MPC controller is com-
posed of a sinusoidal AC component and a zero sequence DC component. Thus, the object and
cost function of the zero sequence voltage MPC control is integrated into the three separate MPC
configurations which is consistent with the illustration in (6.7). The three phase local MPC track-
ing for zero sequence voltage control guarantees a stabilized common mode capacitor voltage and
low leakage current.

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7.2.4 Local Level Per Phase LC Filter MPC

The explicit MPC method is designed for the switch side capacitor voltage and inductor current
control by following the local level per phase MPC algorithms in Chapter 6 from (6.3) to (6.12).
As is shown in Fig. 7.4 of the control diagram, the three-phase capacitor voltages are controlled in
𝑎𝑏𝑐 frame to follow the references from the cascaded grid current controller’s outputs. The switch
side inductor currents are also regulated with the MPC by adjusting the weighting factor between
𝑖 𝐿,𝑎𝑏𝑐 and 𝑢 𝑐,𝑎𝑏𝑐 .
For the MPC implementation, in every control period, the MPC controller receives the mea-
sured switch side inductor current, 𝑖 𝐿,𝑎𝑏𝑐 , capacitor voltage, 𝑣 𝑐,𝑎𝑏𝑐 , grid current, 𝑖 𝑔,𝑎𝑏𝑐 , from ADC
and capacitor voltage reference, 𝑣 ∗𝑐,𝑎𝑏𝑐 from the grid current controller. An offline generated piece-
wise affine search tree is applied to derive the optimal duty cycle for the explicit MPC.

7.2.5 Modular MPC Concept Based on Software-Defined Architecture

The proposed regulated THI control structure is designed based on the software-defined power
electronics architecture in Fig. 5.1. The whole control structure is composed of central control
layer and local level MPC control modules. The central controller is functioned as a pivot to collect
the ADC data from local modules, manage the converged branch power control, redistribute the
power flow for local modules and generate voltage/current references for local modules. The local
module focuses on the MPC control, ADC sampling and PWM modulation of LC filtered switch
leg. Thus, the reference commands are allocated to the local control modules and the ADC data
are collected for the local and central controllers. The modular MPC concept enables a more
general power converter control with random number of power modules to satisfy the topological
and power rating requirements. To satisfy different topological requirements, the local MPC can
be applied to single/three phase DC/AC or DC/DC converters. Also, the number of paralleled
modules is adjustable with central controller to redistribute the power flow for local modules to
meet different power rating demands.
The comparative analysis of the proposed modular MPC and the conventional methods can be

180
concluded as: (1) Firstly, the grid side inductor current is controlled with PI while the output ca-
pacitor voltage and switch side inductor current are controlled with MPC. No grid side inductance
value is needed for the two-layer cascaded control structure which both improves the dynamic per-
formance from inner MPC loop and avoids the MPC parametric error caused by the uncertainty
of grid side inductance. (2) Secondly, the proposed MPC is operated in a modular way for each
phase 𝐿𝐶 filter with simpler state space matrix formulation and smaller size of C code for exper-
imental implementation in DSP. The state space matrix of A is 2×2 which is smaller than 4×4 in
[109] and 6×6 in [126]. The generated C code file for MPC implementation is only 5kB which is
undemanding for a less costly DSP; (3) Thirdly, the proposed local MPC controllers and central
controller can be implemented in different interrupts, cores or digital control devices with different
frequencies. CAN protocols can be leveraged to communicate among the controllers. The local
MPC controllers are configured with higher frequencies than the central controller. This imple-
mentation is designed to enable a higher control bandwidth for the local MPC than the central
controller to improve the dynamic performance. Due to the simplified C code file of the proposed
MPC controller, the execution time of each MPC algorithm is within 5us. Thus, the local MPC
can be implemented with a frequency of 40kHz while the central controller is operating at 20kHz;
(4) Finally, the local MPC controllers are implemented in 𝑎𝑏𝑐 reference frame for the switch side
𝐿𝐶 filter components. And the grid side inductor current is manipulated by the central level grid
current controller. Thus, as is shown in equation (6.5a), the state space matrices are only composed
of the static parameters of switch side inductance, 𝐿 𝑓 𝑠 , output capacitance, 𝐶 𝑓 , and control period,
𝑇𝑠 . Different from the formulations of state space matrices in [109] and [126], no dynamic param-
eter, such as the grid angular velocity 𝜔, is included in the state space matrices. A PLL controller
is designed to provide the accurate grid angular velocity. All static parameters for the state space
matrices guarantee an offline generated explicit MPC function which saves the execution time for
the online operation of MPC algorithm.

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 (a) (b)

(c)

Figure 7.5: (a) Conventional (b) proposed regulated third harmonic injection methods and (c) the
detailed control diagram of the zero sequence stabilized RTHI.

(a) (b)

Figure 7.6: (a) Sinusoidal THI and (b) Triangular space vector injection.

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7.3 Regulated Third Harmonic Injection

A regulated third harmonic voltage injection (RTHI) method is proposed in this chapter based
on the zero voltage MPC to improve the DC bus voltage utilization. Different from the con-
ventional THI (Con-THI) in Fig. 7.5(a) to directly apply the third order sinusoidal waveform or
triangular space vector component to the duty cycle for modulation, the proposed RTHI in Fig.
7.5(b) extracts the third order/triangular components from the central level grid side inductor cur-
rent controller output after reversed Park transformation and add them to the zero-sequence voltage
reference, 𝑣 𝑑𝑐 /2, to formulate a new third-harmonic-based zero-sequence reference for the MPC.
The main advantages of the proposed RTHI include: (1) As is shown in Fig. 7.4, the injection of
third order/triangular components will be regulated by the MPC constraints before applying to the
duty cycle of PWM. Thus, compared to the traditional direct duty cycle side injection methods,
the stability and robustness of the system are improved. (2) By leveraging the proposed modified
𝐿𝐶 𝐿 converter to connect the capacitors common point to positive/negative DC bus in Fig. 7.1(b),
the injected third harmonic components will be bypassed by the modified paths without flowing
into the grid. Thus, the grid-connected power quality will be improved compared to the conven-
tional THI methods. The third order sinusoidal (Sin-RTHI) and triangular space vector (Tri-RTHI)
components injection methods are analyzed in this section.

7.3.1 Third Harmonic Sinusoidal Injection (Sin-RTHI)

The sinusoidal injection method is implemented by deriving the third order of grid fundamental
frequency component to be superimposed to the zero-sequence voltage reference of MPC. The Sin-
RTHI zero-sequence voltage reference for MPC can be expressed as:

𝑣 ∗0,3𝑟 𝑑 = 𝑣 𝑑𝑐 /2 + 𝑉𝑚 𝐷 3𝑟 𝑑 𝑠𝑖𝑛(3𝜔𝑡). (7.10)

Thus, the 𝑎𝑏𝑐 frame Sin-RTHI three-phase capacitor voltage references, 𝑣 ∗𝑐,𝑎𝑏𝑐 , distributed to the
local MPC controllers can be expressed as

183
 𝑣 ∗𝑐,𝑎 = 𝑣 ∗𝑐,𝑎 + 𝑉𝑚 𝐷 3𝑟 𝑑 𝑠𝑖𝑛(3𝜔𝑡) (7.11a)
2𝜋
𝑣 ∗𝑐,𝑏 = 𝑣 ∗𝑐,𝑏 + 𝑉𝑚 𝐷 3𝑟 𝑑 𝑠𝑖𝑛(3(𝜔𝑡 − )) (7.11b)
3
2𝜋
𝑣 ∗𝑐,𝑐 = 𝑣 ∗𝑐,𝑐 + 𝑉𝑚 𝐷 3𝑟 𝑑 𝑠𝑖𝑛(3(𝜔𝑡 + )). (7.11c)
3

where 𝑉𝑚 and 𝐷 3𝑟 𝑑 are the amplitude of fundamental component and third harmonic injection
depth, respectively. The angular speed, 𝜔, and phase shift can be derived based on the PLL con-
troller. By leveraging the THI to the proposed zero-sequence voltage MPC as is shown in Fig.
7.5(b), the peak to peak capacitor voltage can be reduced to improve the DC bus utilization and
avoid the duty cycle saturation in lower DC bus voltage. Fig. 7.6(a) shows the simulation wave-
forms of third order, fundamental frequency and injected capacitor voltages in one grid period.

7.3.2 Triangular Space Vector Injection (Tri-RTHI)

The triangular space vector injection method is implemented by deriving the mean value of
maximum and minimum grid fundamental frequency component capacitor voltage to be super-
imposed to the zero-sequence voltage reference of MPC. The Tri-RTHI zero-sequence voltage
reference for MPC can be expressed as:

𝑣 ∗0,3𝑟 𝑑 = 𝑣 𝑑𝑐 /2 − 𝐷 3𝑟 𝑑 [𝑚𝑎𝑥(𝑣 ∗𝑐,𝑎𝑏𝑐 ) + 𝑚𝑖𝑛(𝑣 ∗𝑐,𝑎𝑏𝑐 )]. (7.12)

Thus, the 𝑎𝑏𝑐 frame Tri-RTHI three-phase capacitor voltage references, 𝑣 ∗𝑐,𝑎𝑏𝑐 , distributed to the
local MPC controllers can be expressed as

184
 𝑣 ∗𝑐,𝑎 = 𝑣 ∗𝑐,𝑎 − 𝐷 3𝑟 𝑑 [𝑚𝑎𝑥(𝑣 ∗𝑐,𝑎𝑏𝑐 ) + 𝑚𝑖𝑛(𝑣 ∗𝑐,𝑎𝑏𝑐 )] (7.13a)

𝑣 ∗𝑐,𝑏 = 𝑣 ∗𝑐,𝑏 − 𝐷 3𝑟 𝑑 [𝑚𝑎𝑥(𝑣 ∗𝑐,𝑎𝑏𝑐 ) + 𝑚𝑖𝑛(𝑣 ∗𝑐,𝑎𝑏𝑐 )] (7.13b)

𝑣 ∗𝑐,𝑐 = 𝑣 ∗𝑐,𝑐 − 𝐷 3𝑟 𝑑 [𝑚𝑎𝑥(𝑣 ∗𝑐,𝑎𝑏𝑐 ) + 𝑚𝑖𝑛(𝑣 ∗𝑐,𝑎𝑏𝑐 )]. (7.13c)

As is shown in Fig. 7.6(b) of the triangular component injection, the DC bus utilization can also
be improved to avoid the duty cycle saturation issue.
To evaluate the effectiveness of the THI in Fig. 7.5, a voltage gain can be defined as the ratio
of the fundamental component capacitor voltage peak value, 𝑣 𝑏𝑎𝑠𝑒 , to the reference modulation
waveform peak value, 𝑣𝑇 𝐻𝐼 ,

𝑣 𝑏𝑎𝑠𝑒
𝐺𝑣 = . (7.14)
𝑣𝑇 𝐻𝐼

The maximum voltage gain of the continuous THI methods can be derived at the 𝜋/3 when the
third harmonic is at zero crossing point. Thus,

1
𝐺 𝑣,𝑚𝑎𝑥 = ≈ 1.155. (7.15)
𝑠𝑖𝑛(𝜋/3)

By leveraging the proposed THI methods, the DC bus voltage can be reduced by a factor of
1.15 and the voltage stress, switching losses on the power switches can be decreased, accordingly.

7.3.3 Advantages of Zero-sequence Controlled RTHI

The advantages of the zero-sequence controlled RTHI are addressed in this subsection. The
detailed working principle of the zero-sequence controlled RTHI is shown in Fig. 7.5(c). Dif-
ferent from the conventional THI in Fig. 7.5(a), the proposed RTHI methods extract the third
order/triangular components from the central level grid side inductor current controller output af-
ter reversed Park transformation and superpose the third order/triangular components, 𝑣 ∗3𝑟 𝑑 , with

185
 (a) (b)

Figure 7.7: (a) Sinusoidal RTHI and (b) zoomed waveforms.

the zero sequence voltage reference, 𝑣 𝑑𝑐 /2, as the new zero sequence reference for the local MPC
to track. However, the conventional THI methods directly add the third order components onto the
duty cycle for PWM modulation which brings two drawbacks: (1) The directly added third order
components are from the output of PI controllers. No constraints and regulations are implemented
before the third order components are pushed to the PWM modulation. Thus, compared to con-
ventional THI, the the proposed zero sequence stabilized RTHI is more robust and stable from the
control perspective; (2) The conventional THI induces extra third harmonics to the grid with the
traditional inverter topology which could deteriorate the power quality at PCC. The proposed zero
sequence controlled RTHI combined with the proposed topology can bypass the third harmonics
without injecting harmonics to the grid. The power quality will be improved automatically without
extra optimization methods in [146] and [147] to reduce the THD at PCC.

7.4 Results

The proposed method is validated experimentally on the non-isolated three-phase converter

with grid simulator. The testing parameters are 450Vdc to 208Vac with switching frequency

186
 (a) (b)

Figure 7.8: (a) Triangular RTHI and (b) zoomed waveforms.

(a) (b)

Figure 7.9: (a) The transients from sinusoidal RTHI to constant zero-sequence voltage control and
(b) zoomed waveforms.

of 100kHz. The 𝐿𝐶 𝐿 filter parameters are 45𝜇H for 𝐿 𝑓 𝑠 , 12𝜇F for 𝐶 𝑓 and 450𝜇H for 𝐿 𝑓 𝑔 .
C3M0021120K SiC from Cree and TMS320F28379D from TI are applied for switches and con-
troller, respectively.

187
 (a) (b)

Figure 7.10: (a) The transients from triangular RTHI to constant zero-sequence voltage control and
(b) zoomed waveforms.

7.4.1 Third Harmonic Injection Test

The regulated third harmonic injection methods are validated in Fig. 7.7 and Fig. 7.8(a).
Specifically, the sinusoidal RTHI in Fig. 7.7 achieves a voltage gain of 1.13 and the triangular
RTHI in Fig. 7.8(a) achieves a voltage gain of 1.12, respectively. Also, the transient waveforms
from Sin-RTHI and Tri-RTHI modes to constant zero-sequence voltage (Const-𝑣 0 ) mode are shown
in Fig. 7.9 and Fig. 7.10, respectively. The voltage gain, THD, third harmonic percentage of
capacitor voltage, grid current/voltage and leakage current performance of the proposed Sin-THI,
Tri-THI and Const-𝑣 0 methods are compared with conventional THI (Con-THI) and no THI cases
which are shown in table 7.1. The proposed RTHI methods can improve the DC bus utilization by
12% to 13%. The grid current/voltage THD are maintained within 1.5% with the proposed RTHI
with less than 3% of third harmonics to be injected to the grid. However, the conventional THI
method deteriorates the grid THD to be larger than 15% with more than 15% of third harmonics
to be injected to the grid. Thus, compared with the Con-THI, the proposed RTHI methods can
achieve maximum voltage gain with lowest grid current/voltage THD and minimum third harmonic
components which means the RTHI can avoid the harmonics to be injected to the grid.

188
Figure 7.11: The leakage currents and common mode voltages in Sin-RTHI, Tri-RTHI, Constant-
𝑣 0 , proposed topology without Constant-𝑣 0 control and conventional modes.

7.4.2 Leakage Current Test

The common mode voltage and leakage current waveforms of the Sin-RTHI, Tri-RTHI, Const-
𝑣 0 and non-THI are shown in Fig. 7.11. Also, the leakage current values are summarized in table

Table 7.1: The comparison of proposed and conventional methods.

Sin-RTHI Tri-RTHI Const-𝑣 0 Con-THI No THI
Topology Proposed Proposed Proposed Convent. Convent.
𝐺𝑣 1.13 1.12 1 1.11 1
𝑇 𝐻𝐷 𝑣𝑐 15.3% 17.6% 2.3% 18.5% 2.5%
𝑇 𝐻𝐷 𝑖𝑔 1.2% 1.4% 1.3% 17.4% 1.6%
𝑇 𝐻𝐷 𝑣𝑔 0.93% 1.1% 0.91% 15.3% 1.2%
𝑣𝑐 3𝑟 𝑑 % 10.2% 13.5% 1.5% 17.6% 1.8%
𝑖𝑔3𝑟 𝑑 % 2.1% 2.9% 2.7% 16.3% 2.6%
𝑣𝑔3𝑟 𝑑 % 1.6% 1.7% 1.5% 16.7% 1.2%
𝑖 𝑙 𝑘𝑔 13.3mA 14.5mA 12.7mA 416mA 392mA

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7.1. The zero-sequence voltage is controlled by the MPC to be half of DC bus voltage in Const-
𝑣 0 mode and with the injected third harmonic components in Sin-RTHI and Tri-THI modes. The
leakage current are all limited to be within 15mA for the three modes which are 30 times lower than
the conventional method. Thus, both the common mode voltage and current are compliant with the
UL and IEC standard requirements. Also, to further study the independent effects of zero sequence
voltage control and the modified topology on the reduction of leakage current, the leakage current
and common mode voltage of the modified topology without zero sequence voltage control have
been shown in Fig. 7.11 where the leakage current is 80mA. Thus, both the zero sequence voltage
control and modified topology contribute to the leakage current reduction. The modified topology
attenuates 5 times of the leakage current compared with the conventional topology. Furthermore,
the zero sequence voltage control reduces another 5 times of the leakage current compared to the
modified topology without zero sequence control case.

7.5 Summary

This chapter proposes a modular model predictive control method for a novel non-isolated
three-phase DC/AC converter with the capabilities of zero-sequence voltage stabilization and reg-
ulated third harmonic injection. The proposed non-isolated topology is designed to connect the
common point of three-phase 𝐿𝐶 𝐿 capacitors and positive/negative DC bus terminals to bypass
the zero-sequence leakage current. The zero-sequence voltage MPC controller stabilizes the zero-
sequence capacitor voltage to be a constant of half DC bus. Thus, the leakage current flowing
through the grid is attenuated. The proposed regulated third harmonic voltage injection methods
improve the DC bus utilization. By adding the third harmonic to the zero-sequence voltage MPC
reference, the stability and robustness are improved. And compared to the traditional THI meth-
ods in the aspect of grid THD, the grid power quality is improved since no extra harmonics are
injected to the grid and there is no need for optimization algorithm to reduce the grid THD. Per
phase explicit modular MPC simplifies the execution complexity on DSP and does not need to
update the angular speed in the state space matrix which makes it possible to implement the MPC

190
optimization offline. Compared with the traditional PI controller, the proposed MPC improves the
dynamic performance and control bandwidth with faster response. Compared with the traditional
MPC controller, no grid side inductance value is needed for the two-layer cascaded control struc-
ture which both improves the dynamic performance from inner MPC loop and avoids the MPC
parametric error caused by the uncertainty of grid side inductance.

191
 Chapter 8: Conclusion and Publications

8.1 Conclusion

This dissertation presents the design and development of software-defined power electronics
architecture to abstract the electrified energy conversion system by leveraging advanced control,
estimation and magnetic optimization methods. For the application-oriented power electronics
problems, the developed software-defined architecture generalizes the power electronics design
procedures with a reconfigurable multi-layer concept. Various types of electrified load/source have
been applied to the proposed system.
The variable-frequency critical-soft-switching control method is developed for the local power
module to replace the high turn-on loss with low turn-off loss. Both DC/DC converter and DC/AC
inverters are validated with the proposed method. The VF-CSS contributes to the efficiency im-
provement of 3%.
A high performance inductor design method is developed to enable mega-hertz frequency
critical-soft-switching for high efficiency and power density. The most crucial magnetic com-
ponent of switch side inductor is optimized with litz type of PCB winding and adjustable core
structures. A neural network model is leveraged to analyze the performance of litz PCB wind-
ing loss. The designed inductors have been compared with the existing commercial inductors and
showed the advantages of 4 times less loss, 40% less volume and 50◦ C less temperature rise.
A modular model predictive control method is designed to improve the dynamic performance
and reduce the oscillation caused by the variable-frequency critical-soft-switching operation. The
developed modular MPC increases the control bandwidth with higher reference tracking speed and
less overshoot issue.
A hierarchical software-defined power electronics architecture is proposed based on the MPC

192
and VF-CSS for local power module and high level control functions to generalize the electri-
fied energy conversion system and improve the power converter performance. Several merits are
achieved including: (1) generalized design procedures to reduce the repetitive power electronics
design processes; (2) reconfigurable architecture to form different power converter topologies with
the corresponding control functions; (3) wide application interfaces to be applicable for various
types of electrified load/source; (4) redundant mechanism with self-healing to diagnose and sub-
stitute the fault circuit components. Based on the generalized architecture, several design cases
have been implemented experimentally including isolated/non-isolated DC/DC converter, grid-
tied inverter, battery charger and motor traction inverter to validate the feasibility of the proposed
concept.
A high efficiency and power density grid-tied inverter is designed based on the VF-CSS and
modular MPC to achieve an efficiency above 99% at the rated power of 15kW and a power density
of 10.4kW/L. The designed litz PCB winding inductor is leveraged to be combined with the VF-
CSS to achieve more than 1MHz switching frequency. The modified power module combined with
a zero-sequence voltage control method enables a non-isolated inverter topology with low leakage
current and low cost.
An MPC-based regulated third harmonic injection technique is developed for the improve-
ment of DC bus voltage utilization in a modified zero-sequence stabilized 𝐿𝐶 𝐿 inverter. The
proposed MPC-based regulated third harmonic injection method is implemented through zero-
sequence voltage reference tracking. The output voltage/current distortion is largely attenuated
and the robustness is improved compared to the conventional third harmonic injection methods.
Also the computation burden is decreased without the need of extra output distortion optimization
algorithms.

8.2 Publications

Google Scholar link available at

https://scholar.google.com/citations?user=U2y3pVsAAAAJ&hl=en&oi=ao

193
8.2.1 Journals

1. L. Zhou, M. Jahnes and M. Preindl, “Modular Model Predictive Control of a 15kW, Kilo-to-
Mega-Hertz Variable-Frequency Critical-Soft-Switching Non-Isolated Grid-Tied Inverter with
High Efficiency," in IEEE Transactions on Power Electronics.

2. L. Zhou and M. Preindl, "Decentralized Circulating Current Attenuation with Model Predic-
tive Control for Distributed/Shunted Single/Three-Phase Grid-Tied Inverters," in IEEE Trans-
actions on Power Electronics.

3. L. Zhou and M. Preindl, “Optimal Tracking and Resonance Damping Design of Cascaded
Modular Model Predictive Control for Common-Mode Stabilized Grid-Tied LCL Inverter," in
IEEE Transactions on Power Electronics

4. L. Zhou, M. Jahnes, M. Eull, W. Wang and M. Preindl, “Control Design of a 99% Efficiency
Transformerless EV Charger Providing Standardized Grid Services," in IEEE Transactions on
Power Electronics, vol. 37, no. 4, pp. 4022-4038, April 2022.

5. L. Zhou and M. Preindl, “Inductor Design for Nonisolated Critical Soft Switching Converters
Using Solid and Litz PCB and Wire Windings Leveraging Neural Network Model," in IEEE
Transactions on Power Electronics, vol. 37, no. 3, pp. 3357-3373, March 2022.

6. L. Zhou and M. Preindl, “Variable-Switching Constant-Sampling Frequency Critical Soft

Switching MPC for DC/DC Converters," in IEEE Transactions on Energy Conversion, vol.
36, no. 2, pp. 1548-1561, June 2021.

7. L. Zhou, M. Jahnes, M. Eull, W. Wang, G. Cen and M. Preindl, “Robust Control Design
for Ride-Through/Trip of Transformerless Onboard Bidirectional EV Charger with Variable-
Frequency Critical-Soft-Switching," in IEEE Transactions on Industry Applications.

194
 8. B. Agrawal*, L. Zhou*, A. Emadi and M. Preindl, “Variable-Frequency Critical Soft-Switching
of Wide-Bandgap Devices for Efficient High-Frequency Nonisolated DC-DC Converters," in
IEEE Transactions on Vehicular Technology, vol. 69, no. 6, pp. 6094-6106, June 2020. (*
indicates the co-first authorship)

9. L. Zhou, F. Gao and T. Xu, “A Family of Neutral-Point-Clamped Circuits of Single-Phase

PV Inverters: Generalized Principle and Implementation," in IEEE Transactions on Power
Electronics, vol. 32, no. 6, pp. 4307-4319, June 2017.

10. L. Zhou, F. Gao and T. Xu, “Implementation of Active NPC Circuits in Transformer-Less
Single-Phase Inverter With Low Leakage Current," in IEEE Transactions on Industry Appli-
cations, vol. 53, no. 6, pp. 5658-5667, Nov.-Dec. 2017.

11. M. Eull, L. Zhou, M. Jahnes and M. Preindl, “Bidirectional Nonisolated Fast Charger Inte-
grated in the Electric Vehicle Traction Drivetrain," in IEEE Transactions on Transportation
Electrification, vol. 8, no. 1, pp. 180-195, March 2022.

* * *

12. L. Zhou and M. Preindl, “Modular Model Predictive Control with Regulated Third Harmonic
Injection for Zero-Sequence Stabilized LCL Inverter," in IEEE Transactions on Industry Ap-
plications. (Major revision)

13. L. Zhou and M. Preindl, “Optimization-Based Estimation and Model Predictive Control for
High Performance, Low Cost Software-Defined Power Electronics," in IEEE Transactions on
Power Electronics. (Major revision)

14. J. Nie, L. Zhou, M. Kaye, C. Silveira, A. Nwokolo, X. Jiang and M. Preindl, “High-Performance
Optimal Power Flow Estimation for EV-Interfaced Microgrids with Standardized Grid Ser-
vices," in IEEE Transactions on Industry Applications. (Major revision)

195
8.2.2 International Conferences

1. L. Zhou and M. Preindl, “Integrated Design of Receding Horizon Estimation and Model Pre-
dictive Control for LC-Based Power Module with High Performance and Low Cost," 2022
IEEE Transportation Electrification Conference and Expo (ITEC). (Accepted)

2. L. Zhou and M. Preindl, “Zero Sequence Third Harmonic Injection of Grid Connected Inverter
with Zero Sequence Power Balancing Compensation," 2022 IEEE Transportation Electrifica-
tion Conference and Expo (ITEC). (Accepted)

3. L. Zhou, M. Eull, W. Wang, G. Cen and M. Preindl, “Design of Transformerless Electric Ve-
hicle Charger with Symmetric AC and DC Interfaces," 2021 IEEE Applied Power Electronics
Conference and Exposition (APEC), 2021, pp. 2769-2774

4. L. Zhou and M. Preindl, “Optimal Frequency and Critical Soft Switching Control of DC/DC
Converter," 2019 IEEE Energy Conversion Congress and Exposition (ECCE), 2019, pp. 1536-
1541

5. L. Zhou and M. Preindl, “Three-Phase Transformer-less Hybrid-Bypass Inverter," 2019 IEEE

Energy Conversion Congress and Exposition (ECCE), 2019, pp. 4592-4596

6. L. Zhou and M. Preindl, “Optimal-Frequency Critical Soft Switching Method of Synchronous

DC/DC Converter Based on Model Predictive Control," 2019 IEEE Applied Power Electronics
Conference and Exposition (APEC), 2019, pp. 2989-2994

7. L. Zhou and M. Preindl, “Variable-Frequency Explicit Model Predictive Control of Wide Band
Gap DC/DC Converter with Critical Soft Switching," 2019 IEEE Applied Power Electronics
Conference and Exposition (APEC), 2019, pp. 2995-2999

8. L. Zhou, F. Gao, W. Wang and M. Preindl, “Transformerless Three Phase NPC Inverter with
Reduced Switches," 2018 IEEE Energy Conversion Congress and Exposition (ECCE), 2018,
pp. 4766-4770

196
 9. L. Zhou and M. Preindl, “Bidirectional Transformerless EV Charging System with Low De-
vice Cost and Leakage Current," 2018 IEEE Energy Conversion Congress and Exposition
(ECCE), 2018, pp. 7203-7208

10. L. Zhou and M. Preindl, “Bidirectional Transformerless EV Charging System via Reconfig-
uration of 4×4 Drivetrain," 2018 IEEE Energy Conversion Congress and Exposition (ECCE),
2018, pp. 3923-3927

11. J. Nie, L. Zhou et al., “Optimal Power Flow Estimation of Microgrid Considering the Grid
Services of EV Batteries," 2021 IEEE Transportation Electrification Conference and Expo
(ITEC), 2021, pp. 249-254

12. W. Wang, L. Zhou, M. Eull and M. Preindl, “Comparison of Litz Wire and PCB Inductor De-
signs for Bidirectional Transformerless EV Charger with High Efficiency," 2021 IEEE Trans-
portation Electrification Conference and Expo (ITEC), 2021, pp. 339-346

13. M. Eull, W. Wang, L. Zhou and M. Preindl, “Zero Sequence Voltage Control Enabling Trans-
formerless Electric Vehicle Chargers," 2021 IEEE Transportation Electrification Conference
and Expo (ITEC), 2021, pp. 861-868

14. L. Zhou, F. Gao, G. Shen, T. Xu and W. Wang, “Low leakage current transformerless three-
phase photovoltaic inverter," 2016 IEEE Energy Conversion Congress and Exposition (ECCE),
2016, pp. 1-5

15. W. Wang, F. Gao, L. Zhang, M. Chen and L. Zhou, “Optimal switching counts modulation of
H7 current source inverter," 2016 IEEE Energy Conversion Congress and Exposition (ECCE),
2016, pp. 1-6

16. L. Zhou, F. Gao, C. Jia and T. Xu, “Half bridge NPC inverter and its three phase application
with constant common mode voltage," 2016 IEEE Energy Conversion Congress and Exposi-
tion (ECCE), 2016, pp. 1-6

197
17. L. Zhou, F. Gao, G. Shen and M. Chen, “Highly reliable transformerless neutral point clamped
inverter with separated inductors," 2016 IEEE Energy Conversion Congress and Exposition
(ECCE), 2016, pp. 1-6

18. T. Xu, F. Gao and L. Zhou, “Practical implementation of global synchronous pulse width
modulation with time delay compensation and distributed calculation capabilities," 2016 IEEE
Energy Conversion Congress and Exposition (ECCE), 2016, pp. 1-6

19. L. Zhou and F. Gao, “Low leakage current single-phase PV inverters with universal neutral-
point-clamping method," 2016 IEEE Applied Power Electronics Conference and Exposition
(APEC), 2016, pp. 410-416

20. L. Zhou and F. Gao, “Dual buck inverter with series connected diodes and single inductor,"
2016 IEEE Applied Power Electronics Conference and Exposition (APEC), 2016, pp. 2259-
2263

21. L. Zhou and F. Gao, “Improved transformerless dual buck inverters with buffer inductors,"
2016 IEEE Applied Power Electronics Conference and Exposition (APEC), 2016, pp. 2935-
2941

22. L. Zhou, F. Gao, T. Xu and W. Duan, “Dual Half-Cycle-Bridges Single-Phase Photovoltaic

Inverter," 2015 IEEE Energy Conversion Congress and Exposition (ECCE), 2015, pp. 2490-
2497

23. L. Zhou, F. Gao and T. Yang, “Neutral-point-clamped circuits of single-phase PV inverters:

Generalized principle and implementation," 2015 IEEE Energy Conversion Congress and Ex-
position (ECCE), 2015, pp. 442-449

8.2.3 Patents

1. M. Preindl and L. Zhou. “Methods, systems, and devices for soft switching of power convert-
ers." U.S. Patent Application No. 17/076,133.

198
2. M. Eull, L. Zhou, W. Wang, G. Cen and M. Preindl. “Non-isolated dc fast charger for electri-
fied vehicles." U.S. Patent Application No. 17/173,524.

199
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