PAAVAI COLLEGE OF ENGINEERING
DEPARTMENT OF BIOMEDICAL ENGINEERING
ANNA UNIVERSITY REGULATION – 2021
LESSON PLAN
SUBJECT CODE/ NAME : BM3402 / ANALOG AND DIGITAL
INTEGRATED CIRCUITS
YEAR / SEMESTER : II/IV
DEPARTMENT : BME
BATCH : 2022-2026
UNIT I - INTRODUCTION TO OPERATIONAL AMPLIFIER AND ITS APPLICATIONS
Operational amplifier –ideal characteristics, Performance Parameters, Linear and Nonlinear Circuits and
their analysis- voltage follower, Inverting amplifier, Non-inverting Amplifiers, Differentiator, Integrator,
Voltage to Current converter, Instrumentation amplifier, Low pass, High pass filter and band pass filters,
Comparator, Multivibrator and Schmitt trigger, Triangular wave generator.
Objective: To study the circuit configuration and introduce practical applications of linear integrated
circuits
S.No Time Tentative Teaching
Topics to be covered Ref
. (Minutes) Date Method
1.
Operational amplifier 55 13.03.24(2) T1 CB/L
2. ideal characteristics, Performance
55 14.03.24(7) T1 CB/L
Parameters
3. Linear and Nonlinear Circuits and
55 15.03.24(5) T1 CB/L
their analysis
4.
voltage follower 55 16.03.24(1) T1 CB/L
5. Inverting amplifier, Non-inverting
55 16.03.24(6) T1 CB/L
Amplifiers
6.
Differentiator 55 19.03.24(7) T1 CB/L
7.
Integrator 55 20.03.24(2) T1 CB/L
8.
Voltage to Current converter 55 21.03.24(7) T1 CB/L
9.
Instrumentation amplifier 55 22.03.24(5) T1 CB/L
10. Low pass, High pass filter and band
55 23.03.24(1) T1 PPT/L
pass filters
11.
Multivibrator and Schmitt trigger 55 23.03.24(6) T1 CB/L
12.
Triangular wave generator 55 26.03.24(7) T1 CB/L
UNIT II - DIGITAL TO ANALOG AND ANALOG TO DIGITAL CONVERTERS AND PLL
Analog switches, High speed sample and hold circuit and IC‘s, Types of D/A converter -Weighted
resistor, R-2R ladder DAC, D/A Accuracy and Resolution. A/D converter - Flash, Dual slope,
Successive approximation, A/D Accuracy and Resolution. Voltage controlled oscillator, Voltage to
Frequency converters. PLL-Closed loop analysis of PLL, Frequency multiplication/ division, FSK
demodulator.
OBJECTIVE: To introduce the concept of application of ADC and DAC in real time systems and
Phase Locked Loop with applications.
Time Tentative Teaching
S.No. Topics to be covered Ref
(Minutes) Date Method
Analog switches, High speed
1. sample and hold circuit and 55 27.0324(2) T1 CB/L
IC‘s,Types of D/A converter
Weighted resistor, R-2R ladder
2. 55 28.03.24(7) T1 CB/L
DAC
3. R-2R ladder DAC 55 29.03.24(5) T1 CB/L
4. D/A Accuracy and Resolution 55 30.03.24(1) T1 CB/L
A/D converter - Flash, Dual slope,
5. 55 30.03.24(6) T1 PPT/L
Successive approximation
6. A/D Accuracy and Resolution 55 02.04.24(7) T1 CB/L
Voltage controlled oscillator,
7. 55 03.04.24(2) T1 CB/L
Voltage to Frequency converters
8. PLL-Closed loop analysis of PLL 55 04.04.24(7) T1 PPT/L
Frequency multiplication/ division,
9. 55 05.04.24(5) T1 PPT/L
FSK demodulator
UNIT III THE BASIC GATES ANDCOMBINATIONAL LOGIC CIRCUITS
Number Systems – Decimal, Binary, Octal, Hexadecimal, 1‘s and 2‘s complements, Codes – Binary,
BCD, 84-2-1, 2421, Excess 3, Biquinary, Gray, Alphanumeric codes, Boolean theorems, Logic gates,
Universal gates, Sum of products and product of sums, Minterms and Maxterms, Karnaugh map and
Tabulation methods. Logic families- TTL, MOS, CMOS, BiCMOS - Comparison of Logic families.
OBJECTIVE: To introduce the design of various combinational digital circuits using logic gates.
Time
Tentative Teaching
S.No. Topics To Be Covered (Minutes Ref
Date Method
)
1. Number Systems – Decimal, Binary,
Octal, Hexadecimal, 1‘s and 2‘s 55 06.04.24(1) T2 CB/L
complements, Codes
2. Binary, BCD, 84-2-1, 2421, Excess
55 06.04.24(6) T2 CB/L
3
3. Biquinary, Gray, Alphanumeric
55 09.04.24(7) T2 CB/L
codes
4.
Boolean theorems, Logic gates 55 10.04.24(2) T2 CB/L
5. Universal gates, Sum of products
55 11.04.24(7) T2 CB/L
and product of sums
6. Minterms and Maxterms, Karnaugh
55 12.04.24(5) T2 CB/L
map
7.
Tabulation methods 55 13.04.24(1) T2 CB/L
8.
Logic families- TTL, MOS, CMOS 55 13.04.24(6) T2 PPT/L
9. BiCMOS - Comparison of Logic
55 16.04.24(7) T2 PPT/L
families
UNIT IV COMBINATIONAL LOGIC CIRCUITS
Problem formulation and design of combinational circuits - Code-Converters, Half and Full Adders,
Binary Parallel Adder – Carry look ahead Adder, BCD Adder, Magnitude Comparator, Decoder,
Encoder, Priority Encoder, Mux/Demux.
OBJECTIVE: To bring out the analysis and design procedures for synchronous and asynchronous
sequential circuits
Time Tentative Teaching
S.No Topics To Be Covered Ref
(Minutes) Date Method
1. Problem formulation 55 17.04.24(2) T1 CB/L
2. design of combinational circuits 55 18.04.24(7) T1 CB/L
3. Code-Converters 55 19.04.24(5) T1 CB/L
4. Half and Full Adders 55 20.04.24(1) T1 CB/L
5. Binary Parallel Adder 55 20.04.24(6) T1 CB/L
6. Carry look ahead Adder 55 30.04.24(2) T1 CB/L
7. BCD Adder, Magnitude Comparator
55 02.05.24(7) T1 CB/L
8. Decoder, Encoder 55 03.05.24(5) T1 CB/L
9. Priority Encoder 55 04.05.24(1) T1 CB/L
10. Mux/Demux
55 04.05.24(6) T1 CB/L
UNIT V SEQUENTIAL LOGIC CIRCUITS
Flip flops – SR, JK, T, D, Master/Slave FF, Triggering of FF, Analysis and design of clocked sequential
circuits – state minimization, state assignment, circuit implementation. Counters, Ripple Counters, Ring
Counters. Types of Registers, Serial In - Serial Out, Serial In - Parallel out, Parallel In -Serial Out,
Parallel In - Parallel Out, Universal Shift Register
OBJECTIVE: To bring out the analysis and design procedures for synchronous and asynchronous
sequential circuits
Time Tentative Teaching
S.No Topics To Be Covered Ref
(Minutes) Date Method
1.
Flip flops – SR 55 07.05.24(7) T2 CB/L
2.
JK, T, D, 55 08.05.24(2) T2 CB/L
3.
Master/Slave FF Triggering of FF 55 09.05.24(7) T2 CB/L
4.
Analysis and design of clocked
55 10.05.24(5) T2 CB/L
sequential circuits
5.
State minimization, state
55 11.05.24(1) T2 CB/L
assignment
6.
Counters, Ripple Counters 55 11.05.24(6) T2 CB/L
7.
Ring Counters, 55 14.05.24(7) T2 CB/L
8.
Serial In - Serial Out, Serial In -
55 15.05.24(2) T2 CB/L
Parallel out
9.
Parallel In -Serial Out, Parallel In -
55 16.05.24(7) T2 CB/L
Parallel Out
10.
Universal Shift Register 55 17.05.24(5) T2 CB/L
Course Delivery Plan
Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Re Re Re Re Rev
II,I III,
I I,II II III III IV V V visi visi visi visi isio
II IV
on on on on n
1 2 3 4 5
Units
TEXT BOOKS:
1. Sergio Franco, “Design with operational amplifiers and analog integrated circuits”, Mc Graw
Hill Education, 3rd Edition, 2017
2. John.F.Wakerly, “Digital design principles and practices”, Pearson Education, 5th Edition,
2018
REFERENCES:
1. Taub and Schilling, “Digital Integrated Electronics”, Mc Graw Hill, 2017.
2. Charles H.Roth, Jr, “Fundamentals of Logic Design”, Jaico Books, 7th Edition, 2013.
3. M. Morris Mano and Michael D.Ciletti, “Digital Design”, Pearson, 5th Edition, 2013.
4. S Salivahanan and V S Kanchana Bhaaskaran, Linear Integrated Circuits, McGraw Hill
Education, 3rd Edition, 2018
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