19-0230; Rev 3; 3/11

Calibrated, Quad, 12-Bit

Voltage-Output DACs with Serial Interface
_______________General Description ____________________________Features

MAX536/MAX537
The MAX536/MAX537 combine four 12-bit, voltage-output ♦ Four 12-Bit DACs with Output Buffers
digital-to-analog converters (DACs) and four precision ♦ Simultaneous or Independent Control of Four
output amplifiers in a space-saving 16-pin package. DACs via a 3-Wire Serial Interface
Offset, gain, and linearity are factory calibrated to provide ♦ Power-On Reset
the MAX536’s ±1 LSB total unadjusted error. The ♦ SPI/QSPI and MICROWIRE Compatible
MAX537 operates with ±5V supplies, while the MAX536
uses -5V and +10.8V to +13.2V supplies. ♦ ±1 LSB Total Unadjusted Error (MAX536)
♦ Full 12-Bit Performance without Adjustments
Each DAC has a double-buffered input, organized as
an input register followed by a DAC register. A 16-bit ♦ ±5V Supply Operation (MAX537)
serial word is used to load data into each input/DAC ♦ Double-Buffered Digital Inputs
register. The serial interface is compatible with either ♦ Buffered Voltage Output
SPI/QSPI™ or MICROWIRE™, and allows the input and ♦ 16-Pin DIP/SO Packages
DAC registers to be updated independently or simulta-
neously with a single software command. The DAC reg- ______________ Ordering Information
isters can be simultaneously updated with a hardware
LDAC pin. All logic inputs are TTL/CMOS compatible. PIN- INL
PART TEMP RANGE
PACKAGE (LSB)
________________________Applications MAX536ACPE+ 0°C to +70°C 16 PDIP ±0.5
Industrial Process Controls MAX536BCPE+ 0°C to +70°C 16 PDIP ±1
Automatic Test Equipment MAX536ACWE+ 0°C to +70°C 16 Wide SO ±0.5
Digital Offset and Gain Adjustment MAX536BCWE+ 0°C to +70°C 16 Wide SO ±1

Motion Control Devices MAX536AEPE+ -40°C to +85°C 16 PDIP ±0.5

MAX536BEPE+ -40°C to +85°C 16 PDIP ±1
Remote Industrial Controls
MAX536AEWE+ -40°C to +85°C 16 Wide SO ±0.5
Microprocessor-Controlled Systems
MAX536BEWE+ -40°C to +85°C 16 Wide SO ±1
________________Functional Diagram +Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information continued at end of data sheet.
DGND VDD
SDO LDAC AGND VSS TP REFAB
__________________Pin Configuration
DECODE MAX536/MAX537 TOP VIEW
CONTROL
INPUT DAC OUTA
DAC A +
REG A REG A
OUTB 1 16 OUTC
INPUT DAC OUTB OUTA 2 15 OUTD
REG B REG B DAC B
16-BIT VSS 3 14 VDD
SHIFT MAX536
REGISTER INPUT DAC OUTC AGND 4
MAX537 13 TP
REG C REG C DAC C
REFAB 5 12 REFCD
INPUT DAC OUTD DGND 6
DAC D 11 SDO
REG D REG D
SR LDAC 7 10 SCK
CONTROL
SDI 8 9 CS

CS SCK REFCD
SDI DIP/SO

SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537

ABSOLUTE MAXIMUM RATINGS

VDD to AGND or DGND Continuous Power Dissipation (TA = +70°C)
MAX536 ............................................................-0.3V to +13.2V Plastic DIP (derate 10.53mW/°C above +70°C) .................842mW
MAX537 .................................................................-0.3V to +7V Wide SO (derate 9.52mW/°C above +70°C).................762mW
VSS to AGND or DGND ............................................-7V to +0.3V Operating Temperature Ranges
SDI, SCK , CS, LDAC, TP, SDO MAX53_AC_E/BC_E.............................................0°C to +70°C
to AGND or DGND..................................-0.3V to (VDD + 0.3V) MAX53_AE_E/BE_E ..........................................-40°C to +85°C
REFAB, REFCD to AGND or DGND ..........-0.3V to (VDD + 0.3V) Storage Temperature Range .............................-65°C to +150°C
OUT_ to AGND or DGND ..........................................VDD to VSS Lead Temperature (soldering, 10s) .................................+300°C
Maximum Current into Any Pin............................................50mA Soldering Temperature (reflow) .......................................+260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—MAX536
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE—ANALOG SECTION
Resolution N 12 Bits
MAX536A ±1.0
TA = +25°C
MAX536B ±2.0
MAX536AC ±2.0
Total Unadjusted Error (Note 1) TUE LSB
MAX536BC ±3.0
TA = TMIN to TMAX
MAX536AE ±2.5
MAX536BE ±3.5
MAX536A ±0.15 ±0.50
Integral Nonlinearity INL LSB
MAX536B ±1
Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB
MAX536A ±2.5
TA = +25°C
MAX536B ±5.0
MAX536AC ±5.0
Offset Error mV
MAX536BC ±7.5
TA = TMIN to TMAX
MAX536AE ±6.1
MAX536BE ±8.5
RL = ∞ -0.1 ±1.0
Gain Error MAX536_C/E -0.6 ±1.5 LSB
RL = 5kΩ
MAX536_M ±2.0
VDD Power-Supply Rejection
PSRR TA = +25°C, 10.8V < VDD < 13.2V ±0.02 ±0.125 LSB/V
Ratio
VSS Power-Supply Rejection Ratio PSRR TA = +25°C, -5.5V < VDD < -4.5V ±0.03 ±0.30 LSB/V

2 ____________________________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX536 (continued)

MAX536/MAX537
(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MATCHING PERFORMANCE (TA = +25°C)
MAX536A ±1.0
Total Unadjusted Error TUE LSB
MAX536B ±2.0
Gain Error ±0.1 ±1.0 LSB
MAX536A ±1.2 ±2.5
Offset Error mV
MAX536B ±1.2 ±5.0
Integral Nonlinearity INL ±0.2 ±1.0 LSB
REFERENCE INPUT
Reference Input Range REF 0 VDD - 4 V
Reference Input Resistance RREF Code dependent, minimum at code 555 5 kΩ
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth VREF = 2VP-P 700 kHz
Input code = VREF = 10VP-P at 400Hz -100
Reference Feedthrough dB
all 0s VREF = 10VP-P at 4kHz -82
Total Harmonic Distortion Plus
THD+N VREF = 2.0VP-P at 50kHz 0.024 %
Noise
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Leakage Current VIN = 0V or VDD 1.0 µA
Input Capacitance (Note 2) 10 pF
DIGITAL OUTPUT (SDO)
Output Low Voltage VOL SDO sinking 5mA 0.13 0.40 V
Output Leakage Current SDO = 0V to VDD ±10 µA
DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF)
Voltage Output Slew Rate 5 V/µs
Output Settling Time To ±0.5 LSB of full scale 3 µs
Digital Feedthrough 5 nV-s
Digital Crosstalk (Note 3) VREF = 5V 8 nV-s
POWER SUPPLIES
Positive Supply Range VDD 10.8 13.2 V
Negative Supply Range VSS -4.5 -5.5 V
Positive Supply Current TA = +25°C 8 18
IDD mA
(Note 4) TA = TMIN to TMAX 25
Negative Supply Current TA = +25°C -6 -16
ISS mA
(Note 4) TA = TMIN to TMAX -23

_______________________________________________________________________________________ 3
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX536 (continued)
MAX536/MAX537

(VDD = +12V, VSS = -5V, REFAB/REFCD = 8V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset
tPOR 20 µs
Pulse Width (Note 2)
SCK Clock Period tCP 100 ns
SCK Pulse Width High tCH 30 ns
SCK Pulse Width Low tCL 30 ns
CS Fall to SCK Rise
tCSS 20 ns
Setup Time
SCK Rise to CS Rise
tCSH 10 ns
Hold Time
SDI Setup Time tDS 40 26 ns
SDI Hold Time tDH 0 ns
SCK Rise to SDO Valid 1kΩ pullup on SDO SDO high 78 105
tDO1 ns
Propagation Delay (Note 6) to VDD, CLOAD = 50pF SDO low 50 80
SCK Fall to SDO Valid 1kΩ pullup on SDO SDO high 81 110
tDO2 ns
Propagation Delay (Note 7) to VDD, CLOAD = 50pF SDO low 53 85
CS Fall to SDO Enable
tDV 27 45 ns
(Note 8)
CS Rise to SDO Disable
tTR 40 60 ns
(Note 9)
SCK Rise to CS Fall Delay tCS0 Continuous SCK, SCK edge ignored 20 ns
CS Rise to SCK Rise
tCS1 SCK edge ignored 20 ns
Hold Time
LDAC Pulse Width Low tLDAC 30 ns
CS Pulse Width High tCSW 40 ns

Note 1: TUE is specified with no resistive load.

Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
Note 5: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 8: SDO changes from High-Z state to 90% of final value.
Note 9: SDO rises 10% toward High-Z state.

4 _______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS—MAX537

MAX536/MAX537
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

STATIC PERFORMANCE—ANALOG SECTION
Resolution N 12 Bits
MAX537A ±0.15 ±0.50
Integral Nonlinearity INL LSB
MAX537B ±1
Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB
MAX537A ±3.0
TA = +25°C
MAX537B ±6.0
MAX537AC ±6.0
Offset Error mV
MAX537BC ±9.0
TA = TMIN to TMAX
MAX537AE ±7.0
MAX537BE ±11.0
RL = ∞ -0.3 ±1.5
Gain Error LSB
RL = 5kΩ -0.8 ±3.0
VDD Power-Supply Rejection Ratio PSRR TA = +25°C, 4.5V ≤ VDD ≤ 5.5V ±0.01 ±0.5 LSB/V
VSS Power-Supply Rejection Ratio PSRR TA = +25°C, -5.5V ≤ VSS ≤ -4.5V ±0.02 ±0.7 LSB/V
MATCHING PERFORMANCE (TA = +25°C)
Gain Error ±0.1 ±1.25 LSB
MAX537A ±0.3 ±3.0
Offset Error mV
MAX537B ±0.3 ±6.0
Integral Nonlinearity INL ±0.35 ±1.0 LSB
REFERENCE INPUT
Reference Input Range REF 0 VDD - 2.2 V
Reference Input Resistance RREF Code dependent, minimum at code 555 hex 5 kΩ
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth VREF = 2VP-P 700 kHz
VREF = 10VP-P at
-100
400Hz
Reference Feedthrough Input code = all 0s dB
VREF = 10VP-P at
-82
4kHz
Total Harmonic Distortion Plus
THD+N VREF = 850mVP-P at 100kHz 0.024 %
Noise
DIGITAL INPUTS (SDI, SCK, CS, LDAC)
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.8 V
Input Leakage Current VIN = 0V or VDD 1.0 µA
Input Capacitance (Note 2) 10 pF

_______________________________________________________________________________________ 5
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537

ELECTRICAL CHARACTERISTICS—MAX537 (continued)

(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL OUTPUT (SDO)
VDD - VDD -
Output High Voltage VOH SDO sourcing 2mA V
0.5 0.25
Output Low Voltage VOL SDO sinking 2mA 0.13 0.40 V
DYNAMIC PERFORMANCE (RL = 5kΩ, CL = 100pF)
Voltage Output Slew Rate 5 V/µs
Output Settling Time To ±0.5 LSB of full scale 5 µs
Digital Feedthrough 5 nV-s
Digital Crosstalk (Note 3) 5 nV-s
POWER SUPPLIES
Positive Supply Range VDD 4.5 5.5 V
Negative Supply Range VSS -4.5 -5.5 V
TA = +25°C 5.5 12
Positive Supply Current (Note 4) IDD mA
TA = TMIN to TMAX 16
TA = +25°C -4.7 -10
Negative Supply Current (Note 4) ISS mA
TA = TMIN to TMAX -14
TIMING CHARACTERISTICS (Note 5)
Internal Power-On Reset Pulse
tPOR 50 µs
Width (Note 2)
SCK Clock Period tCP 100 ns
SCK Pulse Width High tCH MAX537_C/E 35 ns
SCK Pulse Width Low tCL MAX537_C/E 35 ns
CS Fall to SCK Rise Setup Time tCSS MAX537_C/E 40 ns
SCK Rise to CS Rise Hold Time tCSH 0 ns
SDI Setup Time tDS MAX537_C/E 40 24 ns
SDI Hold Time tDH 0 ns
SCK Rise to SDO Valid
tDO1 CLOAD = 50pF, MAX537_C/E 116 200 ns
Propagation Delay (Note 6)
SCK Fall To SDO Valid
tDO2 CLOAD = 50pF, MAX537_C/E 123 210 ns
Propagation Delay (Note 7)

6 _______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface

MAX536/MAX537
ELECTRICAL CHARACTERISTICS—MAX537 (continued)
(VDD = +5V, VSS = -5V, REFAB/REFCD = 2.5V, AGND = DGND = 0V, RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CS Fall to SDO Enable tDV CLOAD = 50pF, MAX537_C/E 75 140 ns
CS Rise to DSO Disable (Note 10) tTR CLOAD = 50pF, MAX537_C/E 70 130 ns
SCK Rise to CS Fall Delay tCSO Continuous SCK, SCK edge ignored 35 ns
CS Rise to SCK Rise Hold Time tCS1 SCK edge ignored, MAX537_C/E 35 ns
LDAC Pulse Width High tLDAC MAX537_C/E 50 ns
CS Pulse Width High tCSW MAX537_C/E 100 ns
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC.
Note 4: Digital inputs at 2.4V; with digital inputs at CMOS levels, IDD decreases slightly.
Note 5: All input signals are specified with tR = tF ≤ 5ns. Logic input swing is 0 to 5V.
Note 6: Serial data clocked out of SDO on SCK’s falling edge. (SDO is an open-drain output for the MAX536. The MAX537’s SDO
pin has an internal active pullup.)
Note 7: Serial data clocked out of SDO on SCK’s rising edge.
Note 10: When disabled, SDO is internally pulled high.

_______________________________________________________________________________________ 7
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537

__________________________________________Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)
MAX536
MAX536 MAX536 MAX536
INTEGRAL NONLINEARITY REFERENCE VOLTAGE INPUT TOTAL HARMONIC DISTORTION PLUS NOISE
ERROR vs. REFERENCE VOLTAGE FREQUENCY RESPONSE vs. REFERENCE FREQUENCY
1.0 0.200
MAX536/7-01
20

MAX1536/7-03
MAX536/7-02
VSS = -5V REFAB SWEPT 2VP-P DAC CODE = ALL 1s
VOUTA MONITORED 0.175 REFAB = 10VP-P
10
0.6
RELATIVE OUTPUT (dB) 0.150
0 RL = 10kΩ, CL = 100pF

THD + NOISE (%)

INL ERROR (LSB)

0.2 VDD = +15V 0.125

-10
0.100
RL = NO LOAD, CL = 0pF
-0.2 -20
VDD = +12V 0.075
-30
0.050
--0.6
-40 0.025
-1.0 -50 0
0 4 8 12 16 1k 10k 100k 1M 10M 10 100 200
REFERENCE VOLTAGE (V) FREQUENCY (Hz) FREQUENCY (kHz)

MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE MAX536
MAX536
vs. REFERENCE FREQUENCY SUPPLY CURRENT vs. TEMPERATURE
FULL-SCALE ERROR vs. LOAD
0.200 1 10
MAX1536/7-03b

MAX536/7-05
MAX536/7-04

DAC CODE = ALL 1s

0.175 REFAB = 5VP-P 0 6 IDD
FULL-SCALE ERROR (LSB)

0.150 VDD = +15V

SUPPLY CURRENT (mA)

-1
THD + NOISE (%)

VSS = -5V
0.125 2

0.100 RL = 10kΩ, CL = 100pF -2

-2
0.075
-3
RL = NO LOAD, CL = 0pF ISS
0.050
-6
-4
0.025

0 -5 -10
10 100 200 0.1 1 10 100 1000 -60 -20 20 60 100 140
FREQUENCY (kHz) LOAD (kΩ) TEMPERATURE (°C)

MAX536 MAX536
REFERENCE FEEDTHROUGH AT 400Hz REFERENCE FEEDTHROUGH AT 4kHz

REFAB, REFAB,
5V/div 5V/div
0V 0V

OUTA, OUTA,
100µV/div 200µV/div

500µs/div 50µs/div
INPUT CODE = ALL 0s INPUT CODE = ALL 0s

8 _______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)

MAX536/MAX537
(TA = +25°C, unless otherwise noted.)

MAX536 MAX536
MAX536 NEGATIVE FULL-SCALE SETTLING TIME
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) (ALL BITS ON TO ALL BITS OFF)

CS,
5V/div
CS,
5V/div

OUTA,
5V/div

OUTA,
2V/div OUTA,
5mV/div

5µs/div 1µs/div
VDD = +15V, VSS = -5V, REFAB = 5V, CL = 100pF, RL = 10kΩ VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ

MAX536
POSITIVE FULL-SCALE SETTLING TIME MAX536
(ALL BITS OFF TO ALL BITS ON) DIGITAL FEEDTHROUGH

CS,
5V/div SCK,
5V/div
OUTA,
5V/div

OUTA, OUTA,
-10V OFFSET AC-COUPLED,
5mV/div
10mV/div

1µs/div
VDD = +15V, VSS = -5V, REFAB = 10V, CL = 100pF, RL = 10kΩ VDD = +15V, VSS = -5V, REFAB = 10V, CS = HIGH,
DIN TOGGLING AT 1⁄2 THE CLOCK RATE,
OUTA = 5V

_______________________________________________________________________________________ 9
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537

____________________________Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)
MAX537
MAX537 MAX537 MAX537
INTEGRAL NONLINEARITY REFERENCE VOLTAGE INPUT TOTAL HARMONIC DISTORTION PLUS NOISE
ERROR vs. REFERENCE VOLTAGE FREQUENCY RESPONSE vs. FREQUENCY
2.0 20 0.200
MAX536/7-06

MAX536/7-07

MAX1536/7-14
REFAB SWEPT 2VP-P REFAB = 2.5VP-P
VDD = +5V
1.5 10 VOUTA MONITORED 0.175
VSS = -5V
1.0 0.150
RELATIVE OUTPUT (dB)
0

THD + NOISE (%)

INL ERROR (LSB)

0.5 0.125
-10 RL = 10kΩ, CL = 100pF
0 0.100
-20
-0.5 0.075
-30 RL = NO LOAD, CL = 0pF
-1.0 0.050
-1.5 -40 0.025
-2.0 -50 0
0 1 2 3 4 5 1k 10k 100k 1M 10M 10 100 200
VREF (V) FREQUENCY (Hz) FREQUENCY (kHz)

MAX537
MAX537 MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
FULL-SCALE ERROR vs. LOAD SUPPLY CURRENT vs. TEMPERATURE
vs. FREQUENCY
0.200 2 5

MAX536/7-11
MAX536/7-10
MAX1536/7-09

0.175 REFAB = 1VP-P

1
3 IDD
FULL-SCALE ERROR (LSB)

0.150 VDD = +5V

SUPPLY CURRENT (mA)

0
THD + NOISE (%)

VSS = -5V
0.125 1

0.100 -1
RL = 10kΩ, CL = 100pF -1
0.075 -2
ISS
0.050
-3 -3
0.025
RL = NO LOAD, CL = 0pF
-4 -5
0
10 100 200 0.1 1 10 100 1000 -60 -20 20 60 100 140
FREQUENCY (kHz) LOAD (kΩ) TEMPERATURE (°C)
MAX537 MAX537
REFERENCE FEEDTHROUGH AT 400Hz REFERENCE FEEDTHROUGH AT 4kHz

REFAB,
REFAB,
1V/div
1V/div
0V 0V

OUTA, OUTA,
AC-COUPLED, AC-COUPLED,
100µV/div 100µV/div

500µs/div 50µs/div
INPUT CODE = ALL 0s INPUT CODE = ALL 0s

10 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)

MAX536/MAX537
(TA = +25°C, unless otherwise noted.)

MAX537
MAX537
MAX537 NEGATIVE FULL-SCALE SETTLING TIME
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON) (ALL BITS ON TO ALL BITS OFF)

CS,
CS, 5V/div
5V/div

OUTA,
5mV/div
OUTA,
1V/div

5µs/div 1µs/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ

MAX537
POSITIVE FULL-SCALE SETTLING TIME MAX537
(ALL BITS OFF TO ALL BITS ON) DIGITAL FEEDTHROUGH

CS, SCK,
5V/div 5V/div

OUTA, OUTA,
5mV/div AC-COUPLED,
20mV/div

1µs/div 100ns/div
VDD = +5V, VSS = -5V, REFAB = 2.5V, CL = 100pF, RL = 10kΩ VDD = +5V, VSS = -5V, REFAB = 2.5V, CS = HIGH,
DIN TOGGLING AT 1⁄2 THE CLOCK RATE,
OUTA = 1.25V

______________________________________________________________________________________ 11
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________Pin Description
MAX536/MAX537

PIN NAME FUNCTION

1 OUTB DAC B Output Voltage
2 OUTA DAC A Output Voltage
3 VSS Negative Power Supply
4 AGND Analog Ground
5 REFAB Reference Voltage Input for DAC A and DAC B
6 DGND Digital Ground
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of all input
7 LDAC
registers to their respective DAC registers.
8 SDI Serial Data Input. Data is shifted into an internal 16-bit shift register on SCK's rising edge.
Chip-Select Input (active low). A low level on CS enables the input shift register and SDO.
9 CS
On CS’s rising edge, data is latched into the appropriate register(s).
10 SCK Shift Register Clock Input
Serial Data Output. SDO is the output of the internal shift register. SDO is enabled when CS is low.
11 SDO
For the MAX536, SDO is an open-drain output. For the MAX537, SDO has an active pullup to VDD.
12 REFCD Reference Voltage Input for DAC C and DAC D
13 TP Test Pin. Connect to VDD for proper operation.
14 VDD Positive Power Supply
15 OUTD DAC D Output Voltage
16 OUTC DAC C Output Voltage

_______________Detailed Description
The MAX536/MAX537 contain four 12-bit voltage-output
DACs that are easily addressed using a simple 3-wire R R R
VOUT
serial interface. They include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register 2R 2R 2R 2R 2R
(see the Functional Diagram on the front page).
D0 D9 D10 D11
The DACs are “inverted” R-2R ladder networks that
convert 12-bit digital inputs into equivalent analog out-
put voltages in proportion to the applied reference-volt-
age inputs. DAC A and DAC B share the REFAB refer- REF

ence input, while DAC C and DAC D share the REFCD

AGND
reference input. The two reference inputs allow different
full-scale output voltage ranges for each pair of DACs.
Figure 1 shows a simplified circuit diagram of one of SHOWN FOR ALL 1s ON DAC
the four DACs.
Figure 1. Simplified DAC Circuit Diagram
Reference Inputs
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets a digitally programmable voltage source as:
the full-scale output voltage for its two correspond- VOUT_ = NB (VREF)/4096
ing DACs. The REFAB/REFCD voltage range is 0V to
where NB is the numeric value of the DAC’s binary input
(VDD - 4V) for the MAX536 and 0V to (VDD - 2.2V) for the
code (0 to 4095) and VREF is the reference voltage.
MAX537. The output voltages VOUT_ are represented by

12 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
The input impedance at each reference input is code is 5µs when loaded with 5kΩ in parallel with 100pF

MAX536/MAX537
dependent, ranging from a low value of typically 6kΩ (loads less than 5kΩ degrade performance).
(with an input code of 0101 0101 0101) to a high value Output dynamic responses and settling performances
of 60kΩ (with an input code of 0000 0000 0000). Since of the MAX536/MAX537 output amplifier are shown in
the input impedance at the reference pins is code the Typical Operating Characteristics.
dependent, load regulation of the reference source is
important. Serial-Interface Configurations
The REFAB and REFCD reference inputs have a 5kΩ The MAX536/MAX537’s 3-wire or 4-wire serial interface is
guaranteed minimum input impedance. When the two compatible with both MICROWIRE (Figure 2) and
reference inputs are driven from the same source, the SPI/QSPI (Figure 3). In Figures 2 and 3, LDAC can be tied
effective minimum impedance becomes 2.5kΩ. either high or low for a 3-wire interface, or used as the
fourth input with a 4-wire interface. The connection
The reference input capacitance is also code depen- between SDO and the serial-interface port is not neces-
dent and typically ranges from 125pF to 300pF. sary, but may be used for data echo. (Data held in the
shift register of the MAX536/MAX537 can be shifted out
Output Buffer Amplifiers
of SDO and returned to the microprocessor for data veri-
All MAX536/MAX537 voltage outputs are internally
fication; data in the MAX536/MAX537 input/DAC regis-
buffered by precision unity-gain followers with a typical
ters cannot be read.)
slew rate of 5V/µs for the MAX536 and 3V/µs for the
MAX537. With a 3-wire interface (CS, SCK, SDI) and LDAC tied
high, the DACs are double-buffered. In this mode,
With a full-scale transition at the MAX536 output (0 to
depending on the command issued through the serial
8V or 8V to 0), the typical settling time to ±0.5 LSB is
interface, the input register(s) may be loaded
3µs when loaded with 5kΩ in parallel with 100pF (loads
without affecting the DAC register(s), the DAC register(s)
less than 5kΩ degrade performance).
can be loaded directly, or all four DAC registers may be
With a full-scale transition at the MAX537 output (0 to simultaneously updated from the input registers. With a 3-
2.5V or 2.5V to 0), the typical settling time to ±0.5 LSB wire interface (CS, SCK, SDI) and LDAC tied low (Figure

5V
5V
†RP †RP
1kΩ 1kΩ

SDO* MISO* SS
SCK SK

SDI MOSI
SDI SO

MAX536 MAX536 SCK SCK SPI/QSPI

SDO* SI* MICROWIRE PORT
MAX537 PORT MAX537

CS I/O
CS I/O

LDAC** I/O
LDAC** I/O
CPOL = 0, CPHA = 0
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES. *THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
†THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
†THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO VDD,
SO RP IS NOT NECESSARY.
SO RP IS NOT NECESSARY.

Figure 2. Connections for MICROWIRE Figure 3. Connections for SPI/QSPI

_______________________________________________________________________________________ 13
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface

;;; ;;
MAX536/MAX537

CS

COMMAND
EXECUTED
SCK
1 8 9 16

SDI
D15 D14 D13.......... ..........D2 D1 D0
MSB LSB

SDO
Q15.......... ...........Q0
MSB FROM LSB FROM
PREVIOUS WRITE PREVIOUS WRITE

; ;;;;
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or VDD)

CS

INPUT REGISTER(S)
UPDATED
SCK
1 8 9 16

SDI
D15 D14 D13 .......... .......... D2 D1 D0
MSB LSB

SDO
Q15.......... .......... Q0
MSB FROM LSB FROM
PREVIOUS WRITE PREVIOUS WRITE
LDAC

DACs
UPDATED

Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC

CS tCSW

tCSS tCH tCP tCSH

tCSO tCL tCSI

SCK
tDS
tDH

SDI

tDV tDO2 tTR

tDO1
SDO

LDAC*

*USE OF LDAC IS OPTIONAL tLDAC

Figure 6. Detailed Serial-Interface Timing Diagram

14 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
4), the DAC registers remain transparent. Any time an Interface timing is optimized when serial data is clocked out

MAX536/MAX537
input register is updated, the change appears at the DAC of the microcontroller/microprocessor on one clock edge
output with the rising edge of CS. and clocked into the MAX536/MAX537 on the other edge.
The 4-wire interface (CS, SCK, SDI, LDAC) is similar to Table 1 lists the serial-interface programming commands.
the 3-wire interface with LDAC tied high, except LDAC is For certain commands, the 12 data bits are “don’t cares”.
a hardware input that simultaneously and asynchronously The programming command Load-All-DACs-From-Shift-
loads all DAC registers from their respective input regis- Register allows all input and DAC registers to be simultane-
ters when driven low (Figure 5). ously loaded with the same digital code from the input shift
register. The NOP (no operation) command allows the regis-
Serial-Interface Description ter contents to be unaffected and is useful when the
The MAX536/MAX537 require 16 bits of serial data. Data is MAX536/MAX537 are configured in a daisy-chain (see the
sent MSB first and can be sent in two 8-bit packets or one Daisy-Chaining Devices section). The command to change
16-bit word (CS must remain low until 16 bits are trans- the clock edge on which serial data is shifted out of the
ferred). The serial data is composed of two DAC address MAX536/MAX537 SDO pin also loads data from all input reg-
bits (A1, A0), two control bits (C1, C0), and the 12 data bits isters to their respective DAC registers.
D11…D0 (Figure 7). The 4-bit address/control code deter-
mines the following: 1) the register(s) to be updated and/or Serial-Data Output
the status of the input and DAC registers (i.e., whether they The serial-data output, SDO, is the internal shift register’s
are in transparent or latch mode), and 2) the edge on which output. The MAX536/MAX537 can be programmed so that
data is clocked out of SDO. data is clocked out of SDO on SCK’s rising (Mode 1) or
Figure 6 shows the serial-interface timing requirements. The falling (Mode 0) edge . In Mode 0, output data at SDO lags
chip-select pin (CS) must be low to enable the DAC’s serial input data at SDI by 16.5 clock cycles, maintaining compati-
interface. When CS is high, the interface control circuitry is bility with MICROWIRE, SPI/QSPI, and other serial interfaces.
disabled and the serial data output pin (SDO) is driven high In Mode 1, output data lags input data by 16 clock cycles.
(MAX537) or is a high-impedance open drain (MAX536). CS On power-up, SDO defaults to Mode 1 timing.
must go low at least tCSS before the rising serial clock (SCK) For the MAX536, SDO is an open-drain output that should be
edge to properly clock in the first bit. When CS is low, data is pulled up to +5V. The data sheet timing specifications for
clocked into the internal shift register via the serial data input SDO use a 1kΩ pullup resistor. For the MAX537, SDO is a
pin (SDI) on SCK’s rising edge. The maximum guaranteed complementary output and does not require an external
clock frequency is 10MHz. Data is latched into the appropri- pullup.
ate MAX536/MAX537 input/DAC registers on CS’s rising Test Pin
edge. The test pin (TP) is used for pre-production analysis of the IC.
Connect TP to VDD for proper MAX536/MAX537 operation.
MSB ..................................................................................LSB
Failure to do so affects DAC operation.
16 Bits of Serial Data
Daisy-Chaining Devices
Address Control Data Bits Any number of MAX536/MAX537s can be daisy-chained by
Bits Bits MSB.............................................LSB connecting the SDO pin of one device (with a pullup resistor,
A1 A0 C1 C0 D11................................................D0 if appropriate) to the SDI pin of the following device in the
chain (Figure 8).
4 Address/
12 Data Bits Since the MAX537’s SDO pin has an internal active pullup,
Control Bits
the SDO sink/source capability determines the time required
Figure 7. Serial-Data Format (MSB Sent First) to discharge/charge a capacitive load. Refer to the serial
data out V OH and V OL specifications in the Electrical
Characteristics.

______________________________________________________________________________________ 15
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
MAX536/MAX537

Table 1. Serial-Interface Programming Commands

16-BIT SERIAL WORD
LDAC FUNCTION
A1 A0 C1 C0 D11…D0
0 0 0 1 12-bit DAC data 1 Load DAC A input register; DAC output unchanged.
0 1 0 1 12-bit DAC data 1 Load DAC B input register; DAC output unchanged.
1 0 0 1 12-bit DAC data 1 Load DAC C input register; DAC output unchanged.
1 1 0 1 12-bit DAC data 1 Load DAC D input register; DAC output unchanged.
0 0 1 1 12-bit DAC data 1 Load input register A; all DAC registers updated.
0 1 1 1 12-bit DAC data 1 Load input register B; all DAC registers updated.
1 0 1 1 12-bit DAC data 1 Load input register C; all DAC registers updated.
1 1 1 1 12-bit DAC data 1 Load input register D; all DAC registers updated.
X 0 0 0 12-bit DAC data X Load all DACs from shift register.
X 1 0 0 XXXXXXXXXXXX X No operation (NOP)
0 X 1 0 XXXXXXXXXXXX 1 Update all DACs from their respective input registers.
Mode 1 (default condition at power-up), DOUT clocked out on
1 1 1 0 XXXXXXXXXXXX X SCK’s rising edge. All DACs updated from their respective
input registers.
Mode 0, DOUT clocked out on SCK’s falling edge. All DACs
1 0 1 0 XXXXXXXXXXXX X
updated from their respective input registers.
0 0 X 1 12-bit DAC data 0 Load DAC A input register; DAC A is immediately updated.
0 1 X 1 12-bit DAC data 0 Load DAC B input register; DAC B is immediately updated.
1 0 X 1 12-bit DAC data 0 Load DAC C input register; DAC C is immediately updated.
1 1 X 1 12-bit DAC data 0 Load DAC D input register; DAC D is immediately updated.

“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.

When daisy-chaining MAX536s, the delay from CS Additionally, when daisy-chaining devices, the maximum
low to SCK high (tCSS) must be the greater of: clock frequency is limited to:
tDV + tDS 1
fSCK(max) = ——————————————
or 2 (tDO + tRC - 38ns + tDS)
tTR + tRC + tDS - tCSW
For example, with t RC = 23ns (5V ±10% supply with
where tRC is the time constant of the external pullup resistor Rp = 1kΩ and C = 30pF), the maximum clock frequency is
(Rp) and the load capacitance (C) at SDO. For tRC < 20ns, 8.7MHz.
tCSS is simply tDV + tDS. Calculate tRC from the following
Figure 9 shows an alternate method of connecting several
equation:
MAX536/MAX537s. In this configuration, the data bus is
tRC = Rp (C) ln
[( VPULLUP
VPULLUP - 2.4V )] common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
where VPULLUP is the voltage to which the pullup resistor is
connected. required for each IC.

16 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface

MAX536/MAX537
+5V +5V +5V

RP* RP* RP*

1kΩ 1kΩ 1kΩ
MAX536 MAX536 MAX536
SCK SCK MAX537 SCK MAX537 SCK MAX537

DIN SDI SDO SDI SDO SDI SDO

CS CS CS CS

TO OTHER
SERIAL DEVICES

* THE MAX537 HAS AN ACTIVE INTERNAL PULLUP, SO RP IS NOT NECESSARY.

Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface

DIN

SCK

LDAC

CS1

CS2 TO OTHER
SERIAL DEVICES
CS3

CS CS CS

LDAC LDAC LDAC

MAX536 MAX536 MAX536

SCK MAX537 SCK MAX537 SCK MAX537

SDI SDI SDI

Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are
driven separately, thus controlling which data are written to devices 1, 2, 3…

______________________________________________________________________________________ 17
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
__________Applications Information Bits 6 and 7 are not used. Writes to these bits are ignored.
MAX536/MAX537

The PORT D Data Direction Register (DDRD) deter-

Interfacing to the M68HC11*
mines whether the port bits are inputs or outputs. Its
PORT D of the 68HC11 supports SPI. The four registers
configuration is shown below:
used for SPI operation are the Serial Peripheral Control
Register, the Serial Peripheral Status Register, the Serial BIT
Peripheral Data I/O Register, and PORT D’s Data Direction 7 6 5 4 3 2 1 0
Register. These registers have a default starting location of NAME
$1000. – – DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose Setting DDD_ = 0 configures the port bit as an input, while
inputs. Setting bit 6 (SPE) of the Serial Peripheral Control setting DDD_ = 1 configures the port bit as an output. Writes
Register (SPCR) configures PORT D for SPI as follows: to bits 6 and 7 have no effect.
BIT In SPI mode with MSTR = 1, when a PORT D bit is expected
7 6 5 4 3 2 1 0 to be an input (SS, MISO, RXD), the corresponding DDRD bit
NAME (DDD_) is ignored. If the bit is expected to be an output
– – SS SCK MOSI MISO TXD RXD (SCK, MOSI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.

Table 2. Serial Peripheral Control-Register Definitions

NAME DEFINITION
Serial Peripheral Interrupt Enable. Clearing SPIE disables the SPI hardware-interrupt request; the SPSR is polled to
SPIE determine when an SPI data transfer is complete. Setting SPIE requests a hardware interrupt when the Serial Peripheral
Status Register’s SPIF bit or MODF bit is set.
Setting SPE (Serial Peripheral System Enable) configures PORT D for SPI. Clearing SPE configures the port as a general-
SPE
purpose I/O port.
DWOM When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
MSTR Master/Slave select option
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
CPOL
clock idles low.
CPHA Determines the clock phase.
SPI Clock-Rate Select
SPR1 SPR0
0 0 µP clock divided by 2
SPR1/0
0 1 µP clock divided by 4
1 0 µP clock divided by 16
1 1 µP clock divided by 32

Table 3. Serial Peripheral Status-Register Definitions

NAME DEFINITION
SPIF SPIF is set when an SPI data transfer is complete. It is cleared by reading the SPSR and then accessing the SPDR.
The Write Collision flag is set when a write to the SPDR occurs while a data transfer is in progress. It is cleared by read-
WCOL
ing the SPSR and then accessing the SPDR.

The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
MODF
has its SS line (PORT D) pulled low, and cleared by reading the SPSR followed by a write to the SPCR.

*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.

18 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface

MAX536/MAX537
Table 4. M68HC11 Programming Code

______________________________________________________________________________________ 19
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
SS is an input intended for use in a multimaster environ- Unipolar Output
MAX536/MAX537

ment. However, SS or unused PORT D bit RXD, TXD, or For a unipolar output, the output voltages and the reference
possibly MISO (if DAC readback is not used) should be inputs are the same polarity. Figure 10 shows the
configured as a general-purpose output and used as CS by MAX536/MAX537 unipolar output circuit, which is also the typ-
setting the appropriate Data Direction Register bit. ical operating circuit. Table 5 lists the unipolar output codes.
The SPCR configuration (memory location $1028) is shown Bipolar Output
below: The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
BIT
and two resistors are required per DAC. With R1 = R2:
7 6 5 4 3 2 1 0
NAME VOUT = VREF [(2NB/4096) - 1]
SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 where NB is the numeric value of the DAC’s binary input
SETTING AFTER RESET code. Table 6 shows digital codes and corresponding
0 0 0 0 0 1 U* U* output voltages for Figure 11’s circuit.
SETTING FOR TYPICAL SPI COMMUNICATION Table 5. Unipolar Code Table
0 1 0 1 0 0 0** 1**
DAC CONTENTS
*U = Unknown ANALOG OUTPUT
MSB LSB
**Depends on µP clock frequency.
4095
Always configure the 68HC11 as the “master” controller 1111 1111 1111 +VREF ( ——— )
4096
and the MAX536/MAX537 as the “slave” device.
2049
When MSTR = 1 in the SPCR, a write to the Serial 1000 0000 0001 +VREF ( ——— )
4096
Peripheral Data I/O Register (SPDR), located at memory
location $102A, initiates the transmission/reception of 1000 0000 0000
2048 +VREF
+VREF ( ——— ) = ————
data. The data transfer is monitored and the appropri- 4096 2
ate flags are set in the Serial Peripheral Status
Register (SPSR). 2047
0111 1111 1111 +VREF ( ——— )
4096
The SPSR configuration is shown below:
1
BIT 0000 0000 0001 +VREF ( ——— )
7 6 5 4 3 2 1 0 4096
NAME 0000 0000 0000 0V
SPIF WCOL – MODF – – – –
RESET CONDITIONS Table 6. Bipolar Code Table
0 0 0 0 0 0 0 0
DAC CONTENTS
ANALOG OUTPUT
An example of 68HC11 programming code for a MSB LSB
two-byte SPI transfer to the MAX536/MAX537 is given in 1111 1111 1111 2047 )
+VREF ( ———
Table 4. SS is used for CS, the high byte of MAX536/ 2048
MAX537 digital data is stored in memory location $0100,
1 )
and the low byte is stored in memory location $0101. 1000 0000 0001 +VREF ( ———
2048
Interfacing to Other Controllers 1000 0000 0000 0V
When using MICROWIRE, refer to the section on Inter- 1 )
0111 1111 1111 -VREF ( ———
facing to the M68HC11 for guidance, since MICROWIRE 2048
can be considered similar to SPI when CPOL = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31 2047 )
0000 0000 0001 -VREF ( ———
2048
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Bit- 2048 ) = -V
0000 0000 0000 -VREF ( ——— REF
pushing involves arbitrarily assigning I/O port bits as 2048
interface control lines, and then writing to the port each
time a signal transition is required. 1
NOTE: 1 LSB = (VREF) (
4096
)
20 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface

MAX536/MAX537
+12V (+5V)
REFERENCE INPUTS
MAX536 5 12 14 13
MAX537 MAX536
REFAB REFCD VDD TP
MAX537
R1 R2
DAC A 2
OUTA VREF

+12V (+5V)

1
DAC B OUTB

VOUT

16 DAC
DAC C OUTC OUTPUT

–5V

15 R1 = R2 = 10kΩ 0.1%
DAC D OUTD

VSS AGND DGND

3 4 6 NOTES: ( ) ARE FOR MAX537.
-5V VREF IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537.
NOTE: ( ) ARE FOR MAX537.

Figure 10. Unipolar Output Circuit Figure 11. Bipolar Output Circuit

+12V
(+5V) +12V (+5V)

AC 15kΩ
REFERENCE 5 13 14
INPUT
REFAB TP VDD
+4V (+750mV)
5 13 14 +
10kΩ REFAB TP VDD VIN
-4V
DAC A 2
(-750mV) - OUTA

DAC B 1
OUTB
AGND MAX536/MAX537
4
MAX536/MAX537 + VSS DGND
VSS AGND DGND VBIAS
3 6
3 4 6 -
-5V
-5V

NOTES: ( ) ARE FOR MAX537.

NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
DIGITAL INPUTS NOT SHOWN.

Figure 12. AC Reference Input Circuit Figure 13. AGND Bias Circuit

______________________________________________________________________________________ 21
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Offsetting AGND
MAX536/MAX537

AGND can be biased from DGND to the reference voltage

to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage VOUTA is:
3 VOUTA = VBIAS + NB (VIN)
VSS
where VBIAS is the positive offset voltage (with respect
to DGND) applied to AGND, and NB is the numeric
MAX536 value of the DAC’s binary input code. Since AGND is
1N5817 MAX537 common to all four DACs, all outputs will be offset by
VBIAS in the same manner. As the voltage at AGND
4
increases, the DAC’s resolution decreases because its
AGND full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
Power-Supply Considerations
On power-up, VSS should come up first, VDD next, then
REFAB or REFCD. If supply sequencing is not possible,
tie an external Schottky diode between VSS and AGND
Figure 14. When VSS and VDD cannot be sequenced, tie a as shown in Figure 14. On power-up, all input and DAC
Schottky diode between VSS and AGND. registers are cleared (set to zero code) and SDO is in
Mode 0 (serial data is shifted out of SDO on the clock’s
Using an AC Reference rising edge).
In applications where the reference has AC signal compo- For rated MAX536 performance, V DD should be 4V
nents, the MAX536/MAX537 have multiplying capability higher than REFAB/REFCD and should be between
within the reference input range specifications. Figure 12 10.8V and 13.2V. When using the MAX537, VDD should
shows a technique for applying a sine-wave signal to the be at least 2.2V higher than REFAB/REFCD and should
reference input where the AC signal is offset before being be between 4.75V and 5.5V. Bypass both VDD and VSS
applied to REFAB/REFCD. The reference voltage must with a 4.7µF capacitor in parallel with a 0.1µF capacitor
never be more negative than DGND. to AGND. Use short lead lengths and place the bypass
The MAX536’s total harmonic distortion plus noise capacitors as close to the supply pins as possible.
(THD+N) is typically less than 0.012%, given a 5VP-P signal Grounding and Layout Considerations
swing and input frequencies up to 35kHz, or given a 2VP-P Digital or AC transient signals between AGND and
swing and input frequencies up to 50kHz. The typical -3dB DGND can create noise at the analog outputs. Tie
frequency is 700kHz as shown in the Typical Operating AGND and DGND together at the DAC, then tie this
Characteristics graphs. point to the highest quality ground available.
For the MAX537, with an input signal amplitude of Good PCB ground layout minimizes crosstalk between
0.85mVP-P, THD+N is typically less than 0.024% with a DAC outputs, reference inputs, and digital inputs.
5kΩ load in parallel with 100pF and input frequencies up Reduce crosstalk by keeping analog lines away from
to 100kHz, or with a 2kΩ load in parallel with 100pF and digital lines. Wire-wrapped boards are not recommend-
input frequencies up to 95kHz. ed.

22 ______________________________________________________________________________________
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Ordering Information (continued) Package Information

MAX536/MAX537
PIN- INL For the latest package outline information and land patterns
PART TEMP RANGE (footprints), go to www.maxim-ic.com/packages. Note that a
PACKAGE (LSB)
“+”, “#”, or “-” in the package code indicates RoHS status only.
MAX537ACPE+ 0°C to +70°C 16 PDIP ±0.5 Package drawings may show a different suffix character, but
MAX537BCPE+ 0°C to +70°C 16 PDIP ±1 the drawing pertains to the package regardless of RoHS status.
MAX537ACWE+ 0°C to +70°C 16 Wide SO ±0.5 PACKAGE PACKAGE OUTLINE LAND
MAX537BCWE+ 0°C to +70°C 16 Wide SO ±1 TYPE CODE NO. PATTERN NO.
MAX537AEPE+ -40°C to +85°C 16 PDIP ±0.5 16 PDIP P16+9 21-0043 —
MAX537BEPE+ -40°C to +85°C 16 PDIP ±1 16 SO W16+7 21-0042 90-0107
MAX537AEWE+ -40°C to +85°C 16 Wide SO ±0.5
MAX537BEWE+ -40°C to +85°C 16 Wide SO ±1
+Denotes a lead(Pb)-free/RoHS-compliant package.

______________________________________________________________________________________ 23
 Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Revision History
MAX536/MAX537

REVISION REVISION PAGES

DESCRIPTION
NUMBER DATE CHANGED
0 1/94 Initial release —
Removed dice and ceramic SB packages and changed voltage supply
3 3/11 1–7, 13, 21, 22, 23
specifications

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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