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0.5 V Supply Voltage Reference Based on the MOSFET ZTC Condition

Conference Paper · September 2015

DOI: 10.1145/2800986.2800988

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0.5 V Supply Voltage Reference Based on the MOSFET ZTC
Condition

David Cordova Pedro Toledo Hamilton Klimach

NSCAD Microeltrônica NSCAD Microeltrônica PGMICRO- UFRGS
Porto Alegre, RS, Brazil PGMICRO- UFRGS Porto Alegre, RS, Brazil
[email protected] Porto Alegre, RS, Brazil
[email protected]
[email protected]
Sergio Bampi Eric Fabris
PGMICRO- UFRGS NSCAD Microeltrônica
Porto Alegre, RS, Brazil PGMICRO- UFRGS
[email protected] Porto Alegre, RS, Brazil
[email protected]

ABSTRACT General Terms

The continuous scaling of CMOS devices has required the Design
consequent reduction of the supply voltages. There is a
need for analog and RF circuits able to operate under at Keywords
supplies lower than 0.5 V. This paper presents a voltage ref-
erence based on the MOSFET zero-temperature condition Voltage reference, Schottky diode, Zero temperature coeffi-
(ZTC) that operates with a low 0.5 V supply. The circuit is cient.
composed by a diode-connected MOS transistor operating 1. INTRODUCTION
near the ZTC condition that is biased by a proportional-to-
absolute-temperature (PTAT) current reference implemented As the dimensions of thin-oxide transistors scale, the sup-
with Schottky-diodes. The ZTC condition is analysed using ply voltage for these most aggressively scaled devices needs
a continuous MOSFET model that is valid from weak to to be reduced below 1 V in order to limit the electrical fields
strong inversion and the circuit behaviour is described by and guarantee sufficient device reliability . These effects of
theoretical expressions. Our reference circuit is designed for technology and power supply scaling still provide significant
3 versions: each with MOSFETs of different threshold volt- density and cost improvements for digital circuits. The de-
age (standard-VT , low-VT , and zero-VT ), all available in the sign of analog and RF CMOS circuits wich can take advan-
130 nm CMOS process used. These designs result in three tage of highly scaled devices is an open area of research [1].
different and very low reference voltages: 312, 237, and 51 That is the case of the voltage references operating with
mV. All 3 designed reference operate in the range of 0.45 to ultra-low voltage supplies, which have been the subject of
1.2 V of supply voltages, consuming 1 uA of typical supply much research in CMOS design in the recent years [2].
current. Post-layout simulations present a Temperature Co- Many strategies have been explored to allow the reduc-
efficients (TCs) of 214, 372, and 953 ppm/°C in a temper- tion of the voltage references supply voltage, like the use of
ature range from -55 to 125°C, respectively. Monte-Carlo Schottky diodes instead of PN junction diodes [3, 4], since
simulations show the fabrication variability impact on the the former ones present lower forward bias voltage (0.2 to
circuit performance. The voltage reference was designed in 0.4 V) than the last ones (0.5 to 0.6 V) for the same current
a 130 nm process and it uses 0.014 mm2 of silicon area. density, being both diodes compatible with current CMOS
processes.
The mutual compensation of the mobility and the thresh-
old voltage temperature dependencies, known as the MOS-
Categories and Subject Descriptors FET zero-temperature coefficient (ZTC), has also been used
to design voltage references [5], [6, 7].
B.4 [Very Large Scale Integration Design]: Analog and This paper proposes a 0.5 V supply voltage reference based
Mixed-Signal Circuits on the MOSFET ZTC condition, where a proportional-to-
absolute-temperature (PTAT) current is used to bias a diode-
Permission to make digital or hard copies of all or part of this work for connected MOS transistor in the vicinity of and below the
personal or classroom use is granted without fee provided that copies are not
made or distributed for profit or commercial advantage and that copies bear ZTC bias point for the gate-to-bulk voltage. The PTAT cur-
this notice and the full citation on the first page. Copyrights for components rent reference is implemented using Schottky diodes aiming
of this work owned by others than ACM must be honored. Abstracting with at low voltage supply operation.
credit is permitted. To copy otherwise, or republish, to post on servers or to The paper is organized as follows: Section II presents and
redistribute to lists, requires prior specific permission and/or a fee. Request analyses the MOSFET ZTC condition. In Section III, the
permissions from [email protected]. design of the reference circuit is presented and simulation
SBCCI ’15, August 31 - September 04, 2015, Salvador, Brazil
© 2015 ACM. ISBN 978-1-4503-3763-2/15/08 $15.00 results are shown in Section IV. Section V draws the main
DOI: http://dx.doi.org/10.1145/2800986.2800988. conclusions from this work.
2. MOSFET ZTC CONDITION MODELING

Drain Current (uA)

The drain current MOSFET ZTC condition derives from 10 I D / W = 15 μ A / μ m
the mutual cancellation of the mobility and threshold volt-
age dependencies on temperature, which happens at a par- V GZ , SVT = 420 mV
ticular gate-to-bulk voltage bias of the MOSFET. The drain
current ZTC operating bias point was first defined in [5]
and later in other publications, always based on the strong
inversion quadratic MOSFET model, which is simplified. ∘
C
125 ∘ C
5C
∘
From [5], the ZTC operating point is given by Eqs. (1) 27 −5 L= 1 μ m
and (2).
1
0.3 0.4 0.5
VGZ = VT 0 (T0 ) + nVSB − αVT 0 T0 (1)
( a) Gate Voltage (V)
0
IDZ µn (T0 )T02 Cox
JDZ = = αV2 T 0 (2)
(W/L) 2n 500

Gate Voltage (mV)

where T0 is the room temperature, VT 0 (T0 ) is the thresh- Δ I D >0
old voltage at room temperature, n is the slope factor, VSB
is the source-bulk voltage, αVT 0 is the thermal coefficient Δ I D =0
of the threshold voltage (stressing that VT decreases with 400
T ), µn (T0 ) is the low field mobility at room temperature, Δ I D <0
0
Cox is the oxide capacitance per unit of area and W L
is the α VT =−0.45mV / ∘ C
transistor aspect ratio. JDZ can be defined as ZTC normal- β Z =−3.33μ V / ∘ C
ized drain-current and one can readily conclude that VGZ 300
and JDZ are only dependent on device fabrication processes. -55 -25 5 35 65 95 125
Fig. 1 (a) shows the drain current (in a log scale) as a
function of the gate-bulk voltage (VGB ) of a saturated long- ( b) Temperature (°C)
channel NMOSFET, simulated under temperatures ranging
from −55o C to +155o C, for a standard-VT nmos transistor
transistor in a commercial 130nm CMOS process. The ZTC Figure 1: (a) ZTC condition for an NMOS transistor
operation point can be seen around VGB ≈ 420mV for a in a 130 nm process, and (b) VGB (T ) for ∆Id > 0,
transistor with VT = 160mV and L = 1um, resulting that ∆Id = 0 and ∆Id < 0.
the ZTC point occurs for an overdrive voltage around 260
mV, meaning the transistor operates in moderate to strong
inversion. off voltage, γ is the body effect coefficient, VF B is the flat
In a more general analysis we can suppose that the ZTC band voltage, and φF is the Fermi potential at the bulk of
condition can also occur in moderate inversion, such as the the semiconductor under the transistor channel. Eqs. (5)
one presented in [8], where a more complete MOSFET model and 6) relate the source and drain inversion coefficients (for-
was used [9]. From this MOSFET model, the ZTC operation ward and reverse), if,r , with external voltages applied, VG ,
condition was investigated from this set of Eqs. (3), (4), (5), VS and VD , using the bulk terminal as the reference. Re-
(6), (7) and (8). garding the first order temperature dependence of VT 0 and
µn , αVT 0 presents a dependence for wide ranges of doping
ID = IF − IR = IS (if − ir ) (3) concentration (Na ) and oxide thickness (tox ) and αµ is the
temperature dependence power coefficient for the mobility
model.
0 φ2t W W
IS = µn Cox n = ISQ (4) From [8], if one derives the drain current expression for
2 L L temperature in the saturation region (ir << if ), the condi-
tion for which its temperature dependence is negligible can
VP − VS(D) = φt f (if (r) ) ∴ be found, i.e., (∂ID )/(∂T )|T =T1 = 0. Using the Eqs. (3) to
p p
 (8) and after some analytical work, we can derive that:
f (if (r) ) = 1 + if (r) − 2 + ln 1 + if (r) − 1 (5)
  !
|αVT 0 |q αµ + 2 −if z
VG − VT 0 (T ) p = p +
VP = ∴ VT 0 (T ) = VF B + 2φF + γ 2φF (6) nk 2 1 + if z − 1
n hp p i
1 + if z − 2 + ln 1 + if z − 1 (9)
VT 0 (T ) = VT 0 (T0 ) − |αVT 0 |(T − T0 ) (7)
where k is the Boltzmann constant, q is the elementary
T
  αµ electric charge, and if z is defined as the ZTC forward inver-
µn (T ) = µn (T0 ) (8) sion level. Eq. (9) interpretation is such that if the transistor
T0
is biased such that the inversion level at the source is if z ,
where IF (R) is the forward (reverse) current, if (r) is the
the drain current is insensitive to temperature. Now using
forward (reverse) inversion coefficient, IS is the normaliza-
the assumption αµ ≈ −2 [5] along with Eq. (9) and (5),
tion current, φt is the thermal voltage, VP is called the pinch-
a simple expression for the ZTC gate-bulk voltage (VGZ -
related to if z ) is found. In this CMOS process the Schottky diode is formed with a
cobalt silicide region (anode) formed over the lightly doped
VGZ = VT 0 (T0 ) + nVS − αVT 0 T0 (10) n-type region (cathode) near the surface, that is created by
a deep n-type implant. The work function of the cobalt
Eq. (10) presents the same result already derived from silicide is such that the diode has a low forward voltage
the strong inversion quadratic model in Eq. (1). The ZTC when compared to a silicon junction diode under the same
drain-current, related to if z , can be found using Eq. (3) junction current density, making the schottky diode a good
under the saturation condition if >> ir : replacement for their bipolar counterpart in the design of
IDZ voltage references with ultra-low voltage supplies.
= JDZ = ISQ (T0 )if z (11) The simulated I-V characteristics for two Schottky diodes
(W/L)
with different junction areas are shown in Fig. 2 in the tem-
Finally, the ZTC vicinity condition can be analyzed using perature range of -55 to 125 °C, presenting forward voltages
Eqs. (5) and (6), in the range from 0.2 to 0.4 V at room temperature. The
Temperature Coefficient (TC) and the forward voltage at
VGB (if ) = nφt f (if ) + VT 0 (T ) + nVS (12) -55 °C of the these diodes are shown in Fig. 3 as a func-
tion of the bias current, where the top Fig. 3 (a) indicates
Eq. (12) can be expanded in Taylor’s series around the
the TC dependence on the consumption, and the bottom
ZTC forward inversion level (if z ). Therefore, the first order
Fig. 3 (b) shows the maximum voltage across the diode as
approximation is given by
a function of the diode bias current. Since our voltage refer-
∂VGB ence is designed for a 0.5 V supply voltage with low power
VGB (if ) ≈ VGZ + (if − if z ) (13) consumption, and the design should target lower fabrication
∂if if =if z mismatch spread, we chose the 5x5 µm2 diode biased at 1
where µA.
∂VGB nφt Fig. 4 shows the forward voltage across the 5x5 µm2
= p (14) Schottky diode biased at 1 µA, presenting a voltage drop
∂if 2( 1 + if − 1) from 390 to 140 mV in the temperature range from -55 to
For the αµ ≈ −2 [5], combining Eq. (13), (14), and the 125 °C, and around 280 mV at room temperature with and
term nφt extracted from Eq. (9), we get average CTAT temperature sensitivity of -1.45 mV/°C.

αVT 0 ∆if
VGB (T ) ≈ VGZ − p T = VGZ − βz ∆if T
2f (if z )( 1 + if z − 1)
(15)
where ∆if = if − if z indicates how far the transistor 1E-4
Diode Current (A)

A 1 =5x5 μ m2
is biased from ZTC operating point and βz is defined as

C
∘
2

27
the ZTC slope. As the if = Id /IS from the Eq. (3), the 1E-5 A 2 =2x2 μ m

@
1
A
dependency of VGB (T ) on the temperature can be be found ∘ C
5 C

C
∘

1E-6 12

∘
C
27

55
such that: @

55
∘ C @

−
A 1
5

−
12
2
A

@
@
1E-7 @

2
A
βz ∆Id

1
A2

A
VGB (T ) = VGZ − T (16)
ISQ W V f @ 27 C =[200 −300 ] mV
1E-8
∘
L

Eq. (16) shows that VGB presents a linear temperature 0 0.1 0.2 0.3 0.4 0.5
dependence in the vicinity of VGZ , and that this dependence
can be positive or negative, depending on the ∆Id chosen, Voltage (V)
as shown in Fig. 1 (b). Finally, we can readily conclude that
a MOSFET transistor biased on ZTC vicinity can be easily
compensated with a PTAT or CTAT current reference, the Figure 2: Simulated I-V characteristics of a Schottky
option depending only if it is operating below or above ZTC diode [2x2 µm2 and 5x5 µm2 ] at [-55, 27 and, 125]
point. This fundamental concept is used the design of our °C.
proposed very-low voltage reference, to operate down to 0.5
V supply.

For our low-voltage reference design, a low power PTAT

3. VOLTAGE REFERENCE ANALYSIS AND current reference is required. This PTAT current reference
DESIGN is generated using the difference of the forward voltage of
two schottky diodes operating with different junction cur-
3.1 Schottky-diode based P T AT Current Ref- rent densities, obtained with identical current sources ap-
erence plied in Schottky diodes with different total areas. Fig. 5
Schottky diodes can be fabricated in almost any current shows the schematic diagram of the PTAT current reference
CMOS mixed-signal fabrication process, while silicon junc- where the operational amplifier was implemented with two
tion diodes are omnipresent in bulk MOSFETs. Since our stages for power supply rejection (PSRR) improvement. The
proposed circuit was designed in a commercial 130 nm IBM PTAT current analysis was derived in [10], and it is shown
CMOS process, the data presented here refers to the devices below, where UT is the thermal potential, proportional to
available in this process. the absolute temperature.
 -1.1 2
2μ m
A 2= 2x
TC (mV/°C)

2
A 1= 5x5 μ m
-1.4
I PTAT
-1.7 VX VY
0.1 1.1 2.1 3.1 4.1 R
Bias Current (uA)
( a) 1:K

480
VFB at -55°C (mV)

2
μm Figure 5: Low-voltage supply PTAT current refer-
A 2= 2x2 ence.
420 μm
2

A 1= 5x5
The schematic of the voltage reference circuit, depicted
360 in Fig. 7, consists of a low supply PTAT current reference
biasing diode-connected NMOS transistors in the vicinity
300 of the ZTC point condition. The PTAT current reference
0.1 1.1 2.1 3.1 4.1 counterbalance the complementary-to-absolute-temperature
(CTAT) behavior of the ZTC vicinity resulting the temper-
(b ) Bias Current (uA) ature sensitivity compensation. The necessary (W/L) as-
pect ratio of the diode-connected NMOS transistors, for a
given PTAT current reference (T CP T AT ), may be found sim-
Figure 3: (a) Temperature Coefficient vs Bias Cur- ply combining Eq. (19) with Eqs. (5) and (6) and making
rent, and (b) Forward Voltage at -55 °C vs Bias Cur- (∂VGB )/(∂T )|T =T0 = 0. Therefore, we get
rent .
IP T AT = I0 (1 + T CP T AT (T − T0 )) (19)
Forward Voltage, Vf (mV)

400 V f @ 27 C =280 mV
∘    2
W 2nI0 T CP T AT αµ
= − (20)
300 L Cox 2|αVT 0 | T0
Fig. 6 shows the diode-connected current-voltage behav-
200 ior of the ’standard’, ’low’ and ’zero’ threshold voltage (VT )
−1.45 mV /◦C transistors available in the 130-µm CMOS technology, with
W/L = 3µm/0.42µm, presenting nominal VT values of 340,
100 245 and 5 mV, respectively. The drain current ID as a func-
-55 -25 5 35 65 95 125 tion of the drain-to-source voltage VDS indicates that zero-
VT transistors of the same dimensions present, as expected,
Temperature (°C) current levels three orders of magnitude higher than that of
the standard-VT transistor, under the same biasing condi-
tions, making it very attractive for low-voltage applications.
Figure 4: Forward Voltage vs temperature of a The reference voltage VREF is obtained from from the
Schottky diode with cathode area 5x5 µm2 biased diode-connected NMOS transistor voltage drop, as shown
at 1µA. in Fig. 7. Three different voltage references (VR) were
designed with a different nmos transistor. The design in
Fig. 7 has the ’standard-VT ’ (SV T ), the ’low-VT ’ (LV T )
and the ’zero-VT ’ (ZV T ) transistors, all supported in this
nUT ln (K) R technology.
IP T AT = , where = 1 + T C1 (T − T0 )
R R(T0 )
(17) 4. SIMULATION RESULTS
Using a nominal supply voltage of 0.5 V the proposed volt-
∂IP T AT 1 1 age reference shown in Fig. 7 was validated with Cadence®
T C P T AT = · =
∂T IP T AT (T0 ) T0 [1 + T C1 (T − T0 )]2 simulations, using the models provided by the foundry and
(18) inside the temperature range from -55 to 125°C. DC and AC
simulations were run to estimate the following performance
3.2 Complete Circuit Analysis and Design parameters: PTAT current (IP T AT ) and reference voltages
 156μ m
V DD=0.5V

M A3 M A4 M A5 M1 M2 M 3 I PTAT M 4 I PTAT M 5 I PTAT MSVT, MLVT, MZVT M1,2,3,4,5 Cc MA1, MA2,

MA3, MA4

VX VY

92μ m
VX VY V REF SVT V REF LVT V REF ZVT
M A1 M A2 M A6
R
D1 D2
M SVT
C1
M LVT
C2
M ZVT
C3 C1,C2,C3 D1, D2 R
CC
1 :8
Two−stage Amplifer I PTAT Core Voltage References CMOS 130nm

Figure 7: Proposed 0.5-V CMOS voltage reference schematic circuit and layout.

FETs, ’standard-VT ’ (SV T ), ’low-VT ’ (LV T ) and ’zero-VT ’

1E-5 (ZV T ) shown in Fig. 7. The simulated nominal reference
voltages obtained were, respectively, of 312 mV, 237 mV
1E-6 Zero − V T and 51 mV with TCs of 214 ppm/°C, 372 ppm/°C and 953
Low − V T ppm/°C, respectively.
1E-7
ID (A)

1E-8

Voltage Reference (mV)

1E-9 Standard 317 Standard V T
1E-10 TC =214 ppm / ∘ C
-0.2 0 0.2 0.4 0.6 0.8 1 1.2 315 V REF @ 27 C =312 mV
∘

VDS (V)
313

Figure 6: ID vs. VDS for the standard-VT , low-VT 311

and zero-VT with (W/L = 3µm/0.42µm). -55 -25 5 35 65 95 125
Temperature (°C)
(VREF ), temperature coefficient (T C), line regulation (LR),
power supply rejection ratio (P SRR) and power consump-
tion. Figure 9: Voltage reference (standard-VT ) variation
Fig. 8 shows the temperature dependence of the PTAT over temperature.
current reference, that was designed for a nominal value of
1 µA under 27°C and a temperature coefficient T C of 4000
ppm/°C. The PTAT TC is not constant, and decreases at
Voltage Reference (mV)

high temperatures, above 90°C, as can be deduced from Fig.

8. 239 Low V T

237
Current Reference(uA)

1.3 TC = 372 ppm / ∘ C

TC=4000 ppm/ ∘ C V REF @ 27 C =237 mV
235
∘

I REF @ 27 C = 1 μ A
∘

0.9 233
-55 -25 5 35 65 95 125
Temperature (°C)
0.5
-55 -25 5 35 65 95 125
Figure 10: Voltage reference (low-VT ) variation over
Temperature (°C) temperature.

Fig. 12 exhibits the simulated power supply rejection

Figure 8: PTAT current reference variation over (PSRR) of the reference voltage at room temperature.
temperature. The impact of the fabrication process variations on the ref-
erence performance was estimated using Monte Carlo anal-
The temperature sensitivity of the voltage reference is ysis. Table 1 summarizes the performance variations (mean
shown in Figs. 9, 10 and 11 for the three threshold MOS- and standard deviation) for IP T AT , VREF , T C, LR NF, and
 Voltage Reference (mV) 54
Table 1: Simulated Performance of the SUB-1V VDD
Zero V T Schottky based reference.
TC= 953 ppm / ∘ C
V REF @ 27 C = 51 mV
∘
Process CMOS 0.13-μm? Unit
52 Temp. Rage
VDD, N OM
-55 ↔ 125
0.5
°C
V
VDD Range 0.45 ↔ 1.2 V
VREF ⊕ 312 238 52 mV
IP T AT ⊕ 1 uA

50 LR (VREF )
LR (IP T AT )
35.5 39
466
13.5 mV/V
nA/V
-55 -25 5 35 65 95 125 VREF † μ= 312 ; σv= 17.8 μ= 237 ; σv= 23.2 μ= 51 ; σv= 11.7 mV
VREF μ/σv 5.7 9.7 22.5 %

Temperature (°C) TC (VREF ) †

98% Samples
μ= 214; σv= 133
< 440
μ= 372; σv= 268
< 810
μ= 953; σv= 676
< 2300
ppm/°C
PSRR@ DC † μ= -28; σv= 1.3 μ= -27.5; σv= 1.45 μ= -36.8; σv= 1.8
dB
100% Samples < -26 < -24 < -33
PSRR@100 kHz † μ= -20; σv= 2 μ= -19; σv= 2 μ= -27; σv= 2.3
dB
Figure 11: Voltage reference (zero-VT ) variation over 100% Samples < -18 < -15 < -20
PSRR@1 MHz † μ= -14; σv= 1.2 μ= -13.3; σv= 1.2 μ= -11; σv= 1.7
temperature. 100% Samples < -10 < -11 < -8
dB
Power⊕ 5.9 uW
Area 0.014 mm2
Power Supply Rejection Ratio (dB)

⊕ ? †
@( °27C, VDD, N OM ); Simulation results; Process and Mismatch (1000 runs )

0
PSRR @ DC SVT , LVT =−28 dB
Table 2: Performance comparison for SUB-1V VDD
-30 Schottky based reference

PSRR @ DC , ZVT =−37 dB

This Work? [11] [4]
CMOS Process 0.13 μm? 90 nm 0.5 μm Unit
-60 Temp. Rage -55 ↔ 125 5 ↔ 100 5 ↔ 70 °C
1E+0 1E+3 1E+6 1E+9 VDD, N OM 0.5 0.6 2.5 V
VDD, M IM 0.45 0.5 1.2 V
Frequency (Hz) VREF ⊕ 312 251 400 mV
∆VREF /∆VDD 4.7 3 1.4 mV/100mV
TC (VREF ) † 214 263 107 ppm/°C
Power⊕ 5.9 450 59.4 uW
Figure 12: Power supply rejection ratio of the pro- Area 0.014 0.02 N/A mm2
posed voltage reference. ⊕
@(°27C, VDD, N OM );
?
Simulation results; †
Process and Mismatch (1000 runs )

P SRR, as shown in the second, third, and fourth columms

in Table 1 for the herein considered SV T , LV T , and ZV T 130 nm CMOS process (’standard-VT ’, ’low-VT ’ and ’zero-
transistor cases, respectively. VT ’), resulting nominal reference voltages of 312 mV, 237
No experimental measured data is available at the moment mV and 51 mV with TCs of 214 ppm/°C, 372 ppm/°C and
for the voltage references, as the circuits are undergoing fab- 953 ppm/°C, respectively, in the temperature range from -
rication. Measured data will be provided in the future for 55 to +125°C. The total power consumption of our design is
these VRs at the time of paper presentation. Table 2 shows just 5.9 µW. This is at least 10 times lower when compared
a comparison between other Schottky-diode-based voltage to the other Schottky-diode implementations. Therefore,
references reported. Our proposed topology was designed to the proposed voltage reference could be a good option for
optimize power consumption in a wider temperature range, low-voltage and low-power applications.
while maintaining a comparable T C to the other implemen- The proposed topology shows that Schottky-diode-based
tations. Our design used at least 10 times lower current than voltage references in CMOS offer a promising alternative for
the previous works in Table 2. the design of ultra-low voltage references.

5. CONCLUSIONS Acknowledgments
In this paper a voltage reference operating with 0.5 V The authors acknowledge the Brazilian funding agencies CNPq
power supply voltage and based on the MOSFET ZTC con- and CAPES, and the IC-Brazil Program for financial sup-
dition is presented. It was demonstrated that the use of port and MOSIS for access to chip fabrication services.
Schottky diodes instead of the bipolar junction diodes helps
the supply voltage reduction of a PTAT current source, that 6. REFERENCES
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