IP100A LF

Preliminary Data Sheet

Integrated 10/100 Ethernet MAC + PHY

Features General Description
Single chip 10/100BASE, half or full duplex The IP100A LF is a single-chip, full duplex,
Ethernet Media Access Controller 10/100Mbps Ethernet MAC + PHY incorporating a
IEEE 802.3 compliant 32-bit PCI with bus master support. The IP100A
100BASE-TX/100BASE-FX/10BASE-T LF is designed for use in a variety of applications
PCI Bus master scatter/gather DMA on any including workstation NICs, PC motherboards,
byte boundary and other systems utilizing a PCI bus that require
Full operation with PCI Clock from 25 MHz to network connectivity to an Ethernet or Fast
33 MHz Ethernet LAN.
PCI Revision 2.2 compliant
On-chip transmit and receive FIFO buffers The IP100A LF includes a PCI bus interface unit,
On-chip LED drivers IEEE 802.3 compliant MAC, transmit and receive
Power management capabilities for ACPI 1.0 FIFO buffers, IEEE 802.3 compliant 100BASE-TX,
compliant systems 10BASE-T, and 100BASE-FX PHY, serial
WakeOnLAN support EEPROM interface and LED drivers.
Management statistics gathering
IP multicast receive and filter support using The IP100A LF implements a rich set of control
64 bit hash table and status registers. Accessible via the PCI
Transmit polling interface, these registers provide a host system
Auto pad insertion for short packets visibility into the features and operating state of
Programmable minimum Inter Packet Gap the IP100A LF. Network management statistics
Supports auto MDI-MDIX function are also recorded, and host access to registers of
Smart Cable Analyzer (SCA) Support the PHY device are facilitated through the IP100A
Capable of using 93C46 EEPROM LF’s PCI interface.
On-chip crystal oscillator
On-chip voltage regulator The IP100A LF supports features for use in
2.5/3.3V CMOS with 5V tolerant I/O “Green PCs” or systems where control over
0.25µm technology system power consumption is desired. The
128-pin PQFP IP100A LF supports several power down states,
Support Lead Free package (Please refer to and the ability to issue a system “wake event” via
the Order Information) reception of unique, user defined Ethernet frames.
In addition, the IP100A LF can assert a wake
event in response to changes in the Ethernet link
status

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 IP100A LF
Preliminary Data Sheet
Block Diagram

PCI
RSTN
PCICLK
GNTN
IDSEL MDI
INTAN TXP
PMEN
TXN
REQN
AD[31..0] RXP
CBEN[3:0] RXN
PAR
FFSD
FRAMEN TxDMA
IRDYN TxFIFO
Logic EEPROM
TRDYN
DEVSELN Media Physical EEOP
STOPN EEDO
PCI Bus
Access Layer EEDI
PERRN
SERRN EESK
Control
VDET (PCS, EECS
Interface
PMA,
(MAC) PMD)
MISCELLANEOUS LED
RxDMA
X1 RxFIFO LED_LINK
X2 Logic LED_10N
ISET LED_100N
LED_TXN
LED_RXN
LAST_GASP
LEDDPLXN

CTRL25
TEST

RSTN
VCC2
VCC1
AVCC25
AVCC33
GND

FIGURE 1: IP100A LF Block Diagram

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 IP100A LF
Preliminary Data Sheet
Contents
Features....................................................................................................................................................... 1
General Description..................................................................................................................................... 1
Block Diagram ............................................................................................................................................. 2
Contents ...................................................................................................................................................... 3
Revision History........................................................................................................................................... 6
1 PIN Designations .................................................................................................................................. 7
2 PIN Diagram.......................................................................................................................................... 8
3 PIN Descriptions ................................................................................................................................... 9
PIN Descriptions (continued) ................................................................................................................... 10
PIN Descriptions (continued) ................................................................................................................... 11
4 Acronyms and Glossary...................................................................................................................... 13
5 Standards Compliance........................................................................................................................ 13
6 Functional Description ........................................................................................................................ 13
6.1 Media Access Control............................................................................................. 13
6.2 Physical Layer ........................................................................................................ 14
6.3 On-Chip Voltage Regulator..................................................................................... 14
6.4 PCI Bus Interface.................................................................................................... 14
6.5 TxDMA Logic .......................................................................................................... 14
6.6 TxFIFO.................................................................................................................... 15
6.7 RxDMA Logic .......................................................................................................... 15
6.8 RxFIFO ................................................................................................................... 15
6.9 EEPROM Interface ................................................................................................. 15
7 Operation ............................................................................................................................................ 16
7.1 Initialization ............................................................................................................. 16
7.2 Register Programming............................................................................................ 16
7.3 TxDMA and Frame Transmission........................................................................... 17
7.4 Frame Reception and RxDMA................................................................................ 19
7.5 Interrupts................................................................................................................. 22
8 Statistics.............................................................................................................................................. 22
8.1 Transmit Statistics .................................................................................................. 22
8.2 Receive Statistics ................................................................................................... 23
9 PCI Bus Master Operation .................................................................................................................. 23
10 Power Management............................................................................................................................ 24
10.1 Wake Event............................................................................................................. 27
10.2 Power Down ........................................................................................................... 27
11 Registers and Data Structures............................................................................................................ 28
11.1 PHY Registers ........................................................................................................ 28
11.1.1 Control Register...................................................................................................... 28
11.1.2 Status Register ....................................................................................................... 29
11.1.3 PHY Identifier 1....................................................................................................... 30
11.1.4 PHY Identifier 2....................................................................................................... 30
11.1.5 Auto-Negotiation Advertisement............................................................................. 31
11.1.6 Auto-Negotiation Link Partner Ability...................................................................... 31
11.1.7 Phy Specification Control Register ......................................................................... 32
11.1.8 Phy Debug Control Register ................................................................................... 33
11.1.9 Phy Status Monitor Register ................................................................................... 33
11.1.10 SCA Settings .......................................................................................................... 34
11.2 DMA Data Structures.............................................................................................. 35
11.2.1 RxDMAFragAddr .................................................................................................... 35
11.2.2 RxDMAFragLen ...................................................................................................... 36
11.2.3 RxDMANextPtr ....................................................................................................... 36
11.2.4 RxFrameStatus....................................................................................................... 36

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 IP100A LF
Preliminary Data Sheet
11.2.5 TxDMAFragAddr..................................................................................................... 38
11.2.6 TxDMAFragLen ...................................................................................................... 38
11.2.7 TxDMANextPtr ........................................................................................................ 38
11.2.8 TxFrameControl...................................................................................................... 39
11.3 Wake Event Data Structures .................................................................................. 40
11.3.1 MagicSequence ...................................................................................................... 41
11.3.2 MagicSyncStream................................................................................................... 41
11.3.3 PseudoCRC ............................................................................................................ 41
11.3.4 PseudoPattern ........................................................................................................ 42
11.3.5 Terminator............................................................................................................... 42
11.4 LAN I/O Registers................................................................................................... 43
11.4.1 AsicCtrl.................................................................................................................... 44
11.4.2 DMACtrl .................................................................................................................. 48
11.4.3 EepromCtrl.............................................................................................................. 50
11.4.4 EepromData............................................................................................................ 51
11.4.5 FIFOCtrl .................................................................................................................. 51
11.4.6 HashTable............................................................................................................... 52
11.4.7 IntEnable................................................................................................................. 52
11.4.8 IntStatus.................................................................................................................. 53
11.4.9 IntStatusAck............................................................................................................ 54
11.4.10 MACCtrl0 ................................................................................................................ 55
11.4.11 MACCtrl1 ................................................................................................................ 56
11.4.12 MaxFrameSize........................................................................................................ 58
11.4.13 PhyCtrl .................................................................................................................... 58
11.4.14 ReceiveMode.......................................................................................................... 59
11.4.15 RxDMABurstThresh................................................................................................ 59
11.4.16 RxDMAListPtr ......................................................................................................... 60
11.4.17 RxDMAPollPeriod ................................................................................................... 60
11.4.18 RxDMAStatus ......................................................................................................... 60
11.4.19 RxDMAUrgentThresh ............................................................................................. 61
11.4.20 StationAddress ....................................................................................................... 62
11.4.21 TxDMABurstThresh ................................................................................................ 62
11.4.22 TxDMAListPtr.......................................................................................................... 63
11.4.23 TxDMAPollPeriod ................................................................................................... 63
11.4.24 TxDMAUrgentThresh.............................................................................................. 64
11.4.25 TxReleaseThresh ................................................................................................... 64
11.4.26 TxStatus.................................................................................................................. 65
11.4.27 WakeEvent.............................................................................................................. 66
11.5 Statistic Registers ................................................................................................... 67
11.5.1 BroadcastFramesReceivedOk................................................................................ 67
11.5.2 BroadcastFramesTransmittedOk............................................................................ 67
11.5.3 CarrierSenseErrors................................................................................................. 68
11.5.4 FramesAbortedDueToXSColls ............................................................................... 68
11.5.5 FramesLostRxErrors............................................................................................... 69
11.5.6 FramesReceivedOk ................................................................................................ 69
11.5.7 FramesTransmittedOk ............................................................................................ 70
11.5.8 FramesWithDeferredXmission................................................................................ 70
11.5.9 FramesWithExcessiveDeferal................................................................................. 71
11.5.10 LateCollisions ......................................................................................................... 71
11.5.11 MulticastFramesReceivedOk.................................................................................. 72
11.5.12 MulticastFramesTransmittedOk.............................................................................. 72
11.5.13 MultipleCollisionFrames.......................................................................................... 73
11.5.14 OctetsReceivedOk.................................................................................................. 73
11.5.15 OctetsTransmittedOk.............................................................................................. 74
11.5.16 SingleCollisionFrames ............................................................................................ 74
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 IP100A LF
Preliminary Data Sheet
11.6 LAN PCI Configuration Registers ........................................................................... 75
11.6.1 CacheLineSize........................................................................................................ 76
11.6.2 CapId ...................................................................................................................... 76
11.6.3 CapPtr..................................................................................................................... 76
11.6.4 CISPointer............................................................................................................... 77
11.6.5 ClassCode .............................................................................................................. 77
11.6.6 ConfigCommand..................................................................................................... 78
11.6.7 ConfigStatus ........................................................................................................... 79
11.6.8 Data ........................................................................................................................ 80
11.6.9 DeviceId .................................................................................................................. 80
11.6.10ExpRomBaseAddress............................................................................................. 81
11.6.11HeaderType ............................................................................................................ 81
11.6.12InterruptLine............................................................................................................ 82
11.6.13InterruptPin ............................................................................................................. 82
11.6.14IoBaseAddress ....................................................................................................... 82
11.6.15LatencyTimer .......................................................................................................... 83
11.6.16MaxLat .................................................................................................................... 83
11.6.17MemBaseAddress .................................................................................................. 83
11.6.18MinGnt .................................................................................................................... 84
11.6.19NextItemPtr ............................................................................................................. 84
11.6.20PowerMgmtCap ...................................................................................................... 85
11.6.21PowerMgmtCtrl ....................................................................................................... 86
11.6.22RevisionId ............................................................................................................... 86
11.6.23SubsystemId ........................................................................................................... 87
11.6.24SubsystemVendorId ............................................................................................... 87
11.6.25VendorId ................................................................................................................. 87
11.7 EEPROM Data Format ........................................................................................... 88
11.7.1 AsicCtrl.................................................................................................................... 88
11.7.2 ConfigParm ............................................................................................................. 89
11.7.3 FunctionsCtrl........................................................................................................... 90
11.7.4 StationAddress ....................................................................................................... 90
11.7.5 SubsystemId ........................................................................................................... 91
11.7.6 SubsystemVendorId ............................................................................................... 91
12 Signal Requirements........................................................................................................................... 92
12.1 Absolute Maximum Ratings .................................................................................... 92
12.2 Operating Ranges................................................................................................... 92
12.3 AC Characteristics .................................................................................................. 94
12.4 Thermal Data .......................................................................................................... 96
13 Order Information ................................................................................................................................ 96
14 Physical Dimensions ........................................................................................................................... 97

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 IP100A LF
Preliminary Data Sheet
Revision History
Revision
Date Revision
Number
Version 1.0 2003-06-25 First Release
Version 10 2005-01-25 1. Add the order information for lead free package.
Version 11 2005-03-14 1. Modify pin name of Pin 17,18,20,21,22,24,35,43,48,49
Version 12 2005-04-22 1. Describe EepromCtrl register bit 12 and bit 13 in detail
Version 13 2005-05-19 1. Add IP100A thermal data
Version 14 2005-10-20 1. Remove 93C56 and EEOP support.
2. Modify FFSD pin definition, in page 11.
Version 15 2006-04-27 1. Add “Support Auto MDI-MDIX function” description
Version 16 2006-10-18 1. Modify RxDMALastFrag pin description, in page 36.
Version 17 2007-03-30 1. Modify Pin Diagram in page 8.
2. Modify LED_LINK Pin Type in page 11

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 IP100A LF
Preliminary Data Sheet
1 PIN Designations
PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME PIN NO. PIN NAME
1 NC 33 GND 65 GND 97 GND
2 AD5 34 ISET 66 VCC2 98 NC
3 AD4 35 AVSS 67 PCICLK 99 VCC2
4 AD3 36 TXP 68 REQN 100 FRAMEN
5 NC 37 TXN 69 AD31 101 IRDYN
6 AD2 38 NC 70 AD30 102 TRDYN
7 AD1 39 AVCC25 71 AD29 103 DEVSELN
8 NC 40 NC 72 AD28 104 STOPN
9 AD0 41 RXP 73 AD27 105 PERRN
10 NC 42 RXN 74 VCC2 106 VCC1
11 VCC2 43 AVSS 75 GND 107 SERRN
12 NC 44 AVCC25 76 AD26 108 PAR
13 GND 45 CTRL25 77 AD25 109 GND
14 LED_LINK 46 AVSS 78 GND 110 GND
15 NC 47 AVCC33 79 AD24 111 VCC2
16 LED_TXN 48 NC 80 CBEN3 112 CBEN1
17 EESK / 49 NC 81 VCC1 113 AD15
LED_10N
18 EEDI / 50 NC 82 IDSEL 114 AD14
LED_100N
19 GND 51 NC 83 AD23 115 AD13
20 NC 52 NC 84 AD22 116 AD12
21 LED_RXN 53 NC 85 AD21 117 AD11
EEDO
22 54 NC 86 AD20 118 AD10
/LED_DPLXN
23 GND 55 NC 87 GND 119 NC
24 VCC1 56 NC 88 AD19 120 VCC1
25 TEST 57 NC 89 GND 121 VCC2
26 NC 58 NC 90 AD18 122 GND
27 NC 59 INTAN 91 VCC2 123 AD9
28 EECS 60 VDET 92 VCC1 124 AD8
29 NC 61 RSTN 93 AD17 125 CBEN0
30 LAST_GASPN 62 GNTN 94 NC 126 AD7
31 X2 63 PMEN 95 AD16 127 AD6
32 X1 64 NC 96 CBEN2 128 FFSD
TABLE 1 : IP100A LF Pin Designations

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 IP100A LF
Preliminary Data Sheet
2 PIN Diagram

FRAMEN

PCICLK
TRDYN

CBE2N

CBE3N
IRDYN

IDSEL

REQN
VCC2

VCC1
VCC2

VCC1

VCC2

VCC2
AD16

AD17

AD18

AD19

AD20
AD21
AD22
AD23

AD24

AD25
AD26

AD27
AD28
AD29
AD30
AD31
GND

GND

GND

GND

GND

GND
NC

NC
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
102
101
100

DEVSELN 103 64 NC
STOPN 104 63 PMEN
PERRN 105 62 GNTN
VCC1 106 61 RSTN
SERRN 107 60 VDET
PAR 108 59 INTAN
GND 109 58 NC
GND 110 57 NC
VCC2 111 56 NC
CBE1N 112 55 NC
AD15 113 54 NC
AD14
AD13
AD12
114
115
116
117
IP100A LF 53
52
51
50
NC
NC
NC
NC
AD11
AD10 118 49 NC
NC 119 48 NC
VCC1 120 47 AVCC33
VCC2 121 IC Plus Corp. 46 AVSS
GND 122 45 CTRL25
123 44 AVCC25
AD9
AD8 124 Fast Ethernet NIC Chip 43 AVSS
CBE0N 125 42 RXN
AD7 126 41 RXP
AD6 127 40 NC
FFSD 128 39 AVCC25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
1
2
3
4
5
6
7
8
9
NC

NC

NC

NC

NC
GND

NC
LED_TXN

GND
NC
LED_RXN
EEDO / LED_DPLXN
GND
EESK / LED_10N
EEDI / LED_100N

NC
NC

NC
LAST_GASPN

GND

TXN
NC
TEST

ISET
AD5
AD4
AD3

AD2
AD1

AD0

VCC2

VCC1

X2
X1
LED_LINK

EECS

AVSS
TXP

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 IP100A LF
Preliminary Data Sheet
3 PIN Descriptions
PIN NAME PIN TYPE PIN DESCRIPTION
PCI INTERFACE
RSTN INPUT Reset, asserted LOW. RSTN will cause the IP100A LF to reset all of its
functional blocks. RSTN must be asserted for a minimum duration of 10
PCICLK cycles.
PCICLK INPUT PCI Bus Clock. This clock is used to drive the PCI bus interfaces and the
internal DMA logic. All bus signals are sampled on the rising edges of
PCICLK. PCICLK can operate from 25MHz to 33MHz.
GNTN INPUT PCI Bus Grant, asserted LOW. GNTN signals access to the PCI bus has
been granted to IP100A LF.
IDSEL INPUT Initialization Device Select. The IDSEL is used to select the IP100A LF
during configuration read and write transactions.
INTAN OUTPUT Interrupt Request, asserted LOW. The IP100A LF asserts INTAN to
request an interrupt, when any one of the programmed interrupt event
occurs.
PMEN OUTPUT Wake Event, assertion level is programmable (see the WakePolarity bit of
the WakeEvent register). The IP100A LF asserts PMEN to signal the
detection of a wake event.
REQN OUTPUT Request, asserted LOW. The IP100A LF asserts REQN to request PCI bus
master operation.
AD IN/OUT PCI Bus Address/Data. Address and data are multiplexed on the AD pins.
[31..0] The AD pins carry the physical address during the first clock cycle of a
transaction, and carry data during the subsequent clock cycles.
CBEN IN/OUT PCI Bus Command/Byte Enable, asserted LOW. Bus command and byte
[3..0] enables are multiplexed on the CBEN pins. CBEN specify the bus
command during the address phase transaction, and carry byte enables
during the data phase.
PAR IN/OUT Parity. PCI Bus parity is even across AD[31..0] and CBEN[3..0]. The
IP100A LF generates PAR during address and write data phases as a bus
master, and during read data phase as a target. It checks for correct PAR
during read data phase as bus master, during every address phase as a
bus slave, and during write data phases as a target.
FRAMEN IN/OUT PCI Bus Cycle Frame, asserted LOW. FRAMEN is an indication of a
transaction. It is asserted at the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of
the transaction.
IRDYN IN/OUT Initiator Ready, asserted LOW. A bus master asserts IRDYN to indicate
valid data phases on AD[31..0] during write data phases, indicates it is
ready to accept data during read data phases. A target will monitor IRDYN.
TRDYN IN/OUT Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid
read data phases, and to indicate it is ready to accept data during write
data phases. A bus master will monitor TRDYN.
STOPN IN/OUT Stop, asserted LOW. STOPN is driven by the slave target to inform the bus
master to terminate the current transaction.
TABLE 2 : IP100A LF Pin Descriptions

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 IP100A LF
Preliminary Data Sheet
PIN Descriptions (continued)
PIN NAME PIN TYPE PIN DESCRIPTION
PCI INTERFACE (continued)
PERRN IN/OUT Parity Error, asserted LOW. The IP100A LF asserts PERRN when it
checks and detects a bus parity errors. When it is generating PAR output,
the IP100A LF monitors for any reported parity error on PERRN.
SERRN OUTPUT System Error, asserted LOW.
VDET INPUT Power Detect. The IP100A LF detects PCI bus power supply loss when
VDET is LOW.
EEPROM INTERFACE
EECS OUTPUT EEPROM Chip Select. EECS is asserted by the IP100A LF to access the
EEPROM. EECS is connected directly to the chip select input of the
EEPROM device.
EESK OUTPUT EEPROM Serial Clock. EESK is an output connected directly to the clock
input of the EEPROM device.
EEDI OUTPUT EEPROM Data Input. EEDI is an output connected directly to the data input
of the EEPROM device. This pin is shared with LED100N pin.
EEDO INPUT EEPROM Data Output. EEDO is an input connected directly to the data
output of the EEPROM device. This pin is shared with Duplex LED pin.
LED DRIVERS
LED_TXN OUTPUT Transmit Status LED. This pin will stay LOW during transmission period
and HIGH if no data or pulse is beening sent from IP100A LF.
LED_RXN OUTPUT Receiving Status LED. This pin will stay LOW during receiving period and if
no data has been received, the LED_RXN status will be HIGH.
LED_DPLXN OUTPUT Duplex Status LED. LED_DPLXN is the duplex status LED driver. The
duplex status LED driver is LOW when the link is full duplex, and HIGH
when the link is half duplex. Additional functionality of the speed status
LED signal is based on the LEDMode bit of the AsicCtrl register.
TABLE 2 : IP100A LF Pin Descriptions

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 IP100A LF
Preliminary Data Sheet
PIN Descriptions (continued)
PIN NAME PIN TYPE PIN DESCRIPTION
LED DRIVERS (continued)
LED_10N OUTPUT 10Mb/sec Connection Status LED. This pin will output LOW to indicate
10Mb/sec Transmission if the connection between 2 devices have
negoatiated to link at 10Mb/sec.
LED_100N OUTPUT 100Mb/sec Connection Status LED. This pin will output LOW to indicate
100Mb/sec Transmission if the connection between 2 devices have
negoatiated to link at 100Mb/sec.
LED_LINK OUTPUT Link Status LED. LED_LINK is the link status LED driver. The functionality
of the link status LED signal is based on the LEDMode bit of the AsicCtrl
register. A 4.7K pull-down resistor is placed between this pin and GND
regardless of whether the LED is connected to this pin.
MDI
RXP INPUT Receive input. When in 100BASE-TX mode, this receives MLT3 data from
the isolation transformer. When in 100BASE-FX mode, this is a PECL input.
RXN INPUT Receive input. When in 100BASE-TX mode, this receives MLT3 data from
the isolation transformer. When in 100BASE-FX mode, this is a PECL input.
TXP OUTPUT Transmit output. When in 100BASE-TX mode, this is an MLT-3 driver.
When in 100BASE-FX mode, this is a PECL driver.
TXN OUTPUT Transmit output. When in 100BASE-TX mode, this is an MLT-3 driver.
When in 100BASE-FX mode, this is a PECL driver.
FFSD INPUT This pin is used to select TP or Fiber mode. For 100BASE-FX applications,
FFSD is connected to the signal detect output pin of a fiber optic module at
PECL level. Connecting this pin to GND will force the IP100A into TP
mode.
MISCELLANEOUS
CTRL25 OUTPUT This is a controller pin to monitor correct 2.5V supply to IC.
LAST_GASPN INPUT This pin monitors the PCI voltage. If the voltage is dropped to certain value,
LAST_GASPN will indicate IP100A LF to transmit LAST GASP frame to inform
the other end that IP100A LF is not functioning till SYSTEM POWER ON or
RESET.
X1 OSCIN 25MHz Crystal Oscillator Input. The external 25MHz crystal and capacitor
is connected to the on-chip crystal oscillator circuit through X1 input.
Alternately, X1 can be driven by an external clock source.
X2 OSCOUT 25MHz Crystal Oscillator Output. The external crystal and capacitor is also
connected to the output of the on-chip crystal oscillator circuit through X2.
When X1 is driven by an external clock source, X2 should be left unconnected.
ISET ANALOG Band Gap Resistor. Connect a 6.2kohm, 1% resister between ISET and GND.
TEST INPUT Test. Enables the IP100A LF test modes.
NC Reserved. These Pins must keep floating at application circuit.
POWER AND GROUND
VCC2 POWER +3.3 volt I/O power supply.
VCC1 POWER +2.5 volt digital logic power supply.
AVCC25 POWER +2.5 volt analog power supply.
AVCC33 POWER +3.3 volt analog power supply.
AVSS GROUND Analog Ground

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 IP100A LF
Preliminary Data Sheet
PIN NAME PIN TYPE PIN DESCRIPTION
GND GROUND Power return.
TABLE 2 : IP100A LF Pin Descriptions

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 IP100A LF
Preliminary Data Sheet
4 Acronyms and Glossary
LAN Local Area Network
MAC Media Access Control Layer, or a device implementing the functions of this layer (a Media
Access Controller)
PCI Peripheral Component Interface
NIC Network Interface Cards
FIFO First In First Out
EPROM Erasable Programmable Read Only Memory
EEPROM Electrically Erasable Programmable Read Only Memory
LED Light Emitting Diode
PHY Physical Layer, or device implementing functions of the Physical Layer
CSMA/CD Carrier Sense Multiple Access with Collision Detect
FCS Frame Check Sequence
SFD Start of Frame Delimiter
CRC Cyclic Redundancy Check
IP Internet Protocol
TFD Transmit Frame Descriptor
RFD Receive Frame Descriptor
DMA Direct Memory Access
ACPI Advanced Configuration and Power Management

5 Standards Compliance
The IP100A LF implements functionality compliant with the following standards:
• IEEE 802.3 Fast Ethernet
• IEEE 802.3 Full Duplex Flow Control
• PCI Local Bus Revision 2.2
• PCI Bus Power Management Interface Revision 1.1
• ACPI Revision 1.0

6 Functional Description
The IP100A LF is composed of various functional blocks as shown in Figure 1 on page 2. An overview of
the functions performed by each block are as follows:

6.1 Media Access Control

The MAC block implements the IEEE Ethernet 802.3 Media Access Control functions with 802.3 Full
Duplex and Flow Control enhancements. In half duplex mode, the MAC implements the CSMA/CD
algorithm. Full duplex mode by definition does not utilize CSMA/CD, allowing data to be transmitted on
demand. An optional flow control mechanism in full duplex mode is provided via the MAC Control PAUSE
function. Additionally, the MAC also performs the following functions in either half or full duplex mode:
• Optional transmit FCS generation
• Padding to the minimum legal frame size
• Preamble and SFD generation
• Preamble and SFD removal
• Receive frame FCS checking and optional FCS stripping
• Receive frame destination address matching
• Support for multicast and broadcast frame reception or rejection (via filtering)
• Selective InterFrame Gap to avoid capture effect
• MAC Loopback
The MAC is responsible for generation of hardware signals to update the internal statistics counters.

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 IP100A LF
Preliminary Data Sheet

6.2 Physical Layer

The IP100A LF supports both IEEE 802.3 100BASE-TX and 100BASE-FX signaling. The 100BASE-X
transmit logic performs 4B5B encoding/decoding, parallel to serial, and serial to parallel conversion, and
NRZ-NRZI signaling. In the case of 100BASE-TX, scrambling and MLT-3 encoding are also done before
the data is transmitted on to the media. The receive 100BASE-X circuitry, recovering data from either an
MLT-3 signal (100BASE-TX) or a PECL input (100BASE-FX), generates four bit nibbles to send to the MAC.

The Media Dependent Interface selection is done by the FFSD pin. If the FFSD pin is connected directly
to GND, the IP100A LF PHY layer is operating in TX mode. If FFSD is connected to the signal detect,
then the PHY layer is in 100BASE-FX mode.

The IP100A LF PHY also includes a full set of registers for controlling the PHY as outlined in the IEEE
802.3 specification.

6.3 On-Chip Voltage Regulator

The IP100A LF has an integrated voltage regulator for reduced system cost. The voltage regulator is used
to provide the 2.5 V power to the PCB. When used with a 2N2905 PNP transistor based circuit as shown in
Figure 2, the CTRL25 pin will regulate the current through the transistor, providing a stable 2.5 V reference.
VCC2 VCC1

IP100A LF
MMBT2907A
Voltage
CTRL25 Comparator
150 inside IC

2.2K, 1%

33 2.0K, 1%

0.1u

FIGURE 2: External PNP Transistor Based Regulator Circuit

6.4 PCI Bus Interface

The PCI Bus Interface implements the protocols and signals needed to operate the IP100A LF in a PCI
bus. The IP100A LF can be either a PCI bus master or slave. The PCI Bus Interface is also responsible
for managing the DMA interfaces and the host processors access to the IP100A LF registers. Arbitration
logic within the PCI Bus Interface block accepts bus requests from the TxDMA Logic and RxDMA Logic.

The PBI also manages interrupt generation for a host processor.

6.5 TxDMA Logic

The IP100A LF supports a multi-frame, multi-fragment DMA gather process. Descriptors representing
frames are built and linked in system memory by a host processor. The TxDMA Logic is responsible for
transferring the multi-fragment frame data from the host memory into the TxFIFO.

The TxDMA Logic monitors the amount of free space in the TxFIFO, and uses this value to decide when
to request a TxDMA. A TxDMABurstThresh register is used to delay the bus request until there is enough
free space in the TxFIFO for a long burst.

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To prevent a TxFIFO under run condition the TxDMA logic forwards an urgent request to the arbiter,
regardless of the TxDMABurstThresh constraint, when the number of occupied bytes in the TxFIFO
drops below the value in TxDMAUrgentThresh register.

6.6 TxFIFO
The IP100A LF uses 2K bytes of transmit data buffer between the TxDMA Logic and Transmit MAC.
When the TxDMA logic determines there is enough space available in the TxFIFO, the TxDMA Logic will
move any pending frame data into the TxFIFO. The TxReleaseThresh register value determines the
amount of data which must be transmitted out of the TxFIFO before the FIFO memory space occupied by
that data can be released for use by another frame.

A TxReleaseError occurs when a frame experiences a collision after the TxFIFO release threshold has
been crossed. The IP100A LF will not be able to retransmit this frame from the TxFIFO and the complete
frame must be transferred from the host system memory to the TxFIFO again by TxDMA Logic.

6.7 RxDMA Logic

The IP100A LF supports a multi-frame, multi-fragment DMA scatter process. Descriptors representing
frames are built and linked in system memory by the host processor. The RxDMA Logic is responsible for
transferring the frame data from the RxFIFO to the host memory.

The RxDMA Logic monitors the number of bytes in the RxFIFO. After a number of bytes have been
received, the frame is “visible”. A frame is visible if:
• The frame being received is determined not to be a runt, OR
• The entire frame has been received

After a frame becomes visible, the RxDMA Logic will issue a request to the arbiter when the number of
bytes in the RxFIFO is greater than the value in the RxDMABurstThresh. To prevent receive overruns, a
RxDMA Urgent Request is made when the amount of free space in the RxFIFO falls below the value in
RxDMAUrgentThresh.

6.8 RxFIFO
The IP100A LF uses 2K bytes of receive data buffer between the Receive MAC and RxDMA Logic. The
values in RxDMABurstThresh determine how many bytes of a frame must be received into RxFIFO
before RxDMA Logic is allowed to begin data transfer.

6.9 EEPROM Interface

The external serial EEPROM is used for non-volatile storage of such information as the node address,
system ID, and default configuration settings. As part of initialization after system reset, the IP100A LF
reads from the EEPROM and places the data into certain host-accessible registers. IP100A LF is able to
read and write to 93LC46 series EEPROM. The correct connection is shown in section 17.2.

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Preliminary Data Sheet

7 Operation
7.1 Initialization
The IP100A LF provides several resets. The assertion of the hardware reset signal on the PCI bus
causes a complete reset of the IP100A LF. A similar reset is available via software using the GlobalReset
bit of the AsicCtrl register. The AsicCtrl register also allows for selective reset of particular functional
blocks of the IP100A LF. See the Registers and Data Structures section for details on using the AsicCtrl
register for resetting the IP100A LF.

Shortly after reset, the IP100A LF will read the contents of an external EEPROM, placing the data read
into the following registers:
• ConfigParm
• AsicCtrl (least significant 16 bits)
• SubsystemVendorId
• SubsystemId
• StationAddress
• Data

There are several other registers which must be configured by the host during initialization. These registers
include the IP100A LF PCI configuration registers which are set during a Power On Self Test (POST)
routine performed by the host system. Specifically, the registers set during this stage of initialization are:
• ConfigCommand enables adapter operation by allowing it to respond to and generate PCI bus cycles.
ConfigCommand is also used to enable parity error generation.
• loBaseAddress sets the I/O base address for the IP100A LF registers.
• MemBaseAddress sets the memory base address for the IP100A LF registers.
• ExpRomBaseAddress sets the base address and size for an installed expansion ROM, if any.
• CacheLineSize indicates the system’s cache line size. This value is used by the IP100A LF to
optimize bus master data transfers.
• LatencyTimer sets the length of time the IP100A LF can hold the PCI bus as a bus master.
• InterruptLine maps IP100A LF’s interrupt request to a specific interrupt line (level) on the system
board.
• AsicCtrl is used to setup internal operations and parameters.

The IP100A LF can be accessed across the PCI bus without setting the PCI registers or loading data
from an external EEPROM. In this Forced Configuration mode (useful for embedded applications without
an EEPROM), the IP100A LF is configured as follows:
• I/O base address 0x200
• I/O target cycles enabled
• Memory target cycles disabled
• Bus master cycles enabled

7.2 Register Programming

After initialization, an additional set of registers specific to operation of the Ethernet network must be
programmed.

The first setting relates to the Auto-Negotiation function. The IP100A LF PHY layer performs the
Auto-Negotiation process, and the host system must communicate with the PHY to determine the link
status. Once the result of Auto-Negotiation is determined, if a full duplex mode has been chosen, the
host system must set the FullDuplexEnable bit in the MACCtrl0 register. Other modes chosen during
Auto-Negotiation do not require any IP100A LF register settings.

The ReceiveMode register determines which types of frames, based on address matching mechanism,
the IP100A LF will receive. The end station address is loaded from the EEPROM, or the host system can

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Preliminary Data Sheet
set the address directly. Then, by setting the ReceiveUnicast bit in the ReceiveMode register, the IP100A
LF will receive unicast frames whose destination address matches the value in the StationAddress
register.

The ReceiveMulticastHash bit in ReceiveMode enables a filtering mechanism for Ethernet multicast
frames. This filtering mechanism uses a 64-bit hash table (HashTable register) for selective reception of
Ethernet multicast frames.

Additionally, Ethernet frames containing IP multicast destination addresses can also be received by
setting the ReceiveIPMulticast bit in the ReceiveMode register. IP multicast, or Host Extension for IP
Multicasting, datagrams map to frames with Ethernet destination addresses of 0x01005e****** (where *
represents any hexadecimal value).

The MACCtrl0 and MACCtrl1 registers are used to configure parameters including full duplex, flow
control, and statistics gathering.

In half duplex mode, the IP100A LF implements the CSMA/CD algorithm. If multiple nodes on the same
network attempt to transmit simultaneously, a collision will occur resulting in re-transmission. In full
duplex mode, the IP100A LF can transmit and receive frames simultaneously without incurring collisions.
To configure the IP100A LF for full duplex mode operation, the host system must detect a full duplex
physical link via the PHY Status Register, and must set the FullDuplexEnable bit in the MACCtrl0
register.

The IEEE 802.3x Full Duplex standard defines a special frame known as the PAUSE MAC Control frame.
The PAUSE frame is used to implement flow control in full duplex networks allowing stations on opposite
ends of a full duplex link the ability to inhibit transmission of data frames for a specified period of time.
The PAUSE frame format is defined as shown in Figure 3.
LENGTH
FIELD
(BYTES)
DA 0x0180C2000001 6

SA 6

TYPE 0x8808 2

OPCODE 0x0001 2

PAUSE TIME 2

PAD 42

FIGURE 3: PAUSE Frame

Whenever the FlowControlEnable bit in the MACCtrl0 register is set, the IP100A LF looks for any
incoming PAUSE frame. If found, the IP100A LF inhibits transmission of all data frames for the time
specified in the two-byte pause_time field. The pause_time field is specified in slot times relative to the
current data rate; one slot time is 51.2 us at 10 Mbps, and 5.12 us at 100 Mbps. The transmission of
PAUSE frames is the responsibility of the host. The MAC Control frame must be constructed by the host
and placed into the TxFIFO. For end station applications, host system should only accept PAUSE frames,
and not generate them. Flow control is designed to originate from network devices such as switches.

7.3 TxDMA and Frame Transmission

The TxDMA Logic transfers frame data from the host system memory to the IP100A LF based on a

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 IP100A LF
Preliminary Data Sheet
linked list of frame descriptors called TFDs. The host system creates a list of TFDs in system memory,
where each TFD contains the memory locations of one or more fragments of a frame as shown in Figure
4.
HOST SYSTEM MEMORY

TxDMANextPtr

TxFrameControl

1st TxDMAFragAddr

1st TxDMAFragLen

TFD 2nd TxDMAFragAddr

2nd TxDMAFragLen

Last TxDMAFragAddr

Last TxDMAFragLen

1st Data Frag (Buffer)

2nd Data Frag (Buffer)

Last Data Frag (Buffer)

FIGURE 4: TxDMA Data Structure

The TFD format is covered in the Registers and Data Structures section.

The resulting linked list of TFDs is referred to as the TxDMAList, as shown in Figure 5.
HOST SYSTEM MEMORY

TFD1

TFD2

FIGURE 5: TxDMA List of Two TFDs

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Preliminary Data Sheet

In the simple case of a single frame, the host system must create a TFD within the host system memory
containing the addresses and lengths of the fragments of data to be transmitted. The host system must
write zero into TxDMANextPtr since this is the only frame. The host starts the TxDMA Logic by writing
the memory location (a non-zero address) of the TFD into TxDMAListPtr register. The TxDMA Logic
begins transferring data into the IP100A LF.

The IP100A LF first fetches the fragment addresses and fragment lengths from the TFD and writes them
one at a time into registers, which are used to control the data transfer operations. If the TxDMA Logic
transfers more data than can fit into the TxFIFO, an overrun will occur.

The TxDMAListPtr I/O register within the IP100A LF contains the physical address that points to the
head of the TxDMAList. TxDMAListPtr must point to addresses which are on 8-byte boundaries. A value
of zero in the TxDMAListPtr register implies there are no pending TFD’s for the IP100A LF to process.

Generally, it is desirable for the host system to queue multiple frames. Multiple TFD’s are linked together
in a list by pointing the TxDMANextPtr of each TFD at the next TFD. The last TFD in the linked list should
have a value of zero for it’s TxDMANextPtr.

The TxDMA process returns to the idle state upon detection of a zero value for TxDMANextPtr. When a
new frame is available to transfer, the host system must write the address of the new TFD into the
TxDMANextPtr memory location of the last TFD, and either set the TxEnable bit, or utilize the IP100A
LF’s automatic polling capability. Using automatic polling, the IP100A LF will monitor the TxDMANextPtr
memory location until a non-zero value is found at that location in system memory. The
TxDMAPollPeriod register controls this polling function, which is enabled when TxDMAPollPeriod
contains a non-zero value. The value written to TxDMAPollPeriod determines the TxDMANextPtr polling
interval.

In response to a TxDMAComplete interrupt, when data transfer by TxDMA is finished, the host
acknowledges the interrupt and returns the frame data buffers to the system. In the case of a multi-frame
TxDMAList, multiple frames may have been transferred by TxDMA when the host system enters its
interrupt service routine. The host system can traverse the list of TFD’s, examining the TxDMAComplete
bit in each TFD to determine which frames have been transferred by TxDMA.

The IP100A LF fetches the TFC before frame data transfer, and again at the end of TxDMA operation to
examine the TxDMAIndicate bit. This allows the host system to change TxDMAIndicate while data transfer
of the frame is in progress. For instance, a frame’s TFD might be at the end of the TxDMAList when it starts
TxDMA, so the host system would probably set TxDMAIndicate to generate an interrupt. However, if
during the TxDMA process of this frame, the host system added a new TFD to the end of the list, it might
clear TxDMAIndicate in the currently active TFD so that the interrupt is delayed until the next TFD.

The IP100A LF has the ability to automatically round up the length of a transmit frame. This is useful in
some NOS environments in which frame lengths need to be an even number of words. The frame length is
rounded up to either a word or dword boundary, depending upon the value of WordAlign. Host systems
may disable frame length word-alignment by setting the WordAlign bits in the TransmitFrameControl to x1.

The MAC will initiate frame transmission (if transmission is enabled) as soon as either the entire frame is
resident in the TxFIFO register.

As a frame transmits out of the TxFIFO, it is desirable to be able to release the FIFO space so that it may
be used for another frame. The value programmed into TxReleaseThresh determines how much of a
frame must be transmitted before its FIFO space can be released.

7.4 Frame Reception and RxDMA

The frame RxDMA mechanism is similar to the TxDMA mechanism. RxDMA is structured around a

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 IP100A LF
Preliminary Data Sheet
linked list of frame descriptors, called RFDs. RFDs contain pointers to the fragment buffers into which the
IP100A LF is to place receive data, as shown in Figure 6.
HOST SYSTEM MEMORY

RxDMANextPtr

RxFrameStatus

1st RxDMAFragAddr

1st RxDMAFragLen

RFD 2nd RxDMAFragAddr

2nd RxDMAFragLen

Last RxDMAFragAddr

Last RxDMAFragLen

1st Data Frag (Buffer)

2nd Data Frag (Buffer)

Last Data Frag (Buffer)

FIGURE 6: RxDMA Data Structure

The RFD format is covered in the Registers and Data Structures section.

Similar to TFDs, the resulting linked list of RFDs is referred to as the RxDMAList. One option available to
RxDMA that differs from TxDMA is that the RxDMAList can be formed into a ring as shown in Figure 7. A
host system can allocate a number of full size frame buffers, create a RFD for each one, and link the
RFDs into a circular list. As frames are received and transferred by RxDMA, a RxDMAComplete interrupt
will be generated for each frame.

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HOST SYSTEM MEMORY

RFD 1

RFD 2

RFD n

FIGURE 7: RxDMA List Shown in Ring

The host system must create a RxDMAList and the associated buffers prior to reception of a frame. One
approach calls for the host system to allocate a block of full size (i.e. large enough to hold a maximum
size Ethernet frame of 1518 bytes) frame buffers in system data space and create RFDs that point to
them. Another approach is for the host system to request the buffers from the protocol ahead of time.

After reset, the IP100A LF receive function is disabled. Once the RxEnable bit is set, frames will be
received according to the matching mode programmed in ReceiveMode register. Reception can be
disabled by setting the RxDisable bit. If set while a frame is being received, RxDisable only takes effect
after the active frame reception is finished.The receive function begins with the RxDMA Logic in the idle
state. The RxDMA Logic will begin processing a RxDMAList as soon as a non-zero address is written
into the RxDMAListPtr register. The host system creates a RFD with the addresses and lengths of the
buffers to be used and programs the RxDMAListPtr register to point to the head of the list. The host
system must program a zero into the RxDMANextPtr of the last RFD to indicate the end of the
RxDMAList. When a frame is received in the RxFIFO, the IP100A LF fetches the fragment address and
fragment length values one by one from the current RFD, and writes these values into internal registers
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transferred by RxDMA. The host system can read RxDMAListPtr to determine which RFDs in the list
have been used. The host system begins at the head of the RFD list, and traverses the list until it
reaches the RFD whose address matches RxDMAListPtr. However, since I/O operations are costly, it is
more efficient to use the RxDMAComplete bit in each RFD to determine which frames have been
transferred by RxDMA.
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Preliminary Data Sheet

In some host systems, it may be desirable to copy received frame data out of the scatter buffer to the
protocol buffer while the frame is still being transferred by RxDMA. The RxDMAStatus register is
provided for this purpose. If the host system sets the RxDMAHalt bit in the DMACtrl register, reads the
RxDMAListPtr register and the RxDMAStatus register, then sets the RxDMAResume bit in the DMACtrl
register, the host system can determine how much of the frame has been transferred by RxDMA. The
RxDMAStatus register indicates the number of bytes transferred by RxDMA for the current RFD pointed
to by the RxDMAListPtr register. The host system can then perform memory copies out of the RFD buffer
concurrently with the RxDMA operation.

7.5 Interrupts
The term “interrupt” is used loosely to refer to interrupts and indications. An interrupt is the actual assertion
of the hardware interrupt signal on the PCI bus. An indication, or a set bit in the IntStatus register, is the
reporting of any event enabled by the host. The host system will configure the IP100A LF to generate an
interrupt for any indication that is of interest to it. There are 10 different types of interrupt indications that
can be generated by the IP100A LF. The IntEnable register controls which of the 10 indication bits can
assert a hardware interrupt. In order for an indication bit to be allowed to generate an interrupt, its
corresponding bit-position in IntEnable must be set. When responding to an interrupt, the host reads the
IntStatus register to determine the cause of the interrupt. The least significant bit of IntStatus,
InterruptStatus, is always set whenever any of the interrupts are asserted. InterruptStatus must be explicitly
acknowledged (cleared) by writing a 1 into the bit in order to prevent spurious interrupts on the host bus.

Interrupts are acknowledged by the host carrying out various actions specific to each interrupt.

8 Statistics
The IP100A LF implements 16 statistics counters of various widths. Each statistic implemented complies
to the corresponding definition given in the IEEE 802.3 standard. Setting the StatisticsEnable bit in the
MACCtrl1 register enables the gathering of statistics. Reading a statistics register will clear the read
register. Statistic registers may be read without disabling statistics gathering. For diagnostics and testing
purposes, the host system may write a value to a statistic register, in which case the value written is
added to the current value of the register. Whenever one or more of the statistics registers reaches 75%
of its maximum value, an UpdateStats interrupt is generated. Reading that statistics register will
acknowledge the UpdateStats interrupt. A summary of the transmit and receive statistics follows.
Detailed descriptions of the statistic registers related to data transmission and reception can be found in
the Registers and Data Structures section.

8.1 Transmit Statistics

• FramesTransmittedOk: The number frames of all types transmitted without errors. Loss of carrier is
not considered to be an error by this statistic.
• BroadcastFramesTransmittedOk: The number of frames with broadcast destination address that are
transmitted without errors.
• MulticastFramesTransmittedOk: The number of frames with multicast destination address that are
transmitted without errors.
• OctetsTransmittedOk: The number of total octets for all frames transmitted without error.
• FramesWithDeferredXmission: A count of frames whose transmission was delayed on it’s first
attempt because network traffic.
• FramesWithExcessiveDeferral: If the transmission of a frame has been deferred for an excessive
period of time due to network traffic, the event is recorded in this statistic.
• SingleCollisionFrames: Frames that are transmitted without errors after one and only one collision
(including late collisions) are counted by this register.
• MultipleCollisionFrames: All frames transmitted without error after experiencing from 2 through 15
collisions (including late collisions) are counted here.

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• LateCollisions: Every occurrence of a late collision (there could be more than one per frame
transmitted) is counted by this statistic.
• FramesAbortedDueToXSColls: If the transmission of a frame had to be aborted due to excessive
collisions, the event is recorded in this statistic.
• CarrierSenseErrors: Frames that were transmitted without error but experienced a loss of carrier are
counted by this statistic.

8.2 Receive Statistics

• FramesReceivedOk: Frames of all types that are received without error are counted here.
• BroadcastFramesReceivedOk: Frames of broadcast destination address that are received without
error are counted here.
• MulticastFramesReceivedOk: Frames of multicast destination address that are received without
error are counted here.
• OctetsReceivedOk: A total octet count for all frames received without error.
• FramesLostRxErrors: This is a count of frames that would otherwise be received by the IP100A LF,
but could not be accepted due to an overrun condition in the RxFifo.

9 PCI Bus Master Operation

The IP100A LF supports all of the PCI memory commands and decides on a burst-by-burst basis which
command to use in order to maximize bus efficiency. The list of PCI memory commands is shown below.
For all commands, “read” and “write” are with respect to the IP100A LF (i.e. read implies the IP100A LF
obtains information from an off-chip location, write implies the IP100A LF sends information to an off-chip
location).
• Memory Read (MR)
• Memory Read Multiple (MRM).
• Memory Write (MW)
• Memory Write Invalidate (MWI)

MR is used for all fetches of descriptor information. For reads of transmit frame data, MR, or MRM is
used, depending upon the remaining number of bytes in the fragment, the amount of free space in the
TxFIFO, and whether the RxDMA Logic is requesting a bus master operation.

MW is used for all descriptor writes. Writes of receive frame data use either MW or MWI, depending
upon the remaining number of bytes in the fragment, the amount of frame data in the RxFIFO, and
whether the TxDMA Logic is requesting a bus master operation.

The IP100A LF provides three configuration bits to control the use of advanced memory commands. The
MWlEnable bit in the ConfigCommand configuration register allows the host to enable or disable the use
of MWI. The MWIDisable bit in DMACtrl allows the host system the ability to disable the use of MWI.
MWIDisable is cleared by default, enabling MWI.

The IP100A LF provides a set of registers that control the PCI burst behavior. These registers allow a
trade-off to be made between PCI bus efficiency and under run/overrun frequency. Arbitration logic
within the PCI Bus Interface block accepts bus requests from the TxDMA Logic and RxDMA Logic. The
TxDMA Logic uses the TxDMABurstThresh register, as described in the TxDMA Logic section, to delay
the bus request until there is enough free space in the TxFIFO for a long, efficient burst. The TxDMA
Logic can also make an urgent bus request as described in the TxDMA Logic section, where burst
efficiency is sacrificed in favor of avoiding a TxFIFO under run condition.

The RxDMA process is described in the RxDMA Logic section. Typically, RxDMA requests will be forwarded
to the Arbiter, however RxDMA Urgent Requests are also possible in order to prevent RxFIFO overruns.

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10 Power Management
The IP100A LF supports operating system directed power management according to the ACPI
specification. Power management registers in the PCI configuration space, as defined by the PCI Bus
Power Management Interface specification, Revision 1.0 are described in 10.0.

The IP100A LF supports several power management states. The PowerState field in the PowerMgmtCtrl
register determines IP100A LF’s current power state. The power states are defined as follows:
• D0 Uninitialized (power state 0) is entered as a result of hardware reset, or after a transition from D3
Hot to D0. This state is the same as D0 Active except that the PCI configuration registers are
uninitialized. In this state, the IP100A LF is unable to respond to PCI I/O, memory and configuration
cycles and can not operate as a PCI master The IP100A LF cannot signal wake (PMEN) from the D0
state.
• D0 Active (power state 0) is the normal operational power state for the IP100A LF. In this state, the
PCI configuration registers have been initialized by the system, including the IoSpace,
MemorySpace, and Bus-Master bits in ConfigCommand, so the IP100A LF is able to respond to PCI
I/O, memory and configuration cycles and can operate as a PCI master. The IP100A LF cannot
signal wake (PMEN) from the D0 state.
• D1 (power state 1) is a “light-sleep” state. The IP100A LF optionally supports this state determined
by the D1Support bit in the ConfigParm word in EEPROM. The D1 state allows transition back to D0
with no delay. In this state, the IP100A LF responds to PCI configuration accesses, to allow the
system to change the power state. In D1 the IP100A LF does not respond to any PCI I/O or memory
accesses. The IP100A LF’s function in the D1 state is to recognize wake events and link state events
and pass them on to the system by asserting the PMEN signal on the PCI bus.
• D2 (power state 2) is a partial power-down state. The IP100A LF optionally supports this state
determined by the D2Support bit in the ConfigParm word in EEPROM. D2 allows a faster transition
back to D0 than is possible from the D3 state. In this state, the IP100A LF responds to PCI
configuration accesses, to allow the system to change the power state. In D2 the IP100A LF does
not respond to any PCI I/O or memory accesses. The IP100A LF’s function in the D2 state is to
recognize wake events and link state events and pass them on to the system by asserting the PMEN
signal on the PCI bus.
• D3 Hot (power state 3) is the full power-down state for the IP100A LF. In D3 Hot, the IP100A LF
loses all PCI configuration information except for the value in PowerState. In this state, the IP100A
LF responds to PCI configuration accesses, to allow the system to change the power state back to
D0 Uninitialized. In D3 hot, the IP100A LF does not respond to any PCI I/O or memory accesses.
The IP100A LF’s main responsibility in the D3 Hot state is to recognize wake events and link state
events and signal those to the system by asserting the PMEN signal on the PCI bus.
• D3 Cold (power state undefined) is the power-off state for the IP100A LF. The IP100A LF does not
function in this state. When power is restored, the system guarantees the assertion of hardware
reset, which puts the IP100A LF into the D0 Uninitialized state.

The IP100A LF can generate wake events to the system as a result of Wake Packet reception, Magic
Packet reception, or due to a change in the link status. The WakeEvent register gives the host system
control over which of these events are passed to the system. Wake events are signaled over the PCI bus
using the PMEN pin.

A Wake Packet event is controlled by the WakePktEnable bit in WakeEvent register. WakePktEnable
has no effect when IP100A LF is in the D0 power state, as the wake process can only take place in
states D1, D2, or D3. When the IP100A LF detects a Wake Packet, it signals a wake event on PMEN (if
PMEN assertion is enabled), and sets the WakePktEvent bit in the WakeEvent register. The IP100A LF
can signal that a wake event has occurred when it receives a pre-defined frame from another station.
The host system transfers a set of frame data patterns into the transmit FIFO using the transmit DMA
function before placing the IP100A LF in a power-down state. Once powered down, the IP100A LF
compares receive frames with the frame patterns in the transmit FIFO. When a matching frame is
received (and also passes the filtering mode set in the ReceiveMode register), a wake event is signaled.
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Preliminary Data Sheet

The frame patterns in the transmit FIFO specify which bytes in received frames are to be examined.
Each byte in the transmit FIFO specifies a four bit relative offset (from the start of the received frame) in
the most significant nibble and a four bit length indicator in the least significant nibble. Relative offsets
describe the number of bytes of the received frame to skip from the last relevant byte, beginning with
byte 0x00. Relative offsets with a value of 0xF indicate the actual relative offset is larger than 15, and is
specified by the next 8 bit value in the transmit FIFO. Length indicators with a value of 0xF indicate the
actual length indicator is larger than 15, and is specified by the next 8 bit value in the transmit FIFO. If
both the relative offset, and the length indicator are 0xF, the first byte following the relative offset/length
indicator pair is the actual relative offset, and the second following byte is the actual length indicator. A
byte value of 0x00 indicates the end of the pattern for that wake frame. Immediately following the
end-of-pattern is a 4-byte CRC. The calculation used to for the CRC is the same polynomial as the
Ethernet MAC FCS.

An example pseudo-packet (based on the ARP packet example from Appendix A of the “OnNow
Network Device Class Power Management Specification”) which would be loaded into the transmit FIFO
of the IP100A LF is shown in Figure 8.
TxFIFO
0xc2
0x71
0xf4
0x10
pseudo
0x00
packet
0xf3
0x19
0x08
0xd7

FIGURE 8: Example Pseudo Packet

Using the pseudo packet in Figure 8, the IP100A LF will assert a wake event if a packet of the form
shown in Figure 9 is received whereby a 32-bit CRC over the indicated bytes of the received packet
yields the value 0xf31908d7.

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Preliminary Data Sheet
Byte Offset
Received Packet
Within Packet

byte 12 0x0c
byte 13 0x0d

byte 21 0x15

byte 38 0x26
byte 39 0x27
byte 40 0x28
byte 41 0x29

FIGURE 9: Example Wake Packet

The IP100A LF also supports Magic Packet™ technology developed by Advanced Micro Devices to
allow remote wake-up of a sleeping station on a network via transmission of a special frame. Once the
IP100A LF has been placed in Magic Packet mode and put to sleep, it scans all incoming frames
addressed to it for a data sequence consisting of 16 consecutive repetitions of its own 48-bit Ethernet
MAC StationAddress. This sequence can be located anywhere within the frame, but must be preceded
by a synchronization stream.

The synchronization stream is defined as 6 bytes of 0xFF. For example, if the MAC address
programmed into the StationAddress register is 0x11:22:33:44:55:66, then the IP100A LF would be
scanning for the frame data shown in Figure 10.
Received Packet

0xFFFFFFFFFFFF
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566
0x112233445566

FIGURE 10: Example Magic Packet

Magic Packet wake up is controlled by the MagicPktEnable bit in the WakeEvent register. A wake event

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Preliminary Data Sheet
can only take place in the D1, D2, or D3 states, and MagicPktEnable has no effect when the IP100A LF
is in the D0 power state. The Magic Packet must also pass the address matching criteria set in
ReceiveMode. A Magic Packet may also be a broadcast frame. When the IP100A LF detects a Magic
Packet, it signals a wake event on PMEN (if PMEN assertion is enabled), and sets the MagicPktEvent bit
in WakeEvent.

The IP100A LF can also signal a wake event when it senses a change in the network link state, either
from LINK_OK to LINK_FAIL, or vice versa. Link state wake is controlled by the LinkEventEnable bit in
the WakeEvent register. At the time LinkEventEnable is set by the host system, the IP100A LF samples
the current link state. It then waits for the link state to change. If the link state changes before the IP100A
LF returns to state D0 or LinkEventEnable is cleared, LinkEvent is set in WakeEvent, and (if it is enabled)
the PMEN signal is asserted.

10.1 Wake Event

When a desired wake event occurs, the IP100A LF sets the appropriate event bit in the WakeEvent
register, sets the PmeStatus bit in the PowerMgmtCtrl register, and asserts the PMEN signal.

The host system responds to PMEN by scanning the power management configuration registers of all
devices, looking for the device which asserted PMEN. If the device with the IP100A LF signaled wake,
the system will find PmeStatus set in IP100A LF’s PowerMgmtCtrl register. The operating system then
clears the PmeEn bit in the PowerMgmtCtrl register causing PMEN to be de-asserted.

The operating system raises the power state (probably to D0) by writing to the PowerState bits in the
PowerMgmtCtrl register. If the IP100A LF was previously in the D3 state, PCI configuration is lost and
must be restored by the operating system.

The host system must set TxReset to clear any wake patterns out of the transmit FIFO (if this is not done,
the patterns will be treated as frames and transmitted once the transmitter is enabled).

The host system reads the WakeEvent register to determine the wake event, and if requested, passes it
back to the operating system. The host system restores any volatile state that was saved in the power
down sequence. The host system re-enables interrupts by programming IntEnable. The host system
restores the RxDMAList (and any other data structures required for operation). Any wake packets in the
receive FIFO are transferred by receive DMA and passed to the operating system.

10.2 Power Down

D0u and D0i are mutually exclusive. The moment that the IoBaseAddress register or the
MemBaseAddress is written by the host, then IP100A LF enters D0u. When D0u is active, the PHY is
completely powered down and all clocks (AsicClk, TxClk, RxClk) are gated off except PciClk. The
IP100A LF consumes less than 70 mA in D0u. Make sure that the LED drivers are off. When IP100A LF
is in D0i, the PHY is powered up and ready to transmit and receive packets. In Forced Config mode
(motherboard applications), IP100A LF is always in D0i mode. Another way to indicate D0u is to check
the non-zero value in the programmable field of IoBaseAddress or MemBaseAddress. In WOL the PHY
should be fully functional to receive Magic Packets. In WOL mode, D0u should be forced to low before
passing to the PHY.

When in the D3 state, if PMEN is de-asserted on the PCI bus the IP100A LF will enter Power Down.
When in Power Down mode, the PHY is completely powered down. All clocks (AsicClk, TxClk, RxClk)
except PciClk are gated off. When the PCI bus is powered down, the IP100A LF consumes less than 5
mA.

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Preliminary Data Sheet
11 Registers and Data Structures
11.1 PHY Registers
The IP100A LF includes a full set of PHY registers which can be accessed through the internal
MDC/MDIO interface. The MAC and PHY, although integrated, act as if they are separate. The PHY
registers must be accessed throught the PhyCtrl register.

11.1.1 Control Register

Class............................. PHY Registers, Control
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x00
Default .......................... 0x3100
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15 Reset R/W 1 = Software Reset (self clearing). While the IP100A LF is
resetting, Reset will remain a logic 1 and write attempts to any
PHY Registers are not accepted.
0 = Normal operation.
14 Loopback R/W 1 = PHY loopback mode. When Loopback is a logic 1, the IP100A
LF will be isolated from the network media. All transmit data
from the MAC will return to the MAC as receive data. Collision
indications are disabled unless Collision Test is a logic 1.
0 = Normal operation.
13 Speed R/W 1 = 100 Mb/s.
0 = 10 Mb/s.
12 Auto-Negotiation R/W 1 = Auto-negotiation enabled.
0 = Auto-negotiation disabled.
11 Power Down R/W 1 = PHY power down. When Power Down is a logic 1, the IP100A
LF PHY will enter Power Down mode. While in Power Down
mode, the IP100A LF PHY will not respond to transmit data, or
received data but will respond to management transactions.
0 = Normal operation.
10 Isolate R/W 1 = Isolate PHY. When Isolate is a logic 1, the IP100A LF PHY
will be isolated from the MAC. When isolated, the IP100A LF
will not respond to transmit or receive data, but will respond to
management transactions.
0 = Normal operation.
9 Restart R/W 1 = Restart auto-negotiation (self clearing). When Restart
Auto-Negotiation Auto-Negotiation is a logic 1, the IP100A LF will restart
Auto-Negotiation, depending on the Auto-Negotiation bit. If
the Auto-Negotiation bit is a logic 0, then Restart
Auto-Negotiation has no effect.
0 = Normal operation.
8 Duplex Mode R/W 1 = Full duplex.
0 = Half duplex.

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BIT BIT NAME R/W BIT DESCRIPTION
7 Collision Test R/W 1 = Enable COL test. If Collision Test is a logic 1 and transmit
data is sent to the PHY, the IP100A LF PHY will assert the
collision signal within 512 bit times (where 1 bit time = 100ns
for 10Mbps operation and 1 bit time = 10ns for 100Mbps
operation). When transmit data is removed, the IP100A LF
PHY will deassert the collision signal within 4 bit times.
0 = Normal operation.
6..0 Reserved N/A Reserved for future use.

11.1.2 Status Register

Class............................. PHY Registers
Access Method............. Accessed through PhyCtrl register
Register Address.......... 0x01
Default .......................... 0x7849
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15 100BASE-T4 R 1 = PHY 100BASE-T4 capable.
0 = PHY not 100BASE-T4 capable.
14 100BASE-X Full R 1 = PHY 100BASE-X Half Duplex capable.
Duplex 0 = PHY not 100BASE-X Half Duplex capable.
13 100BASE-X Half R 1 = PHY 100BASE-X Half Duplex capable.
Duplex 0 = PHY not 100BASE-X Half Duplex capable.
12 10BASE-T Full R 1 = PHY 10BASE-T Full Duplex capable.
Duplex 0 = PHY not 10BASE-T Full Duplex capable.
11 10BASE-T Half R 1 = PHY 10BASE-T Half Duplex capable.
Duplex 0 = PHY not 10BASE-T Half Duplex capable.
10..7 Reserved N/A Reserved for future use.
6 Preamble R 1 = Management preamble may be suppressed.
Suppression 0 = Management preamble required.
5 Auto-Negotiation R 1 = Auto-Negotiation complete.
Complete 0 = Auto-Negotiation not complete.
If Auto-Negotiation Complete is a logic 1, the auto-negotiation
process is complete and the contents of the Auto-Negotiation Link
Partner Ability and Auto-Negotiation Expansion registers are
valid. If Auto-Negotiation Complete is a logic 0, the
Auto-Negotiation process is not complete, and the contents of the
Auto-Negotiation Link Partner Ability and Auto-Negotiation
Expansion registers are undefined. If the Auto-Negotiation bit of
the Control Register is a logic 0, then Auto-Negotiation Complete
is always a logic 0.
4 Remote Fault R 1 = Remote Fault detected.
0 = Remote Fault not detected.
If Remote Fault is a logic 1, the IP100A LF has detected a remote
fault condition. Remote Fault will remain a logic 1 until the remote
fault condition no longer exists, and Remote Fault is read by the
host system.

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BIT BIT NAME R/W BIT DESCRIPTION
3 Auto-Negotiation R 1 = Auto-Negotiation capable.
Ability 0 = Auto-Negotiation incapable.
If Auto-Negotiation Ability is a logic 1, the IP100A LF is capable of
performing Auto-Negotiation. Auto-Negotiation Ability depends on
the external mode setting of the IP100A LF.
2 Link Status R 1 = Link is up.
0 = Link is down.
When Link Status is a logic 0, Link Status will remain a logic 0
until the link state changes, and Link Status is read by the host
system.
1 Jabber Detect R 1 = Jabber detected.
0 = Jabber not detected.
When Jabber Detect is a logic 1, Jabber Detect will remain a logic
0 until the jabber condition no longer exists, and Jabber Detect is
read by the host system.
0 Extended Capability R 1 = Extended capabilities register exists.

11.1.3 PHY Identifier 1

Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x02
Default .......................... 0x0243
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..0 PHY ID Number R Bits 3 through 18 of the OUI.
OUI = 0090C3

11.1.4 PHY Identifier 2

Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x03
Default .......................... 0x0D80
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..10 PHY ID Number R Bits 19 through 24 of the OUI.
9..4 Model Number R Manufacturer’s model number.
3..0 Revision Number R Four bit manufacturer’s revision number.

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11.1.5 Auto-Negotiation Advertisement
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x04
Default .......................... 0x01E1
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15 Next Page capable R/W 1 = Next Page capable.
0 = Next Page incapable.
14 Reserved N/A Reserved for future use.
13 Remote Fault R/W 1 = Remote Fault supported.
0 = Remote Fault not supported.
12..11 Reserved N/A Reserved for future use.
10 Pause R/W 1 = Pause function supported.
0 = Pause not supported.
9 100BASE-T4 R/W 1 = 100BASE-T4 capable.
0 = 100BASE-T4 incapable.
8 100BASE-TX Full R/W 1 = PHY 100BASE-TX Full Duplex capable.
Duplex 0 = PHY not 100BASE-TX Full Duplex capable.
7 100BASE-TX Half R/W 1 = PHY 100BASE-TX Half Duplex capable.
Duplex 0 = PHY not 100BASE-TX Half Duplex capable.
6 10BASE-T Full R/W 1 = PHY 10BASE-T Full Duplex capable.
Duplex 0 = PHY not 10BASE-T Full Duplex capable.
5 10BASE-T Half R/W 1 = PHY 10BASE-T Half Duplex capable.
Duplex 0 = PHY not 10BASE-T Half Duplex capable.
4..0 Selector Field R/W IEEE 802.3 selector field

11.1.6 Auto-Negotiation Link Partner Ability

Class............................. PHY Registers
Access Method............. Accessed through PhyCtrl register
Register Address.......... 0x05
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15 Next Page R 1 = Next Page capable.
0 = Next Page incapable.
14 Acknowledge R 1 = Link Code Word received.
0 = Link Code Word not received.
13 Remote Fault R 1 = Remote Fault detected.
0 = Remote Fault not detected.
If Remote Fault is a logic 1, then the Remote Fault bit of the
Status Register register will be a logic 1.
12..10 Reserved N/A Reserved for future use.
9 100BASE-T4 R 1 = 100BASE-T4 capable.
0 = 100BASE-T4 incapable.

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BIT BIT NAME R/W BIT DESCRIPTION
8 100BASE-TX Full R 1 = 100BASE-TX Full Duplex capable.
Duplex 0 = Not 100BASE-TX Full Duplex capable.
7 100BASE-TX Half R 1 = 100BASE-TX Half Duplex capable.
Duplex 0 = Not 100BASE-TX Half Duplex capable.
6 10BASE-T Full R 1 = 10BASE-T Full Duplex capable.
Duplex 0 = Not 10BASE-T Full Duplex capable.
5 10BASE-T Half R 1 = 10BASE-T Half Duplex capable.
Duplex 0 = Not 10BASE-T Half Duplex capable.
4..0 Selector Field R Selector Field

11.1.7 Phy Specification Control Register

Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x16
Default .......................... 0x03A4
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15:6 Reserved
5 AUTOMDIX_ON RO AutoCrossOver can be set to enabled by setting this bit to 1, even
when AN is disabled
4 FEF_DISABLE R/W Set high to disable the functionality of Far-End Fault when the
chip operates at fiber mode
0: Enable FEF
1: Disable FEF
3 REPEAT_MODE R/W Set high to let IP100A LF operate at repeat mode
0: Not Repeat mode
1: Repeat mode
2 JABBER_ENA R/W Set high to enable jabber detection mechanism when IP100A LF
operates at 10BASE-T
0: Disable
1: Enable
1 HEARTBEAT_ENA R/W Set high to enable heartbeat detection mechanism when IP100A
LF operates at 10BASE-T
0: Disable
1: Enable
0 BYPASS_DSPRST R/W Set high to disable DSP reset watch-dog timer
0: Not Bypass
1: Bypass

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11.1.8 Phy Debug Control Register
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x17
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15:6 Reserved RO Reserved for future use
5 NWAY_SPEED_UP RW Set high to speed up all timers during NWAY procedure
4 DSP_SPEED_UP RW Set high to speed up DSP training sequcences
3 FORCE_LINK RW Set high to force link-up
2 BYPASS_SCRAM RW Set high to bypass PCS scrambler/de-scrambler
1..0 NWAY_DEBUG_SE RW These 2 bits are used to select NWAY debug output
L

11.1.9 Phy Status Monitor Register

Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x18
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15 LDSP_SLEEPING RO When set to high, indicating IP100A LF is in link-down sleeping
mode
14 LINK_OK RO When set to high, indicating link status is OK
13 DESCRAM _LOCK RO When set to high, indicating PCS de-scrambler is locked on data
12 10BASE_ RO When set to high, indicating the cable polarity is reversal (this bit
POLARITY is meaningful only chip operates at 10BASE-T)
11 RESLOVED RO To indicate the resolved speed mode
_SPEED 0: 10BASE-T
1: 100BASE-TX/FX
10 RESLOVED RO To indicate the resolved duplex mode
_DUPLEX 0: Half Duplex
1: Full Duplex
9 MDI/MDIX RO To indicate either at MDI or MDIX state
0: MDI (Not Crossover)
1: MDIX(Crossover)
8..0 NWAY_DEBUG RO NWAY debug output
_OUT

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Preliminary Data Sheet
11.1.10 SCA Settings
Class............................. PHY Registers
Access Method ............. Accessed through PhyCtrl register
Register Address .......... 0x22
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15 SCA_mode R/W 1=set to SCA mode.
0=default.
14 SCA_chsel R/W 1= Test MDIX channel.
0= Test MDI channel
13..11 Reseverd N/A Reseve for future use
10 SCA_tx_pulse R/W 1= Send a pulse for each write operation
0= do nothing
9..8 SCA_phase R/W 00= phase do not increment
01= phase increment by 1 for each write operation
11= phase decrement by 1 for each write operation
10= Reserved
7..0 SCA_capture_len R/W ADC outputs capture time after sending a pulse. The value must
be greater than 0 for a capture event

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 IP100A LF
Preliminary Data Sheet
11.2 DMA Data Structures
A TFD is used to move data destined for transmission onto an Ethernet network, from the host system
memory to the transmit FIFO within the IP100A LF. A TFD is 16 to 512 bytes in length, and it’s location in
host system memory is indicated by the value in the TxDMAListPtr register.

A RFD is used to move data obtained from an Ethernet network, from the receive FIFO within the IP100A
LF to the host system memory. A RFD is 16 to 512 bytes in length, and it’s location in host system
memory is indicated by the value in the RxDMAListPtr register. There are two formats for an RFD,
differentiated by the ImpliedBufferEnable bit of the RxFrameStatus field.

Figure 11 shows the two DMA data structures.

HOST SYSTEM MEMORY HOST SYSTEM MEMORY

Offset from Offset from
TFD Start RFD Start

TxDMANextPtr 0x00 RxDMANextPtr 0x00

TxFrameControl 0x04 RxFrameStatus 0x04

TxDMAFragAddr0 0x08 RxDMAFragAddr0 0x08

TxDMAFragLen0 0x0c RxDMAFragLen0 0x0c

TFD TxDMAFragAddr1 0x10 RFD RxDMAFragAddr1 0x10

TxDMAFragLen1 0x14 RxDMAFragLen1 0x14

TxDMAFragAddrn 0x08+n*0x08 RxDMAFragAddrn 0x08+n*0x08

TxDMAFragLenn 0x0C+n*0x08 RxDMAFragLenn 0x0C+n*0x08

FIGURE 11: TFD and RFD DMA Data Structures

11.2.1 RxDMAFragAddr
Class............................. DMA Data Structures, RFD
Base Address ............... Start of RFD
Address Offset .............. 0x08+n*0x08 for nth fragment (where n=0,1,...63)
Access Mode ................ Read/Write
Width ............................ 32 bits

BIT BIT NAME BIT DESCRIPTION

31..0 RxDMAFragAddr Receive DMA Fragment Address. The RxDMAFragAddr contains the
physical address of a contiguous block of system memory to which
receive data is to be transferred by receive DMA. A fragment can start on
any byte boundary.

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Preliminary Data Sheet
11.2.2 RxDMAFragLen
Class............................. DMA Data Structures, RFD
Base Address ............... Start of RFD
Address Offset .............. 0x0C+n*0x08 for nth fragment (where n=0,1,...63)
Access Mode ................ Read/Write
Width ............................ 32 bits

The RxDMAFragLen contains fragment length and control information for the block of data pointed to by
the corresponding RxDMAFragAddr.

BIT BIT NAME BIT DESCRIPTION

12..0 FragLen Fragment Length. The length of the contiguous block of data pointed to
by the previous RxDMAFragAddr.
30..13 Reserved Reserved for future use.
31 RxDMALastFrag Set by the host system to indicate the last fragment of the receive frame.

11.2.3 RxDMANextPtr
Class............................. DMA Data Structures, RFD
Base Address ............... Start of RFD
Address Offset .............. 0x00
Access Mode ................ Read/Write
Width ............................ 32 bits

BIT BIT NAME BIT DESCRIPTION

31..0 RxDMANextPtr Receive DMA Next Pointer. RxDMANextPtr contains the physical
address of the next RFD in the receive DMA list. For the last RFD in the
receive DMA list, RxDMANextPtr must be 0x00000000. RFDs must be
aligned on 8-byte physical address boundaries.

11.2.4 RxFrameStatus
Class............................. DMA Data Structures, RFD
Base Address ............... Start of RFD
Address Offset .............. 0x04
Access Mode ................ Read/Write
Width ............................ 32 bits

At the end of a receive DMA transfer, the IP100A LF writes the value of the RxDMAStatus register to
RxFrameStatus.

BIT BIT NAME BIT DESCRIPTION

12..0 RxDMAFrameLen Receive DMA Frame Length. RxDMAFrameLen indicates the true frame
length, except in the case where the frame is larger than the total number
of bytes specified in all of the FragLen subfields of the RxDMAFragLen
RFD field in which case, the RxDMAOverflow bit will be set.
13 Reserved Reserved for future use.

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BIT BIT NAME BIT DESCRIPTION
14 RxFrameError Receive Frame Error. RxFrameError indicates that an error occurred
during receipt of the frame. The host system should examine
RxFIFOOverrun, RxRuntFrame, RxAlignmentError, RxFCSError, and
RxOversizedFrame to determine the type of error(s). RxFrameError is
undefined until RxDMAComplete is a logic 1.
15 RxDMAComplete Receive DMA Complete. RxDMAComplete indicates the frame transfer
from the IP100A LF to the host system is complete.
16 RxFIFOOverrun Receive FIFO Overrun. RxFIFOOverrun indicates the data was not
removed from the receive FIFO fast enough to keep up with the rate data
was entering the receive FIFO from the media. Bytes may be missing
from the frame at one or more unpredictable locations within the frame.
RxFIFOOverrun is undefined until RxDMAComplete is a logic 1.
17 RxRuntFrame Received Runt Frame. RxRuntFrame indicates the received frame was a
runt (less than 60 bytes in length, measured from the DA field to the end
of the Data field). RxRuntFrame is undefined until RxDMAComplete is a
logic 1.
18 RxAlignmentError Receive Alignment Error. RxRuntFrame indicates that the received frame
had an alignment error. RxAlignmentError is undefined until
RxDMAComplete is a logic 1.
19 RxFCSError Receive Frame Check Sequence Error. RxFCSError indicates a FCS
checksum error on the frame data. RxFCSError is undefined until
RxDMAComplete is a logic 1
20 RxOversizedFrame Receive Oversized Frame. RxOversizedFrame indicates the frame size
was equal to or greater than the value set in the MaxFrameSize register.
RxOversizedFrame is undefined until RxDMAComplete is a logic 1.
22..21 Reserved Reserved for future use.
23 DribbleBits Dribble Bits. DribbleBits indicates that the frame had accompanying
dribble bits. DribbleBits is informational only, and does not indicate a
frame error.
24 RxDMAOverflow Receive DMA Overflow. RxDMAOverflow indicates that the RFD did not
have sufficient buffer space to hold all of the frame data. For this
condition, the IP100A LF transfers as much data as possible and
discards the remainder of the frame.
27..25 Reserved Reserved for future use.
28 ImpliedBufferEnable Implied Buffer Enable. ImpliedBufferEnable enables a special receive
DMA mode. If ImpliedBufferEnable is a logic 1 when the IP100A LF reads
the RFD, the IP100A LF will assume there is one receive buffer of length
1528 bytes, starting immediately after ReceiveFrameStatus at (RFD
address + 0x08).
The host system sets ImpliedBufferEnable when it prepares the RFD.
The IP100A LF tests ImpliedBufferEnable before receive DMA for a
frame begins at the same time it tests the RxDMAComplete bit. When the
IP100A LF updates RxFrameStatus field at the end of the receive DMA
operation (in order to set RxDMAComplete) the value written to
ImpliedBufferEnable is undefined. The host system cannot assume a
certain value is left in ImpliedBufferEnable after the RFD is used.
Therefore, the host system must write the desired value to
ImpliedBufferEnable every time after releasing a RFD to the IP100A LF.
31..29 Reserved Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
11.2.5 TxDMAFragAddr
Class............................. DMA Data Structures, TFD
Base Address ............... Start of TFD
Address Offset.............. 0x08+n*0x08 for nth fragment (where n=0,1,...63)
Access Mode................ Read/Write
Width ............................ 32 bits

BIT BIT NAME BIT DESCRIPTION

31..0 TxDMAFragAddr Transmit Fragment Address. TxDMAFragAddr contains the physical
address of a contiguous block of data to be transferred from the host
system to the IP100A LF. A fragment can start on any byte boundary.

11.2.6 TxDMAFragLen
Class............................. DMA Data Structures, TFD
Base Address ............... Start of TFD
Address Offset .............. 0x0C+n*0x08 for nth fragment (where n=0,1,...63)
Access Mode ................ Read/Write
Width ............................ 32 bits

Transmit Fragment Length (TxDMAFragLen) contains fragment length and control information for the
block of data pointed to by the corresponding TxDMAFragAddr.

BIT BIT NAME BIT DESCRIPTION

12..0 FragLen Fragment Length. FragLen is the length of the contiguous block of data
pointed to by TxDMAFragAddr. The maximum fragment length is 8192
bytes.
30..13 Reserved Reserved for future use.
31 TxDMAFragLast Transmit DMA Last Fragment. TxDMAFragLast is set by the host system
to indicate the last fragment of the transmit frame and that the IP100A LF
should proceed to the next TFD.

11.2.7 TxDMANextPtr
Class............................. DMA Data Structures, TFD
Base Address ............... Start of TFD
Address Offset .............. 0x00
Access Mode ................ Read/Write
Width ............................ 32 bits

BIT BIT NAME BIT DESCRIPTION

31..0 TxDMANextPtr Transmit DMA Next Pointer. TxDMANextPtr contains the physical
address of the next TFD in the transmit DMA list. A value of zero for
TxDMANextPtr accompanies the last frame of the list and it indicates
there are no more TFD’s in the transmit DMA list. All TFD’s must be
aligned on a 8-byte physical address boundary.

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 IP100A LF
Preliminary Data Sheet
11.2.8 TxFrameControl
Class............................. DMA Data Structures, TFD
Base Address ............... Start of TFD
Address Offset .............. 0x04
Access Mode ................ Read/Write
Width ............................ 32 bits

TxFrameControl contains frame control information for the transmit DMA function and the transmit function.

BIT BIT NAME BIT DESCRIPTION

1..0 WordAlign Word Alignment. WordAlign determine the boundary to which transmit
frame lengths are rounded up in the transmit FIFO, and transmitted onto
the network medium.
BIT 1 BIT 0 ALIGNMENT
0 0 Align to Double Word
1 0 Align t o Word
x 1 Alignment Disabled
When using word alignment, it is the responsibility of the host system to
recognize that any added bytes necessary to achieve the desired
alignment may affect byte oriented functions and fields (i.e. if the Ethernet
Length/Type field holds a frame length, this value is not updated to reflect
any bytes added via word alignment).
9..2 FrameId Frame Identification. FrameId can be used as a frame ID or sequence
number and can be used by the host system (via the TxStatus register) to
determine frames which experienced errors.
12..10 Reserved Reserved for future use.
13 FcsAppendDisable FCS Append Disable. If FcsAppendDisable is a logic 1, the IP100A LF
will not append the 4-byte FCS to the end of each transmit frame. In this
case, the host system must supply the frame’s FCS as part of the data
transferred via transmit DMA. An exception exists when a transmit under
run occurs; in this case a guaranteed-bad FCS will be appended to the
frame by the IP100A LF. When FcsAppendDisable is a logic 0, the
IP100A LF will compute and append FCS for each transmit frame.
14 Reserved Reserved for future use.
15 TxIndicate Transmit Indicate. If TxIndicate is a logic 1, the IP100A LF will issue a
TxComplete interrupt when transmission of the frame completes.
16 TxDMAComplete Transmit DMA Complete. When TxDMAComplete is a logic 1, the frame
transfer by transmit DMA is complete. The IP100A LF sets
TxDMAComplete to a logic 1 after completing transfer via transmit DMA,
all fragments specified in the TFD.
30..17 Reserved Reserved for future use.
31 TxDMAIndicate Transmit DMA Indicate. If TxDMAIndicate is a logic 1, the IP100A LF will
issue a TxDMAComplete interrupt upon completion of transmit DMA for
this frame. The TFC is read twice by the IP100A LF; the first time to write
the TFC to the transmit FIFO before frame data transfer, and again after
the transmit DMA operation is complete to test TxDMAIndicate in order to
determine whether to generate an interrupt. This dual read process
allows the host system time to change TxDMAIndicate while the transmit
DMA transfer is in progress.

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 IP100A LF
Preliminary Data Sheet
11.3 Wake Event Data Structures
The first Wake Event Data Structure is the Pseudo Packet. A Pseudo Packet is a set of patterns loaded
into the IP100A LF TxFIFO which specify bytes to be examined within received frames. A CRC is
calculated over these bytes and compared with a CRC value supplied in the Pseudo Packet. If a match is
found, the IP100A LF issues a Wake Event. The matching technique may result in false wake events
being reported to the host system. Each Pseudo Packet consists of one or more byte-offset/byte-count
pairs (or Pseudo Patterns), a terminator symbol, and a 4-byte CRC value. The byte offsets within the
Pseudo Patterns indicate the number of received frame bytes to be skipped in order to reach the next
group of bytes to be included in the CRC calculation. The byte-counts within the Pseudo Patterns
indicate the number of bytes in the next group to be included in the CRC calculation. The terminator
indicates the end of the Pseudo Patterns for the Pseudo Packet. Immediately following the terminator is
a 4-byte CRC. If there is another Pseudo Packet, it will immediately follow the CRC value.

The second Wake Event Data Structure is the Magic Packet. Magic Packets are uniquely formatted
frames, which upon reception invoke a Wake Event by the IP100A LF. Once the IP100A LF has been
placed in Magic Packet mode and put to sleep, it scans all incoming frames addressed to it for a data
sequence consisting of a synchronization stream followed immediately by 16 consecutive repetitions of
the station’s own 48-bit Ethernet MAC station address. The sequence can be located anywhere within
the received frame.

The pseudo packet and Magic Packet data structures are shown in Figure 12

IP100A Received Packet

PseudoPattern 1 0x00
Ethernet Header
0x01

PseudoPattern n 0x00+n-1
pseudo
Terminator 0x00+n 0x00
packet MagicSyncStream
0x00+n+1
0x06

PseudoCRC

Magic
MagicSequence
PacketTM

Ethernet CRC

FIGURE 12 : Wake Event Data Structures, Pseudo Packet and Magic Packet

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 IP100A LF
Preliminary Data Sheet
11.3.1 MagicSequence
Class............................. Wake Event Data Structures, Magic Packet
Base Address ............... Start of Magic Packet
Address Offset .............. 0x06
Access Mode ................ Read only
Width ............................ 768 bits

BIT BIT NAME BIT DESCRIPTION

767..0 MagicSequence Magic Sequence. A sequence of 96 bytes, consisting of 16 consecutive,
identical 6 bytes sequences, where each 6 byte sequence equals the
station address of the station receiving the Magic Packet.

11.3.2 MagicSyncStream
Class............................. Wake Event Data Structures, Magic Packet
Base Address ............... Start of Magic Packet
Address Offset .............. 0x00
Access Mode ................ Read only
Width ............................ 48 bits

BIT BIT NAME BIT DESCRIPTION

47..0 MagicSyncStream Magic Packet Sync Stream. A stream of 6 bytes with the value 0xff
indicates the start of the MagicSequence.

11.3.3 PseudoCRC
Class............................. Wake Event Data Structures, Pseudo Packet
Base Address ............... Start of Pseudo Packet
Address Offset .............. 0x00+n+1 for n PseudoPatterns
Access Mode ................ Write only
Width ............................ 32 bits

The 32-bit CRC as defined in the IEEE 802.3 Ethernet standard for the FCS, taken over the bytes
(indicated by the PseudoPattern values) of a received frame.

BIT BIT NAME BIT DESCRIPTION

7..0 PsuedoCRCbyte0 The least significant byte of the PseudoCRC.
15..8 PsuedoCRCbyte1 The second lest significant byte of the PseudoCRC.
23..16 PsuedoCRCbyte2 The second most significant byte of the PseudoCRC.
31..24 PsuedoCRCbyte3 The most significant byte of the PseudoCRC.

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 IP100A LF
Preliminary Data Sheet
11.3.4 PseudoPattern
Class............................. Wake Event Data Structures, Pseudo Packet
Base Address ............... Start of Pseudo Packet
Address Offset .............. 0x00 thru 0x00+n-1 for nth PseudoPattern
Access Mode ................ Write only
Width ............................ 8 bits

BIT BIT NAME BIT DESCRIPTION

3..0 ByteCount ByteCount can take on a value of 0x0 to 0xe. A value of 0xf indicates an
extended value. The extended value will occupy 8 bits and is contained in
the next PseudoPattern. If both the ByteOffset and the ByteCount values
are 0xf, the next PseudoPattern will be the extended ByteOffset, and the
PseudoPattern after that will be the extended ByteCount.
7..4 ByteOffset ByteOffset can take on a value of 0x0 to 0xe. A value of 0xf indicates an
extended value. The extended value will occupy 8 bits and is contained in
the next PseudoPattern. If both the ByteOffset and the ByteCount values
are 0xf, the next PseudoPattern will be the extended ByteOffset, and the
PseudoPattern after that will be the extended ByteCount.

11.3.5 Terminator
Class............................. Wake Event Data Structures, Pseudo Packet
Base Address ............... Start of Pseudo Packet
Address Offset .............. 0x00+n for n PseudoPattern
Access Mode ................ Write only
Width ............................ 8 bits

BIT BIT NAME BIT DESCRIPTION

7..0 Terminator A value of 0x00 indicates the end of the PseudoPattern.

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 IP100A LF
Preliminary Data Sheet
11.4 LAN I/O Registers
The host interacts with the IP100A LF mainly through slave registers, which occupy 128 bytes in the host
system’s I/O space, memory space, or both. Generally, registers are referred to as “I/O registers”,
implying that the registers may in fact be mapped and accessed by the host system in memory space.
I/O registers must be accessed with instructions that are no larger than the bit-width of that register.

The IP100A LF LAN I/0 register layout is show in Figure 13.

ADDR
BYTE 3 BYTE 2 BYTE 1 BYTE 0
OFFSET
HashTable[63..32] 0x64
HashTable[31..0] 0x60
PhyCtrl TxReleaseThresh ReceiveMode 0x5C
MaxFrameSize StationAddress[47..32] 0x58
StationAddress[31..0] 0x54
MACCtrl1 MACCtrl0 0x50
IntStatus IntEnable 0x4C
IntStatusAck 0x48
TxStatus WakeEvent 0x44
0x40
0x3C
FIFOCtrl 0x38
EepromCtrl EepromData 0x34
AsicCtrl 0x30
0x2C
0x28
0x24
0x20
0x1C
0x18
RxDMAUrgent- RxDMABurst- 0x14
RxDMAPollPeriod
Thresh Thresh
RxDMAListPtr 0x10
RxDMAStatus 0x0C
TxDMAUrgent- TxDMABurst- 0x08
TxDMAPollPeriod
Thresh Thresh
TxDMAListPtr 0x04
DMACtrl 0x00
FIGURE 13 : IP100A LF I/O Register Map

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 IP100A LF
Preliminary Data Sheet
11.4.1 AsicCtrl
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x30
Default .........................0x00004000 (default values for LED Speed, LED, Mode, PhySpeed10,
PhySpeed100, PhyMedia are dependent on EEPROM settings, and
ForcedConfig[1..0], ForcedCon-fig[2] are dependent on ED signal pin states)
Width ............................ 32 bits

AsicCtrl provides chip-specific, non-host-related settings. The contents of the least significant byte of
AsicCtrl are read from EEPROM at reset.

BIT BIT NAME R/W BIT DESCRIPTION

0 LEDFlashSpeed R The LED flahing Speed can be defined by this bit and could be
set by EEPROM only.
0: Fast Speed (5ms, 35ms).
1: Low Speed (20ms, 60ms).
1 LED Mode R The Bit decide LED Mode, could be set by EEPROM only.
Light Emitting Diode Mode. LEDMode is used to control the LED
signal pins functionality. When LEDMode is a logic 0 the LED
signal pins operate in LED mode 0. When LEDMode is a logic 1
the LED signal pins operate in LED mode 1.
Note:
When LED Mode 0 is set, the period of 1 cycle alternating
between logic 1/0 is 100ms. The LED ON period is 20ms and
OFF period is 80ms.
When LED Mode 1 is set, the period of 1 cycle alternating
between logic 1/0 is 200ms. The LED ON period is 40ms and
OFF period is 160ms.
LED
MODE 0 MODE 1
SIGNAL PIN
LED_LINK This interface is not Continuous logic 0 when
functioning under MODE 0 Ethernet link is valid.
LED_10N Continuous logic 0 when Continuous logic 0
Ethernet link is operate at when Ethernet link is
10Mb/sec operate at 10Mb/sec
LED_100N Continuous logic 0 when Continuous logic 0
Ethernet link is operate at when Ethernet link is
100Mb/sec operate at 100Mb/sec
LED
MODE 0 MODE 1
SIGNAL PIN
LED_TXN Logic 0 indicates the Logic 0 indicates the link
frames are transmitting has established, while
in progress, while logic 1 logic 1 indicates link is
means no data is been down. Alternating logic
sent. 1 and 0 indicates the
transmission or
receiving is in progress.
LED_RXN Logic 0 indicates the Logic 0 indicates the link
frames are been has established, while
received. Logic 1 logic 1 indicates link is
indicates no frame is down. Alternating logic

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
been received. 1 and 0 indicates the
data receiving is in
progress.
LED_DPLXN Logic 0 means the link is Logic 0 means the link
established based on is established based on
FULL Duplex Mode, FULL Duplex Mode,
while logic 1 indicates while logic 1 indicates
HALF Duplex Mode. HALF Duplex Mode.
Alternating logic 1 and 0
indicates COLLISION
has occurred.
2 TxLargeEnable R/W Transmit Large Frames Enable. If TxLargeEnable is a logic 1, the
IP100A LF may transmit frames which are larger in size than the
IP100A LF transmit FIFO.
3 RxLargeEnable R/W Receive Large Frames Enable. If RxLargeEnable is a logic 1, the
IP100A LF may receive frames which are larger than the IP100A
LF receive FIFO.
4 ExpRomDisable R/W Expansion ROM Disable. If ExpRomDisable is a logic 1,
accesses to the on-adapter Expansion ROM are disabled and
read to the Expansion ROM return 0x00000000 while writes to
the Expansion ROM are ignored.
5 PhySpeed10 R Physical Device 10Mbps Capable. If PhySpeed10 is a logic 1, the
IP100A LF PHY is capable of operating at 10Mbps.
6 PhySpeed100 R Physical Device 100Mbps Capable. If PhySpeed100 is a logic 1,
the IP100A LF PHY is capable of operating at 100Mbps.
7 PhyMedia R Physical Device Media Type. If PhyMedia is a logic 0, copper
media is in use. If PhyMedia is a logic 1, fiber media is in use. The
combination of PhyMedia, PhySpeed100, and PhySpeed10
defines the capabilities of the PHY.
PHY PHY PHY PHY CAPABILITY
MEDIA SPEED100 SPEED10
0 0 0 Undefined
0 0 1 10BASE-T
0 1 0 100BASE-T
0 1 1 100BASE-T or 10BASE-T
1 0 0 Undefined
1 0 1 10BASE-F
1 1 0 100BASE-F
1 1 1 100BASE-F or 10BASE-F
9..8 ForcedConfig[1..0] R/W Forced Configuration. ForcedConfig[1..0] is used to enable and
select a Forced Configuration mode for the IP100A LF. Forced
Configuration mode is targeted toward embedded applications
which do not utilize an EEPROM. In Forced Configuration mode,
the IP100A LF is accessed via a PCI bus without first performing
PCI configuration or loading parameters from an EEPROM.
The ForcedConfig[1..0] bits 9 through 8 can also be set on reset
using ED[4:3].
BIT 9 BIT 8 FORCED CONFIGURATION MODE
0 0 None
0 1 1
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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
0 1 1
1 X Reserved
In Forced Configuration mode 1, the IP100A LF is configured as
follows:
I/O base address = 0x200
I/O target cycles = enabled
Memory target cycles = disabled
Bus master cycles = enabled
Expansion ROM cycles = disabled.
10 Reserved N/A Reserved for future use.
12..11 Reserved N/A Reserved for future use.
13 SpeedupMode R/W Speed Up Mode. SpeedupMode is used for simulation purposes
only. When SpeedupMode is a logic 1 IP100A LF operation is
modified to decrease simulation time. SpeedupMode can also be
set on reset using signal pin 20.
14 Reserved N/A
15 Reserved N/A Reserved for future use.
16 GlobalReset W Global Reset. When GlobalReset is a logic 1, the IP100A LF resets
the logic functions and registers specified by the DMA, FIFO,
Network, Host, and AutoInit bits (related to both the transmit and
receive processes as applicable). The LAN PCI Configuration
Registers are not affected by GlobalReset. GlobalReset is
self-clearing.
17 RxReset W Receive Reset. When RxReset is a logic 1 the IP100A LF resets
all of the receive logic functions and registers specified by the
DMA, FIFO, and Network bits. RxReset is self-clearing, and
should not be used after initialization except to recover from
receive errors such as a receive FIFO over run.
18 TxReset W Transmit Reset. When TxReset is a logic 1 the IP100A LF resets
all of the transmit logic functions and registers specified by the
DMA, FIFO, and Network bits. TxReset is self clearing, and is
required to be used after a transmit underrun error.
19 DMA W DMA Reset. DMA selects (when a logic 1) or excludes (when a
logic 0) the IP100A LF DMA functions and registers (see below)
for/from reset based on the value of the GlobalReset, RxReset,
and TxReset bits. The DMA bit is self-clearing.
20 FIFO W FIFO Reset. FIFO selects (when a logic 1) or excludes (when a
logic 0) the IP100A LF FIFO functions and registers for/from reset
based on the value of the GlobalReset, RxReset, and TxReset
bits. The FIFO bit is self-clearing.
21 Network W Network Reset. Network selects (when a logic 1) or excludes
(when a logic 0) the IP100A LF network functions and registers
for/from reset based on the value of the GlobalReset, RxReset,
and TxReset bits. The Network bit is self-clearing.
23 AutoInit W Automatic Initialization Reset. AutoInit selects (when a logic 1) or
excludes (when a logic 0) the IP100A LF auto-initialization logic
function for/from re-loading IP100A LF parameters from an
EEPROM based on the value of the GlobalReset bit. The AutoInit
bit is self-clearing.
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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
24 Reserved N/A Reserved for future use.
25 InterruptRequest W Interrupt Request. When InterruptRequest is a logic 1, the
IntRequested bit of the IntStatus register is set to a logic 1.
InterruptRequest is self-clearing.
26 ResetBusy R/W Reset Busy. When ResetBusy is a logic 1 a reset process is in
progress. After asserting a reset using the GlobalReset, RxReset,
or TxReset bits, the ResetBusy bit must be polled (or periodically
read) until it is a logic 0 indicating the reset operation is complete.
31..27 Reserved N/A Reserved for future use.

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 IP100A LF
Preliminary Data Sheet

11.4.2 DMACtrl
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x00
Default .......................... 0x00000000
Width ............................ 32 bits

DMACtrl controls some of the bus master functions in the receive DMA and transmit DMA logic, and
contains status bits. DMACtrl is cleared by a reset.

BIT BIT NAME R/W BIT DESCRIPTION

0 RxDMAHalted R Receive DMA Halted. RxDMAHalted is a logic 1 whenever
receive DMA is halted by setting RxDMAHalt or an implicit halt
due to fetching a RFD with RxDMAComplete in RxFrameStatus
already a logic 1. RxDMAHalted is cleared by setting
RxDMAResume to a logic 1.
1 TxDMACmplReq R Transmit DMA Complete Request. TxDMACmplReq is equivalent
to the TxDMAIndicate field in the TxFrameControl of the current
TFD.
2 TxDMAHalted R Transmit DMA Halted. TxDMAHalted is a logic 1whenever
transmit DMA is halted by setting TxDMAHalt. TxDMAHalted is
cleared by setting TxDMAResume to a logic 1.
3 RxDMAComplete R Receive DMA Complete. RxDMAComplete is equivalent to the
RxDMAComplete bit in the IntStatus register. RxDMAComplete is
different from the RxDMAComplete bit in RxDMAStatus.
RxDMAComplete is latched once a frame receive DMA transfer
has completed. RxDMAComplete is cleared by acknowledging
the RxDMAComplete bit in the IntStatus register.
4 TxDMAComplete R TxDMAComplete. TxDMAComplete is the same as the
TxDMAComplete bit in IntStatus register. TxDMAComplete is
cleared by acknowledging the TxDMAComplete bit in the
IntStatus register.
7..5 Reserved N/A Reserved for future use.
8 RxDMAHalt W Receive DMA Halt. If RxDMAHalt is a logic 1, the receive DMA is
halted. RxDMAHalt is self-clearing and writing a 0 is ignored. See
RxDMAHalted to determine the running state of receive DMA.
9 RxDMAResume W Receive DMA Resume. If RxDMAResume is a logic 1, the receive
DMA is resumed. RxDMAResume is self-clearing and writing a 0
is ignored. See RxDMAHalted to determine the running state of
receive DMA.
10 TxDMAHalt W Transmit DMA Halt. If TxDMAHalt is a logic 1, the transmit DMA is
halted. TxDMAHalt is self-clearing and writing a 0 is ignored. See
TxDMAHalted to determine the running state of transmit DMA.
11 TxDMAResume R/W Transmit DMA Resume. If TxDMAResume is a logic 1, the
transmit DMA is resumed. TxDMAResume is self-clearing and
writing a 0 is ignored. See TxDMAHalted to determine the running
state of transmit DMA.
13..12 Reserved N/A Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
14 TxDMAInProg R Transmit DMA in Progress. If TxDMAInProg is a logic 1, a
transmit DMA operation is in progress. TxDMAInProg is primarily
used by the host system in an under run recovery routine. The
host system waits for TxDMAInProg to be a logic 0 before setting
the TxReset bit of the AsicCtrl register to clear the under run
condition. Before checking TxDMAInProg, issue TxDMAHalt.
15 DMAHaltBusy R DMA Halt Busy. DMAHaltBusy indicates that a DMA Halt
operation (TxDMAHalt or RxDMAHalt) is in progress and the host
system should wait for DMAHaltBusy to be cleared before
performing other actions.
16 Reserved N/A Reserved for future use.
17 Reserved N/A Reserved for future use.
18 Reserved N/A Reserved for future use.
19 Reserved N/A Reserved for future use.
20 MWIDisable R/W PCI MWI Command Disable. If Setting MWIDisable is a logic 1,
the IP100A LF will not use the Memory Write Invalidate (MWI)
PCI command.
21 Reserved N/A Reserved for future use.
22 RxDMAOverrun- R/W Receive DMA Overrun Frame. If RxDMAOverrunFrame is a logic 0,
Frame receive DMA will discard receive overrun frames without transferring
them to the host system. WhenRxDMAOverrunFrame is a logic 1,
receive DMA will transfer overrun frames to the host system.
Overrun frames are any frame which is received while the receive
FIFO is full.
29..23 Reserved N/A Reserved for future use.
30 TargetAbort R Bus Target Abort. TargetAbort is a logic 1 when the IP100A LF
experiences a target abort sequence when operating as a bus
master. TargetAbort indicates a fatal error, and must be cleared
before further transmit DMA or receive DMA operation can
proceed. TargetAbortt is cleared via the GlobalReset, and DMA
bits of the AsicCtrl register.
31 MasterAbort R Bus Master Abort. MasterAbort is a logic 1 when the IP100A LF
experiences a master abort sequence when operating as a bus
master. MasterAbort indicates a fatal error, and must be cleared
before further transmit DMA or receive DMA operation can
proceed. MasterAbortt is cleared via the GlobalReset, and DMA
bits of the AsicCtrl register.

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 IP100A LF
Preliminary Data Sheet
11.4.3 EepromCtrl
Class............................. LAN I/O Registers, External Interface Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x36
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

5:0 EepromAddress R/W EEPROM Address. EepromAddress identify one of the 256,
sixteen-bit words to be the target for the ReadRegister,
WriteRegister or EraseRegister commands.
7:6 EepromCommand R/W Bits 7 and 6 are further defined to identify a sub-command based
on the value of EepromOpcode. The definition of bits 7 and 6 are
valid when the EepromOpcode in bits 9 and 8 equals 00.
BIT 7 BIT 6 SUB-COMMAND
0 0 WriteDisable
0 1 WriteAII
1 0 EraseAll
1 1 WriteEnable
9..8 EepromOpcode R/W EEPROM Operation Code. EepromOpcode specifies one of three
individual commands and a single group of four sub-commands.
If both bit 9 and bit 8 are logic zero, the Opcode function will be
based on the value in bit 6 and bit 7, otherwise bit 6 and bit 7 does
not have any affect to these 2 bits.
BIT 9 BIT 8 OPCODE COMMAND
0 0 Don’t Care
0 1 WriteRegister
1 0 ReadRegister
1 1 Don’t Care
Note, after every WriteRegister, EraseRegister opcode, or
WriteAll or EraseAll subcommand, the IP100A LFwill
automatically issue a WriteDisable command to the EEPROM.
Therefore, a WriteEnable command must be issued to the
EEPROM prior to every WriteRegister, EraseRegister opcode, or
WriteAll or EraseAll subcommand.
10..11 Reserved Reserve for future use
12 93C46TypeSel R/W When the 93C46TypSel is logic 1, IP100A LF accesses the
93C46 EEPROM by normal address code.
And when this bit is set to logic 0, IP100A LF read/write the
93C46 EEPROM via special address code. This function is
designed for special usage only.
13 EepromSel RO EEPROM Select. If this bit is logic 0, it means that IP100A LF is
connected to 93C46 series EEPROM.
14 Reserved RO Read back as 1.
15 EepromBusy R EEPROM Busy. EepromBusy is a logic 1 during the execution of
EEPROM commands. Further commands should not be issued to
EepromCtrl nor should data be read from Eeprom-Data while
EepromBusy is a logic 1.

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 IP100A LF
Preliminary Data Sheet
11.4.4 EepromData
Class............................. LAN I/O Registers, External Interface Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x34
Default .......................... 0x0000
Width ............................ 16 bits

EepromData is a 16-bit data register for use with the adapter’s serial EEPROM. Data from the EEPROM
should be read by the host system from EepromData register based on the state of the EepromBusy bit
of the EepromCtrl register. Data to be written to the EEPROM is written to EepromData prior to issuing
the write command to EepromCtrl.

BIT BIT NAME R/W BIT DESCRIPTION

15..0 EepromData R/W EEPROM Data. Data read from, or to be written to, the external
EEPROM.

11.4.5 FIFOCtrl
Class............................. LAN I/O Registers, FIFO Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x3a
Default .......................... 0x0000
Width ............................ 16 bits

FIFOCtrl provides various control and indications for the transmit FIFO and the receive FIFO diagnostic.

BIT BIT NAME R/W BIT DESCRIPTION

0 RAMTest Mode R/ W RAM Tes t Mode. I f RAMTestMode is a logic 1, the FIFO RAM is
in the test mode.
8..1 Reserved N/A Reserved for future use.
9 RxOverrunFrame R/ W Receive Overrun Frame. RxOverrunFrame determines how the
IP100A LF handles receive overrun frames. If RxOverrunFrame is a
logic 0, the IP100A LF discards all overrun frames. If
RxOverrunFrame is a logic 1, the IP100A LF will retain all overrun
frames, so that they may be inspected by the host for diagnostic
purposes.
10 Reserved N/A Reserved for future use.
11 RxFIFOFull R Receive FIFO Full. If RxFIFOFull is a logic 1, the receive FIFO is
full. RxFIFOFull does not in itself indicate an overrun condition.
However, if more data is received while RxFIFOFull is a logic 1,
an overrun will occur. RxFIFOFull is cleared as soon as the
receive FIFO is no longer full.
13..12 Reserved N/A Reserved for future use.
14 Transmitting R Transmit Indicator. Transmitting is set to a logic 1 whenever a
frame is being transmitted or during a transmit deferral).
15 Receiving R Receive Indicator. Receiving is set to a logic 1 whenever a frame
is being received. No action is expected on the part of the host
based on the state of Receiving.

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 IP100A LF
Preliminary Data Sheet
11.4.6 HashTable
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x66, 0x64, 0x62, 0x60
Default .......................... 0x0000000000000000
Width ............................ 64 bits (accessible as 4, 16 bit words)

The host system stores a 64-bit hash table in this register for selectively receiving multicast frames.
Setting the ReceiveMulticastHash bit in ReceiveMode register enables the filtering mechanism.

BIT BIT NAME R/W BIT DESCRIPTION

15..0 HashTableWord0 R/W The least significant word of the hash table, corresponding to
address 0x60.
31..16 HashTableWord1 R/W The second least significant word of the hash table,
corresponding to address 0x62.
47..32 HashTableWord2 R/W The second most significant word of the hash table,
corresponding to address 0x64.
63..48 HashTableWord3 R/W The most significant word of the hash table, corresponding to
address 0x66.

The IP100A LF applies a cyclic-redundancy-check (the same CRC used to calculate the frame data FCS)
to the destination address of all incoming multicast frames (with multicast bit set). The low-order 6 bits of
the CRC result are used as an addressing index into the hash table. The MSB of HashTable[3] is the
most significant bit, and the LSB of HashTable[0] is the least significant bit, addressed by the 6-bit index.
If the HashTable bit addressed by the index is a logic 1, the frame is accepted by the IP100A LF and
transferred to higher layers. If the addressed hash table bit is a logic 0, the frame is discarded.

11.4.7 IntEnable
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x4c
Default .......................... 0x0000
Width ............................ 16 bits

Enables individual interrupts as specified in the IntStatus register. Setting a bit in IntEnable will allow the
specific source to generate an interrupt on the PCI bus. IntEnable is cleared by a read of IntStatusAck.

BIT BIT NAME R/W BIT DESCRIPTION

0 Reserved N/A Reserved for future use.
1 EnHostError R/W Enable Host Error Interrupt. Enables the HostError interrupt.
2 EnTxComplete R/W Enable Transmit Complete Interrupt. Enables the TxComplete
interrupt.
3 EnMACControlFrame R/W Enable MAC Control Frame Interrupt. Enables the
MACControlFrame interrupt.
4 EnRxComplete R/W Enable Receive Complete Interrupt. Enables the RxComplete
interrupt.
5 Reserved R/W Reserved for future use.
6 EnIntRequested R/W Enable Interrupt Requested Interrupt. Enables the IntRequested
interrupt.

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Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
7 EnUpdateStats R/W Enable Update Stats Interrupt. Enables the UpdateStats interrupt.
8 EnLinkEvent R/W Enable Link Event Interrupt. Enables the LinkEvent interrupt.
9 EnTxDMAComplete R/W Enable Transmit DMA Complete Interrupt. Enables the
TxDMAComplete interrupt.
10 EnRxDMAComplete R/W Enable Receive DMA Complete Interrupt. Enables the
RxD-MAComplete interrupt.
11 Reserved N/A Reserved for future use.
15..12 Reserved N/A Reserved for future use.

11.4.8 IntStatus
Class….......................... LAN I/O Registers, Interrupt
Base Address …............ IoBaseAddress register value
Address Offset …........... 0x4e
Default …....................... 0x0000
Width …......................... 16 bits

IntStatus indicates the source of interrupts and indications on the IP100A LF. All bits except
InterruptStatus are the interrupt causing sources for the IP100A LF. Each interrupt source can be
individually disabled using the IntEnable register. The host system may acknowledge most interrupts by
writing a logic 1 into the corresponding IntStatus bit, which will cause the IP100A LF to clear the interrupt
indication.

BIT BIT NAME R/W BIT DESCRIPTION

0 InterruptStatus R/W Interrupt Status. InterruptStatus is a logic 1 when the IP100A LF
is driving the bus interrupt signal (INTAN). InterruptStatus is a
logical OR of all the interrupt causing sources after they have
been filtered through the IntEnable register.
1 HostError R/W Host Error Interrupt. HostError is a logic 1 when a catastrophic
error related to the bus interface occurs. Catastrophic bus
interface errors include PCI target abort and PCI master abort.
A HostError interrupt requires a setting the GlobalReset and DMA
bits of the AsicCtrl register.
2 TxComplete R/W Transmit Complete. TxComplete is a logic 1 when a frame whose
TxIndicate bit in the TFD’s TxFrameControl field is a logic 1, has
been successfully transmitted or for any frame that experiences a
transmission error.
A TxComplete interrupt requires writing to TxStatus register to
advance the status queue.
3 MACControlFrame R/W MAC Control Frame Received Interrupt. MACControlFrame is a
logic 1 when a MAC Control frame has been received by the
IP100A LF.
4 RxComplete R/W Receive Complete Interrupt. RxComplete is a logic 1 when one or
more entire frames have been received into the receive FIFO.
RxComplete is automatically acknowledged by the receive DMA
logic as it transfers frames.
5 Reserved R/W Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
6 IntRequested R/W Interrupt Requested Interrupt. IntRequested is a logic 1 after the
host system requests an interrupt by setting InterruptRequest bit
of the AsicCtrl register.
7 UpdateStats R/W Update Statistics Interrupt. UpdateStats is a logic 1 to indicate
that one or more of the statistics registers is nearing an overflow
condition (typically half of its maximum value). The host system
should respond to an UpdateStats interrupt by reading all of the
statistic registers, thereby acknowledging and clearing
UpdateStats bit.
8 LinkEvent R/W Link Event Interrupt. LinkEvent is a logic 1 to indicate a change in
the state of the Ethernet link.
9 TxDMAComplete R/W Transmit DMA Complete Interrupt. TxDMAComplete is a logic 1
to indicate that a transmit DMA operation has completed, and the
frame’s corresponding TFD had the TxDMAComplete bit in the
TxFrameControl field set to a logic 1.
10 RxDMAComplete R/W Receive DMA Complete Interrupt. RxDMAComplete is a logic 1 to
indicate that a frame receive DMA operation has completed.
11 Reserved N/A Reserved for future use.
15..12 Reserved N/A Reserved for future use.

11.4.9 IntStatusAck
Class............................. LAN I/O Registers, Interrupt
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x4a
Default .......................... 0x0000
Width ............................ 16 bits

IntStatusAck is another version of the IntStatus register, having the same bit definition as IntStatus, but
providing additional functionality to reduce the number of I/O operations required to perform common
tasks related to interrupt handling. In addition to returning the IntStatus value, when read IntStatusAck
also acknowledges the TxDMAComplete, RxDMAComplete, IntRequested, MACControlFrame, and
LinkEvent interrupt bits within the IntStatus register (if they are set), and clears the IntEnable register
(preventing subsequent events from generating an interrupt).

BIT BIT NAME R/W BIT DESCRIPTION

0 InterruptStatus R See InterruptStatus in the IntStatus register.
1 HostError R See HostError in the IntStatus register.
2 TxComplete R See TxComplete in the IntStatus register.
3 MACControlFrame R See MACControlFrame in the IntStatus register.
4 RxComplete R See RxComplete in the IntStatus register.
5 Reserved R Reserved for future use.
6 IntRequested R See IntRequested in the IntStatus register.
7 UpdateStats R See UpdateStats in the IntStatus register.
8 LinkEvent R See LinkEvent in the IntStatus register.
9 TxDMAComplete R See TxDMAComplete in the IntStatus register.
10 RxDMAComplete R See RxDMAComplete in the IntStatus register.

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
11 Reserved N/A Reserved for future use.
15..12 Reserved N/A Reserved for future use.

11.4.10 MACCtrl0
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x50
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

1..0 IFSSelect R/W Inter-Frame Spacing Select. IFSSelect indicates the minimum
number of bit times between the end of one Ethernet frame, and the
beginning of another when the IP100A LF is deferring after a
collision with the IP100A LF the last device to successfully acquire
the network (in half duplex mode). By selecting a large value for
IFSSelect, the IP100A LF will become less “aggressive” on the
network and may defer more often (preventing the IP100A LF from
“capturing” the network). The performance of the IP100A LF may
decrease as the IFSSelect value is increased from the standard
value.
BIT1 BIT0 INTER-FRAME SPACING IN BIT TIMES
0 0 96 (802.3 standard value, and default)
0 1 128
1 0 224
1 1 544
4..2 Reserved N/A Reserved for future use.
5 FullDuplexEnable R/W Full Duplex Enable. Setting FullDuplexEnable to a logic 1
configures the IP100A LF to function in a full duplex manner.
When operating in full duplex, the IP100A LF disables transmitter
deference to receive traffic, allowing simultaneous receive and
transmit traffic. Operation in full duplex has the side-effect of
disabling CarrierSenseErrors statistics collection, since full duplex
operation requires carrier sense to be masked to the transmitter.
TxReset and RxReset bits in AsicCtrl must be set for changes
ofFullDuplexEnable to take effect.
6 RcvLargeFrames R/W Receive Large Frames. RcvLargeFrames determines the frame size
at which the RxOversizedFrame bit of the RxFrameStatus field is set
for receive frames. When RcvLargeFrames is a logic 0, minimum
OversizedFrame size is 1514 bytes. When RcvLargeFrames is set,
minimum OversizedFrame size is 4491 bytes. (This value was the
maximum FDDI frame size of 4500 bytes, subtracting bytes for fields
that have no Ethernet equivalent.)
The frame size at which an OversizedFrame error will be flagged
includes the destination and source addresses, the type/length
field, and the FCS field.
7 Reserved N/A Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
8 FlowControl- R/W Flow Control Enable. If FlowControlEnable is a logic 0, the
Enable IP100A LF treats all incoming frames as data frames. If
FlowControlEnable is a logic 1, flow control is enabled and the
IP100A LF will act upon incoming flow control PAUSE frames. If
FlowControlEnable is a logic 1, FullDuplexEnable should also be
set to a logic 1.
9 RcvFCS R/W Receive FCS. If RcvFCS is a logic 1, the IP100A LF will include
the receive frame’s FCS along with the frame data transferred to
the host system. If RcvFCS is a logic 0, the IP100A LF will
remove the FCS from the frame before transferring the frame to
the host system. The state of RcvFCS does not affect the IP100A
LF’s checking of the frame’s FCS and its posting of FCS errors.
RcvFCS should only be changed when the receiver is disabled
(via the RxDisable bit of the MACCtrl1 register) and after resetting
the receive FIFO (via the FIFO bit of the AsicCtrl register).
10 FIFOLoopback R/W FIFO Loopback. If FIFOLoopback is a logic 1, the IP100A LF will
enter FIFO Loopback Mode and force data to loopback from the
transmit FIFO directly into the receive FIFO. When using FIFO
Loopback Mode, it is the host system’s responsibility to ensure that
proper interframe spacing is ensured. To accommodate proper
interframe spacing, the host system must not load more than one
transmit frame into the transmit FIFO at a time while in FIFO
Loopback Mode. The TxReset and RxReset bits of the AsicCtrl
register must be set after changing the value of FIFOLoopback.
11 MACLoopback R/W MAC Loopback. If MACLoopback is a logic 1, the IP100A LF will
enter MAC Loopback Mode and force data to loopback from the
MAC transmit interface to the MAC receive interface. The
TxReset and RxReset bits in AsicCtrl register must be set after
changing the value of MACLoopback.
15..12 Reserved N/A Reserved for future use.

Note: External loopback is controlled by the PHY. To utilize external loopback, the host system must
enable a loopback mode within the PHY using the MII Management Interface. For the true “on-the-wire”
loopback mode, use a loopback plug (connector), clear the FIFOLoopback, and MACLoopback and any
PHY loopback bits to zero, set the FullDuplexEnable bit to a logic 1, and enable the full duplex mode
within the PHY.

11.4.11 MACCtrl1
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x52
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

0 CollisionDetect R Collision Detect. CollisionDetect provides a real-time indication of
the state of the COL signal within the IP100A LF.
1 CarrierSense R Carrier Sense. CarrierSense provides a real-time indication of the
state of the CRS signal within IP100A LF.

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
2 TxInProg R Transmit In Progress. TxInProg provides a real-time indication
that a frame is being transmitted. If TxInProg is a logic 1, a frame
transmission is in progress. TxInProg is used by the host system
during under run recovery to delay before setting the issuing a
TxReset bit in the AsicCtrl register.
3 TxError R Transmit Error. If a transmit under run occurs (indicated via the
TxUnderrun bit of the TxStatus register), TxError is a logic 1,
indicating that the transmitter needs to be reset via the TxReset
bit in the AsicCtrl register.
4 Reserved N/A Reserved for future use.
5 StatisticsEnable W Statistics Enable. Writing a logic 1 to StatisticsEnable will enable
the IP100A LF’s statistic registers. The state (enabled/disabled)
of the IP100A LF’s statistic registers is shown via
StatisticsEnabled.
6 StatisticsDisable W Statistics Disable. Writing a logic 1 to StatisticsDisable will disable
the IP100A LF’s statistic registers. The state (enabled/disabled)
of the IP100A LF’s statistic registers is shown via
StatisticsEnabled.
7 StatisticsEnabled R Statistics Enabled. If StatisticsEnabled is a logic 1, the IP100A
LF’s statistic registers are enabled.
8 TxEnable W Transmit Enable. Writing a logic 1 to TxEnable will enable the
IP100A LF to transmit frames. The state (enabled/disabled) of the
IP100A LF’s transmitter is shown via TxEnabled.
9 TxDisable W Transmit Disable. Writing a logic 1 to TxDisable will disable the
IP100A LF from transmitting frames. The state (enabled/disabled)
of the IP100A LF’s transmitter is shown via TxEnabled.
10 TxEnabled R Transmit Enabled. If TxEnabled is a logic 1, the IP100A LF’s
transmitter is enabled.
11 RxEnable W Receive Enable. Writing a logic 1 to RxEnable will enable the
IP100A LF to receive frames. The state (enabled/disabled) of the
IP100A LF’s receiver is shown via RxEnabled.
12 RxDisable W Receive Disable. Writing a logic 1 to RxDisable will disable the
IP100A LF from receiving frames. The state (enabled/disabled) of
the IP100A LF’s receiver is shown via RxEnabled.
13 RxEnabled R Receive Enabled. If RxEnabled is a logic 1, the IP100A LF’s
receiver is enabled.
14 Paused R Paused. If Paused is a logic 1, the IP100A LF has received a
PAUSE MAC Control Frame and the IP100A LF has halted the
transmitter for the duration indicated in the PAUSE Frame’s
pause_time field. Paused will become a logic 0 when the IP100A
LF’s transmitter ends is pause operation.
15 Reserved N/A Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
11.4.12 MaxFrameSize
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x5a
Default .......................... 0x1514 or 0x4491 based on the RcvLargeFrames bit in the MACCtrl0 register
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..0 MaxFrameSize R/W Maximum Frame Size. Received frames with sizes equal to or
larger than MaxFrameSize will be flagged as oversize via the
RxOversizedFrame bit in RxDMAStatus field of the frame’s RFD.

11.4.13 PhyCtrl
Class............................. LAN I/O Registers, External Interface Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5e
Default .......................... 0x00
Width ............................ 8 bits

PhyCtrl contains control bits for the internal MII Management Interface. The MII Management Interface is
used to access registers in the IP100A LF PHY. The host system accesses the MII Management
Interface by writing and reading bit patterns to the PhyCtrl register.

BIT BIT NAME R/W BIT DESCRIPTION

0 MgmtClk R/W Management Clock. MgmtClk drives the management clock
(MDC) signal to the PHY.
1 MgmtData R/W Management Data bit. MgmtData is directly connected to the
MDIO signal connected to the PHY. Data can be written to or read
from the PHY by writing or read MgmtData based on the value of
MgmtDir.
2 MgmtDir R/W Management Data Direction. If the MgmtDir is a logic 1, the value
written to MgmtData is driven onto the MDIO signal connected to
the PHY. When MgmtDir is a logic 0, data driven onto MDIO by
the PHY can be read from MgmtData.
3 Reserved N/A Reserved for future use.
4 PhyDuplexPolarity R/W PHY Duplex Polarity. If PhyDuplexPolarity is a logic 0, the duplex
status signal between the PHY and the MAC is active low.
5 PhyDuplexStatus R PHY Duplex Status. If PhyDuplexStatus is a logic 1, the PHY is
operating in full duplex mode. If PhyDuplexStatus is a logic 0, the
PHY is operating in half duplex mode.
6 PhySpeedStatus R PHY Speed Status. PhySpeedStatus provides a real-time
indication of the IP100A LF’s PHY speed. If PhySpeedStatus is a
logic 1, the IP100A LF’s PHY is operating at 100Mbps operation.
If PhySpeedStatus is a logic 0, the IP100A LF’s PHY is operating
at 10Mbps operation.
7 PhyLinkStatus R PHY Link Status. PhyLinkStatus provides a real-time indication of
the IP100A LF’s PHY link state. If PhyLinkStatus is a logic 1, the
IP100A LF’s PHY link is up. If PhyLinkStatus is a logic 0, the
IP100A LF’s PHY link is down.

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 IP100A LF
Preliminary Data Sheet
11.4.14 ReceiveMode
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5c
Default .......................... 0x00
Width ............................ 8 bits

ReceiveMode sets the receive filter of the IP100A LF.

BIT BIT NAME R/W BIT DESCRIPTION

0 ReceiveUnicast R/W Receive Unicast. If ReceiveUnicast is a logic 1, the IP100A LF
receives unicast frames (frames where the DA field matches the
48-bit value in the StationAddress register.
1 ReceiveMulticast R/W Receive Multicast. If ReceiveMulticast is a logic 1, the IP100A LF
receives all multicast frames, including broadcast frames.
2 ReceiveBroadcast R/W Receive Broadcast. If ReceiveBroadcast is a logic 1, the IP100A
LF receives all broadcast frames.
3 ReceiveAllFrames R/W Receive All Frames. If ReceiveAllFrames is a logic 1, the IP100A
LF receives all frames.
4 ReceiveMulticast- R/W Receive Multicast Hash. If ReceiveMulticastHash is a logic 1, the
Hash IP100A LF receives all which pass the hash filtering mechanism
defined in the HashTable register..
5 ReceiveIPMulticast R/W Receive IP Multicast. If ReceiveIPMulticast is a logic 1, the
IP100A LF receives all multicast IP datagrams, which are
mapped into Ethernet multicast frames with destination address
of 01:00:5e:xx:xx:xx as defined in RFC 1112 and RFC 1700. The
first 3 bytes require exact match, and the last 3 bytes are ignored.
7..6 Reserved N/A Reserved for future use.

11.4.15 RxDMABurstThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x14
Default .......................... 0x08
Width ............................ 8 bits

RxDMABurstThresh register sets the threshold for receive DMA bus master requests by the IP100A LF
based upon the number of used bytes in the receive FIFO, in units of 32 bytes. When the used space
exceeds the threshold, the IP100A LF may make a receive DMA request on the PCI bus. However, if the
used space exceeds the RxDMAFrameLen field in the current RFD, the IP100A LF will make receive
DMA bus request regardless of whether the used space exceeds the RxDMABurstThresh or not.
RxDMABurstThresh may be overridden by the urgent request mechanism. See the PCI Bus Master
Operation section for information about the relationship between RxDMABurstThresh and
RxDMAUrgentThresh. Any value less than 0x08 is invalid and is interpreted as 0x08.

BIT BIT NAME R/W BIT DESCRIPTION

7..0 RxDMABurstThresh R/W Receive DMA Burst Threshold. The RxDMABurstThresh is the of
32 byte words which must be present in the receive FIFO prior to
the assertion of a receive DMA bus master request.

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 IP100A LF
Preliminary Data Sheet
11.4.16 RxDMAListPtr
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x10
Default .......................... 0x00000000
Width ............................ 32 bits

RxDMAListPtr is the physical address of the current receive DMA Frame Descriptor in the Receive DMA
List. A value of 0x00000000 for RxDMAListPtr indicates that no more RFDs are available to accept
receive frames. RxDMAListPtr only points to addresses on 8-byte boundaries, so RFDs must be aligned
on 8-byte physical address boundaries. RxDMAListPtr may be written directly by the host system to point
the IP100A LF to the head of a newly created Receive DMA List. RxDMAListPtr is also updated by the
IP100A LF as it processes RFDs in the Receive DMA List. As the IP100A LF finishes processing a RFD,
it loads RxDMAListPtr with the value from the RxDMANextPtr field of the current RFD in order to move
on to the next RFD in the Receive DMA List. If the IP100A LF loads a value of 0x00000000 from the
current RFD, the receive DMA logic enters the idle state, waiting for a non-zero value to be written to
RxDMAListPtr. To avoid access conflicts between the IP100A LF and the host system, the host system
must set the RxDMAHalt bit in the DMACtrl register before writing to RxDMAListPtr.

BIT BIT NAME R/W BIT DESCRIPTION

31..0 RxDMAListPtr R/W Receive DMA List Pointer. RxDMAListPtr is the physical address,
on a 8-byte boundary, of the current RFD in the Receive DMA List.

11.4.17 RxDMAPollPeriod
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x16
Default .......................... 0x00
Width ............................ 8 bits

RxDMAPollPeriod determines the rate at which the current RFD’s RxDMAComplete bit of the
RxFrameStatus field in the RFD is polled for a logic 0. Polling is disabled when RxDMAPollPeriod is 0x00.
RxDMAPollPeriod is specified in increments of 320 ns. The maximum value is 127 (or 40.64 us).

BIT BIT NAME R/W BIT DESCRIPTION

6..0 RxDMAPollPeriod R/W Receive DMA Poll Period. RxDMAPollPeriod is the number of
320ns intervals between polls of the RxDMAComplete bit in the
RxFrameStatus field of the current RFD.
7 Reserved N/A Reserved for future use.

11.4.18 RxDMAStatus
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x0c
Default .......................... 0x00000000
Width ............................ 32 bits

RxDMAStatus shows the status of various operations in the receive DMA logic. Host systems should
read RxDMAStatus only if the RxDMAHalted bit in the DMACtrl register is a logic 1. Otherwise the
IP100A LF may change RFDs between accesses to RxDMAStatus. Many bits of RxDMAStatus are
identical to corresponding bits of the RxFrameStatus field.
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BIT BIT NAME R/W BIT DESCRIPTION

12..0 RxDMAFrameLen R Receive DMA Frame Length.RxDMAFrameLen is similar to the
RxDMAFrameLen bit of the RxFrameStatus field, except that
RxDMAFrameLen provides a real-time indication of the number of
bytes transferred during a receive DMA operation.
13 Reserved N/A Reserved for future use.
14 RxFrameError R See the RxFrameError bit of the RxFrameStatus field.
15 RxDMAComplete R See the RxDMAComplete bit of the RxFrameStatus field.
16 RxFIFOOverrun R See the RxFIFOOverrun bit of the RxFrameStatus field.
17 RxRuntFrame R See the RxRuntFrame bit of the RxFrameStatus field.
18 RxAlignmentError R See the RxAlignmentError bit of the RxFrameStatus field.
19 RxFCSError R See the RxFCSError bit of the RxFrameStatus field.
20 RxOversizedFrame R See the RxOversizedFrame bit of the RxFrameStatus field.
22..21 Reserved N/A Reserved for future use.
23 DribbleBits R See the DribbleBits bit of the RxFrameStatus field.
24 RxDMAOverflow R See the RxDMAOverflow bit of the RxFrameStatus field.
31..25 Reserved N/A Reserved for future use.

11.4.19 RxDMAUrgentThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x15
Default .......................... 0x04
Width ............................ 8 bits

RxDMAUrgentThresh sets a threshold at which the receive DMA logic will make a urgent bus master
request. A urgent receive DMA request will have priority over all other requests on the IP100A LF. The
urgent bus request is made when the free space in the receive FIFO falls below the value in
RxDMAUrgentThresh. A receive DMA urgent request is not subject to the RxDMABurstThresh constraint.
When the receive FIFO is close to overrun, burst efficiency is sacrificed in favor of requesting the bus as
quickly as possible. The value in RxDMAUrgentThresh represents free space in the receive FIFO in
terms of 32-byte portions.

BIT BIT NAME R/W BIT DESCRIPTION

4..0 RxDMAUrgentThresh R/W Receive DMA Urgent Threshold. RxDMAUrgentThresh is the
minimum number of 32-byte words which must be available in the
receive FIFO to avoid a receive DMA urgent request.
7..5 Reserved N/A Reserved for future use.

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11.4.20 StationAddress
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x54, 0x56, 0x58
Default .......................... 0x000000000000
Width ............................ 48 bits (accessible as 3, 16 bit words)

StationAddress is used to define the individual destination address that the IP100A LF will respond to
when receiving frames. Network addresses are generally specified in the form of 01:23:45:67:89:ab,
where the bytes are received left to right, and the bits within each byte are received right to left (Isb to
msb). The actual transmitted and received bits are in the order of 10000000 11000100 10100010
11100110 10010001 11010101.

BIT BIT NAME R/W BIT DESCRIPTION

15..0 StationAddress- R/W The least significant word of the station address, corresponding to
Word0 address 0x54.
31..16 StationAddress- R/W The second least significant word of the station address,
Word1 corresponding to address 0x56.
47..32 StationAddress- R/W The most significant word of the station address, corresponding
Word2 to address 0x58.

The address comparison logic will compare the first 16 received destination address bits against
StationAddressWord0, the second 16 received destination address bits against StationAddressWord1, and
the third 16 received destination address bits against StationAddressWord2. The value set in StationAddress
is not inserted into the source address field of frames transmitted by the IP100A LF. The source address field
for every frame must be specified by the host system as part of the frame data contents.

11.4.21 TxDMABurstThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x08
Default .......................... 0x08
Width ............................ 8 bits

TxDMABurstThresh determines the threshold for when the IP100A LF makes transmit DMA bus master
requests, based upon the available space in the transmit FIFO. TxDMABurstThresh represents free
space in the transmit FIFO in multiples of 32 bytes. When the free space exceeds the threshold, the
IP100A LF may make a transmit DMA request. However, if the free space exceeds the current FragLen
subfield of the TxFrameControl field within the current TFD, the IP100A LF will make transmit DMA bus
request regardless of whether the free space exceeds the TxDMABurstThresh or not.
TxDMABurstThresh may be overridden by the TxDMAUrgentThresh mechanism. See the PCI Bus
Master Operation section for information about the relationship between TxDMABurstThresh and
TxDMAUrgentThresh. Any value less than 0x08 is invalid and is interpreted as 0x08.

BIT BIT NAME R/W BIT DESCRIPTION

4..0 TxDMABurstThresh R/W Transmit DMA Burst Threshold. The number of 32-byte words
which must be available in the transmit FIFO prior to assertion of
a transmit DMA Burst Request.
7..5 Reserved N/A Reserved for future use.

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11.4.22 TxDMAListPtr
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x04
Default .......................... 0x00000000
Width ............................ 32 bits

TxDMAListPtr holds the physical address of the current transmit DMA Frame Descriptor in the transmit
DMA list. A value of zero in TxDMAListPtr is interpreted by the IP100A LF to mean that no more frames
remain to be transferred by transmit DMA. TxDMAListPtr can only point to addresses on 8-byte
boundaries, so TFD’s must be aligned on 8-byte boundaries. TxDMAListPtr may be written directly by
the host system to point the IP100A LF at the head of a newly created transmit DMA list. Writes to
TxDMAListPtr are ignored while the current value in TxDMAListPtr is non-zero. To avoid access conflicts
between the IP100A LF and the host system, the host system must set the TxDMAHalt bit of the
DMACtrl register to a logic 1 before writing to TxDMAListPtr (unless the host system has specific
knowledge that TxDMAListPtr contains zero).

BIT BIT NAME R/W BIT DESCRIPTION

31..0 TxDMAListPtr R/W Transmit DMA List Pointer. TxDMAListPtr holds the physical
address, on a 8-byte boundary, of the current TFD in the transmit
DMA list.
The host may examine the TxDMAListPtr to determine which
frame(s) have been transferred by transmit DMA. Those frames
in the transmit DMA list before the current TxDMAListPtr have
already been transferred by transmit DMA. If the TxDMAListPtr is
zero, then all the frames have been transmitted.

11.4.23 TxDMAPollPeriod
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x0a
Default .......................... 0x00
Width ............................ 8 bits

TxDMAPollPeriod determines the interval at which the current TFD is polled. If the current TFDs,
TxDMANextPtr field is 0x00000000, the TxDMANextPtr field is polled to determine when a new TFD is
ready to be processed. Polling is disabled when TxDMAPollPeriod is 0x00. TxDMAPollPeriod represents
a multiple of 320 ns time intervals. The maximum value is 127 (or 40.64 us).

BIT BIT NAME R/W BIT DESCRIPTION

6..0 TxDMAPollPeriod R/W Transmit DMA Poll Period. The number of 320ns intervals
between polls of the current TFD’s TxDMANextPtr field.
7 Reserved N/A Reserved for future use.

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11.4.24 TxDMAUrgentThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x09
Default .......................... 0x04
Width ............................ 8 bits

When the number of used bytes in the transmit FIFO falls below the value in the TxDMAUrgentThresh,
the transmit DMA logic will make an urgent bus master request. An urgent transmit DMA request will
have priority over the receive DMA, unless it is also making an urgent request. A transmit DMA urgent
request is not subject to the TxDMABurstThresh constraint. The relaxation of the TxDMABurstThresh
constraint for this condition is because the transmit FIFO is close to under run, and burst efficiency is
sacrificed to avoid FIFO under run. TxDMAUrgentThresh represents data in the transmit FIFO in
multiples of 32 bytes.

BIT BIT NAME R/W BIT DESCRIPTION

5..0 TxDMAUrgentThresh R/W Transmit DMA Urgent Threshold. The minimum number of
32-byte words which must be occupied in the transmit FIFO to
avoid assertion of a transmit DMA Urgent Request.
7..6 Reserved N/A Reserved for future use.

11.4.25 TxReleaseThresh
Class............................. LAN I/O Registers, FIFO Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5d
Default .......................... 0x08
Width ............................ 8 bits

TxReleaseThresh determines how much data of a frame must be transmitted before the transmit FIFO
space can be released for use by another frame. Once the number of bytes equal to the value in
TxReleaseThresh have been transmitted, that number of bytes are discarded from the transmit FIFO.
Thereafter, bytes are discarded as they are transmitted to the network. A value of 0xff in TxReleaseThresh
disables the release mechanism and transmit FIFO frame space is not released until the entire frame is
transmitted. The TxReleaseError bit in the TxStatus register indicates when a frame experiences a collision
after its release threshold has been crossed, preventing MAC from retry. When a release error occurs, the
transmitter is disabled, and the frame’s ID or sequence number is visible in TxStatus.

BIT BIT NAME R/W BIT DESCRIPTION

7..0 TxReleaseThresh R/W Transmit Release Threshold. The number of 16 byte words which
must be transmitted before the space in the transmit FIFO
occupied by the transmitted data can be released. To avoid
excessive release errors due to in-window collisions,
TxReleaseThresh should be greater than or equal to 0x04.

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11.4.26 TxStatus
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x46
Default .......................... 0x0000
Width ............................ 16 bits
TxStatus returns the status of frame transmission or transmission attempts. TxStatus actually
implements a queue of up to 31 transmit status bytes. A write of an arbitrary value to TxStatus will
advance the queue to the next transmit status byte.

BIT BIT NAME R/W BIT DESCRIPTION

0 Reserved N/A Reserved for future use.
1 TxReleaseError R Transmit Release Error. If TxReleaseError is a logic 1, a transmit
release error occurred, meaning that the frame transmission
experienced a collision after the front of the frame had already
been released to the transmit FIFO free space. See
TxReleaseThresh register.
2 TxStatusOverflow R Transmit Status Overflow. If TxReleaseError is a logic 1, the TxStatus
stack is full and as a result the transmitter has been disabled. Writing
an arbitrary value to TxStatus clears TxReleaseError but the
transmitter must be re-enabled via the TxEnable bit of the
MACCtrl1 register before transmissions may resume.
3 MaxCollisions R Maximum Collisions. If MaxCollisions is a logic 1, a frame was not
successfully transmitted due to encountering 16 collisions. The
TxEnable bit of the MACCtrl1 register is used to recover from this
condition. The frame is discarded from the transmit FIFO.
4 TxUnderrun R Transmit Underrun. If TxUnderrun is a logic 1 the frame
experienced an under run during the transmit process because
the host system was unable to supply the frame data fast enough
to keep up with the network data rate. An under run will halt the
transmitter and the transmit FIFO. The TxReset bit of the AsicCtrl
register is used to recover from an under run condition.
5 Reserved N/A Reserved for future use.
6 TxIndicateReqd R Transmit Indicate Requested. If TxIndicateReqd is a logic 1, the
TxIndicate bit of the TxFrameControl field for the corresponding
TFD was set.
7 TxComplete R Transmit Complete. If TxComplete is a logic 0, then the
TxReleaseError, TxStatusOverflow, MaxCollisions, TxUnderrun,
and TxIndicateReqd bits are undefined. If the host chooses to poll
TxStatus while waiting for a frame transmission to complete, then
TxComplete is used to determine that a frame transmission
attempt has either experienced an error, or has completed
successfully with the TxIndicate bit set in the TxFrameControl
field of the corresponding TFD.
15..8 TxFrameId R/W Transmit Frame Identification. TxFrameId contains the value from
the FrameId subfield within the TxFrameControl field of TFD
corresponding to the currently transmitting or most recently
transmitted frame. Host systems can use TxFrameId during
transmit error recovery by scanning through the TFD’s in the
transmit DMA list, searching for a match between the TxFrameId
value and a TxFrameControl’s, FrameId value in the TFD.

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11.4.27 WakeEvent
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x45
Default .......................... 0x00
Width ............................ 8 bits

WakeEvent contains enable bits to control which types of events can generate a wake event to the host
system. WakeEvent also contains status bits indicating the specific wake events which have occurred.

BIT BIT NAME R/W BIT DESCRIPTION

0 WakePktEnable R/W Wake Packet Enable. If WakePktEnable is a logic 1, the IP100A
LF may generate wake events via a PCI interrupt due to Wake
Packet reception. The PmeEn bit in the PowerMgmtCtrl register
must be set in order for WakePktEnable to be recognized.
WakePktEnable has no effect in power mode D0.
1 MagicPktEnable R/W Magic Packet Enable. If MagicPktEnable is a logic 1, the IP100A
LF may generate wake events via a PCI interrupt due to Magic
Packet reception. The PmeEn bit in the PowerMgmtCtrl register
must be set in order for MagicPktEnable to be recognized.
MagicPktEnable has no effect in power mode D0.
2 LinkEventEnable R/W Link Event Enable. If LinkEventEnable is a logic 1, the IP100A LF
may generate wake events via a PCI interrupt due to a change in
link status (cable connect or disconnect). The PmeEn bit in the
PowerMgmtCtrl register must be set in order for LinkEventEnable to
be recognized. LinkEventEnable has no effect in power mode D0.
3 WakePolarity R/W Wake Polarity. If WakePolarity is a logic 1, the PMEN signal will
be asserted HIGH. If WakePolarity is a logic 0, the PMEN signal
will be asserted LOW.
4 WakePktEvent R Wake Packet Event. If WakePktEvent is a logic 1, a wake packet
(which meets the reception criteria set by the host system) has
been received. WakePktEnable must be a logic 1 for
WakePktEvent to operate. WakePktEvent is cleared following a
read of the WakeEvent register.
5 MagicPktEvent R Magic Packet Event. If MagicPktEvent is a logic 1, a Magic
Packet packet has been received. MagicPktEnable must be a
logic 1 for MagicPktEvent to operate. MagicPktEvent is cleared
following a read of the WakeEvent register.
6 LinkEvent R Link Event. If LinkEvent is a logic 1, a link status event has occurred.
LinkEventEnable must be a logic 1 for LinkEvent to operate.
LinkEvent is cleared following a read of the WakeEvent register.
7 WakeOnLanEnable R/W Wake On LAN Enable. If WakeOnLanEnable is a logic 1, the
IP100A LF is in WakeOnLan mode regardless of the power
management register settings in the configuration space.
WakeOnLanEnable is loaded from the WakeOnLanEnable bit of
AsicCtrl field within the EEPROM.

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11.5 Statistic Registers
The Statistic registers implement several counters defined in the IEEE 802.3 standard. Note reading a
statistic register will also clear that register. The statistics gathering must be enabled by setting the
StatisticsEnable bit in MACCtrl1 for the statistics registers to count events.

11.5.1 BroadcastFramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7d
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 BroadcastFrames- R/W Broadcast Frames Received OK is the count of the number of
ReceivedOk frames that are successfully received with destination address
equal to the broadcast address (0xFFFFFFFFFFFF).
BroadcastFramesReceivedOk does not include frames received
with frames too long, FCS, length or alignment errors, or frames
lost due to internal MAC sublayer error (i.e.overrun).
BroadcastFramesReceivedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.22.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when BroadcastFramesReceivedOk reaches a
value of 0xC0. BroadcastFramesReceivedOk is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of BroadcastFramesReceivedOk also clears the register.

11.5.2 BroadcastFramesTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7c
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 BroadcastFrames- R/W Broadcast Frames Transmitted is the count of the number of
TransmittedOk frames that are successfully transmitted to the broadcast address
(0xFFFFFFFFFFFF). Frames transmitted to other multicast
addresses are excluded from this statistic.
BroadcastFramesTransmittedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.19.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when BroadcastFramesTransmittedOk reaches
a value of 0xC0. BroadcastFramesTransmittedOk is enabled by
writing a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of BroadcastFramesTransmittedOk also clears the register.

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11.5.3 CarrierSenseErrors
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x74
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

3..0 CarrierSenseErrors R/W Carrier Sense Errors counts the number of times that the carrier
sense signal (CRS) was de-asserted (a logic 0) during the
transmission of a frame without collision. The carrier sense signal
is not monitored for the purpose of this statistic until after the
preamble and start-of-frame delimiter fields of the Ethernet frame
have been transmitted. CarrierSenseErrors will wrap around to
zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.13.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when CarrierSenseErrors reaches a value of
0xC0. CarrierSenseErrors is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of CarrierSenseErrors also clears the register.
7..4 Reserved R/W Reserved for future use.

11.5.4 FramesAbortedDueToXSColls
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7b
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 FramesAborted- R/W Frames Aborted Due to Excess Collisions counts the number of
DueToXSColls frames which are not transmitted successfully due to excessive
collisions. FramesAbortedDueToXSColls will wrap around to zero
after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.11.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesAbortedDueToXSColls reaches a
value of 0xC0. FramesAbortedDueToXSColls is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesAbortedDueToXSColls also clears the register.

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11.5.5 FramesLostRxErrors
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x79
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 FramesLostRxErrors R/W Frames Lost Due to Receive Errors is a count of the number of
frames that should have been received (the destination address
matched the filter criteria) but experienced a receive FIFO
overrun error (the receive FIFO does not have enough free space
to store the received data). FramesLostRxErrors only includes
overruns that become apparent to the host system, and does not
include frames that are completely ignored due to a completely
full receive FIFO at the beginning of frame reception.
FramesLostRxErrors will wrap around to zero after reaching
0xFF. See IEEE 802.3 Clause 30.3.1.1.15.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesLostRxErrors reaches a value of
0xC0. FramesLostRxErrors is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of FramesLostRxErrors also clears the register.

11.5.6 FramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x72
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 FramesReceivedOk R/W Frames Received OK is the count of the number of frames that
are successfully received. FramesReceivedOk does not include
frames received with frames too long, FCS, length or alignment
errors, or frames lost due to internal MAC sublayer error (i.e.
overrun). FramesReceivedOk will wrap around to zero after
reaching 0xFFFF. See IEEE 802.3 Clause 30.3.1.1.5.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesReceivedOk reaches a value of
0xC0. FramesReceivedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of FramesReceivedOk also clears the register.

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11.5.7 FramesTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x70
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 FramesTransmitted- R/W Frames Transmitted OK is a count of the number of frames that
OK are successfully transmitted. FramesTransmittedOk will wrap
around to zero after reaching 0xFFFF. See IEEE 802.3 Clause
30.3.1.1.2.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesTransmittedOk reaches a value
of 0xC0. FramesTransmittedOk is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesTransmittedOk also clears the register.

11.5.8 FramesWithDeferredXmission
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x78
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 FramesWithDeferred- R/W Frames with Deferred Transmit is a count of the number of
Xmission frames that must delay their first attempt of transmission because
the medium was busy. Frames involved in any collisions are not
counted by FramesWithDeferredXmission. FramesWithDeferred-
Xmission wrap around to zero after reaching 0xFF. See IEEE
802.3 Clause 30.3.1.1.9.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesWithDeferredXmission reaches a
value of 0xC0. FramesWithDeferredXmission is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesWithDeferredXmission also clears the register.

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11.5.9 FramesWithExcessiveDeferal
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7a
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 FramesWithExcessi R/W Frames with Excessive Deferrals counts the number of frames
veDeferal that deferred for an excessive period of time (exceeding the defer
limit). FramesWithExcessiveDeferal is only incremented once per
LLC frame. FramesWithExcessiveDeferal will wrap around to
zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.20.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when FramesWithExcessiveDeferal reaches a
value of 0xC0. FramesWithExcessiveDeferal is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of FramesWithExcessiveDeferal also clears the register.

11.5.10 LateCollisions
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x75
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 LateCollisions R/W Late Collisions is a count of the number of times that a collision
has been detected later than 1 slot time into the transmitted
frame. LateCollisions will wrap around to zero after reaching
0xFF. See IEEE 802.3 Clause 30.3.1.1.10.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when LateCollisions reaches a value of 0xC0.
LateCollisions is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of LateCollisions also clears the register.

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11.5.11 MulticastFramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7f
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 MulticastFrames- R/W Multicast Frames Received OK is the count of the number of
ReceivedOk frames that are successfully received to a group destination
address other than the broadcast address (0xFFFFFFFFFFFF).
MulticastFramesReceivedOk does not include frames received
with frames too long, FCS, length or alignment errors, or frames
lost due to internal MAC sublayer error (i.e. overrun).
MulticastFramesReceivedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.21.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MulticastFramesReceivedOk reaches a
value of 0xC0. MulticastFramesReceivedOk is enabled by writing
a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of MulticastFramesReceivedOk also clears the register.

11.5.12 MulticastFramesTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7e
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 MulticastFrames- R/W Multicast Frames Transmitted OK is a count of the number of
TransmittedOk frames that are successfully transmitted to a group destination
address other than the broadcast address (0xFFFFFFFFFFFF).
MulticastFramesTransmittedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.18.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MulticastFramesTransmittedOk reaches a
value of 0xC0. MulticastFramesTransmittedOk is enabled by
writing a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of MulticastFramesTransmittedOk also clears the register.

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 IP100A LF
Preliminary Data Sheet
11.5.13 MultipleCollisionFrames
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x76
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 MultipleCollision- R/W Multiple Collision Frames is a count of the number of frames that
Frames are involved in more than one collision and are subsequently
transmitted successfully. MultipleCollisionFrames will wrap around
to zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.4.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when MultipleCollisionFrames reaches a value
of 0xC0. MultipleCollisionFrames is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl1 register.
A read of MultipleCollisionFrames also clears the register.

11.5.14 OctetsReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x68
Default .......................... 0x00000000
Width ............................ 32 bits (accessible as 2, 16 bit words)

BIT BIT NAME R/W BIT DESCRIPTION

19..0 OctetsReceivedOk R/W Octets Received OK is the count of the number of data and
padding octets in frames that are successfully received.
OctetsReceivedOk does not include frames received with frames
too long, FCS, length or alignment errors, or frames lost due to
internal MAC sublayer error (i.e. overrun). OctetsReceivedOk will
wrap around to zero after reaching 0xFFFFFFFF. See IEEE
802.3 Clause 30.3.1.1.14.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when OctetsReceivedOk reaches a value of
0xC0. OctetsReceivedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of OctetsReceivedOk also clears the register.
31..20 Reserved N/A Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
11.5.15 OctetsTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x6c
Default .......................... 0x00000000
Width ............................ 32 bits (accessible as 2, 16 bit words)

BIT BIT NAME R/W BIT DESCRIPTION

19..0 OctetsTransmitted- R/W Octets Transmitted OK is a count of data and padding octets of
Ok frames successfully transmitte cm d. OctetsTransmittedOk will
wrap around to zero after reaching 0xFFFFFFFF. See IEEE
802.3 Clause 30.3.1.1.8.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when OctetsTransmittedOk reaches a value of
0xC0. OctetsTransmittedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of OctetsTransmittedOk also clears the register.
31..20 Reserved N/A Reserved for future use.

11.5.16 SingleCollisionFrames
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x77
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 Single Collision R/W Single Collision Frames is a count of the number of frames that
Frames are involved in a single collision, and are subsequently
transmitted successfully. SingleCollisionFrames will wrap around
to zero after reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.3.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when SingleCollisionFrames reaches a value
of 0xC0. SingleCollisionFrames is enabled by writing a logic 1 to
the StatisticsEnable bit in the MACCtrl1 register.
A read of SingleCollisionFrames also clears the register.

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 IP100A LF
Preliminary Data Sheet
11.6 LAN PCI Configuration Registers
PCI based systems use a slot-specific block of configuration registers to perform configuration of devices
on the PCI bus. The configuration registers are accessed with PCI Configuration Cycles.

Each PCI bus device is required to decode 256 bytes of configuration registers. Of these, the first 64
bytes are pre-defined by the PCI Specification. The remaining registers may be used as needed for PCI
device-specific configuration registers. In PCI Configuration Cycles, the host system provides a
slot-specific decode signal (IDSEL) which informs the PCI device that a configuration cycle is in progress.
The PCI device responds by asserting DEVSELN, and decoding the specific configuration register from
the address bus and the byte enable signals. See the PCI Expansion ROM specification for information
on generating configuration cycles from driver software.

Figure 14 shows the PCI configuration registers implemented by IP100A LF. All locations within the
256-byte configuration space that are not shown in the table, are not implemented and return zero when
read.

ADDR
BYTE 3 BYTE 2 BYTE 1 BYTE 0
OFFSET
Data PowerMgmtCtrl 0x54
PowerMgmtCap NextItemPtr Capld 0x50
0x4C
0x48
0x44
0x40
MaxLat MinGnt InterruptPin InterruptLine 0x3C
0x38
CapPtr 0x34
ExpRomBaseAddress 0x30
Subsystemld SubsystemVendorld 0x2C
CISPointer 0x28
0x24
0x20
0x1C
0x18
MemBaseAddress 0x14
IoBaseAddress 0x10
HeaderType LatencyTimer CacheLineSize 0x0C
ClassCode Revisionld 0x08
ConfigStatus ConfigCommand 0x04
Deviceld Vendorld 0x00
FIGURE 14 : IP100A LF PCI Register Layout

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 IP100A LF
Preliminary Data Sheet
11.6.1 CacheLineSize
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0c
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 CacheLineSize R/W Cache Line Size. The system BIOS writes the system’s cache line
size into CacheLineSize. The host system uses CacheLineSize to
optimize PCI bus master operation (choosing the best memory
command, etc.). The value in CacheLineSize represents the
number of double words in a cache. CacheLineSize values must
be a power of two, from 0x04 to 0x80 (giving a range of 16 to 512
bytes). CacheLineSize values which are not a power of two,
between 4 and 128 are interpreted as 0x00.

11.6.2 CapId
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x50
Default .......................... 0x01
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 CapId R Capabilities ID. CapId indicates the type of the capability data
structure for the IP100A LF. CapId is set to the value 0x01 to
indicate a PCI Power Management structure.

11.6.3 CapPtr
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x34
Default .......................... 0x50
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 CapPtr R Capabilities Pointer. CapPtr indicates the beginning of a chain of
registers which describe enhanced functions. CapPtr register
returns 0x50, which is the address of the first in a series of power
management registers.

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 IP100A LF
Preliminary Data Sheet
11.6.4 CISPointer
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x28
Default Value ................ 0x00000802
Width ............................ 32 bits

CISPointer identifies the location of the Card Information Structure (CIS). CISPointer contains the offset
of CIS in memory space. CISPointer value is hardwired and can not be changed. Although the CIS is in
memory, it is physically located in the EEPROM. Because the EEPROM access is so slow, the PCI
target will issue a Retry for each new access.

BIT BIT NAME R/W BIT DESCRIPTION

2..0 AddressSpace- R Address Space Indicator. AddressSpaceIndicator specifies the
Indicator base address within the space indicated. The
AddressSpaceOffset is added to AddressSpaceIndicator to
identify the start of the CIS. The AddressSpaceIndicator value is
0x2, indicating the IP100A LF only supports CIS access in the
memory pointed to by the PCI Base Address Register 1.
27..3 AddressSpaceOffset R Address Space Offset. AddressSpaceOffset is the offset from the
base address specified by the PCI Base Address Register 1. The
IP100A LF supports CIS in memory space.
31..28 ROMImageNumber R ROM Image Number. ROMImageNumber is 0x0 indicating the
IP100A LF does not support CIS access in the expansion ROM.

11.6.5 ClassCode
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x09
Default .......................... 0x020000
Width ............................ 24 bits

BIT BIT NAME R/W BIT DESCRIPTION

23..0 ClassCode R Class Code. ClassCode identifies the general function of the PCI
device. A value of 0x020000 indicates an Ethernet network
controller.

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 IP100A LF
Preliminary Data Sheet
11.6.6 ConfigCommand
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x04
Default .......................... 0x0000
Width ............................ 16 bits

ConfigCommand provides control over the adapter’s ability to generate and respond to PCI cycles.
When a zero is written to ConfigCommand, the IP100A LF is logically disconnected from the PCI bus,
except for configuration cycles.

BIT BIT NAME R/W BIT DESCRIPTION

0 IoSpace R/W I/O Space. When IoSpace is a logic the IP100A LF can respond
to I/O space accesses (if the IP100A LF is in the D0 power state).
1 MemorySpace R/W Memory Space. When MemorySpace, and the
AddressDecodeEnable bit in the ExpRomBaseAddress register are
both a logic 1, and if the IP100A LF is in the D0 power state, the
IP100A LF is able to decode accesses to an Expansion ROM (if
present).
2 BusMaster R/W Bus Master. When BusMaster is a logic 1 the IP100A LF is able to
initiate bus master cycles (if the adapter is in the D0 power state).
Note: If the IP100A LF is initialized to PCI-X mode, BusMaster is
ignored when initiating Split Completions.
3 Reserved N/A Reserved for future use.
4 MWlEnable R/W Memory Write and Invalidate Enable. When MWlEnable is a logic
1 the IP100A LF is permitted to use the MWI command.
5 Reserved N/A Reserved for future use.
6 ParityErrorResponse R/W Parity Error Response. When ParityErrorResponse is a logic 1
the IP100A LF responds to parity errors as defined within the PCI
specification. When ParityErrorResponse is a logic 0, the IP100A
LF ignores parity errors.
7 Reserved N/A Reserved for future use.
8 SERREnable R/W System Error Enable. When SERREnable is a logic 1, the SERRN
signal is allowed to transition as appropriate. When SERREnable is
a logic 0, the SERRN signal is a continuous logic 0.
15..9 Reserved N/A Reserved for future use.

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 IP100A LF
Preliminary Data Sheet
11.6.7 ConfigStatus
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset.............. 0x06
Default .......................... 0x0210
Width ............................ 16 bits

ConfigStatus is used to record status information for PCI bus events. Read/write bits inConfigStatus can
only be reset, not set, by writing to this register. Bits are reset by writing a one to the corresponding bit.

BIT BIT NAME R/W BIT DESCRIPTION

3..0 Reserved N/A Reserved for future use.
4 Capabilities R Capabilities. Capabilities is a logic 1 to indicate a set of extended
capabilities registers exists for the IP100A LF. The CapPtr
register indicates the first address location of the extended
capabilities register set.
6..5 Reserved N/A Reserved for future use.
7 FastBackToBack R Fast Back to Back. When FastBackToBack is a logic 1 the
IP100A LF when operating as a Target, supports fast
back-to-back transactions as defined by the criteria in the section
3.4.2 of the PCI specification.
8 DataParityReported R/W Master Data Parity Error. When DataParityReported is a logic 1,
the IP100A LF when operating as a Master, has detected the
PERRN signal asserted, and the ParityErrorResponse bit in the
ConfigCommand register as a logic 1.
10..9 DevselTiming R Device Select Timing. DevselTiming is used to encode the
slowest time with which the IP100A LF asserts the DEVSELN
signal. A value of 0x1 for DevselTiming indicates support for
“medium” speed DEVSELN assertion.
11 SignaledTargetAbort R/W Signaled Target Abort. The IP100A LF sets SignaledTargetAbort
to a logic 1 when the IP100A LF terminates a bus transaction with
target-abort.
12 ReceivedTargetAbort R/W Received Target Abort. The IP100A LF sets
ReceivedTargetAbort to a logic 1 when, operating as a bus
master, a IP100A LF bus transaction is terminated with
target-abort.
13 ReceivedMasterAbort R/W Received Master Abort. The IP100A LF sets
ReceivedMasterAbort to a logic 1 when, operating as a bus
master, a IP100A LF bus transaction is terminated with
master-abort.
14 SignaledSystemError R/W Signaled System Error. When SignaledSystemError is a logic 1,
the IP100A LF asserts the SERRN signal.
15 DetectedParityError R/W Detected Parity Error. When DetectedParityError is a logic 1 the
IP100A LF has detected a parity error, regardless of whether
parity error handling is enabled.

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 IP100A LF
Preliminary Data Sheet
11.6.8 Data
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x57
Default Value ................ 0x00
Width ............................ 8 bits

Data reports the power consumption of the IP100A LF. The values of DataSelect and DataScale in the
PowerMgmtCtrl register are used to interpret the value of Data.

BIT BIT NAME R/W BIT DESCRIPTION

7..0 Data R Data. Data reports power consumption and dissipation of the
IP100A LF at worst-case conditions. To properly interpret the
value read from Data, it must be scaled by the factor indicated in
the DataScale field of the PowerMgmtCtrl register. The value of
Data depends on the value of the DataSelect field of the
PowerMgmtCtrl register.
Data is loaded from the Data field in the EEPROM during a
AutoInit reset.
DATASELECT DATA
0x0 1 * DataScale Watts
D0 Power Consumption
0x1 1 * DataScale Watts
D1 Power Consumption
0x2 1 * DataScale Watts
D2 Power Consumption
0x3 1 * DataScale Watts
D3 Power Consumption
0x4 1 * DataScale Watts
D4 Power Dissipated
0x5 1 * DataScale Watts
D5 Power Dissipated
0x6 1 * DataScale Watts
D6 Power Dissipated
0x7 1 * DataScale Watts
D7 Power Dissipated
0x8 through 0xF 0x00
Reserved.

11.6.9 DeviceId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x02
Default Value ................ 0x0200
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..0 DeviceId R DeviceId contains the 16-bit device ID for the IP100A LF.

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 IP100A LF
Preliminary Data Sheet
11.6.10 ExpRomBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x30
Default .......................... 0x00000000
Width ............................ 32 bits

ExpRomBaseAddress allows the system to define the base address for the adapter’s Expansion ROM.
ExpRomBaseAddress is disabled (read only with a value of 0x00000000) when the IP100A LF is in
Multi-Function Mode (see the Reserved/MultiFunction bit in the AsicCtrl register).

BIT BIT NAME R/W BIT DESCRIPTION

0 AddressDecode- R/W Address Decode Enable. If AddressDecodeEnable is a logic 0,
Enable the IP100A LF’s Expansion ROM is disabled. If
AddressDecodeEnable is a logic 1, and the MemorySpace bit in
the ConfigCommand register is a logic 1, the IP100A LF will
respond to accesses to the expansion ROM space.
14..1 Reserved N/A Reserved for future use.
31..15 RomBaseAddress R/W ROM Base Address. RomBaseAddress contains the expansion
ROM base address, or the upper 16 bits (or 15 bits, depending on
the state of the ExpRomSize bit in the AsicCtrl register) of the
Expansion ROM address range.
If the ExpRomSize bit in the AsicCtrl register is a logic 0, all 16
bits of RomBaseAddress are valid. If the ExpRomSize bit in the
AsicCtrl register is a logic 1, bits 31 through 16 of
RomBaseAddress are valid, with bit 15 ignored (set to a logic 0)
during write operations.

11.6.11 HeaderType
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0e
Default .......................... 0x00 (single function)/0x80 (multi-function)
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 HeaderType R Header Type. If the Reserved/MultiFunction bit in the AsicCtrl
register is a logic 0, HeaderType is set to 0x00 identifying the
IP100A LF as a single-function PCI device and specifying the
configuration register layout.
If the Reserved/MultiFunction bit in the AsicCtrl register is a logic
1, HeaderType is set to 0x80 identifying the IP100A LF as a
multi-function PCI device and specifying the configuration register
layout.

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 IP100A LF
Preliminary Data Sheet
11.6.12 InterruptLine
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3c
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 InterruptLine R/W Interrupt Line. InterruptLine specifies the interrupt level used by the
IP100A LF. By setting InterruptLine the host system may configure
the appropriate interrupt vector for its Interrupt Service Routine.
For 80x86 processor based host systems, InterruptLine
corresponds to the IRQ number (0x00 through 0x0F), with the
value 0xFF corresponding to disabled interrupts.

11.6.13 InterruptPin
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3d
Default .......................... 0x01
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 InterruptPin R Interrupt Pin. InterruptPin indicates which PCI interrupt signal the
IP100A LF will utilize. The IP100A LF always utilizes the INTAN
interrupt signal, corresponding to an InterruptPin value of 0x01.

11.6.14 IoBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x10
Default .......................... 0x00000001
Width ............................ 32 bits

IoBaseAddress is used to define the I/O base address for the IP100A LF. PCI systems requires that the
I/O base address be set as if the system used 32-bit I/O addressing. The upper 25 bits of IoBaseAddress
are read/write accessible, indicating that the IP100A LF requires 128 bytes of I/O space in the system I/O
map.

BIT BIT NAME R/W BIT DESCRIPTION

0 IoBaseAddrInd R I/O Base Address Indicator. When IoBaseAddrInd is a logic 1,
IoBaseAddress contains the valid I/O base address for the IP100A
LF.
6..1 Reserved N/A Reserved for future use.
31..7 IoBaseAddress R/W I/O Base Address. IoBaseAddress contains the 25 bit I/O base
address value. The IP100A LF uses 128 bytes of I/O address
space.

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 IP100A LF
Preliminary Data Sheet
11.6.15 LatencyTimer
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0d
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

2..0 Reserved N/A Reserved for future use.
7..3 LatencyTimer R/W Latency Timer. LatencyTimer indicates, in increments of 8 bus
clocks, the length of time which the IP100A LF may hold the PCI
bus in the presence of other bus requestors. Whenever the
IP100A LF asserts the FRAMEN signal, the latency timer is
started. When the latency timer count expires, the IP100A LF
must relinquish the bus as soon as its GNTN signal has been
deasserted.

11.6.16 MaxLat
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3f
Default .......................... 0x0A
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 MaxLat R Maximum Latency. MaxLat specifies, in 250 ns increments, how
often the IP100A LF requires bus access while operating as a bus
master. Bits 5 through 1 of the MaxLat value are loaded from the
ConfigParm field within an EEPROM during auto initialization of
the IP100A LF.

11.6.17 MemBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x14
Default .......................... 0x00000000
Width ............................ 32 bits

MemBaseAddress can be disabled via loading of the ConfigParm field from an EEPROM during
auto-ini-tialization of the IP100A LF.

BIT BIT NAME R/W BIT DESCRIPTION

0 MemBaseAddrInd R Memory Base Address Indicator. When MemBaseAddrInd is a
logic 1, MemBaseAddrInd contains the valid memory base
address.

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 IP100A LF
Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
2..1 MemMapType R Memory Map Type. MemMapType defines how the host system
maps the IP100A LF’s registers within the host system memory
space. Bit 2 of MemMapType is always a logic 0, while bit 1 is
loaded from the Lower1Meg bit of the ConfigParm field within an
EEPROM during auto initialization of the IP100A LF.
BIT 2 BIT 1 REGISTER MAPPING
0 0 Anywhere within a 32 bit address space
0 1 Lower 1 megabyte of 32 bit address space
1 x Undefined
6..3 Reserved N/A Reserved for future use.
31..7 MemBaseAddress R/W Memory Base Address. MemBaseAddress contains the 25 bit
memory base address value. The IP100A LF uses 128 bytes of
I/O space.

11.6.18 MinGnt
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3e
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 MinGnt R Minimum Grant Time. MinGnt specifies, in 250 ns increments,
how long a burst period the IP100A LF requires when operating
as a bus master. Bits 7 through 4 of the MinGnt value are loaded
from the ConfigParm field within an EEPROM during auto
initialization of the IP100A LF.

11.6.19 NextItemPtr
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x51
Default .......................... 0x00
Width ............................ 8 bits

BIT BIT NAME R/W BIT DESCRIPTION

7..0 NextItemPtr R Next Item Pointer. NextItemPtr indicates the next capability data
structure in the capabilities list. When NextItemPtr is set to the
value 0x00, there are no further data structures.

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 IP100A LF
Preliminary Data Sheet
11.6.20 PowerMgmtCap
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x52
Default Value ................ 0x7602
Width ............................ 16 bits

PowerMgmtCap provides information about the IP100A LF’s power management capabilities. Several
bits are loaded from the EEPROM during auto-initialization.

BIT BIT NAME R/W BIT DESCRIPTION

2..0 Versi on R Version. Version is set to 0x2, indicating PCI Bus Power
Management Specification Revision 1.1.
3 Reserved N/A Reserved for future use.
4 Vaux R Auxiliary Voltage. If Vaux is a logic 1, auxiliary power via the PCI
Bus is required from the system to support PME in the D3cold
state. If Vaux is a logic 0, auxiliary power is supplied from
elsewhere (i.e. not from the PCI Bus) to support PME in the
D3cold state.
8..5 Reserved N/A Reserved for future use.
9 D1Support R D1 Power State Support. When D1Support is a logic 1, the
IP100A LF supports the D1 power state. D1Support is loaded
from the ConfigParm field of an EEPROM during auto
initialization of the IP100A LF.
10 D2Support R D2 Power State Support. When D2Support is a logic 1, the
IP100A LF supports the D2 power state. D2Support is loaded
from the ConfigParm field of an EEPROM during auto
initialization of the IP100A LF.
15..11 PmeSupport R Power Management Event Support. PmeSupport indicates the
power states from which the IP100A LF is able to generate a
power management event by asserting the PMEN signal. Each bit
corresponds to a power state. A logic 1 in a particular bit position
indicates that events can be generated from the indicated power
state.
POWER MANAGEMENT EVENT
BIT BIT BIT BIT BIT
MAY BE GENERATED FROM
15 14 13 12 11
STATE
x x x x 1 D0
x x x 1 x D1
x x 1 x x D2
x 1 x x x D3Hot
1 x x x x D3Cold
PmeSupport bit 11 and 14 are hard-wired to 0 and 1 respectively,
while bits 12, 13, and 15 are loaded from the ConfigParm field of
an EEPROM during auto initialization of the IP100A LF.

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Preliminary Data Sheet
11.6.21 PowerMgmtCtrl
Class............................. LAN PCI Configuration Registers, Power Management
Base Address ............... PCI device configuration header start
Address Offset .............. 0x54
Default Value ................ 0x4000
Width ............................ 16 bits

PowerMgmtCtrl allows control over the power state and the power management interrupts.

BIT BIT NAME R/W BIT DESCRIPTION

1..0 PowerState R/W Power State. PowerState indicates the current power state of the
IP100A LF. If PowerState is set to a value other than 0x0, the
IP100A LF will not respond to PCI I/O or memory cycles, nor will
the IP100A LF be able to generate PCI bus master cycles.
BIT 1 BIT 0 POWER STATE
0 0 D0
0 1 D1
1 0 D2
1 1 D3
7..2 Reserved N/A Reserved for future use.
8 PmeEn R/W Power Management Event Enable. When PmeEn is a logic 1, the
IP100A LF is allowed to report wake events on the PMEN signal.
The criteria for generating wake events is defined by the
WakeEvent register. PmeEn is loaded from the ConfigParm field
of an EEPROM during auto initialization of the IP100A LF.
12..9 DataSelect R/W Data Select. DataSelect is used to select which data is to be
reported through the Data register and DataScale field.
14..13 DataScale R Data Scale. DataScale indicates the scaling factor to be used
when interpreting the value of the Data register. The
interpretation of the scale values is defined as follows:
DATASCALE SCALE FACTOR
0x0 Unknown
0x1 0.1
0x2 0.01
0x3 0.001
15 PmeStatus R/W Power Management Event Status. When PmeStatus is a logic 1 a
wake event has occurred. PmeStatus may be a logic 1 regardless
of the value of PmeEn. Writing a logic 1 to PmeStatus will set
PmeStatus to a logic 0. Writing a logic 0 to PmeStatus has no
effect.

11.6.22 RevisionId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x08
Default .......................... Depends on revision of actual device. See description below.
Width ............................ 8 bits

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Preliminary Data Sheet
BIT BIT NAME R/W BIT DESCRIPTION
7..0 RevisionId R Revision ID. RevisionId contains the revision code for the IP100A
LF.
REVISIONID SILICON REVISION
30 B0

11.6.23 SubsystemId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x2e
Default .......................... 0x0000
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..0 SubsystemId R Subsystem ID. SubsystemId contains the value loaded from the
ConfigParm field within an EEPROM during auto initialization of
the IP100A LF.

11.6.24 SubsystemVendorId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x2c
Default .......................... EEPROM Value
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..0 SubsystemVendorId R Subsystem Vendor ID. SubsystemVendorId contains the value
loaded from the ConfigParm field within an EEPROM during auto
initialization of the IP100A LF.

11.6.25 VendorId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x00
Default .......................... 0x13f0
Width ............................ 16 bits

BIT BIT NAME R/W BIT DESCRIPTION

15..0 VendorId R Vendor ID. VendorId contains the unique 16-bit manufacturer’s ID
as allocated by the PCI Special Interest Group. The manufacturer
ID is 0x13F0.

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 IP100A LF
Preliminary Data Sheet
11.7 EEPROM Data Format
Figure 15 summarizes the layout of the EEPROM.

ADDR
16 BIT WORD
OFFSET
StationAddress 0x12
StationAddress 0x11
StationAddress 0x10
0x0F
0x0E
0x0D
0x0C
0x0B
FunctionsCtrl 0x0A
: :
: :
Subsystemld 0x03
SubsystemVendorld 0x02
AsicCtrl 0x01
ConfigParm 0x00
FIGURE 15 : IP100A LF EEPROM Field Layout

11.7.1 AsicCtrl
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x01
Access Mode ................ Read Only
Width ............................ 16 bits

AsicCtrl supplies the value for the least significant byte of the AsicCtrl register and the WakeEvent
register.

BIT BIT NAME BIT DESCRIPTION

0 LEDFlashSpeed This bit determines the flashing speed of the LED.
Set to 0 will have LED On and Off ratio of 5 : 35 ms(Fast)
Set to 1 will have LED On and Off ratio of 20 : 60 ms(Slow)
LEDFlashSpeed corresponds to the LEDFlashSpeed bit in the AsicCtrl
register.
1 LED Mode 0: Set LED Mode 0
1: Set LED Mode 1
LED Mode corresponds to the LED Mode bit in the AsicCtrl register.
2 TxLargeEnable Transmit Large Frames Enable. TxLargeEnable corresponds to the
TxLargeEnable bit in the AsicCtrl register.
3 RxLargeEnable Receive Large Frames Enable. RxLargeEnable corresponds to the
RxLargeEnable bit in the AsicCtrl register.

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Preliminary Data Sheet
BIT BIT NAME BIT DESCRIPTION
4 ExpRomDisable Expansion ROM Disable. ExpRomDisable corresponds to the
ExpRomDisable bit in the AsicCtrl register.
5 PhySpeed10 Physical Layer Device Speed 10Mbps. PhySpeed10 corresponds to the
PhySpeed10 bit in the AsicCtrl register.
6 PhySpeed100 Physical Layer Device Speed 100Mbps. PhySpeed100 corresponds to
the PhySpeed100 bit in the AsicCtrl register.
7 PhyMedia Physical Layer Device Media. PhyMedia corresponds to the PhyMedia bit
in the AsicCtrl register.
14..8 Reserved Reserved for future use.
15 WakeOnLanEnable Wake On LAN Enable. WakeOnLanEnable corresponds to the
WakeOnLanEnable bit in the WakeEvent register.

11.7.2 ConfigParm
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x00
Access Mode ................ Read Only
Width ............................ 16 bits

BIT BIT NAME BIT DESCRIPTION

0 FastBackToBack Fast Back to Back. FastBackToBack corresponds to the
FastBackToBack bit in the ConfigStatus register.
1 Lower1Meg Lower 1 Megabyte. Lower1Meg corresponds to bit 1 of the MemMapType
bit in the MemBaseAddress register.
2 DisableMemBase Disable Memory Base Address Register. DisableMemBase does not
correspond directly to any register accessible by the host system. If
DisableMemBase is a logic 1 during auto initialization of the IP100A LF,
the MemBaseAddress register will be disabled. When disabled, the value
returned when the MemBaseAddress register is read is undefined.
3 D3ColdPme D3 Cold Power Management Event. D3ColdPme corresponds to the
PmeSupport bit in the PowerMgmtCap register.
4 D1Support D1 Power State Support. D1Support corresponds to the D1Support bit in
the PowerMgmtCap register.
5 D2Support D2 Power State Support. D2Support corresponds to the D2Support bit in
the PowerMgmtCap register.
6 PmeEn Power Management Event Enable. PmeEn corresponds to the PmeEn bit
in the PowerMgmtCtrl register.
10..7 MinGnt Minimum Grant. MinGnt corresponds to bits 7 through 4 of the MinGnt
register.
15..11 MaxLat Maximum Latency. MaxLat corresponds to bits 5 through 1 of the MaxLat
register.

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Preliminary Data Sheet
11.7.3 FunctionsCtrl
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x0A
Access Mode ................ Read Only
Width ............................ 16 bits

BIT BIT NAME BIT DESCRIPTION

0 LDPS Enable Link-Down-Power-Saving mode. Set this bit to 1 will reduce the power
usage of IP100A LF if the link between IP100A LF and another terminal
has terminated.
1 Auto-Cross-Over Enable Auto Cross Function. At logic 1, IP100A LF will be able to use
Enable both crossover UTP wire and non-crossover UTP wire.
2 Reserved Reserved for future use. Default setting as 0
3 Last-Gasp Control Enable Last Gasp Function. At logic 1, IP100A LF will activate last gasp
function, and IP100A LF will be able to send last gasp frames.
6..4 Last-Gasp Repeat These 3 bits will decide the number of Last Gasp Packets to send. Since
Time there are 3 bits controlling the amount of packet sent, thus the maximum
number of packets is 8 frames.
7 Last-Gasp OP Code Decision of the Last Gasp OP Code. This bit determines the OP Code
within the Last Gasp frames.
At 0: Last-Gasp packet send OP Code is 0001
At 1: Last-Gasp packet send OP Code is 0100
15..8 DSP Settings Setting to PHY DSP

11.7.4 StationAddress
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x10, 0x11, 0x12
Access Mode ................ Read Only
Width ............................ 48 bits

BIT BIT NAME BIT DESCRIPTION

15..0 StationAddress0 Station Address 0. StationAddress0 (offset 0x10) corresponds to the
StationAddressWord0 field of the StationAddress register.
31..16 StationAddress1 Station Address 1. StationAddress1 (offset 0x11) corresponds to the
StationAddressWord1 field of the StationAddress register.
47..32 StationAddress2 Station Address 2. StationAddress2 (offset 0x12) corresponds to the
StationAddressWord2 field of the StationAddress register.

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 IP100A LF
Preliminary Data Sheet
11.7.5 SubsystemId
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x03
Access Mode ................ Read Only
Width ............................ 16 bits

BIT BIT NAME BIT DESCRIPTION

15..0 SubsystemId Subsystem ID. SubsystemId corresponds to the SubsystemId register.

11.7.6 SubsystemVendorId
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x02
Access Mode ................ Read Only
Width ............................ 16 bits

BIT BIT NAME BIT DESCRIPTION

15..0 SubsystemVendorId Subsystem Vendor ID. SubsystemVendorId corresponds to the
SubsystemVendorId register.

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 IP100A LF
Preliminary Data Sheet
12 Signal Requirements
Note, all signal requirements are guaranteed by design only.

12.1 Absolute Maximum Ratings

Storage Temperature...................-65ºC to +150ºC
Ambient Temperature ....................-65ºC to +70ºC
Supply Voltage................................-0.3V to +3.6V
Environmental stresses above those listed in Absolute Maximum Ratings may cause permanent damage
resulting in device failure. Functionality at or above the limits listed below is not guaranteed. Exposure to
the environmental stress at the levels listed below for extended periods may adversely affect device
reliability.

12.2 Operating Ranges

Commercial Devices
Temperature (TA ) .............................. 0ºC to +70ºC
Supply Voltages (VCC 3.3V) ................ +3.3V ±5%
Supply Voltages (VCC 2.5V) ................ +2.5V ±5%
Input voltages .......................... +3.3V or +5V ±5%
Operating ranges define the limits of guaranteed device functionality.

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Preliminary Data Sheet
DC Characteristics
DC characteristics are defined over commercial operating ranges unless specified otherwise.

PARAMETER PARAMETER TEST

MIN TYP MAX UNIT
SYMBOL DESCRIPTION CONDITIONS
Vcc 3.3V 3.3V power voltage 3.13 3.47 V
Icc 3.3V 3.3V power current 10.6 mA
Vcc 2.5V 2.5V power voltage 2.37 2.63 V
Icc 2.5V 2.5V power current 159.5 mA
TTL I/O
VIH Input high voltage 2 V
VIL Input low voltage 0.8 V
IIN Input leakage current VIN = VCC /GND -10 10 µA
VOH Output high voltage 2.4 V
VOL Output low voltage 0.4 V
IOTS Output tri-state leakage 10 µA
100BASE-TX RECEIVE
VB RXP/RXN Input Bias Voltage Iol = 4 mA 2.7 V
RIN RXP/RXN Differential Input 6 kΩ
Resistance
SON Signal Detect Turn-On Threshold 5 MHz square 300 365 430 mV
wave input
100BASE-TX TRANSMIT (MEASURED DIFFERENTIALLY AFTER 1:1 TRANSFORMER)
VPDO Peak Differential Output 50Ωfrom each 0.95 1.05 V
output to VCC
VOI Output Voltage Imbalance 50Ωfrom each 0.4 V
output to VCC
Overshoot 5 %
VREF Reference Voltage of ISET 1.25 V
10BASE-T RECEIVE
VB10 RXP/RXM Input Bias Voltage 1.4 V
RIN10 RXP/RXN Differential Input 10 kΩ
Resistance
VSQ Squelch Threshold 5 MHz square 250 mV
wave
10BASE-T TRANSMIT (MEASURED DIFFERENTIALLY AFTER THE 1:1 TRANSFORMER)
VP Peak Differential Output 50Ωfrom each 2.2 2.8 V
output to VCC
TABLE 3 : DC Characteristics

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 IP100A LF
Preliminary Data Sheet
12.3 AC Characteristics

PARAMETER PARAMETER TEST

MIN TYP MAX UNIT
SYMBOL DESCRIPTION CONDITIONS
PCI INTERFACE
Trc RSTN cycle 300 ns
Trr Rising edge or RSTN to chip recovery 1 µs
Tcc PCICLK cycle 30 ns
Tch PCICLK high 11 ns
Tcl PCICLK low 11 ns
Trv PCICLK rise to bused signal valid 2 11 ns
Trvp PCICLK rise to REQN, GNTN valid 2 12 ns
Trzo PCICLK rise to signal on 2 ns
Troz PCICLK rise to signal off 28 ns
Tsu bused signal setup wrt PCICLK rise 7 ns
Tsup1 GNTN setup wrt PCICLK rise 10 ns
Tsup2 REQN setup wrt PCICLK rise 12 ns
Thd signal hold wrt PCICLK rise 0 ns
Trstoff RSTN low to output signal float 40 ns
EEPROM INTERFACE
Tskc EESK cycle 1us - ns
Tskh EESK high 250 - ns
Tskl EESK low 250 - ns
Tcs EECS low 250 - ns
Tpd EEDI valid wrt EESK rise 100 - ns
Tcsk EECS setup wrt EESK rise 50 - ns
Tcsh EECS hold wrt EESK fall 0 - ns
Tdos EEDO setup wrt EESK rise 70 500 ns
Tdoh EEDO hold wrt EESK rise - 500 ns
100BASE-TX MDI
TR /TF Rise/Fall Time 3 5 ns
TIMB Rise/Fall Time Imbalance 0 500 ps
TDCD Duty Cycle Distortion 0.5 ns
TJ Maximum output jitter (peak to peak) 0.7 1.4 ns
10BASE-T MDI
TR10 /TF10 Rise/Fall Time 25 ns
TJ10 Transmit Jitter 3.5 ns

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 IP100A LF
Preliminary Data Sheet
PARAMETER PARAMETER TEST
MIN TYP MAX UNIT
SYMBOL DESCRIPTION CONDITIONS
MISC INTERFACE
Tcc CLK25 cycle 40 40 ns
Tch CLK25 high 16 24 ns
Tcl CLK25 low 16 24 ns
TABLE 4 : Switching Characteristics

trc

RSTN

tcl tcc tch

PCICLK
trv tsu

BUSSED
SIGNALS

trvp tsup2
IP100A LF

REQN
trvp tsup1

GNTN

trzo thd

ANY
SIGNAL
troz trstoff

ANY
SIGNAL

FIGURE 16 : PCI Switching Characteristics

tcs tcsh
EECS

tskl tskc tskh

tcskv
EESK
IP100A LF

tpd

EEDI
A7 A0

tdoh
tdos
EEDO
D15 D0

FIGURE 17 : EEPROM Switching Characteristics

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 IP100A LF
Preliminary Data Sheet
12.4 Thermal Data

Theta Ja Theta Jc Conditions Units

o
38.2 16 2 Layer PCB C/W

13 Order Information
Part No. Package Notice
IP100A 128-PIN QFP -
IP100A LF 128-PIN QFP Lead free

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 IP100A LF
Preliminary Data Sheet
14 Physical Dimensions
128 PQFP Outline Dimensions
HD
D Unit: Inches/mm
128 103

1 102

HE
E

38 65

39 64

e b

GAGE
PLANE
A2
c

L
A1

L1 y
D

Dimensions In Inches Dimensions In mm

Symbol Note:
Min. Nom. Max. Min. Nom. Max.
1. Dimension D & E do not include mold protrusion.
A1 0.010 0.014 0.018 0.25 0.35 0.45 2. Dimension B does not include dambar protrusion.
A2 0.107 0.112 0.117 2.73 2.85 2.97 Total in excess of the B dimension at maximum
b 0.007 0.009 0.011 0.17 0.22 0.27 material condition.
c 0.004 0.006 0.008 0.09 0.15 0.20 Dambar cannot be located on the lower radius of
HD 0.669 0.677 0.685 17.00 17.20 17.40 the foot.
D 0.547 0.551 0.555 13.90 14.00 14.10
HE 0.906 0.913 0.921 23.00 23.20 23.40
E 0.783 0.787 0.791 19.90 20.00 20.10
e - 0.020 - - 0.50 -
L 0.025 0.035 0.041 0.65 0.88 1.03
L1 - 0.063 - - 1.60 -
y - - 0.004 - - 0.10
θ 0° - 12° 0° - 12°

IC Plus Corp.
Headquarters Sales Office
10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, 4F, No. 106, Hsin-Tai-Wu Road, Sec.1,
Hsin-Chu City, Taiwan 300, R.O.C. Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.
TEL: 886-3-575-0275 FAX: 886-3-575-0475 TEL: 886-2-2696-1669 FAX: 886-2-2696-2220
Website: www.icplus.com.tw

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