Interrupts

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Basics

Single Microcontroller can serve many devices

There are 2 ways of doing it

1. Polling
2. Interrupt

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Polling

 Microcontroller continuously monitors the status of a

given device

 When condition is met, it performs service and then

moves on to monitor the next device

 JNB TF0,$

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Interrupt

 An event that informs microcontroller that a device needs

service / attention

 Whenever a device needs attention, it sends an interrupt

to microcontroller

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Polling Vs Interrupt
 A phone with a ringer and a phone without a ringer

 Polling (Phone without a ringer): means that you pick up

the phone regularly to see if someone is on the other end

 Interrupt (Phone with a ringer): means you can do what

you want, and the phone will ring to interrupt you when
someone is on the other end

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Polling Vs Interrupt

 Polling
 Microcontroller can serve many devices
 Time wasted in waiting for certain conditions
 While waiting, no other task can be performed

 Interrupt
 Microcontroller can serve many devices
 Time not wasted in waiting for certain conditions
 Microcontroller can perform other tasks and anytime a device
can interrupt it.

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Interrupts in 8051
6 Interrupts

1. Reset
2. Timer 0 overflow
3. Timer 1 overflow
4. Reception / Transmission of serial character
5. External Event 0
6. External Event 1

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Interrupt SFRs

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Interrupt SFRs
 IE
 Interrupt Enable
 Bit Addressable

 IP
 Interrupt Priority
 Bit addressable

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Interrupt SFRs
 Interrupt Enable – IE

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Interrupt SFRs
Interrupt Enable – IE

 Set EA (Global Interrupt Enable - Bit 7) high to enable any

interrupt

 Set the bit of required interrupt in IE to enable it

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Interrupt SFRs
Interrupt Priority – IP
 2 Levels of interrupt in 8051
 0 (Low priority)
 1 (High priority)

 Priorities of 5 interrupts can be set

 All interrupts except Reset

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Interrupt SFRs
 Interrupt Priority – IP

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Interrupt SFRs
Interrupt Priority – IP
 Nothing can interrupt a high priority interrupt – not even
another high priority interrupt
 A high priority interrupt may interrupt low priority
interrupt
 A low priority interrupt may only occur if no other
interrupt is already being executed
 If 2 interrupts occur at same time, interrupt of higher
priority will execute first
 If both interrupts have same priority, Polling Sequence
(Next Slide) will determine which interrupt will be
executed first

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Polling Sequence
Priority
 External 0 interrupt
Highest

 Timer 0 Interrupt

 External 1 Interrupt

 Timer 1 Interrupt
Lowest

 Serial Interrupt

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How to Set Interrupt Priority

Interrupt Polling Sequence

1. External 0 interrupt (INT0)
2. Timer 0 Interrupt (TF0)
1. MOV IP, # 0000 0100B 3. External 1 Interrupt (INT1)
4. Timer 1 Interrupt (TF1)
5. Serial Interrupt (RI/TI)
2. MOV IP, # 0000 1100B

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IVT
Interrupt Vector Table
 For every interrupt, there is a fixed location in memory
that holds address of its ISR
 ISR is Interrupt Service Routine
 When an interrupt is generated, its ISR is automatically
executed.

 The group of memory locations that hold the addresses

of ISRs is called Interrupt Vector Table (IVT)

 IVT is located in ROM

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Interrupt Vector Table (IVT) of 8051

21 M. Usman Rafique Air University, Spring 2015

Interrupt Flags
 Timer Control – TCON SFR

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Interrupt Flags
 Timer Control – TCON SFR

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Interrupt Flags
 Serial Control – SCON SFR

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Interrupt Flags - Summary

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Clearing Interrupt Flags

 Interrupt flags cleared automatically, except

 Serial Interrupt.
 Serial Interrupt flags are to be manually reset

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What Happens when an Interrupt Occurs?
When interrupt is generated, a microcontroller will take the
following sequence of steps:
 It completes execution of current instruction.
 Saves (pushes) the return address (PC) on to the stack; low byte first.
 The current status of all the Interrupt Enable bits (in IE register) are
stored internally, and interrupts of the same or lower priority are
disabled (blocked).
 It jumps to memory location called IVT that keeps addresses of ISRs
 PC is loaded with address of ISR
 ISR is executed until “RETI= Return from Interrupt” is reached
 At the end of the ISR, the RETI instruction will retrieve the saved status of
interrupt enable bits, thus, enabling the same and lower priority
interrupts again, and retrieves the return address from the stack into PC
and continue to execute from the place it was interrupted.

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What happens when an interrupt ends?
 RETI ends the execution of ISR

 RETI clears the interrupt flags

 Except Serial
 Serial Flags are to be manually reset

 Program resumes from where it left before interrupt

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What Happens when an Interrupt Occurs?

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Important Consideration
Take care of registers
 ISR may change value of useful registers and flags
 A
 B
 PSW
 Carry
 Auxiliary Carry

 May be saved using STACK

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Short Interrupt Routine

ORG 00h
JMP MAIN

ORG 00Bh ; Timer 0 ISR

CPL P1.0
RETI

ORG 30h
MAIN:
.
.
END

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Long Interrupt Routine
ORG 00h
JMP MAIN

ORG 00Bh ; Timer 0 ISR

JMP TOISR

ORG 30h
MAIN:
.
.
JMP MAIN

TOISR: .
.
RETI
END
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Timer Interrupt
Generate 10 Khz Square Wave using Timer 0 Interrupt
Using
 Polling
 Interrupt

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Timer – Polling
Generate 10 Khz Square Wave using Timer 0 Without Interrupt
ORG 00h

MOV TMOD, #02h ; Set Timer 0 to operate in 8-bit auto-reload mode

MOV TH0, #-50 ; Load the high byte of the initial value for Timer 0
MOV TL0, #-50 ; Load the low byte of the initial value for Timer 0

SETB TR0 ; Set Timer 0 run bit, starts the timer

AGAIN:
JNB TF0, $ ; Jump if Timer 0 overflow flag (TF0) is not set
CLR TF0 ; Clear Timer 0 overflow flag
CPL P1^0 ; Complement (toggle) the value of Port 1, bit 0
JMP AGAIN ; Jump back to the label AGAIN

END

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Timer – Interrupt
Generate 10 Khz Square Wave using Timer 0 Interrupt
ORG 00h
JMP MAIN ; Jump to the MAIN label

ORG 0Bh ; Timer 0 ISR (Interrupt Service Routine)

CPL P1^0 ; Complement (toggle) the value of Port 1, bit 0
RETI ; Return from Interrupt

ORG 30h
MAIN:
MOV TMOD, #02h ; Set Timer 0 to operate in 8-bit auto-reload mode
MOV TH0, #-50 ; Load the high byte of the initial value for Timer 0
MOV TL0, #-50 ; Load the low byte of the initial value for Timer 0
SETB TR0 ; Set Timer 0 run bit, starts the timer
MOV IE, #82h ; Enable Timer 0 interrupt (ET0) and global interrupts (EA)
SJMP $ ; Infinite loop
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External Interrupts
 Two External Interrupts
 INT0
 INT1
 Pins
 P3.2
 P3.3
 Two activation levels
 Level Triggered
 Edge Triggered
 If IT0 or IT1 (in TCON) is set, it will make INT0 or INT1
Edge Triggered. Else they will be level triggered
 Default mode is level trigger

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External Interrupts
 TCON SFR

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External Interrupts
Level Triggered
 Default mode

 Interrupt Pins (P3.2 and P3.3) are normally High

 LOW level signal triggers the interrupt

 LOW level input must be removed before end of ISR,

otherwise interrupt will be generated again

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External Interrupts
Edge Triggered
 By making IT0 and IT1, external interrupts will be edge
triggered

 External source must be high for at least 1 machine cycle, and

then Low for at least 1 machine cycle

 For another interrupt to be recognized, pin must go back to a

logic high state and then brought back

 During execution of ISR, external interrupt pin is ignored, no

matter how many times it makes High-to-Low transitions
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Nested and Multiple Interrupts

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Nested and Multiple Interrupts
 What will be the response of the 8051 when the ISR of
one interrupt is in progress and another interrupt is
generated?
 A low-priority interrupt can be interrupted by high-
priority interrupt but not by another low or same-priority
interrupt.
 They will be serviced only after completion of high-
priority interrupts.
 Assume that Timer 0 (TF0) ISR is being executed and external
interrupt 0 (INT0) is asserted. Consider IP = 0000 0001.

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Nested and Multiple Interrupts
 What will be the response of the 8051 when the ISR of one
interrupt is in progress and another interrupt is generated?
 A low-priority interrupt can be interrupted by high-priority
interrupt but not by another low or same-priority interrupt.
 They will be serviced only after completion of high-priority
interrupts.
 Assume that Timer 0 (TF0) ISR is being executed and external
interrupt 0 (INT0) is asserted. Consider IP = 0000 0001.
 ISR of Timer 0 is interrupted and the controller will service the ISR of
external interrupt 0 because it is assigned higher priority (1) using IP
register. Upon completion of ISR of external interrupt 0, the
execution of ISR of Timer 0 is resumed.

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