EFR32BG22C112 Wireless Gecko SoC

Data Sheet

The EFR32BG22C112 Wireless Gecko family of SoCs is part of

KEY FEATURES
the Wireless Gecko portfolio. EFR32BG22C112 Wireless Gecko
SoCs are ideal for enabling energy-friendly Bluetooth 5.2 network- • 32-bit ARM® Cortex®-M33 core with 38.4
ing for IoT devices. MHz maximum operating frequency
• Up to 352 kB of flash and 32 kB of RAM
The single-die solution combines a 38.4 MHz Cortex-M33 with a high performance 2.4 • Energy-efficient radio core with low active
GHz radio to provide an industry-leading, energy efficient, wireless SoC for IoT connec- and sleep currents
ted applications. • Integrated PA with up to 0 dBm (2.4 GHz)
TX power
Wireless Gecko applications include:
• Secure Boot with Root of Trust and
• Asset Tags and Beacons Secure Loader (RTSL)
• Consumer Electronics Remote Controls
• Portable Medical
• Sports, Fitness, and Wellness devices
• Connected Home
• Building Automation and Security

Core / Memory Clock Management Energy Management Security

HF Crystal HF
ARM CortexTM M33 processor Oscillator RC Oscillator
Flash Program Voltage DC-DC
with DSP extensions, Regulator Converter Crypto Acceleration
Memory
FPU and TrustZone Fast Startup Precision LF
RC Oscillator RC Oscillator

Power-On Brown-Out True Random

LDMA LF Crystal Ultra LF RC
ETM Debug Interface RAM Memory Reset Detector Number Generator
Controller Oscillator Oscillator

32-bit bus

Peripheral Reflex System

Radio Subsystem Serial I/O Ports Timers and Triggers Analog I/F
Interfaces
RFSENSE ARM CortexTM
DEMOD External
w/ OOK Detect M0+ Radio USART
Interrupts
Timer/Counter Protocol Timer ADC
Controller
IFADC General Temperature
RX/TX Frontend BUFC RAM PDM
Purpose I/O
Low Energy Timer Watchdog Timer
Sensor
with Integrated PA
AGC Real Time Back-Up Real
FRC EUART Pin Reset
Capture Counter Time Counter
Frequency
Synthesizer MOD CRC I2C Pin Wakeup

Lowest power mode with peripheral operational:

EM0—Active EM1—Sleep EM2—Deep Sleep EM3—Stop EM4—Shutoff

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Feature List

1. Feature List

The EFR32BG22C112 highlighted features are listed below.

• Low Power Wireless System-on-Chip • Wide selection of MCU peripherals
• High Performance 32-bit 38.4 MHz MHz ARM Cortex®-M33 • Analog to Digital Converter (ADC)
with DSP instruction and floating-point unit for efficient sig- • 12-bit @ 1 Msps
nal processing • 16-bit @ 76.9 ksps
• Up to 352 kB flash program memory • Up to 18 General Purpose I/O pins with output state reten-
• Up to 32 kB RAM data memory tion and asynchronous interrupts
• 2.4 GHz radio operation • 8 Channel DMA Controller
• Radio Performance • 12 Channel Peripheral Reflex System (PRS)
• -98.9 dBm sensitivity @ 1 Mbit/s GFSK • 4 × 16-bit Timer/Counter with 3 Compare/Capture/PWM
• -96.2 dBm sensitivity @ 2 Mbit/s GFSK channels
• TX power up to 0 dBm • 1 × 32-bit Timer/Counter with 3 Compare/Capture/PWM
• 2.5 mA radio receive current channels
• 3.4 mA radio transmit current @ 0 dBm output power • 32-bit Real Time Counter
• Low System Energy Consumption • 24-bit Low Energy Timer for waveform generation
• 3.6 mA RX current (1 Mbps GFSK) • 1 × Watchdog Timer
• 4.1 mA TX current @ 0 dBm output power • 2 × Universal Synchronous/Asynchronous Receiver/Trans-
mitter (UART/SPI/SmartCard (ISO 7816)/IrDA/I2S)
• 26 μA/MHz in Active Mode (EM0) at 38.4 MHz
• 1 × Enhanced Universal Asynchronous Receiver/Transmit-
• 1.40 μA EM2 DeepSleep current (32 kB RAM retention and
ter (EUART)
RTC running from LFXO)
• 2 × I2C interface with SMBus support
• 1.75 μA EM2 DeepSleep current (32 kB RAM retention and
RTC running from Precision LFRCO) • Digital microphone interface (PDM)
• 0.17 μA EM4 current • Precision Low-Frequency RC Oscillator to replace 32 kHz
• Supported Modulation Format sleep crystal
• 2 (G)FSK with fully configurable shaping • RFSENSE with selective OOK mode
• Protocol Support • Die temperature sensor with +/-1.5 degree C accuracy after
single-point calibration
• Bluetooth Low Energy (Bluetooth 5.2)
• Wide Operating Range
• 1.71 V to 3.8 V single power supply
• -40 °C to 85 °C
• Security Features
• Secure Boot with Root of Trust and Secure Loader (RTSL)
• Hardware Cryptographic Acceleration for AES128/256,
SHA-1, SHA-2 (up to 256-bit), ECC (up to 256-bit), ECDSA,
and ECDH
• True Random Number Generator (TRNG) compliant with
NIST SP800-90 and AIS-31
• ARM® TrustZone®
• Secure Debug with lock/unlock
• Packages
• QFN32 4 mm × 4 mm × 0.85 mm

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Ordering Information

2. Ordering Information

Table 2.1. Ordering Information

Protocol Max TX Max CPU Flash RAM

Ordering Code Stack Power Speed LFRCO (kB) (kB) GPIO Package Temp Range

EFR32BG22C112F352GM32-C • Bluetooth 0 dBm 38.4 MHz Precision 352 32 18 QFN32 -40 to 85 °C

5.2

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Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Radio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Antenna Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Fractional-N Frequency Synthesizer . . . . . . . . . . . . . . . . . . . . . 8
3.2.3 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.4 Transmitter Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.5 Packet and State Trace . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.6 Data Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.7 Radio Controller (RAC). . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.8 RFSENSE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.1 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.2 Internal and External Oscillators. . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Counters/Timers and PWM . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.1 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.2 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . . . 9
3.5.3 Real Time Clock with Capture (RTCC) . . . . . . . . . . . . . . . . . . . .10
3.5.4 Back-Up Real Time Counter (BURTC) . . . . . . . . . . . . . . . . . . . .10
3.5.5 Watchdog Timer (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . .10
3.6 Communications and Other Digital Peripherals . . . . . . . . . . . . . . . . . . .10
3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . . . .10
3.6.2 Enhanced Universal Asynchronous Receiver/Transmitter (EUART) . . . . . . . . . . .10
3.6.3 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . . . .10
3.6.4 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . . .10
3.6.5 Pulse Density Modulation (PDM) Interface . . . . . . . . . . . . . . . . . . .10
3.7 Security Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL) . . . . . . . . . . . . .11
3.7.2 Cryptographic Accelerator. . . . . . . . . . . . . . . . . . . . . . . . .11
3.7.3 True Random Number Generator . . . . . . . . . . . . . . . . . . . . . .11
3.7.4 Secure Debug with Lock/Unlock. . . . . . . . . . . . . . . . . . . . . . .11
3.8 Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.8.1 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . .12
3.9 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.9.1 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . . .13
3.9.2 Voltage Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.9.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.9.4 Power Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.10 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . . . .14

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 3.11 Core and Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.11.1 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.11.2 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .14
3.11.3 Linked Direct Memory Access Controller (LDMA) . . . . . . . . . . . . . . . .14
3.12 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.13 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .16

4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .19
4.4 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.4.1 DC-DC Operating Limits . . . . . . . . . . . . . . . . . . . . . . . . .22
4.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.6 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.6.1 MCU current consumption using DC-DC at 3.0 V input . . . . . . . . . . . . . . .24
4.6.2 MCU current consumption at 3.0 V . . . . . . . . . . . . . . . . . . . . . .26
4.6.3 MCU current consumption at 1.8 V . . . . . . . . . . . . . . . . . . . . . .28
4.6.4 Radio current consumption at 3.0V using DCDC . . . . . . . . . . . . . . . . .30
4.7 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.8 Wake Up, Entry, and Exit times . . . . . . . . . . . . . . . . . . . . . . . .32
4.9 RFSENSE Low-energy Wake-on-RF . . . . . . . . . . . . . . . . . . . . . .33
4.10 2.4 GHz RF Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . .34
4.10.1 RF Transmitter Characteristics . . . . . . . . . . . . . . . . . . . . . . .34
4.10.2 RF Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . .37
4.11 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4.11.1 High Frequency Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . .40
4.11.2 Low Frequency Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . .41
4.11.3 High Frequency RC Oscillator (HFRCO) . . . . . . . . . . . . . . . . . . .42
4.11.4 Fast Start_Up RC Oscillator (FSRCO) . . . . . . . . . . . . . . . . . . . .43
4.11.5 Precision Low Frequency RC Oscillator (LFRCO) . . . . . . . . . . . . . . . .44
4.11.6 Ultra Low Frequency RC Oscillator . . . . . . . . . . . . . . . . . . . . .44
4.12 GPIO Pins (3V GPIO pins) . . . . . . . . . . . . . . . . . . . . . . . . .45
4.13 Analog to Digital Converter (IADC) . . . . . . . . . . . . . . . . . . . . . . .47
4.14 Temperature Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.15 Brown Out Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.15.1 DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.15.2 LE DVDD BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.15.3 AVDD and IOVDD BODs . . . . . . . . . . . . . . . . . . . . . . . .51
4.16 PDM Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . .52
4.16.1 Pulse Density Modulator (PDM), Common DBUS . . . . . . . . . . . . . . . .52
4.17 USART SPI Main Timing . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.17.1 SPI Main Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . . . . . . .54

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 4.17.2 SPI Main Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . . . . . . .54
4.18 USART SPI Secondary Timing . . . . . . . . . . . . . . . . . . . . . . . .55
4.18.1 SPI Secondary Timing, Voltage Scaling = VSCALE2 . . . . . . . . . . . . . . .55
4.18.2 SPI Secondary Timing, Voltage Scaling = VSCALE1 . . . . . . . . . . . . . . .56
4.19 I2C Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . .57
4.19.1 I2C Standard-mode (Sm) . . . . . . . . . . . . . . . . . . . . . . . .57
4.19.2 I2C Fast-mode (Fm) . . . . . . . . . . . . . . . . . . . . . . . . . .58
4.19.3 I2C Fast-mode Plus (Fm+) . . . . . . . . . . . . . . . . . . . . . . . .59
4.20 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . .59
4.20.1 Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
4.20.2 RF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .61
4.20.3 DC-DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . .62
4.20.4 IADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

5. Typical Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .63

5.1 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.2 RF Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.2.1 2.4 GHz Matching Network . . . . . . . . . . . . . . . . . . . . . . . .64
5.3 Other Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.1 QFN32 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .66
6.2 Alternate Function Table. . . . . . . . . . . . . . . . . . . . . . . . . . .67
6.3 Analog Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . .68
6.4 Digital Peripheral Connectivity . . . . . . . . . . . . . . . . . . . . . . . . .69

7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . . 72

7.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . .72
7.2 QFN32 PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.3 QFN32 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . .76

8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
System Overview

3. System Overview

3.1 Introduction

The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for
secure connected IoT multi-protocol devices requiring high performance and low energy consumption. This section gives a short intro-
duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG22 Reference Manual.

A block diagram of the EFR32BG22C112 family is shown in Figure 3.1 Detailed EFR32BG22C112 Block Diagram on page 7. The
diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features,
consult Ordering Information.

Radio Subsystem Port I/O Configuration IOVDD

RFSENSE DEMOD ARM Cortex M0+TM
w/ OOK Detect Radio Controller Digital Peripherals

RX/TX Frontend IFADC USART

RF2G4_IO BUFC RAM Port A
with Integrated PA PAn
EUART Drivers
AGC
FRC
Frequency I2C
Synthesizer MOD CRC Port B
PBn
LETIMER Drivers

TIMER DBUS
Reset Management Unit, Core and Memory Port Port C
RESETn RTCC Mappers PCn
Brown Out and POR Drivers
ARM Cortex-M33 Core
with Floating Point Unit PDM
Debug Signals Serial Wire and ETM Port D
Debug / Programming Up to 512 KB ISP Flash TRNG PDn
(shared w/GPIO) Drivers
with Debug Challenge I/F Program Memory A A
H P CRYPTOACC
32 KB RAM
B B
Energy Management CRC
PAVDD Trust Zone
RFVDD LDMA Controller
IOVDD Analog Peripherals
Voltage
AVDD
Monitor
Watchdog Internal Temperature
DVDD

ABUS Multiplexers
Timer Reference Sensor
bypass

VREGVDD
Input Mux

DC-DC Voltage Clock Management VDD

VREGSW Converter Regulator 12-16-bit
ULFRCO ADC
DECOUPLE FSRCO
LFRCO
LFXTAL_I
LFXO
LFXTAL_O
HFRCO
HFXTAL_I
HFXO
HFXTAL_O

Figure 3.1. Detailed EFR32BG22C112 Block Diagram

3.2 Radio

The EFR32BG22C112 Wireless Gecko features a highly configurable radio transceiver supporting the Bluetooth Low Energy wireless
protocol.

3.2.1 Antenna Interface

The 2.4 GHz antenna interface consists of a single-ended pin (RF2G4_IO). The external components for the antenna interface in typi-
cal applications are shown in the RF Matching Networks section.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
System Overview

3.2.2 Fractional-N Frequency Synthesizer

The EFR32BG22C112 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthe-
sizer is used in receive mode to generate the LO frequency for the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.

The fractional-N architecture provides excellent phase noise performance, frequency resolution better than 100 Hz, and low energy
consumption. The synthesizer’s fast frequency settling allows for very short receiver and transmitter wake up times to reduce system
energy consumption.

3.2.3 Receiver Architecture

The EFR32BG22C112 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conver-
sion mixer. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital converter (IFADC).

The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.

The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. The 2.4 GHz radio is calibrated at production to improve image rejection performance.

Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation.

3.2.4 Transmitter Architecture

The EFR32BG22C112 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator con-
trols phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shap-
ing filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine
shaping.

3.2.5 Packet and State Trace

The EFR32BG22C112 Frame Controller has a packet and state trace unit that provides valuable information during the development
phase. It features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream

3.2.6 Data Buffering

The EFR32BG22C112 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from
64 bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.

3.2.7 Radio Controller (RAC)

The Radio Controller controls the top level state of the radio subsystem in the EFR32BG22C112. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer

3.2.8 RFSENSE Interface

The RFSENSE block allows the device to remain in EM2, EM3 or EM4 and wake when RF energy above a specified threshold is detec-
ted. When operated in selective mode, the RFSENSE block performs OOK preamble and sync word detection, preventing false wake-
up events.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
System Overview

3.3 General Purpose Input/Output (GPIO)

EFR32BG22C112 has up to 18 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or
input. More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO
pin. The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to
several GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripher-
als. The GPIO subsystem supports asynchronous external pin interrupts.

All of the pins on ports A and port B are EM2 capable. These pins may be used by Low-Energy peripherals in EM2/3 and may also be
used as EM2/3 pin wake-ups. Pins on ports C and D are latched/retained in their current state when entering EM2 until EM2 exit upon
which internal peripherals could once again drive those pads.

A few GPIOs also have EM4 wake functionality. These pins are listed in the Alternate Function Table.

3.4 Clocking

3.4.1 Clock Management Unit (CMU)

The Clock Management Unit controls oscillators and clocks in the EFR32BG22C112. Individual enabling and disabling of clocks to all
peripheral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of
flexibility allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused periph-
erals and oscillators.

3.4.2 Internal and External Oscillators

The EFR32BG22C112 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. The HFXO provides excellent RF clocking performance using a 38.4 MHz crystal. The HFXO can also support an
external clock source such as a TCXO for applications that require an extremely accurate clock frequency over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast start-up at minimal energy consumption combined with a wide frequency range, from 1 MHz to 38.4 MHz.
• An integrated fast start-up RC oscillator (FSRCO) that runs at a fixed 20 MHz
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) for low power operation without an external crystal. Precision mode
enables periodic recalibration against the 38.4 MHz HFXO crystal to improve accuracy to +/- 500 ppm, suitable for BLE sleep inter-
val timing.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.

3.5 Counters/Timers and PWM

3.5.1 Timer/Counter (TIMER)

TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
Peripheral Reflex System (PRS). The core of each TIMER is a 16-bit or 32-bit counter with up to 3 compare/capture channels. Each
channel is configurable in one of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In
compare mode, the channel output reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER
supports generation of pulse-width modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the
compare registers. In addition some timers offer dead-time insertion.

See 3.13 Configuration Summary for information on the feature set of each timer.

3.5.2 Low Energy Timer (LETIMER)

The unique LETIMER is a 24-bit timer that is available in energy mode EM0 Active, EM1 Sleep, EM2 Deep Sleep, and EM3 Stop. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Peripheral Reflex System (PRS), and can be configured to
start counting on compare matches from other peripherals such as the Real Time Clock.

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System Overview

3.5.3 Real Time Clock with Capture (RTCC)

The Real Time Clock with Capture (RTCC) is a 32-bit counter providing timekeeping down to EM3. The RTCC can be clocked by any of
the on-board low-frequency oscillators, and it is capable of providing system wake-up at user defined intervals.

A secondary RTC is used by the RF protocol stack for event scheduling, leaving the primary RTCC block available exclusively for appli-
cation software.

3.5.4 Back-Up Real Time Counter (BURTC)

The Back-Up Real Time Counter (BURTC) is a 32-bit counter providing timekeeping in all energy modes, including EM4. The BURTC
can be clocked by any of the on-board low-frequency oscillators, and it is capable of providing system wake-up at user-defined inter-
vals.

3.5.5 Watchdog Timer (WDOG)

The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by the Peripheral Reflex System (PRS).

3.6 Communications and Other Digital Peripherals

3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
• I2S

3.6.2 Enhanced Universal Asynchronous Receiver/Transmitter (EUART)

The Enhanced Universal Asynchronous Receiver/Transmitter supports full duplex asynchronous UART communication with hardware
flow control, RS-485 and IrDA support. In EM0 and EM1 the EUART provides a high-speed, buffered communication interface.

When routed to GPIO ports A or B, the EUART may also be used in a low-energy mode and operate in EM2. A 32.768 kHz clock
source allows full duplex UART communication up to 9600 baud.

3.6.3 Inter-Integrated Circuit Interface (I2C)

The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as a main or secondary interface
and supports multi-drop buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from
10 kbit/s up to 1 Mbit/s. Bus arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of addresses is provided in active and low energy modes. Note that not all instances of I2C are available in
all energy modes.

3.6.4 Peripheral Reflex System (PRS)

The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality such as simple logic operations (AND, OR, NOT)
can be applied by the PRS to the signals. The PRS allows peripherals to act autonomously without waking the MCU core, saving pow-
er.

3.6.5 Pulse Density Modulation (PDM) Interface

The PDM module provides a serial interface and decimation filter for Pulse Density Modulation (PDM) microphones, isolated Sigma-
delta ADCs, digital sensors and other PDM or sigma delta bit stream peripherals. A programmable Cascaded Integrator Comb (CIC)
filter is used to decimate the incoming bit streams. PDM supports stereo or mono input data and DMA transfer.

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System Overview

3.7 Security Features

The following security features are available on the EFR32BG22C112:

• Secure Boot with Root of Trust and Secure Loader (RTSL)
• Cryptographic Accelerator
• True Random Number Generator (TRNG)
• Secure Debug with Lock/Unlock

3.7.1 Secure Boot with Root of Trust and Secure Loader (RTSL)

The Secure Boot with RTSL authenticates a chain of trusted firmware that begins from an immutable memory (ROM).

It prevents malware injection, prevents rollback, ensures that only authentic firmware is executed and protects Over The Air updates.

More information on this feature can be found in the Application Note AN1218: Series 2 Secure Boot with RTSL.

3.7.2 Cryptographic Accelerator

The Cryptographic Accelerator is an autonomous hardware accelerator which supports AES encryption and decryption with
128/192/256-bit keys, Elliptic Curve Cryptography (ECC) to support public key operations and hashes.

Supported block cipher modes of operation for AES include:

• ECB (Electronic Code Book)
• CTR (Counter Mode)
• CBC (Cipher Block Chaining)
• CFB (Cipher Feedback)
• GCM (Galois Counter Mode)
• CBC-MAC (Cipher Block Chaining Message Authentication Code)
• GMAC (Galois Message Authentication Code)
• CCM (Counter with CBC-MAC)

The Cryptographic Accelerator accelerates Elliptical Curve Cryptography and supports the NIST (National Institute of Standards and
Technology) recommended curves including P-192 and P-256 for ECDH(Elliptic Curve Diffie-Hellman) key derivation and ECDSA (El-
liptic Curve Digital Signature Algorithm) sign and verify operations.

Supported hashes include SHA-1, SHA2/224, and SHA-2/256.

This implementation provides a fast and energy efficient solution to state of the art cryptographic needs.

3.7.3 True Random Number Generator

The True Random Number Generator module is a non-deterministic random number generator that harvests entropy from a thermal
energy source. It includes start-up health tests for the entropy source as required by NIST SP800-90B and AIS-31 as well as online
health tests required for NIST SP800-90C.

The TRNG is suitable for periodically generating entropy to seed an approved pseudo random number generator.

3.7.4 Secure Debug with Lock/Unlock

For obvious security reasons, it is critical for a product to have its debug interface locked before being released in the field.

In addition, the EFR32BG22C112 also provides a secure debug unlock function that allows authenticated access based on public key
cryptography. This functionality is particularly useful for supporting failure analysis while maintaining confidentiality of IP and sensitive
end-user data.

More information on this feature can be found in the Application Note AN1190: EFR32xG2x Secure Debug.

3.8 Analog

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3.8.1 Analog to Digital Converter (IADC)

The IADC is a hybrid architecture combining techniques from both SAR and Delta-Sigma style converters. It has a resolution of 12 bits
at 1 Msps and 16 bits at up to 76.9 ksps. Hardware oversampling reduces system-level noise over multiple front-end samples. The
IADC includes integrated voltage reference options. Inputs are selectable from a wide range of sources, including pins configurable as
either single-ended or differential.

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3.9 Power

The EFR32BG22C112 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages.
Only a single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regu-
lator can be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external
capacitor.

The EFR32BG22C112 device family includes support for internal supply voltage scaling, as well as two different power domains groups
for peripherals. These enhancements allow for further supply current reductions and lower overall power consumption.

3.9.1 Energy Management Unit (EMU)

The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to implement system-wide voltage
scaling and turn off the power to unused RAM blocks to optimize the energy consumption in the target application. The DC-DC regula-
tor operation is tightly integrated with the EMU.

3.9.2 Voltage Scaling

The EFR32BG22C112 supports supply voltage scaling for the LDO powering DECOUPLE, with independent selections for EM0 / EM1
and EM2 / EM3. Voltage scaling helps to optimize the energy efficiency of the system by operating at lower voltages when possible.
The EM0 / EM1 voltage scaling level defaults to VSCALE2, which allows the core to operate in active mode at full speed. The inter-
mediate level, VSCALE1, allows operation in EM0 and EM1 at up to 40 MHz. The lowest level, VSCALE0, can be used to conserve
power further in EM2 and EM3. The EMU will automatically switch the target voltage scaling level when transitioning between energy
modes.

3.9.3 DC-DC Converter

The DC-DC buck converter covers a wide range of load currents, provides high efficiency in energy modes EM0, EM1, EM2 and EM3,
and can supply up to 60 mA for device and radio operation. RF noise mitigation allows operation of the DC-DC converter without signifi-
cantly degrading sensitivity of radio components. An on-chip supply-monitor signals when the supply voltage is low to allow bypass of
the regulator via programmable software interrupt. It employs soft switching at boot and DCDC regulating-to-bypass transitions to limit
the max supply slew-rate and mitigate inrush current.

3.9.4 Power Domains

The EFR32BG22C112 has three peripheral power domains for operation in EM2 and EM3, as well as the ability to selectively retain
configurations for EM0/EM1 peripherals. A small set of peripherals always remain powered on in EM2 and EM3, including all peripher-
als which are available in EM4. If all of the peripherals in PD0B or PD0C are configured as unused, that power domain will be powered
off in EM2 or EM3, reducing the overall current consumption of the device. Likewise, if the application can tolerate the setup time to re-
configure used EM0/EM1 peripherals on wake, register retention for these peripherals can be disabled to further reduce the EM2 or
EM3 current.

Table 3.1. Peripheral Power Subdomains

Always available in EM2/EM3 Power Domain PD0B Power Domain PD0C

RTCC LETIMER0 LFRCO (Precision Mode)

LFRCO (Non-precision mode)1 IADC0

LFXO1 I2C0

BURTC1 WDOG0

RFSENSE1 EUART0

ULFRCO1 PRS

FSRCO DEBUG

Note:
1. Peripheral also available in EM4.

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3.10 Reset Management Unit (RMU)

The RMU is responsible for handling reset of the EFR32BG22C112. A wide range of reset sources are available, including several pow-
er supply monitors, pin reset, software controlled reset, core lockup reset, and watchdog reset.

3.11 Core and Memory

3.11.1 Processor Core

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M33 RISC processor achieving 1.50 Dhrystone MIPS/MHz
• ARM TrustZone security technology
• Embedded Trace Macrocell (ETM) for real-time trace and debug
• Up to 352 kB flash program memory
• Up to 32 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface

3.11.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. In addition to the main flash array where Program code is normally written the MSC also provides an
Information block where additional information such as special user information or flash-lock bits are stored. There is also a read-only
page in the information block containing system and device calibration data. Read and write operations are supported in energy modes
EM0 Active and EM1 Sleep.

3.11.3 Linked Direct Memory Access Controller (LDMA)

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This
reduces both energy consumption and software workload. The LDMA allows operations to be linked together and staged, enabling so-
phisticated operations to be implemented.

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3.12 Memory Map

The EFR32BG22C112 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2. EFR32BG22C112 Memory Map — Core Peripherals and Code Space

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3.13 Configuration Summary

The features of the EFR32BG22C112 are a subset of the feature set described in the device reference manual. The table below de-
scribes device specific implementation of the features. Remaining modules support full configuration.

Table 3.2. Configuration Summary

Module Lowest Energy Mode Configuration

I2C0 EM31

I2C1 EM1

IADC0 EM3

LETIMER0 EM21

PDM EM1 2-channel

TIMER0 EM1 32-bit, 3-channels, +DTI

TIMER1 EM1 16-bit, 3-channels, +DTI

TIMER2 EM1 16-bit, 3-channels, +DTI

TIMER3 EM1 16-bit, 3-channels, +DTI

TIMER4 EM1 16-bit, 3-channels, +DTI

EUART0 EM1 - Full high-speed operation

EM31 - Low-energy operation, 9600 Baud

USART0 EM1 +IrDA, +I2S, +SmartCard

USART1 EM1 +IrDA, +I2S, +SmartCard

Note:
1. EM2 and EM3 operation is only supported for digital peripheral I/O on Port A and Port B. All GPIO ports support digital peripheral
operation in EM0 and EM1.

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Electrical Specifications

4. Electrical Specifications

4.1 Electrical Characteristics

All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TA=25 °C and all supplies at 3.0 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.

Power Supply Pin Dependencies

Due to on-chip circuitry (e.g., diodes), some EFR32 power supply pins have a dependent relationship with one or more other power
supply pins. These internal relationships between the external voltages applied to the various EFR32 supply pins are defined below.
Exceeding the below constraints can result in damage to the device and/or increased current draw.

• VREGVDD & DVDD

• In systems using the DCDC converter, DVDD (the buck converter output) should be connected to the recommended LDCDC and
CDCDC, and should not be driven by an off-chip regulator.
• In systems not using the DCDC converter, DVDD must be shorted to VREGVDD on the PCB (VREGVDD=DVDD)
• DVDD ≥ DECOUPLE
• PAVDD ≥ RFVDD
• AVDD, IOVDD: No dependency with each other or any other supply pin

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4.2 Absolute Maximum Ratings

Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions beyond those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.

Table 4.1. Absolute Maximum Ratings

Parameter Symbol Test Condition Min Typ Max Unit

Storage temperature range TSTG -50 — +150 °C

Voltage on any supply pin1 VDDMAX -0.3 — 3.8 V

Junction temperature TJMAX -G grade — — +105 °C

Voltage ramp rate on any VDDRAMPMAX — — 1.0 V / µs

supply pin

Voltage on HFXO pins VHFXOPIN -0.3 — 1.4 V

DC voltage on any GPIO pin VDIGPIN -0.3 — VIOVDD + V

0.3

DC voltage on RESETn pin2 VRESETn -0.3 — 3.8 V

Input RF level on RF pins PRFMAX2G4 — — +10 dBm

RF2G4_IO

Absolute voltage on RF pin VMAX2G4 -0.3 — VPAVDD + V

RF2G4_IO 0.3

Total current into VDD power IVDDMAX Source — — 200 mA

lines

Total current into VSS IVSSMAX Sink — — 200 mA

ground lines

Current per I/O pin IIOMAX Sink — — 50 mA

Source — — 50 mA

Current for all I/O pins IIOALLMAX Sink — — 200 mA

Source — — 200 mA

Note:
1. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-
tions for more details.
2. The RESETn pin has a pull-up device to the DVDD supply. For minimum leakage, RESETn should not exceed the voltage at
DVDD.

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4.3 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter Symbol Test Condition Min Typ Max Unit

Operating ambient tempera- TA -G temperature grade 1 -40 — +85 °C

ture range

DVDD supply voltage VDVDD EM0/1 1.71 3.0 3.8 V

EM2/3/42 1.71 3.0 3.8 V

AVDD supply voltage VAVDD 1.71 3.0 3.8 V

IOVDDx operating supply VIOVDDx 1.71 3.0 3.8 V

voltage (All IOVDD pins)

PAVDD operating supply VPAVDD 1.71 3.0 3.8 V

voltage

VREGVDD operating supply VVREGVDD DC-DC in regulation3 2.2 3.0 3.8 V

voltage
DC-DC in bypass 60 mA load 1.8 3.0 3.8 V

DC-DC not in use. DVDD exter- 1.71 3.0 3.8 V

nally shorted to VREGVDD

RFVDD operating supply VRFVDD 1.71 3.0 VPAVDD V

voltage

DECOUPLE output capaci- CDECOUPLE 1.0 µF ± 10% X8L capacitor used 1.0 — 2.75 µF
tor4 for performance characterization.

HCLK and SYSCLK frequen- fHCLK VSCALE1, MODE = WS0 — — 40 MHz

cy

PCLK frequency fPCLK VSCALE1 — — 40 MHz

EM01 Group A clock fre- fEM01GRPACLK VSCALE1 — — 40 MHz

quency

EM01 Group B clock fre- fEM01GRPBCLK VSCALE1 — — 40 MHz

quency

Radio HCLK frequency5 fRHCLK VSCALE2 or VSCALE1 — 38.4 — MHz

Note:
1. The device may operate continuously at the maximum allowable ambient TA rating as long as the absolute maximum TJMAX is not
exceeded. For an application with significant power dissipation, the allowable TA may be lower than the maximum TA rating. TA =
TJMAX - (THETAJA x PowerDissipation). Refer to the Absolute Maximum Ratings table and the Thermal Characteristics table for
TJMAX and THETAJA.
2. The DVDD supply is monitored by the DVDD BOD in EM0/1 and the LE DVDD BOD in EM2/3/4.
3. The maximum supply voltage on VREGVDD is limited under certain conditions when using the DC-DC. See the DC-DC specifica-
tions for more details.
4. Murata GCM21BL81C105KA58L used for performance characterization. Actual capacitor values can be significantly de-rated
from their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The
minimum capacitance counting all error sources should be no less than 0.6 µF.
5. The recommended radio crystal frequency is 38.4 MHz. Any crystal frequency other than 38.4 MHz is expressly not supported.
See HFXO specifications for more detail on crystal tolerance.

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4.4 DC-DC Converter

Test conditions: LDCDC = 2.2 µH (Samsung CIG22H2R2MNE), CDCDC = 4.7 µF (Samsung CL10B475KQ8NQNC), VVREGVDD = 3.0 V,
VOUT = 1.8 V, IPKVAL in EM0/1 modes is set to 150 mA, and in EM2/3 modes is set to 90 mA, unless otherwise indicated.

Table 4.3. DC-DC Converter

Parameter Symbol Test Condition Min Typ Max Unit

Input voltage range at VVREGVDD DCDC in regulation, ILOAD = 60 2.2 3.0 3.8* V
VREGVDD pin1 mA, EM0/EM1 mode

DCDC in regulation, ILOAD = 5 1.8 3.0 3.8* V

mA, EM0/EM1 or EM2/EM3 mode

Bypass mode 1.8 3.0 3.8 V

Regulated output voltage VOUT — 1.8 — V

Regulation DC accuracy ACCDC VVREGVDD ≥ 2.2 V, Steady state in -2.5 — 3.3 %

EM0/EM1 mode or EM2/EM3
mode

Regulation total accuracy ACCTOT With mode transitions between -5 — 7 %

EM0/EM1 and EM2/EM3 modes

Steady-state output ripple VR ILOAD = 20 mA in EM0/EM1 mode — 14.3 — mVpp

DC line regulation VREG ILOAD = 60 mA in EM0/EM1 — 5.5 — mV/V

mode, VVREGVDD ≥ 2.2 V

DC load regulation IREG Load current between 100 µA and — 0.27 — mV/mA
60 mA in EM0/EM1 mode

Efficiency EFF Load current between 100 µA and — 91 — %

60 mA in EM0/EM1 mode, or be-
tween 10 µA and 5 mA in
EM2/EM3 mode

Output load current ILOAD EM0/EM1 mode, DCDC in regula- — — 60 mA

tion

EM2/EM3 mode, DCDC in regula- — — 5 mA

tion

Bypass mode — — 60 mA

Nominal output capacitor CDCDC 4.7 µF ± 10% X7R capacitor used 4.7 — 10 µF
for performance characterization2

Nominal inductor LDCDC ± 20% tolerance — 2.2 — µH

Nominal input capacitor CIN CDCDC — — µF

Resistance in bypass mode RBYP Bypass switch from VREGVDD to — 1.75 3 Ω

DVDD, VVREGVDD = 1.8 V

Powertrain PFET switch from — 0.86 1.5 Ω

VREGVDD to VREGSW,
VVREGVDD = 1.8 V

Supply monitor threshold VCMP_RNG Programmable in 0.1 V steps 2.0 — 2.3 V

programming range

Supply monitor threshold ac- VCMP_ACC Supply falling edge trip point -5 — 5 %
curacy

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Parameter Symbol Test Condition Min Typ Max Unit

Supply monitor threshold VCMP_HYST Positive hysteresis on the supply — 4 — %

hysteresis rising edge referred to the falling
edge trip point

Supply monitor response tCMP_DELAY Supply falling edge at -100 mV / — 0.6 — µs

time µs

Note:
1. The supported maximum VVREGVDD in regulation mode is a function of temperature and 10-year lifetime average load current.
See more details in 4.4.1 DC-DC Operating Limits.
2. Samsung CL10B475KQ8NQNC used for performance characterization. Actual capacitor values can be significantly de-rated from
their specified nominal value by the rated tolerance, as well as the application's AC voltage, DC bias, and temperature. The mini-
mum capacitance counting all error sources should be no less than 2.4 µF.

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4.4.1 DC-DC Operating Limits

The maximum supported voltage on the VREGVDD supply pin is limited under certain conditions. Maximum input voltage is a function
of temperature and the average load current over a 10-year lifetime. Figure 4.1 Lifetime average load current limit vs. Maximum input
voltage on page 22 shows the safe operating region under specific conditions. Exceeding this safe operating range may impact the
reliability and performance of the DC-DC converter.

The average load current for an application can typically be determined by examining the current profile during the time the device is
powered. For example, an application that is continuously powered which spends 99% of the time asleep consuming 2 µA and 1% of
the time active and consuming 10 mA has an average lifetime load current of about 102 µA.

Average Lifetime ILOAD (mA)

60 Tj ≤ 125 °C

3.3 3.8
Maximum VVREGVDD (V)

Figure 4.1. Lifetime average load current limit vs. Maximum input voltage

The minimum input voltage for the DC-DC in EM0/EM1 mode is a function of the maximum load current, and the peak current setting.
Figure 4.2 Transient maximum load current vs. Minimum input voltage on page 22 shows the max load current vs. input voltage for
different DC-DC peak inductor current settings.

60
Maximum ILOAD (mA)

36

IPEAK = 150 mA
5 IPEAK = 90 mA

1.8 2.2
Minimum VVREGVDD (V)

Figure 4.2. Transient maximum load current vs. Minimum input voltage

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4.5 Thermal Characteristics

Table 4.4. Thermal Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Thermal Resistance Junction THE- 4-Layer PCB, Natural Convection1 — 35.4 — °C/W
to Ambient QFN32 (4x4mm) TAJA_QFN32_4X4
Package

Note:
1. Measured according to JEDEC standard JESD51-2A. Integrated Circuit Thermal Test Method Environmental Conditions - Natural
Convection (Still Air).

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4.6 Current Consumption

4.6.1 MCU current consumption using DC-DC at 3.0 V input

Unless otherwise indicated, typical conditions are: VREGVDD = 3.0 V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V from DC-
DC. Voltage scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across
process variation at TA = 25 °C.

Table 4.5. MCU current consumption using DC-DC at 3.0 V input

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0 IACTIVE 38.4 MHz crystal, CPU running — 28 — µA/MHz
mode with all peripherals dis- Prime from flash
abled
38.4 MHz crystal, CPU running — 26 — µA/MHz
while loop from flash

38.4 MHz crystal, CPU running — 38 — µA/MHz

CoreMark loop from flash

38 MHz HFRCO, CPU running — 22 — µA/MHz

while loop from flash

26 MHz HFRCO, CPU running — 24 — µA/MHz

while loop from flash

16 MHz HFRCO, CPU running — 27 — µA/MHz

while loop from flash

1 MHz HFRCO, CPU running — 159 — µA/MHz

while loop from flash

Current consumption in EM1 IEM1 38.4 MHz crystal — 17 — µA/MHz

mode with all peripherals dis-
abled 38 MHz HFRCO — 13 — µA/MHz

26 MHz HFRCO — 15 — µA/MHz

16 MHz HFRCO — 18 — µA/MHz

1 MHz HFRCO — 150 — µA/MHz

Current consumption in EM2 IEM2_VS Full RAM retention and RTC run- — 1.40 — µA
mode, VSCALE0 ning from LFXO

Full RAM retention and RTC run- — 1.40 — µA

ning from LFRCO

Full RAM retention and RTC run- — 1.75 — µA

ning from LFRCO in precision
mode

24 kB RAM retention and RTC — 1.32 — µA

running from LFXO

24 kB RAM retention and RTC — 1.66 — µA

running from LFRCO in precision
mode

8 kB RAM retention and RTC run- — 1.21 — µA

ning from LFXO

8 kB RAM retention and RTC run- — 1.20 — µA

ning from LFRCO

8 kB RAM retention and RTC run- — 1.03 — µA

ning from LFXO, Radio RAM and
CPU cache not retained

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Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM3 IEM3_VS 8 kB RAM retention and RTC run- — 1.05 — µA
mode, VSCALE0 ning from ULFRCO

Additional current in EM2 or IPD0B_VS — 0.37 — µA

EM3 when any peripheral in
PD0B is enabled1

Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the
peripherals in each power domain.

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Electrical Specifications

4.6.2 MCU current consumption at 3.0 V

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 3.0 V. DC-DC not used. Voltage
scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-
tion at TA = 25 °C.

Table 4.6. MCU current consumption at 3.0 V

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0 IACTIVE 38.4 MHz crystal, CPU running — 40 — µA/MHz
mode with all peripherals dis- Prime from flash
abled
38.4 MHz crystal, CPU running — 39 — µA/MHz
while loop from flash

38.4 MHz crystal, CPU running — 55 — µA/MHz

CoreMark loop from flash

38 MHz HFRCO, CPU running — 33 50 µA/MHz

while loop from flash

26 MHz HFRCO, CPU running — 35 — µA/MHz

while loop from flash

16 MHz HFRCO, CPU running — 40 — µA/MHz

while loop from flash

1 MHz HFRCO, CPU running — 228 830 µA/MHz

while loop from flash

Current consumption in EM1 IEM1 38.4 MHz crystal — 25 — µA/MHz

mode with all peripherals dis-
abled 38 MHz HFRCO — 19 35 µA/MHz

26 MHz HFRCO — 21 — µA/MHz

16 MHz HFRCO — 27 — µA/MHz

1 MHz HFRCO — 215 770 µA/MHz

Current consumption in EM2 IEM2_VS Full RAM retention and RTC run- — 1.94 — µA
mode, VSCALE0 ning from LFXO

Full RAM retention and RTC run- — 1.95 4.9 µA

ning from LFRCO

24 kB RAM retention and RTC — 1.81 — µA

running from LFXO

24 kB RAM retention and RTC — 2.34 — µA

running from LFRCO in precision
mode

8 kB RAM retention and RTC run- — 1.64 — µA

ning from LFXO

8 kB RAM retention and RTC run- — 1.65 — µA

ning from LFRCO

8 kB RAM retention and RTC run- — 1.39 — µA

ning from LFXO, Radio RAM and
CPU cache not retained

Current consumption in EM3 IEM3_VS 8 kB RAM retention and RTC run- — 1.41 3.7 µA
mode, VSCALE0 ning from ULFRCO

Current consumption in EM4 IEM4 No BURTC, no LF oscillator — 0.17 0.43 µA

mode
BURTC with LFXO — 0.50 — µA

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Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption during IRST Hard pin reset held — 234 — µA

reset

Additional current in EM2 or IPD0B_VS — 0.56 — µA

EM3 when any peripheral in
PD0B is enabled1

Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the
peripherals in each power domain.

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Electrical Specifications

4.6.3 MCU current consumption at 1.8 V

Unless otherwise indicated, typical conditions are: AVDD = DVDD = RFVDD = PAVDD = VREGVDD = 1.8 V. DC-DC not used. Voltage
scaling level = VSCALE1. TA = 25 °C. Minimum and maximum values in this table represent the worst conditions across process varia-
tion at TA = 25 °C.

Table 4.7. MCU current consumption at 1.8 V

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption in EM0 IACTIVE 38.4 MHz crystal, CPU running — 41 — µA/MHz
mode with all peripherals dis- Prime from flash
abled
38.4 MHz crystal, CPU running — 39 — µA/MHz
while loop from flash

38.4 MHz crystal, CPU running — 55 — µA/MHz

CoreMark loop from flash

38 MHz HFRCO, CPU running — 33 — µA/MHz

while loop from flash

26 MHz HFRCO, CPU running — 35 — µA/MHz

while loop from flash

16 MHz HFRCO, CPU running — 40 — µA/MHz

while loop from flash

1 MHz HFRCO, CPU running — 227 — µA/MHz

while loop from flash

Current consumption in EM1 IEM1 38.4 MHz crystal — 25 — µA/MHz

mode with all peripherals dis-
abled 38 MHz HFRCO — 19 — µA/MHz

26 MHz HFRCO — 21 — µA/MHz

16 MHz HFRCO — 27 — µA/MHz

1 MHz HFRCO — 213 — µA/MHz

Current consumption in EM2 IEM2_VS Full RAM retention and RTC run- — 1.87 — µA
mode, VSCALE0 ning from LFXO

Full RAM retention and RTC run- — 1.86 — µA

ning from LFRCO

24 kB RAM retention and RTC — 1.73 — µA

running from LFXO

24 kB RAM retention and RTC — 2.26 — µA

running from LFRCO in precision
mode

8 kB RAM retention and RTC run- — 1.57 — µA

ning from LFXO

8 kB RAM retention and RTC run- — 1.56 — µA

ning from LFRCO

8 kB RAM retention and RTC run- — 1.32 — µA

ning from LFXO, Radio RAM and
CPU cache not retained

Current consumption in EM3 IEM3_VS 8 kB RAM retention and RTC run- — 1.34 — µA
mode, VSCALE0 ning from ULFRCO

Current consumption in EM4 IEM4 No BURTC, no LF oscillator — 0.13 — µA

mode
BURTC with LFXO — 0.44 — µA

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Electrical Specifications

Parameter Symbol Test Condition Min Typ Max Unit

Current consumption during IRST Hard pin reset held — 190 — µA

reset

Additional current in EM2 or IPD0B_VS — 0.54 — µA

EM3 when any peripheral in
PD0B is enabled1

Note:
1. Extra current consumed by power domain. Does not include current associated with the enabled peripherals. See for a list of the
peripherals in each power domain.

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Electrical Specifications

4.6.4 Radio current consumption at 3.0V using DCDC

RF current consumption measured with MCU in EM1, HCLK = 38.4 MHz, and all MCU peripherals disabled. Unless otherwise indica-
ted, typical conditions are: VREGVDD = 3.0V. AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8 V powered from DCDC. TA = 25 °C.
Minimum and maximum values in this table represent the worst conditions across process variation at TA = 25 °C.

Table 4.8. Radio current consumption at 3.0V using DCDC

Parameter Symbol Test Condition Min Typ Max Unit

System current consumption IRX_ACTIVE 1 Mbit/s, 2GFSK, f = 2.4 GHz, — 3.6 — mA

in receive mode, active pack- VSCALE1, EM1P (Radio clocks
et reception only)

1 Mbit/s, 2GFSK, f = 2.4 GHz, — 3.8 — mA

VSCALE1

1 Mbit/s, 2GFSK, f = 2.4 GHz, — 3.9 — mA

VSCALE2

2 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.0 — mA

VSCALE1, EM1P (Radio clocks
only)

2 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.2 — mA

VSCALE1

2 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.4 — mA

VSCALE2

System current consumption IRX_LISTEN 1 Mbit/s, 2GFSK, f = 2.4 GHz, — 3.6 — mA

in receive mode, listening for VSCALE1, EM1P (Radio clocks
packet only)

1 Mbit/s, 2GFSK, f = 2.4 GHz, — 3.8 — mA

VSCALE1

1 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.0 — mA

VSCALE2

2 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.1 — mA

VSCALE1, EM1P (Radio clocks
only)

2 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.3 — mA

VSCALE1

2 Mbit/s, 2GFSK, f = 2.4 GHz, — 4.5 — mA

VSCALE2

System current consumption ITX f = 2.4 GHz, CW, 0 dBm PA, 0 — 4.1 — mA
in transmit mode dBm output power, VSCALE1,
EM1P (Radio clocks only)

f = 2.4 GHz, CW, 0 dBm PA, 0 — 4.3 — mA

dBm output power, VSCALE1

f = 2.4 GHz, CW, 0 dBm PA, 0 — 4.4 — mA

dBm output power, VSCALE2

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Electrical Specifications

4.7 Flash Characteristics

Table 4.9. Flash Characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Flash Supply voltage during VFLASH 1.71 — 3.8 V

write or erase

Program Time tPROG one word (32-bits) 42.1 44 45.6 uSec

average per word over 128 words 10.3 10.9 11.3 uSec

Page Erase Time tPERASE 11.4 12.9 14.4 ms

Mass Erase Time tMERASE Erases all of User Code area 11.7 13 14.3 ms

Program Current IPROG — — 1.45 mA

Page Erase Current IPERASE Page Erase — — 1.34 mA

Mass Erase Current IMERASE Mass Erase — — 1.28 mA

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Electrical Specifications

4.8 Wake Up, Entry, and Exit times

Unless otherwise specified, these times are measured using the HFRCO at 19 MHz.

Table 4.10. Wake Up, Entry, and Exit times

Parameter Symbol Test Condition Min Typ Max Unit

WakeupTime from EM1 tEM1_WU Code execution from flash — 3 — AHB

Clocks

Code execution from RAM — 1.42 — µs

WakeupTime from EM2 tEM2_WU Code execution from flash, No — 13.22 — µs

Voltage Scaling

Code execution from RAM, No — 5.15 — µs

Voltage Scaling

Voltage scaling up one level1 — 37.89 — µs

Voltage scaling up two levels2 — 50.56 — µs

WakupTime from EM3 tEM3_WU Code execution from flash, No — 13.21 — µs

Voltage Scaling

Code execution from RAM, No — 5.15 — µs

Voltage Scaling

Voltage scaling up one level1 — 37.90 — µs

Voltage scaling up two levels2 — 50.55 — µs

WakeupTime from EM4 tEM4_WU Code execution from flash — 8.81 — ms

Entry time to EM1 tEM1_ENT Code execution from flash — 1.29 — µs

Entry time to EM2 tEM2_ENT Code execution from flash — 5.23 — µs

Entry time to EM3 tEM3_ENT Code execution from flash — 5.23 — µs

Entry time to EM4 tEM4_ENT Code execution from flash — 9.96 — µs

Voltage scaling in time in tSCALE Up from VSCALE1 to VSCALE2 — 32 — µs

EM03
Down from VSCALE2 to — 172 — µs
VSCALE1

Note:
1. Voltage scaling one level is between VSCALE0 and VSCALE1 or between VSCALE1 and VSCALE2.
2. Voltage scaling two levels is between VSCALE0 and VSCALE2.
3. During voltage scaling in EM0, RAM is inaccessible and processor will be halted until complete.

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Electrical Specifications

4.9 RFSENSE Low-energy Wake-on-RF

Table 4.11. RFSENSE Low-energy Wake-on-RF

Parameter Symbol Test Condition Min Typ Max Unit

Average current IRFSENSE RF energy below wake threshold — 138 — nA

Selective mode, RF energy above — 131 — nA

threshold but no OOK sync detec-
ted

RF level above which THRESTRIG Threshold set to -34 dBm -28 — — dBm
RFSENSE will detect signal1
Threshold set to -22 dBm -19 — — dBm

RF level below which THRESNOTRIG Threshold set to -34 dBm — — -40 dBm
RFSENSE will not detect sig-
nal1 Threshold set to -22 dBm — — -26 dBm

Sensitivity in selective OOK SENSOOK Sensitivity for > 90% probability of -28 — — dBm
mode1 OOK detection2, threshold set to
-34 dBm

Sensitivity for > 90% probability of -19 — — dBm

OOK detection2, threshold set to
-22 dBm

Note:
1. Values collected with conducted measurements performed at the end of the matching network.
2. Selective wake signal is 1 kHz OOK Manchester-coded, 8 bits of preamble, 32-bit sync word.

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Electrical Specifications

4.10 2.4 GHz RF Transceiver Characteristics

4.10.1 RF Transmitter Characteristics

4.10.1.1 RF Transmitter General Characteristics for the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Table 4.12. RF Transmitter General Characteristics for the 2.4 GHz Band

Parameter Symbol Test Condition Min Typ Max Unit

RF tuning frequency range FRANGE 2400 — 2483.5 MHz

Radio-only current consump- ITX_RADIO f = 2.4 GHz, CW, 0 dBm PA, 0 — 3.4 — mA
tion while transmitting1 dBm output power

Maximum TX power2 POUTMAX 0 dBm PA — 0 — dBm

Minimum active TX power POUTMIN 0 dBm PA — -28 — dBm

Output power variation vs POUTVAR_V 0 dBm PA output power, using — 0.03 — dB

supply voltage variation, fre- DCDC with VREGVDD swept
quency = 2450 MHz from 1.8 to 3.0 V

Output power variation vs POUTVAR_T 0 dBm PA at 0 dBm, (-40 to +85 — 1.0 — dB

temperature, Frequency = °C)
2450 MHz

Output power variation vs RF POUTVAR_F 0 dBm PA, 0 dBm — 0.19 — dB

frequency

Spurious emissions of har- SPURHRM_FCC_ Continuous transmission of CW — -47 — dBm

monics in restricted bands R carrier, Pout = POUTMAX, Test
per FCC Part 15.205/15.209 Frequency = 2450 MHz.

Spurious emissions out-of- SPUROOB_FCC_ Restricted bands 30-88 MHz, — -47 — dBm
band (above 2.483 GHz or R Continuous transmission of CW
below 2.4 GHz) in restricted carrier, Pout = POUTMAX, Test
bands, per FCC part Frequency = 2450 MHz
15.205/15.209
Restricted bands 88 - 216 MHz, — -47 — dBm
Continuous transmission of CW
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz

Restricted bands 216 - 960 MHz, — -47 — dBm

Continuous transmission of CW
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz

Restricted bands > 960 MHz, — -47 — dBm

Continuous transmission of CW
carrier, Pout = POUTMAX, Test
Frequency = 2450 MHz

Spurious emissions out-of- SPUROOB_FCC_ Frequencies above 2.483 GHz or — -26 — dBc
band in non-restricted bands NR below 2.4 GHz, continuous trans-
per FCC Part 15.247 mission CW carrier, Pout =
POUTMAX, Test Frequency =
2450 MHz

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Parameter Symbol Test Condition Min Typ Max Unit

Spurious emissions per ETSI SPURETSI440 47-74 MHz,87.5-108 MHz, — -60 — dBm
EN300.440 174-230 MHz, 470-862 MHz, Pout
= POUTMAX, Test Frequency =
2450 MHz

25-1000 MHz, excluding above — -42 — dBm

frequencies. Pout = POUTMAX,
Test Frequency = 2450 MHz

1G-14G, Pout = POUTMAX, Test — -36 — dBm

Frequency = 2450 MHz

Spurious emissions out-of- SPURETSI328 [2400-2BW to 2400-BW], — -26 — dBm

band, per ETSI 300.328 [2483.5+BW to 2483.5+2BW],
Pout = POUTMAX, Test Frequency
= 2450 MHz

47-74 MHz, 87.5-118 MHz, — -60 — dBm

174-230 MHz, 470-862 MHz, Pout
= POUTMAX, Test Frequency =
2450 MHz

30-47 MHz, 74-87.5 MHz, — -42 — dBm

118-174 MHz, 230-470 MHz,
862-1000 MHz , Pout = POUTMAX,
Test Frequency = 2450 MHz

1G-12.75 GHz, excluding bands — -36 — dBm

listed above, Pout = POUTMAX,
Test Frequency = 2450 MHz

[2400-BW to 2400], [2483.5 to — -16 — dBm

2483.5+BW] Pout = POUTMAX,
Test Frequency = 2450 MHz

Note:
1. Supply current to radio, supplied by DC-DC with 3.0 V, measured at VREGVDD.
2. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this data sheet can be found in the Max TX Power column of the Ordering Information Table.

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4.10.1.2 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Table 4.13. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Parameter Symbol Test Condition Min Typ Max Unit

Transmit 6 dB bandwidth TXBW Pout = 0 dBm — 640 — kHz

Power spectral density limit PSDLIMIT Pout = 0 dBm, Per FCC part — -3.2 — dBm/
15.247 at 0 dBm 3kHz

Per ETSI 300.328 at 10 dBm/1 — 7.1 — dBm

MHz

Occupied channel bandwidth OCPETSI328 Pout = 0 dBm 99% BW at highest — 1.1 — MHz
per ETSI EN300.328 and lowest channels in band

In-band spurious emissions, SPURINB Pout = 0 dbm, Inband spurs at ± 2 — -48 — dBm
with allowed exceptions1 MHz

Pout = 0dbm Inband spurs at ± 3 — -54 — dBm

MHz

Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

4.10.1.3 RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Table 4.14. RF Transmitter Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Parameter Symbol Test Condition Min Typ Max Unit

Transmit 6 dB bandwidth TXBW Pout = 0 dBm — 1220 — kHz

Power spectral density limit PSDLIMIT Pout = 0 dBm, Per FCC part — -5.7 — dBm/
15.247 at 0 dBm 3kHz

Per ETSI 300.328 at 10 dBm/1 — 6.3 — dBm

MHz

Occupied channel bandwidth OCPETSI328 Pout = 0 dBm 99% BW at highest — 2.1 — MHz
per ETSI EN300.328 and lowest channels in band

In-band spurious emissions, SPURINB Pout = 0 dBm, Inband spurs at ± 4 — -47 — dBm
with allowed exceptions1 MHz

Pout = 0 dbm Inband spurs at ± 6 — -53 — dBm

MHz

Note:
1. Per Bluetooth Core_5.1, Vol.6 Part A, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a
frequency which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.

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4.10.2 RF Receiver Characteristics

4.10.2.1 RF Receiver General Characteristics for the 2.4 GHz Band

Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz.

Table 4.15. RF Receiver General Characteristics for the 2.4 GHz Band

Parameter Symbol Test Condition Min Typ Max Unit

RF tuning frequency range FRANGE 2400 — 2483.5 MHz

Radio-only current consump- IRX_RADIO — 2.5 — mA

tion in receive mode1

Receive mode maximum SPURRX 30 MHz to 1 GHz — -63 — dBm

spurious emission
1 GHz to 12 GHz — -53 — dBm

Max spurious emissions dur- SPURRX_FCC 216 MHz to 960 MHz, conducted — -47 — dBm
ing active receive mode, per measurement
FCC Part 15.109(a)
Above 960 MHz, conducted — -47 — dBm
measurement.

2GFSK Sensitivity SENS2GFSK 2 Mbps 2GFSK signal, 1% PER — -93 — dBm

250 kbps 2GFSK signal, 0.1% — -104 — dBm

BER

Note:
1. Supply current to radio, supplied by DC-DC with 3.0 V, measured at VREGVDD.

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4.10.2.2 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz, Packet length is 255 bytes.

Table 4.16. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 1 Mbps Data Rate

Parameter Symbol Test Condition Min Typ Max Unit

Max usable receiver input SAT Signal is reference signal1 — 10 — dBm

level

Sensitivity SENS Signal is reference signal, 37 byte — -98.9 — dBm

payload2

Signal is reference signal, 255 — -97.4 — dBm

byte payload1

With non-ideal signals3 1 — -96.9 — dBm

Signal to co-channel interfer- C/ICC (see notes)1 4 — 8.7 — dB

er

N ± 1 Adjacent channel se- C/I1 Interferer is reference signal at +1 — -6.6 — dB

lectivity MHz offset1 5 4 6

Interferer is reference signal at -1 — -6.5 — dB

MHz offset1 5 4 6

N ± 2 Alternate channel se- C/I2 Interferer is reference signal at +2 — -40.9 — dB

lectivity MHz offset1 5 4 6

Interferer is reference signal at -2 — -39.9 — dB

MHz offset1 5 4 6

N ± 3 Alternate channel se- C/I3 Interferer is reference signal at +3 — -45.9 — dB

lectivity MHz offset1 5 4 6

Interferer is reference signal at -3 — -46.2 — dB

MHz offset1 5 4 6

Selectivity to image frequen- C/IIM Interferer is reference signal at im- — -23.5 — dB

cy age frequency with 1 MHz preci-
sion1 6

Selectivity to image frequen- C/IIM_1 Interferer is reference signal at im- — -40.9 — dB

cy ± 1 MHz age frequency +1 MHz with 1
MHz precision1 6

Interferer is reference signal at im- — -6.6 — dB

age frequency -1 MHz with 1 MHz
precision1 6

Intermodulation performance IM n = 3 (see note7) — -17.1 — dBm

Note:
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -67 dBm.
5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
6. With allowed exceptions.
7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4

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4.10.2.3 RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Unless otherwise indicated, typical conditions are: TA = 25 °C, VREGVDD = 3.0V, AVDD = DVDD = IOVDD = RFVDD = PAVDD = 1.8
V powered from DCDC. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz, Packet length is 255 bytes.

Table 4.17. RF Receiver Characteristics for Bluetooth Low Energy in the 2.4 GHz Band 2 Mbps Data Rate

Parameter Symbol Test Condition Min Typ Max Unit

Max usable receiver input SAT Signal is reference signal1 — 10 — dBm

level

Sensitivity SENS Signal is reference signal, 37 byte — -96.2 — dBm

payload2

Signal is reference signal, 255 — -94.6 — dBm

byte payload1

With non-ideal signals3 1 — -94.4 — dBm

Signal to co-channel interfer- C/ICC (see notes)1 4 — 8.8 — dB

er

N ± 1 Adjacent channel se- C/I1 Interferer is reference signal at +2 — -9.2 — dB

lectivity MHz offset1 5 4 6

Interferer is reference signal at -2 — -6.6 — dB

MHz offset1 5 4 6

N ± 2 Alternate channel se- C/I2 Interferer is reference signal at +4 — -43.3 — dB

lectivity MHz offset1 5 4 6

Interferer is reference signal at -4 — -44.0 — dB

MHz offset1 5 4 6

N ± 3 Alternate channel se- C/I3 Interferer is reference signal at +6 — -48.6 — dB

lectivity MHz offset1 5 4 6

Interferer is reference signal at -6 — -50.7 — dB

MHz offset1 5 4 6

Selectivity to image frequen- C/IIM Interferer is reference signal at im- — -23.8 — dB

cy age frequency with 1 MHz preci-
sion1 6

Selectivity to image frequen- C/IIM_1 Interferer is reference signal at im- — -43.3 — dB

cy ± 2 MHz age frequency +2 MHz with 1
MHz precision1 6

Interferer is reference signal at im- — -9.2 — dB

age frequency -2 MHz with 1 MHz
precision1 6

Intermodulation performance IM n = 3 (see note7) — -18.8 — dBm

Note:
1. 0.017% Bit Error Rate.
2. 0.1% Bit Error Rate.
3. With non-ideal signals as specified in Bluetooth Test Specification RF-PHY.TS.5.0.1 section 4.7.1
4. Desired signal -64 dBm.
5. Desired frequency 2402 MHz ≤ Fc ≤ 2480 MHz.
6. With allowed exceptions.
7. As specified in Bluetooth Core specification version 5.1, Vol 6, Part A, Section 4.4

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4.11 Oscillators

4.11.1 High Frequency Crystal Oscillator

Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table
represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Table 4.18. High Frequency Crystal Oscillator

Parameter Symbol Test Condition Min Typ Max Unit

Crystal Frequency FHFXO see note1 — 38.4 — MHz

Supported crystal equivalent ESRHFXO_38M4 38.4 MHz, CL = 10 pF2 3 — 40 60 Ω

series resistance (ESR)

Supported range of crystal CHFXO_LC 38.4 MHz, ESR = 40 Ohm3 — 10 — pF

load capacitance4

Supply Current IHFXO — 415 — µA

Startup Time TSTARTUP 38.4 MHz, ESR = 40 Ohm, CL = — 160 — µs

10 pF

On-chip tuning cap step SSHFXO — 0.04 — pF

size5

Note:
1. The BLE radio requires a 38.4 MHz crystal with a tolerance of ± 50 ppm over temperature and aging. Please use the recommen-
ded crystal.
2. The crystal should have a maximum ESR less than or equal to this maximum rating.
3. RF performance characteristics have been determined using crystals with an ESR of 40 Ω and CL of 10 pF.
4. Total load capacitance as seen by the crystal.
5. The tuning step size is the effective step size when incrementing one of the tuning capacitors by one count. The step size for the
each of the indivdual tuning capacitors is twice this value.

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4.11.2 Low Frequency Crystal Oscillator

Table 4.19. Low Frequency Crystal Oscillator

Parameter Symbol Test Condition Min Typ Max Unit

Crystal Frequency FLFXO — 32.768 — kHz

Supported Crystal equivalent ESRLFXO GAIN = 0 — — 80 kΩ

series resistance (ESR)
GAIN = 1 to 3 — — 100 kΩ

Supported range of crystal CLFXO_CL GAIN = 0 4 — 6 pF

load capacitance 1
GAIN = 1 6 — 10 pF

GAIN = 2 (see note2) 10 — 12.5 pF

GAIN = 3 (see note2) 12.5 — 18 pF

Current consumption ICL12p5 ESR = 70 kOhm, CL = 12.5 pF, — 357 — nA

GAIN3 = 2, AGC4 = 1

Startup Time TSTARTUP ESR = 70 kOhm, CL = 7 pF, — 63 — ms

GAIN3 = 1, AGC4 = 1

On-chip tuning cap step size SSLFXO — 0.26 — pF

On-chip tuning capacitor val- CLFXO_MIN CAPTUNE = 0 — 4 — pF

ue at minimum setting5

On-chip tuning capacitor val- CLFXO_MAX CAPTUNE = 0x4F — 24.5 — pF

ue at maximum setting5

Note:
1. Total load capacitance seen by the crystal
2. Crystals with a load capacitance of greater than 12 pF require external load capacitors.
3. In LFXO_CAL Register
4. In LFXO_CFG Register
5. The effective load capacitance seen by the crystal will be CLFXO/2. This is because each XTAL pin has a tuning cap and the two
caps will be seen in series by the crystal

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4.11.3 High Frequency RC Oscillator (HFRCO)

Unless otherwise indicated, typical conditions are: AVDD = DVDD = 3.0 V. TA = 25 °C. Minimum and maximum values in this table
represent the worst conditions across process variation, operating supply voltage range, and operating temperature range.

Table 4.20. High Frequency RC Oscillator (HFRCO)

Parameter Symbol Test Condition Min Typ Max Unit

Frequency Accuracy FHFRCO_ACC For all production calibrated fre- -3 — 3 %

quencies

Current consumption on all IHFRCO FHFRCO = 1 MHz — 28 — µA

supplies 1
FHFRCO = 2 MHz — 28 — µA

FHFRCO = 4 MHz — 28 — µA

FHFRCO = 5 MHz — 30 — µA

FHFRCO = 7 MHz — 60 — µA

FHFRCO = 10 MHz — 66 — µA

FHFRCO = 13 MHz — 79 — µA

FHFRCO = 16 MHz — 88 — µA

FHFRCO = 19 MHz — 92 — µA

FHFRCO = 20 MHz — 105 — µA

FHFRCO = 26 MHz — 118 — µA

FHFRCO = 32 MHz — 141 — µA

FHFRCO = 38 MHz — 172 — µA

Clock out current for ICLKOUT_HFRCOD FORECEEN bit of CTRL = 1 and — 2.72 — µA/MHz
HFRCODPLL2 PLL the CLKOUTDIS0 bit of TEST = 1.

FORECEEN bit of CTRL i= 1 and — 0.36 — µA/MHz

the CLKOUTDIS1 bit of TEST = 1.

Startup Time3 TSTARTUP FREQRANGE = 0 to 7 — 1.2 — µs

FREQRANGE = 8 to 15 — 0.6 — µs

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Parameter Symbol Test Condition Min Typ Max Unit

Band Frequency Limits4 fHFRCO_BAND FREQRANGE = 0 3.71 — 5.24 MHz

FREQRANGE = 1 4.39 — 6.26 MHz

FREQRANGE = 2 5.25 — 7.55 MHz

FREQRANGE = 3 6.22 — 9.01 MHz

FREQRANGE = 4 7.88 — 11.6 MHz

FREQRANGE = 5 9.9 — 14.6 MHz

FREQRANGE = 6 11.5 — 17.0 MHz

FREQRANGE = 7 14.1 — 20.9 MHz

FREQRANGE = 8 16.4 — 24.7 MHz

FREQRANGE = 9 19.8 — 30.4 MHz

FREQRANGE = 10 22.7 — 34.9 MHz

FREQRANGE = 11 28.6 — 44.4 MHz

FREQRANGE = 12 33.0 — 51.0 MHz

Note:
1. Does not include additional clock tree current. See specifications for additional current when selected as a clock source for a par-
ticular clock multiplexer.
2. When the HFRCO is enabled for characterization using the FORCEEN bit, the total current will be the HFRCO core current plus
the specified CLKOUT current. When the HFRCO is enabled on demand, the clock current may be different.
3. Hardware delay ensures settling to within ± 0.5%. Hardware also enforces this delay on a band change.
4. The frequency band limits represent the lowest and highest freqeuncy which each band can achieve over the operating range.

4.11.4 Fast Start_Up RC Oscillator (FSRCO)

Table 4.21. Fast Start_Up RC Oscillator (FSRCO)

Parameter Symbol Test Condition Min Typ Max Unit

FSRCO frequency FFSRCO 17.2 20 21.2 MHz

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4.11.5 Precision Low Frequency RC Oscillator (LFRCO)

Table 4.22. Precision Low Frequency RC Oscillator (LFRCO)

Parameter Symbol Test Condition Min Typ Max Unit

Nominal oscillation frequen- FLFRCO — 32.768 — kHz

cy

Frequency accuracy FLFRCO_ACC Normal mode -3 — 3 %

Precision mode1, across operat- -500 — 500 ppm

ing temperature range2

Startup time tSTARTUP Normal mode — 204 — µs

Precision mode1 — 11.7 — ms

Current consumption ILFRCO Normal mode — 175 — nA

Precision mode1, T = stable at 25 — 655 — nA

°C 3

Note:
1. The LFRCO operates in high-precision mode when CFG_HIGHPRECEN is set to 1. High-precision mode is not available in EM4.
2. Includes ± 40 ppm frequency tolerance of the HFXO crystal.
3. Includes periodic re-calibration against HFXO crystal oscillator.

4.11.6 Ultra Low Frequency RC Oscillator

Table 4.23. Ultra Low Frequency RC Oscillator

Parameter Symbol Test Condition Min Typ Max Unit

Oscillation Frequency FULFRCO 0.944 1.0 1.095 kHz

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4.12 GPIO Pins (3V GPIO pins)

Table 4.24. GPIO Pins (3V GPIO pins)

Parameter Symbol Test Condition Min Typ Max Unit

Leakage current ILEAK_IO MODEx = DISABLED, IOVDD = — 1.9 — nA

1.71 V

MODEx = DISABLED, IOVDD = — 2.5 — nA

3.0 V

MODEx = DISABLED, IOVDD = — — 150 nA

3.8 V TA = 85 °C

Input low voltage1 VIL Any GPIO pin — — 0.3*IOVDD V

RESETn — — 0.3*DVDD V

Input high voltage1 VIH Any GPIO pin 0.7*IOVDD — — V

RESETn 0.7*DVDD — — V

Hysteresis of input voltage VHYS Any GPIO pin 0.05*IOVD — — V

D

RESETn 0.05*DVDD — — V

Output high voltage VOH Sourcing 20mA, IOVDD = 3.0 V 0.8 * — — V

IOVDD

Sourcing 8mA, IOVDD = 1.71 V 0.6 * — — V

IOVDD

Output low voltage VOL Sinking 20mA, IOVDD = 3.0 V — — 0.2 * V

IOVDD

Sinking 8mA, IOVDD = 1.71 V — — 0.4 * V

IOVDD

GPIO rise time TGPIO_RISE IOVDD = 3.0 V, Cload = 50pF, — 8.4 — ns

SLEWRATE = 4, 10% to 90%

IOVDD = 1.71 V, Cload = 50pF, — 13 — ns

SLEWRATE = 4, 10% to 90%

GPIO fall time TGPIO_FALL IOVDD = 3.0 V, Cload = 50pF, — 7.1 — ns

SLEWRATE = 4, 90% to 10%

IOVDD = 1.71 V, Cload = 50pF, — 11.9 — ns

SLEWRATE = 4, 90% to 10%

Pull up/down resistance2 RPULL Any GPIO pin. Pull-up to IOVDD: 35 44 55 kΩ

MODEn = DISABLE DOUT=1.
Pull-down to VSS: MODEn =
WIREDORPULLDOWN DOUT =
0.

RESETn pin. Pull-up to DVDD 35 44 55 kΩ

Maximum filtered glitch width TGF MODE = INPUT, DOUT = 1 — 27 — ns

RESETn low time to ensure TRESET 100 — — ns

pin reset

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Parameter Symbol Test Condition Min Typ Max Unit

Note:
1. GPIO input thresholds are proportional to the IOVDD pin. RESETn input thresholds are proportional to DVDD.
2. GPIO pull-ups connect to IOVDD supply, pull-downs connect to VSS. RESETn pull-up connects to DVDD.

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4.13 Analog to Digital Converter (IADC)

Specified at 1 Msps, ADCCLK = 10 MHz, OSR=2, unless otherwise indicated.

Table 4.25. Analog to Digital Converter (IADC)

Parameter Symbol Test Condition Min Typ Max Unit

Main analog supply VAVDD Normal Mode 1.71 — 3.8 V

Maximum Input Range1 VIN_MAX Maximum allowable input voltage 0 — AVDD V

Full-Scale Voltage VFS Voltage required for Full-Scale — VREF / Gain —

measurement

Input Measurement Range VIN Differential Mode - Plus and Mi- -VFS — +VFS V
nus inputs

Single Ended Mode - One input 0 — VFS V

tied to ground

Input Sampling Capacitance Cs Analog Gain = 1x — 1.8 — pF

Analog Gain = 2x — 3.6 — pF

Analog Gain = 4x — 7.2 — pF

Analog Gain = 0.5x — 0.9 — pF

ADC clock frequency fCLK Normal Mode — — 10 MHz

Throughput rate fSAMPLE fCLK = 10 MHz, OSR = 2 — — 1 Msps

fCLK = 10 MHz, OSR = 32 — — 76.9 ksps

Current from all supplies, IADC_CONT Normal Mode, 1 Msps, OSR = 2, — 290 385 µA
Continuous operation fCLK = 10 MHz

Current in Standby mode. ISTBY Normal Mode — 16 — µA

ADC is not functional but can
wake up in 1us.

ADC Startup Time tstartup From power down state — 5 — µs

From Standby state — 1 — µs

ADC Resolution2 Resolution — 12 — bits

— 16 — bits

Differential Nonlinearity DNL Differential Input, OSR = 2, (No -1 +/- 0.25 1.5 LSB12
missing codes) .

Integral Nonlinearity INL Normal Mode, Differential Input, -2.5 +/- 0.65 2.5 LSB12
OSR = 2.

Effective number of bits3 ENOB Differential Input. Gain = 1x, OSR 10.5 11.7 — bits
= 2, fIN = 10 kHz, Internal
VREF=1.21V. OSR=2

Differential Input. Gain = 1x, OSR — 13.5 — bits

= 32, fIN = 2.5 kHz, Internal VREF
= 1.21 V.

Differential Input. Gain = 1x, OSR — 14.3 — bits

= 32, fIN = 2.5 kHz, External
VREF = 1.25 V.

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Parameter Symbol Test Condition Min Typ Max Unit

Signal to Noise + Distortion SNDR Differential Input. Gain=1x, OSR = 65 72.3 — dB

Ratio3 2, fIN = 10 kHz, Internal
VREF=1.21V

Differential Input. Gain=2x, OSR = — 72.3 — dB

2, fIN = 10 kHz, Internal
VREF=1.21V

Differential Input. Gain=4x, OSR = — 68.8 — dB

2, fIN = 10 kHz, Internal
VREF=1.21V

Differential Input. Gain=0.5x, OSR — 72.5 — dB

= 2, fIN = 10 kHz, Internal
VREF=1.21V

Total Harmonic Distortion THD Differential Input. Gain=1x, OSR = — -80.8 -70 dB
2, fIN = 10 kHz, Internal
VREF=1.21V

Spurious-Free Dynamic SFDR Differential Input. Gain=1x, OSR = 72 86.5 — dB

Range 2, fIN = 10 kHz, Internal
VREF=1.21V

Common Mode Rejection CMRR Normal Mode. DC to 100 Hz — 87.0 — dB

Ratio
Normal Mode. AC high frequency — 68.6 — dB

Power Supply Rejection Ra- PSRR Normal mode. DC to 100 Hz — 80.4 — dB

tio
Normal mode. AC high frequency, — 33.4 — dB
using VREF pad.

Normal mode. AC high frequency, — 65.2 — dB

using internal VBGR.

Gain Error GE GAIN=1 and 0.5, using external -0.3 0.069 0.3 %
VREF, direct mode.

GAIN=2, using external VREF, di- -0.4 0.151 0.4 %

rect mode.

GAIN=3, using external VREF, di- -0.7 0.186 0.7 %

rect mode.

GAIN=4, using external VREF, di- -1.1 0.227 1.1 %

rect mode.

Internal VREF4, all GAIN settings -1.5 0.023 1.5 %

Offset OFFSET GAIN=1 and 0.5, Differential Input -3 0.27 3 LSB

GAIN=2, Differential Input -4 0.27 4 LSB

GAIN=3, Differential Input -4 0.25 4 LSB

GAIN=4, Differential Input -4 0.29 4 LSB

External reference voltage VEVREF 1.0 — AVDD V

range1

Internal Reference voltage VIVREF — 1.21 — V

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Parameter Symbol Test Condition Min Typ Max Unit

Note:
1. When inputs are routed to external GPIO pins, the maximum pin voltage is limited to the lower of the IOVDD and AVDD supplies.
2. ADC output resolution depends on the OSR and digital averaging settings. With no digital averaging, ADC output resolution is 12
bits at OSR=2, 13 bits at OSR = 4, 14 bits at OSR = 8, 15 bits at OSR = 16, 16 bits at OSR = 32. Digital averaging has a similar
impact on ADC output resolution. See the product reference manual for additional details.
3. The relationship between ENOB and SNDR is specified according to the equation: ENOB = (SNDR - 1.76) / 6.02.
4. Includes error from internal VREF drift.

4.14 Temperature Sense

Table 4.26. Temperature Sense

Parameter Symbol Test Condition Min Typ Max Unit

Temperature sensor range1 TRANGE -40 — 125 °C

Temperature sensor resolu- TRESOLUTION — 0.25 — °C

tion

Measurement noise (RMS) TNOISE Single measurement — 0.6 — °C

16-sample average (TEMPAVG- — 0.17 — °C

NUM = 0)

64-sample average (TEMPAVG- — 0.12 — °C

NUM = 1)

Temperature offset TOFF Mean error of uncorrected output — 3.14 — °C

across full temperature range

Temperature sensor accura- TACC Direct output accuracy after mean -3 — 3 °C

cy2 3 error (TOFF) removed

After linearization in software, no -2 — 2 °C

calibration

After linearization in software, with -1.5 — 1.5 °C

single-temperature calibration at
25 °C4

Measurement interval tMEAS — 250 — ms

Note:
1. The sensor reports absolute die temperature in °K. All specifications are in °C to match the units of the specified product temper-
aure range.
2. Error is measured as the deviation of the mean temperature reading from the expected die temperature. Accuracy numbers rep-
resent statistical minimum and maximum using ± 4 standard deviations of measured error.
3. The raw output of the temperature sensor is a predictable curve. It can be linearized with a polynomial function for additional ac-
curacy.
4. Assuming calibration accuracy of ± 0.25 °C.

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4.15 Brown Out Detectors

4.15.1 DVDD BOD

BOD Thresholds on DVDD in EM0 and EM1 only, unless otherwise noted. Typical conditions are at TA = 25 °C. Minimum and maxi-
mum values in this table represent the worst conditions across process variation, operating supply voltage range, and operating tem-
perature range.

Table 4.27. DVDD BOD

Parameter Symbol Test Condition Min Typ Max Unit

BOD threshold VDVDD_BOD Supply Rising — 1.64 1.71 V

Supply Falling 1.62 1.65 — V

BOD response time tDVDD_BOD_DE- Supply dropping at 100mV/µs — 0.95 — µs

LAY slew rate1

BOD hysteresis VDVDD_BOD_HYS — 20 — mV

T

Note:
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

4.15.2 LE DVDD BOD

BOD thresholds on DVDD pin for low energy modes EM2 to EM4, unless otherwise noted.

Table 4.28. LE DVDD BOD

Parameter Symbol Test Condition Min Typ Max Unit

BOD threshold VDVDD_LE_BOD Supply Falling 1.5 — 1.71 V

BOD response time tDVDD_LE_BOD_D Supply dropping at 2mV/µs slew — 50 — µs

ELAY rate1

BOD hysteresis VDVDD_LE_BOD_ — 20 — mV

HYST

Note:
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

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4.15.3 AVDD and IOVDD BODs

BOD thresholds for AVDD BOD and IOVDD BOD. Available in all energy modes.

Table 4.29. AVDD and IOVDD BODs

Parameter Symbol Test Condition Min Typ Max Unit

BOD threshold VBOD Supply falling 1.45 — 1.71 V

BOD response time tBOD_DELAY Supply dropping at 2mV/µs slew — 50 — µs

rate1

BOD hysteresis VBOD_HYST — 20 — mV

Note:
1. If the supply slew rate exceeds the specified slew rate, the BOD may trip later than expected (at a threshold below the minimum
specified threshold), or the BOD may not trip at all (e.g., if the supply ramps down and then back up at a very fast rate)

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4.16 PDM Timing Specifications

PDM Microphone Mode

PDM_CLK
tISU tIH tISU tIH

PDM_DAT0-3 L R L R L

PDM Sensor Mode

PDM_CLK
tISU tIH

PDM_DAT0-3

Figure 4.3. PDM Timing Diagrams

4.16.1 Pulse Density Modulator (PDM), Common DBUS

Timing specifications are for all PDM signals routed to the same DBUS (DBUSAB or DBUSCD), though routing to the same GPIO port
is the optimal configuration. CLOAD < 20 pF. System voltage scaling = VSCALE1 or VSCALE2. All GPIO set to slew rate = 6. Data delay
(PDM_CFG1_DLYMUXSEL) = 0.

Table 4.30. Pulse Density Modulator (PDM), Common DBUS

Parameter Symbol Test Condition Min Typ Max Unit

PDM_CLK frequency during FPDM_CLK Microphone mode — — 5 MHz

data transfer
Sensor mode — — 20 MHz

PDM_CLK duty cycle DCPDM_CLK 47.5 — 52.5 %

PDM_CLK rise time tR — — 5.5 ns

PDM_CLK fall time tF — — 5.5 ns

Input setup time tISU Microphone mode 30 — — ns

Sensor mode 20 — — ns

Input hold time tIH 3 — — ns

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4.17 USART SPI Main Timing

CS tCS_MO
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1

MOSI
tSU_MI tH_MI

MISO

Figure 4.4. SPI Main Timing (SMSDELAY = 0)

CS tCS_MO
tSCLK_MO
SCLK
CLKPOL = 0
tSCLK
SCLK
CLKPOL = 1

MOSI
tSU_MI tH_MI

MISO

Figure 4.5. SPI Main Timing (SMSDELAY = 1)

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4.17.1 SPI Main Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.31. SPI Main Timing, Voltage Scaling = VSCALE2

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period 1 2 3 tSCLK 2*tPCLK — — ns

CS to MOSI 1 2 tCS_MO -22 — 22.5 ns

SCLK to MOSI 1 2 tSCLK_MO -14.5 — 14.5 ns

MISO setup time 1 2 tSU_MI IOVDD = 1.62 V 38.5 — — ns

IOVDD = 3.0 V 28.5 — — ns

MISO hold time 1 2 tH_MI -8.5 — — ns

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1
2. Measurement done with 8 pF output loading at 10% and 90% of VDD.
3. tPCLK is one period of the selected PCLK.

4.17.2 SPI Main Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.32. SPI Main Timing, Voltage Scaling = VSCALE1

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period 1 2 3 tSCLK 2*tPCLK — — ns

CS to MOSI 1 2 tCS_MO -33 — 34.5 ns

SCLK to MOSI 1 2 tSCLK_MO -15 — 26 ns

MISO setup time 1 2 tSU_MI IOVDD = 1.62 V 47 — — ns

IOVDD = 3.0 V 39 — — ns

MISO hold time 1 2 tH_MI -9.5 — — ns

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1
2. Measurement done with 8 pF output loading at 10% and 90% of VDD.
3. tPCLK is one period of the selected PCLK.

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4.18 USART SPI Secondary Timing

CS tCS_ACT_MI
tCS_DIS_MI
SCLK
CLKPOL = 0
tSCLK_HI tSCLK_LO
SCLK
CLKPOL = 1 tSU_MO
tSCLK
tH_MO
MOSI
tSCLK_MI

MISO

Figure 4.6. SPI Secondary Timing

4.18.1 SPI Secondary Timing, Voltage Scaling = VSCALE2

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.33. SPI Secondary Timing, Voltage Scaling = VSCALE2

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period 1 2 3 tSCLK 6*tPCLK — — ns

SCLK high time1 2 3 tSCLK_HI 2.5*tPCLK — — ns

SCLK low time1 2 3 tSCLK_LO 2.5*tPCLK — — ns

CS active to MISO 1 2 tCS_ACT_MI 25 — 47.5 ns

CS disable to MISO 1 2 tCS_DIS_MI 19.5 — 38.5 ns

MOSI setup time 1 2 tSU_MO 4.5 — — ns

MOSI hold time 1 2 3 tH_MO 5 — — ns

SCLK to MISO 1 2 3 tSCLK_MI 22 + — 33.5 + ns

1.5*tPCLK 2.5*tPCLK

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tPCLK is one period of the selected PCLK.

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4.18.2 SPI Secondary Timing, Voltage Scaling = VSCALE1

Timing specifications are for all SPI signals routed to the same DBUS (DBUSAB or DBUSCD). All GPIO set to slew rate = 6.

Table 4.34. SPI Secondary Timing, Voltage Scaling = VSCALE1

Parameter Symbol Test Condition Min Typ Max Unit

SCLK period 1 2 3 tSCLK 6*tPCLK — — ns

SCLK high time1 2 3 tSCLK_HI 2.5*tPCLK — — ns

SCLK low time1 2 3 tSCLK_LO 2.5*tPCLK — — ns

CS active to MISO 1 2 tCS_ACT_MI 30.5 — 57.5 ns

CS disable to MISO 1 2 tCS_DIS_MI 25 — 55 ns

MOSI setup time 1 2 tSU_MO 7.5 — — ns

MOSI hold time 1 2 3 tH_MO 8.5 — — ns

SCLK to MISO 1 2 3 tSCLK_MI 24.5 + — 45.5 + ns

1.5*tPCLK 2.5*tPCLK

Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0).
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD).
3. tPCLK is one period of the selected PCLK.

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4.19 I2C Electrical Specifications

4.19.1 I2C Standard-mode (Sm)

CLHR set to 0 in the I2Cn_CTRL register.

Table 4.35. I2C Standard-mode (Sm)

Parameter Symbol Test Condition Min Typ Max Unit

SCL clock frequency1 fSCL 0 — 100 kHz

SCL clock low time tLOW 4.7 — — µs

SCL clock high time tHIGH 4 — — µs

SDA set-up time tSU_DAT 250 — — ns

SDA hold time tHD_DAT 0 — — ns

Repeated START condition tSU_STA 4.7 — — µs

set-up time

Repeated START condition tHD_STA 4.0 — — µs

hold time

STOP condition set-up time tSU_STO 4.0 — — µs

Bus free time between a tBUF 4.7 — — µs

STOP and START condition

Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Electrical Specifications

4.19.2 I2C Fast-mode (Fm)

CLHR set to 1 in the I2Cn_CTRL register.

Table 4.36. I2C Fast-mode (Fm)

Parameter Symbol Test Condition Min Typ Max Unit

SCL clock frequency1 fSCL 0 — 400 kHz

SCL clock low time tLOW 1.3 — — µs

SCL clock high time tHIGH 0.6 — — µs

SDA set-up time tSU_DAT 100 — — ns

SDA hold time tHD_DAT 0 — — ns

Repeated START condition tSU_STA 0.6 — — µs

set-up time

Repeated START condition tHD_STA 0.6 — — µs

hold time

STOP condition set-up time tSU_STO 0.6 — — µs

Bus free time between a tBUF 1.3 — — µs

STOP and START condition

Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Electrical Specifications

4.19.3 I2C Fast-mode Plus (Fm+)

CLHR set to 1 in the I2Cn_CTRL register.

Table 4.37. I2C Fast-mode Plus (Fm+)

Parameter Symbol Test Condition Min Typ Max Unit

SCL clock frequency1 fSCL 0 — 1000 kHz

SCL clock low time tLOW 0.5 — — µs

SCL clock high time tHIGH 0.26 — — µs

SDA set-up time tSU_DAT 50 — — ns

SDA hold time tHD_DAT 0 — — ns

Repeated START condition tSU_STA 0.26 — — µs

set-up time

Repeated START condition tHD_STA 0.26 — — µs

hold time

STOP condition set-up time tSU_STO 0.26 — — µs

Bus free time between a tBUF 0.5 — — µs

STOP and START condition

Note:
1. The maximum SCL clock frequency listed is assuming that an arbitrary clock frequency is available. The maximum attainable
SCL clock frequency may be slightly less using the HFXO or HFRCO due to the limited frequencies available. The CLKDIV
should be set to a value that keeps the SCL clock frequency below the max value listed.

4.20 Typical Performance Curves

Typical performance curves indicate typical characterized performance under the stated conditions.

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Electrical Specifications

4.20.1 Supply Current

Figure 4.7. EM0 and EM1 Typical Supply Current vs. Temperature

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Electrical Specifications

Figure 4.8. EM2 and EM4 Typical Supply Current vs. Temperature

4.20.2 RF Characteristics

Figure 4.9. Transmitter Output Power

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Electrical Specifications

4.20.3 DC-DC Converter

Performance characterized with Samsung CIG22H2R2MNE (LDCDC = 2.2 uH ) and Samsung CL10B475KQ8NQNC (CDCDC = 4.7 uF)

Figure 4.10. DC-DC Efficiency

4.20.4 IADC

Typical performance is shown using 10 MHz ADC clock for fastest sampling speed and adjusting oversampling ratio (OSR).

Figure 4.11. Typical ENOB vs. Oversampling Ratio

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Typical Connections

5. Typical Connections

5.1 Power

Typical power supply connections are shown in the following figures.

Note: PAVDD, RFVDD, AVDD, and IOVDD supply connections are flexible. They may be connected in other configurations or to exter-
nal supplies as long as the supply limits described in 4.1 Electrical Characteristics are met.

VDD
Main +
Supply –

VREGVDD AVDD IOVDD

VREGSW
HFXTAL_I
VREGVSS 38.4 MHz
HFXTAL_O

DVDD LFXTAL_I 32.768 kHz

LFXTAL_O (optional)

DECOUPLE
VDD
CDECOUPLE RFVDD PAVDD

Figure 5.1. EFR32BG22C112 Typical Application Circuit: Direct Supply Configuration without DCDC

VDD
Main +
Supply – CIN

VREGVDD AVDD IOVDD

VDCDC LDCDC
VREGSW
HFXTAL_I
CDCDC VREGVSS 38.4 MHz
HFXTAL_O

DVDD LFXTAL_I 32.768 kHz

LFXTAL_O (optional)

DECOUPLE
CDECOUPLE RFVDD PAVDD

Figure 5.2. EFR32BG22C112 Typical Application Circuit: DCDC Configuration, PAVDD and RFVDD from DCDC output, AVDD
and IOVDD from main supply

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Typical Connections

VDD VDCDC
Main +
Supply – CIN

VREGVDD AVDD IOVDD

VDCDC LDCDC
VREGSW
HFXTAL_I
CDCDC VREGVSS 38.4 MHz
HFXTAL_O

DVDD LFXTAL_I 32.768 kHz

LFXTAL_O (optional)

DECOUPLE
CDECOUPLE RFVDD PAVDD

Figure 5.3. EFR32BG22C112 Typical Application Circuit: DCDC Configuration with PAVDD, RFVDD, AVDD, and IOVDD from
DCDC output

5.2 RF Matching Networks

5.2.1 2.4 GHz Matching Network

The recommended RF matching network circuit diagram is shown in Figure 5.4 Typical RF impedance-matching network circuit on
page 64. Typical component values are shown in Table 5.1 Component Values on page 64. Please refer to the development board
Bill of Materials for specific part recommendation including tolerance, component size, recommended manufacturer, and recommended
part number.

L1 C3
RF2G4_IO 50Ω
C1 C2

Figure 5.4. Typical RF impedance-matching network circuit

Table 5.1. Component Values

Designator Value

C1 1.2 pF

C2 1.3 pF

L1 2.6 nH

C3 18 pF

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Typical Connections

5.3 Other Connections

Other components or connections may be required to meet the system-level requirements. Application Note AN0002.2: "EFR32 Wire-
less Gecko Series 2 Hardware Design Considerations" contains detailed information on these connections. Application Notes can be
accessed on the Silicon Labs website (www.silabs.com/32bit-appnotes).

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Pin Definitions

6. Pin Definitions

6.1 QFN32 Device Pinout

Figure 6.1. QFN32 Device Pinout

The following table provides package pin connections and general descriptions of pin functionality. For detailed information on the sup-
ported features for each GPIO pin, see 6.2 Alternate Function Table, 6.3 Analog Peripheral Connectivity, and 6.4 Digital Peripheral
Connectivity.

Table 6.1. QFN32 Device Pinout

Pin Name Pin(s) Description Pin Name Pin(s) Description

PC00 1 GPIO PC01 2 GPIO

PC02 3 GPIO PC03 4 GPIO

PC04 5 GPIO PC05 6 GPIO

HFXTAL_I 7 High Frequency Crystal Input HFXTAL_O 8 High Frequency Crystal Output

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Pin Definitions

Pin Name Pin(s) Description Pin Name Pin(s) Description

Reset Pin. The RESETn pin is internally

RESETn 9 RFVDD 10 Radio power supply
pulled up to DVDD.

RFVSS 11 Radio Ground RF2G4_IO 12 2.4 GHz Single-ended RF input/output

PAVDD 13 Power Amplifier (PA) power supply PB02 14 GPIO

PB01 15 GPIO PB00 16 GPIO

PA00 17 GPIO PA01 18 GPIO

PA02 19 GPIO PA03 20 GPIO

PA04 21 GPIO PA05 22 GPIO

Decouple outputput for on-chip voltage

PA06 23 GPIO DECOUPLE 24 regulator. An external decoupling ca-
pacitor is required at this pin.

VREGSW 25 DCDC regulator switching node VREGVDD 26 DCDC regulator input supply

VREGVSS 27 DCDC ground DVDD 28 Digital power supply

AVDD 29 Analog power supply IOVDD 30 I/O power supply

PD01 31 GPIO PD00 32 GPIO

6.2 Alternate Function Table

A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows what functions are
available on each device pin.

Table 6.2. GPIO Alternate Function Table

GPIO Alternate Function

PC00 GPIO.EM4WU6 GPIO.THMSW_EN

PC05 GPIO.EM4WU7

PB01 GPIO.EM4WU3

PB00 IADC0.VREFN

PA00 IADC0.VREFP

PA01 GPIO.SWCLK

PA02 GPIO.SWDIO

GPIO.TRACEDA-
PA03 GPIO.SWV GPIO.TDO
TA0

PA04 GPIO.TDI GPIO.TRACECLK

PA05 GPIO.EM4WU0

PD01 LFXO.LFXTAL_I LFXO.LF_EXTCLK

PD00 LFXO.LFXTAL_O

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Pin Definitions

6.3 Analog Peripheral Connectivity

Many analog resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avali-
able on each GPIO port. When a differential connection is being used Positive inputs are restricted to the EVEN pins and Negative
inputs are restricted to the ODD pins. When a single ended connection is being used positive input is avaliable on all pins. See the
device Reference Manual for more details on the ABUS and analog peripherals.

Table 6.3. ABUS Routing Table

Peripheral Signal PA PB PC PD

EVEN ODD EVEN ODD EVEN ODD EVEN ODD

IADC0 ana_neg Yes Yes Yes Yes Yes Yes Yes Yes

ana_pos Yes Yes Yes Yes Yes Yes Yes Yes

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Pin Definitions

6.4 Digital Peripheral Connectivity

Many digital resources are routable and can be connected to numerous GPIO's. The table below indicates which peripherals are avalia-
ble on each GPIO port.

Table 6.4. DBUS Routing Table

Peripheral.Resource PORT

PA PB PC PD

CMU.CLKIN0 Available Available

CMU.CLKOUT0 Available Available

CMU.CLKOUT1 Available Available

CMU.CLKOUT2 Available Available

EUART0.CTS Available Available Available Available

EUART0.RTS Available Available Available Available

EUART0.RX Available Available Available Available

EUART0.TX Available Available Available Available

FRC.DCLK Available Available

FRC.DFRAME Available Available

FRC.DOUT Available Available

I2C0.SCL Available Available Available Available

I2C0.SDA Available Available Available Available

I2C1.SCL Available Available

I2C1.SDA Available Available

LETIMER0.OUT0 Available Available

LETIMER0.OUT1 Available Available

MODEM.ANT0 Available Available Available Available

MODEM.ANT1 Available Available Available Available

MODEM.ANT_ROLL_OVER Available Available

MODEM.ANT_RR0 Available Available

MODEM.ANT_RR1 Available Available

MODEM.ANT_RR2 Available Available

MODEM.ANT_RR3 Available Available

MODEM.ANT_RR4 Available Available

MODEM.ANT_RR5 Available Available

MODEM.ANT_SW_EN Available Available

MODEM.ANT_SW_US Available Available

MODEM.ANT_TRIG Available Available

MODEM.ANT_TRIG_STOP Available Available

MODEM.DCLK Available Available

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Pin Definitions

Peripheral.Resource PORT

PA PB PC PD

MODEM.DIN Available Available

MODEM.DOUT Available Available

PDM.CLK Available Available Available Available

PDM.DAT0 Available Available Available Available

PDM.DAT1 Available Available Available Available

PRS.ASYNCH0 Available Available

PRS.ASYNCH1 Available Available

PRS.ASYNCH10 Available Available

PRS.ASYNCH11 Available Available

PRS.ASYNCH2 Available Available

PRS.ASYNCH3 Available Available

PRS.ASYNCH4 Available Available

PRS.ASYNCH5 Available Available

PRS.ASYNCH6 Available Available

PRS.ASYNCH7 Available Available

PRS.ASYNCH8 Available Available

PRS.ASYNCH9 Available Available

PRS.SYNCH0 Available Available Available Available

PRS.SYNCH1 Available Available Available Available

PRS.SYNCH2 Available Available Available Available

PRS.SYNCH3 Available Available Available Available

TIMER0.CC0 Available Available Available Available

TIMER0.CC1 Available Available Available Available

TIMER0.CC2 Available Available Available Available

TIMER0.CDTI0 Available Available Available Available

TIMER0.CDTI1 Available Available Available Available

TIMER0.CDTI2 Available Available Available Available

TIMER1.CC0 Available Available Available Available

TIMER1.CC1 Available Available Available Available

TIMER1.CC2 Available Available Available Available

TIMER1.CDTI0 Available Available Available Available

TIMER1.CDTI1 Available Available Available Available

TIMER1.CDTI2 Available Available Available Available

TIMER2.CC0 Available Available

TIMER2.CC1 Available Available

TIMER2.CC2 Available Available

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Pin Definitions

Peripheral.Resource PORT

PA PB PC PD

TIMER2.CDTI0 Available Available

TIMER2.CDTI1 Available Available

TIMER2.CDTI2 Available Available

TIMER3.CC0 Available Available

TIMER3.CC1 Available Available

TIMER3.CC2 Available Available

TIMER3.CDTI0 Available Available

TIMER3.CDTI1 Available Available

TIMER3.CDTI2 Available Available

TIMER4.CC0 Available Available

TIMER4.CC1 Available Available

TIMER4.CC2 Available Available

TIMER4.CDTI0 Available Available

TIMER4.CDTI1 Available Available

TIMER4.CDTI2 Available Available

USART0.CLK Available Available Available Available

USART0.CS Available Available Available Available

USART0.CTS Available Available Available Available

USART0.RTS Available Available Available Available

USART0.RX Available Available Available Available

USART0.TX Available Available Available Available

USART1.CLK Available Available

USART1.CS Available Available

USART1.CTS Available Available

USART1.RTS Available Available

USART1.RX Available Available

USART1.TX Available Available

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
QFN32 Package Specifications

7. QFN32 Package Specifications

7.1 QFN32 Package Dimensions

Figure 7.1. QFN32 Package Drawing

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
QFN32 Package Specifications

Table 7.1. QFN32 Package Dimensions

Dimension Min Typ Max

A 0.80 0.85 0.90

A1 0.00 0.02 0.05

A3 0.20 REF

b 0.15 0.20 0.25

D 3.90 4.00 4.10

E 3.90 4.00 4.10

D2 2.60 2.70 2.80

E2 2.60 2.70 2.80

e 0.40 BSC

L 0.20 0.30 0.40

K 0.20 — —

R 0.075 — 0.125

aaa 0.10

bbb 0.07

ccc 0.10

ddd 0.05

eee 0.08

fff 0.10

Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
QFN32 Package Specifications

7.2 QFN32 PCB Land Pattern

Figure 7.2. QFN32 PCB Land Pattern Drawing

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
QFN32 Package Specifications

Table 7.2. QFN32 PCB Land Pattern Dimensions

Dimension Typ

L 0.76

W 0.22

e 0.40

S 3.21

S1 3.21

L1 2.80

W1 2.80

Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.101 mm (4 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 2x2 array of 1.10 mm x 1.10 mm openings on a 1.30 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
10. Above notes and stencil design are shared as recommendations only. A customer or user may find it necessary to use
different parameters and fine tune their SMT process as required for their application and tooling.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
QFN32 Package Specifications

7.3 QFN32 Package Marking

FFFF
PPPPPP
TTTTTT
YYWW
Figure 7.3. QFN32 Package Marking

The package marking consists of:

• FFFF – The product family codes.
1. Family Code ( B | M | F )
2. G (Gecko)
3. Series (2)
4. Device Configuration (1, 2, 3, ...)
• PPPPPP – The product option codes.
• 1-2. MCU Feature Codes
• 3-4. Radio Feature Codes
• 5. Flash (J = 1024k | I = 768k | H = 512k | W= 352k | G = 256k | F = 128k)
• 6. Temperature grade (G = -40 to 85 °C | I = -40 to 125 °C )
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.

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 EFR32BG22C112 Wireless Gecko SoC Data Sheet
Revision History

8. Revision History

Revision 1.1

June 2021

• Updated lowest energy mode for I2C0, IADC0 and EUART0 to EM3 in 3.13 Configuration Summary.
• Added footnote for crystal load capacitance with Gain=2 test condition in 4.11.2 Low Frequency Crystal Oscillator.
• Added timing specification for RESETn low time in 4.12 GPIO Pins (3V GPIO pins).
• Added IADC 16 bit typical resolution and updated footnote in 4.13 Analog to Digital Converter (IADC).
• Corrected clock reference to PCLK in 4.17 USART SPI Main Timing and 4.18 USART SPI Secondary Timing.
• Added note regarding flexible power supply connections and additional application circuit in 5.1 Power.
• Corrected by removal IADC0.VREFN pinout from 6.2 Alternate Function Table; IADC0.VREFN connected internally to ground.
• Replaced select terms with inclusive lexicon.
• Minor formatting and styling updates, including TOC locations and boilerplate information throughout document.

Revision 1.0

June, 2020

• 3.7.2 Cryptographic Accelerator: Removed text referencing DPA.

• 3.7.4 Secure Debug with Lock/Unlock: Removed text referencing Secure Element.
• 4.1 Electrical Characteristics:
• Expanded Power Supply Pin Dependencies section to include more details and restrictions on DECOUPLE.
• Finalized remaining MIN / MAX specifications according to characterization and qualification results.
• Corrected BLE Bit Error Rate conditions for sensitivity measurements with 255 byte payload.
• Added GPIO hysteresis specification.
• Updated DCDC lifetime condition guideance in 4.4.1 DC-DC Operating Limits.
• Expanded IADC descriptions to include information at higher oversampling ratios and added typical performance curve.

Revision 0.5

February, 2020

• 1. Feature List: Updated list slightly to highlight different features.

• Removed references to non-BLE radio features.
• Expanded 3.7 Security Features section and corrected security details.
• Added 3.9.2 Voltage Scaling section.
• 4.1 Electrical Characteristics:
• Additional characterization results and test limits added where available.
• Removed thermistor driver specification table until full software support becomes available.
• Removed references and sections pertaining to packages other than QFN32.
• Updated 5.2 RF Matching Networks section with recommended match values.

Revision 0.4

December, 2019

• Initial release.

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Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software imple-
menters using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each
specific device, and “Typical” parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon
Labs reserves the right to make changes without further notice to the product information, specifications, and descriptions herein, and does not give warranties as to the
accuracy or completeness of the included information. Without prior notification, Silicon Labs may update product firmware during the manufacturing process for security or
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authorized to be used within any FDA Class III devices, applications for which FDA premarket approval is required or Life Support Systems without the specific written consent
of Silicon Labs. A “Life Support System” is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in
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