ES Unit 1 QBWA
ES Unit 1 QBWA
Voice data on the line is sent in asynchronous mode. Over a telephone line the communication is
asynchronous.
Total power consumption by the system while in running, waiting and idle states should be limited.
Process Deadlines
Meeting the deadline of all processes in the system while keeping the memory, power dissipation,
processor clock rate and cost at minimum is a challenge.
Flexibility and upgrade ability
Flexibility and upgrade ability in design while keeping the cost minimum and advanced versions
of a product to be introduced in the market later on.
Reliability
Designing a reliable product by design, testing and verification is a challenge.
Verification refers to an activity to ensure that specific functions are correctly implemented.
2. Define embedded system. Explain its architecture with neat diagram. (Nov’14)
An embedded system is a system that has embedded software and computer hardware, which makes
it a system dedicated for an application or specific part of an application or product or part of a
larger system.
It is any device that includes a programmable computer but is not itself intended to be a general
purpose computer.
Program Flow and data path Control Unit (CU) —includes a fetch unit for fetching instructions
from the memory.
Execution Unit (EU) —includes circuits for arithmetic and logical unit (ALU), and for
instructions for a program control task, say, data transfer instructions, halt, Interrupt, or jump to
another set of instructions or call to another routine or sleep or reset
General purpose microprocessor
For example, Intel 80x86, Sparc, or Motorola 68HCxxx
Embedded general purpose processor
Fast context switching features, use of on-chip Compilers, for example, Intel XScale Applications
Personal Internet Client Architecture-based PDAs, cell phones and other wireless devices,
Application Specific Instruction-Set Processor (ASIP)
Microcontroller — Intel, Motorola, Hitachi, TI, Philips and ARM , for example, an Intel MCS51,
Philips 51XA, 51MX, or Motorola — 68HC11, 68HC12, 68HC16
DSP or Typically a Texas Instruments- C28xSeries, C54xx or C64xx or Analog Devices SHARC
or
Tiger SHARC, Motorola 5600xx
Media processor TI DSP TMS320DM310 or Trimedia Phillips Media Processor 1x00series for
Processing Streaming and Data Networks and Image, Video and Speech: PNX 1300, PNX
1500(2002)
IO processor or Network processor or A domain specific processor
GPP or ASIP core (s)
GPP or ASIP integrated into either an Application Specific Integrated Circuit (ASIC), or a Very
Large Scale Integrated Circuit (VLSI) circuit or a FPGA core integrated with processor unit(s) in
a VLSI (ASIC) chip
Application Specific System Processor (ASSP)
Typically a set top box processor or mpeg video-processor or network application processor or
mobile application processor
Single purpose processor or Application Specific Instruction processor
Floating point Coprocessor
Pixel coprocessor and image codec in digital camera
Graphic processor, Speech processor
Adaptive filtering processor, Communication protocol stack processor
Encryption engine, Decryption engine
Multi core processors or multiprocessor system using GPPs
Multiprocessor system for Real time performance in a video-conference system,
Embedded firewall cum router, High-end cell phone.
Hardware Elements in the Embedded Systems Power Source
System own supply with separate supply rails for IOs, clock, basic processor and memory and
analog units
Supply from a system to which the embedded system interfaces, for example in a network card,
Charge pump concept used in a system of little power needs, for examples, in the mouse or
contact- less smart card.
Power Dissipation Management
Clever real-time programming by Wait and Stop instructions
Clever reduction of the clock rate during specific set of instructions
Optimizing the codes and
Clever enabling and disabling of use of caches or cache blocks
Clock Oscillator Circuit and Clocking Units
Appropriate clock oscillator circuit
Real Time Clock (System Clock) and Timers driving hardware and software
Reset Circuit
Reset on Power-up
External and Internal Reset circuit
Reset on Timeout of Watchdog timer
Memory
a. Functions Assigned to the ROM or EPROM or Flash
Storing 'Application' program from where the processor fetches the instruction codes
Storing codes for system booting, initializing, initial input data and Strings.
Storing Codes for RTOS.
Storing Pointers (addresses) of various service routines.
b. Functions Assigned to the Internal, External and Buffer RAM
Storing the variables during program run,
Storing the stacks,
Storing input or output buffers for example, for speech or image
c. Functions Assigned to the EEPROM or Flash
Storing non-volatile results of processing
d. Functions Assigned to the Caches
Storing copies of the instructions, data and branch-transfer instructions in advance from external
memories
Storing temporarily the results in write back caches during fast processing
Interrupts Handler
Interrupt Handling element for the external port interrupts, IO interrupts, timer and
RTC interrupts, software interrupts and Exceptions
Linking Embedded System Hardware
Linking and interfacing circuit for the Buses by using the appropriate multiplexers, and decoders,
demultiplexers Interface the various system units
3. Elaborate in detail about Very Large Instruction Word (VLIW) Architecture. (Nov’14)
The new architecture that has attracted a great deal of attention in the DSP community is the Very
Long Instruction Word (VLIW).
The very long instruction word processing increases the number of instructions processed per cycle.
It is essentially a concatenation of several short instructions and requires multiple execution units,
running in parallel, to carry out the instructions in a single cycle.
The new architecture makes use of extensive parallelism whilst retaining some of the good features
of previous DSP processors. VLIW architecture executes multiple instructions/cycle and use
simple, regular instruction sets.
The very long instruction word processor consists of architecture that reads a relatively large group
of instructions and executes them at the same time.
The VLIW processor combines many simple instructions into a single long instruction word that
uses different registers.
A language complier or pre-processor separates program instructions into basic operations that are
performed by the processor in parallel.
These ope rati ons ar e pl aced int o a “ve r y lon g inst ructi on word” that the
processor can then disassemble, and then transfer each operation to an appropriate execution unit.
For example, the group might contain four instructions are not dependent on each other so they can
be executed simultaneously.
IF – Instruction Fetch
ID – Instruction Decode
EX - Execute
MEM – Memory Access
WB – Write Back
There are several ways to achieve performance: technology advances, better machine organization,
better architecture, and also the optimization and improvements in compiler technology.
By technology, machine performance can be enhanced only in proportion to the amount
of technology improvements and this is, more or less, available to everyone.
It is in the machine organization and the machine architecture where the skills and experience of
computer design are shown. RISC deals with these two levels - more precisely their interaction and
trade-off.
Typically the instruction execution time is divided in five stages, machine cycles, and as soon as
processing of one stage is finished, the machine proceeds with executing the second stage.
However, when the stage becomes free it is used to execute the same operation that belongs to the
next instruction.
The operation of the instructions is performed in a pipeline fashion, similar to the assembly line in
the factory process.
6. Describe in detail about three ways of communication.
Synchronous Communication
When a byte (character) or frame (a collection of bytes) of data is received or transmitted at
constant time intervals with uniform phase differences, the communication is called synchronous.
Bits of a data frame are sent in a fixed maximum time interval. Iso-synchronous is a special case
when the maximum time interval can be varied.
Two characteristics of synchronous communication are as follows:
Bytes (or frames) maintain a constant phase difference. It means they are synchronous, that is,
in synchronization. There is no permission for sending either bytes or the frames at random
time intervals; this mode therefore does not provide for handshaking during the
communication interval. The master is the one whose clock pulses guide the transmission and
slave is the one which synchronizes the bits as per the master clock.
A clock ticking at a certain rate must always be there to serially transmit the bits of all the
bytes. The clock is not always implicit to the synchronous data receiver. The transmitter
generally transmits the clock rate information in the synchronous communication of the data.
There are two separate lines for the data bits and clock. The parallel-in serial-out (PISO) and serial-
in parallel-out (SIPO) are used for transmitting and receiving the signals for data, respectively.
There is a common line and the clock information is encoded by modulating the clock with the
stream of bits. There are preceding and succeeding additional synchronizing and signalling bits.
There are five common methods of encoding the clock information into a serial stream of the bits:
Frequency Modulation (FM)
Manchester coding