INTEGRATED CIRCUITS

DATA SHEET

TDA8366
I2C-bus controlled PAL/NTSC TV
processor
Objective specification January 1995
File under Integrated Circuits, IC02

Philips Semiconductors
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

FEATURES
• Multistandard vision IF circuit (positive and
negative modulation)
• Video identification circuit in the IF circuit which is
independent of the synchronization for stable On Screen
Display (OSD) under ‘no-signal’ conditions
• Source selection with 2 Colour Video Blanking GENERAL DESCRIPTION
Synchronization (CVBS) inputs and a Y/C (or extra
The TDA8366 is an I2C-bus controlled PAL/NTSC TV
CVBS) input
processor. The circuit has been designed for use with the
• Output signals of the video switch circuit for the teletext baseband chrominance delay line TDA4665 and for
decoder and a Picture-In-Picture (PIP) processor DC-coupled vertical and East-West (EW) output stages.
• Integrated chrominance trap and bandpass filters
The device can process both CVBS and Y/C input signals
(automatically calibrated)
and has a linear RGB-input with fast blanking.
• Integrated luminance delay line
The peaking circuit generates asymmetrical overshoots
• Asymmetrical peaking in the luminance channel with a
(the amplitude of the ‘black’ overshoots is approximately
(defeatable) noise coring function
2 times higher as the one of the ‘white’ overshoots) and
• PAL/NTSC colour decoder with automatic search contains a (defeatable) coring function.
system
The RGB control circuit contains a black-current stabilizer
• Easy interfacing with the TDA8395 (SECAM decoder) circuit with internal clamp capacitors. The white point of the
for multistandard applications picture tube is adjusted via the I2C-bus.
• RGB control circuit with black-current stabilization and
The deflection control circuit provides a drive pulse for the
white point adjustment; to obtain a good grey scale
horizontal output stage, a differential sawtooth current for
tracking the black-current ratio of the 3 guns depends on
the vertical output stage and an East-West drive current for
the white point adjustment
the East-West output stage.These signals can be
• Linear RGB inputs and fast blanking manipulated for geometry correction of the picture.
• Horizontal synchronization with two control loops and The supply voltage for the IC is 8 V. The IC is available in
alignment-free horizontal oscillator an SDIP package with 52 pins and in a QFP package with
• Vertical count-down circuit 64 pins (see Chapter “Ordering information”).
• Geometry correction by means of modulation of the The pin numbers indicated in this document are
vertical and EW drive referenced to the SDIP52; SOT247-1 package; unless
• I2C-bus control of various functions otherwise indicated.
• Low dissipation (850 mW)
• Small amount of peripheral components compared with
competition ICs
• Only one adjustment (vision IF demodulator)
• Y, U and V inputs and outputs.

January 1995 2
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

ORDERING INFORMATION

PACKAGE
TYPE NUMBER
NAME DESCRIPTION VERSION
TDA8366 SDIP52 plastic shrink dual in-line package; 52 leads (600 mil) SOT247-1
TDA8366H QFP64(1) plastic quad flat package; 64 leads (lead length 1.95 mm); SOT319-2
body 14 × 20 × 2.8 mm
Note
1. When using IR reflow soldering it is recommended that the Drypack instructions in the “Quality Reference Handbook”
(order number 9398 510 63011) are followed.

QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Supply
VP supply voltage − 8.0 − V
IP supply current − 100 − mA
Input voltages
V46,47(rms) video IF amplifier sensitivity (RMS value) − 70 − µV
V15(p-p) external CVBS input (peak-to-peak value) − 1.0 − V
V9(p-p) S-VHS luminance input voltage (peak-to-peak value) − 1.0 − V
V8(p-p) S-VHS chroma input voltage (burst amplitude) − 0.3 − V
(peak-to-peak value)
V21,22,23(p-p) RGB inputs (peak-to-peak value) − 0.7 − V
Output signals
Vo(p-p) demodulated CVBS output (peak-to-peak value) − 2.5 − V
I52 tuner AGC output current range 0 − 5 mA
V36(p-p) TXT output voltage (peak-to-peak value) − 1.0 − V
V13(p-p) PIP output voltage (peak-to-peak value) − 1.0 − V
V28(p-p) −(R−Y) output voltage (peak-to-peak value) − 525 − mV
V27(p-p) −(B−Y) output voltage (peak-to-peak value) − 675 − mV
V26 Y output voltage − 450 − mV
V19,18,17(p-p) RGB output signal amplitudes (peak-to-peak value) − 2.0 − V
I38 horizontal output current 10 − − mA
I44,45 vertical output current 1 − − mA
I43 EW drive output current 0.5 − − mA

January 1995 3
January 1995
PH1LF
DEC DIG
FBI
processor
DEC BG PH2LF
SCO

BLOCK DIAGRAM
VP2 ( 8 V)

V P1 ( 8 V) SCL SDA HOUT

Philips Semiconductors

10 35 5 6 41 7 3 40 39 37 38
AGCOUT 52
(TUNER) TOP 2 VCO 2nd LOOP AND 43
AGC FOR IF I C-BUS
51 AND ref HORIZONTAL EW GEOMETRY EWD
AND TUNER TRANSCEIVER
CONTROL OUTPUT
DEC AGC 48
POL EHTO
47 44
IFIN2 CONTROL DACs SYNC HORIZONTAL/
IF AMPLIFIER VERTICAL VDR (pos)
46 17 x 6 bits SEPARATOR VERTICAL 45
IFIN1 AND DEMODULATOR GEOMETRY
2 x 4 bits AND 1st LOOP DIVIDER VDR (neg)
IFDEM2 2 49
POL VSC
50
I ref

1 TDA8366 VERTICAL BLACK

I2C-bus controlled PAL/NTSC TV

VIDEO 16
IFDEM1 SYNC CURRENT BLKIN
AMPLIFIER
SEPARATOR WHITE STABILIZER
AFC AND
SAMPLE AND HOLD MUTE POINT BRI CONTR 20
ref BCLIN

4
19
IDENT DELAY RGB MATRIX RO
AFC FILTER 18
VIDEO MUTE TRAP BANDPASS AND AND GO
TUNING 17
PEAKING OUTPUT BO
VIDEO
IDENTIFICATION SW
SW SAT
HUE
G-Y MATRIX RGB INPUT
PAL/NTSC
CVBS - SWITCH S-VHS - SWITCH AND AND
DECODER
SAT CONTROL SWITCH
12 42 4 11 15 8 9 13 36 14 31 34 33 32 28 27 30 29 26 25 21 22 23 24 MLA745 - 1

GND1 GND2 IFVO CVBS INT DEC FT DET

RYO BYO RYI BYI RI GI BI
CVBS EXT PIPO
4.4 3.6 LUMIN RGBIN
SOUND CHROMA CVBS/TXT MHz MHz
TRAP TDA4661 LUMOUT
CVBS/Y
SEC ref XTAL2 XTAL1

handbook, full pagewidth

TDA8366

Fig.1 Block diagram (SDIP52; SOT247-1).

Objective specification
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

PINNING

PIN
SYMBOL DESCRIPTION
SDIP52 QFP64
IFDEM1 1 11 IF demodulator tuned circuit 1
IFDEM2 2 12 IF demodulator tuned circuit 2
DECDIG 3 13 decoupling digital supply
IFVO 4 14 IF video output
SCL 5 16 serial clock input
SDA 6 17 serial data input/output
DECBG 7 18 bandgap decoupling
CHROMA 8 20 chrominance input (S-VHS)
CVBS/Y 9 21 external CVBS/Y input
VP1 10 22 main supply voltage 1 (+8 V)
CVBSINT 11 29 internal CVBS input
GND1 12 25 ground 1
PIPO 13 27 picture-in-picture output
DECFT 14 28 decoupling filter tuning
CVBSEXT 15 24 external CVBS input
BLKIN 16 30 black-current input
BO 17 31 blue output
GO 18 32 green output
RO 19 33 red output
BCLIN 20 35 beam current limiter input
RI 21 37 red input for insertion
GI 22 38 green input for insertion
BI 23 39 blue input for insertion
RGBIN 24 40 RGB insertion input
LUMIN 25 42 luminance input
LUMOUT 26 43 luminance output
BYO 27 44 (B−Y) signal output
RYO 28 45 (R−Y) signal output
BYI 29 46 (B−Y) signal input
RYI 30 47 (R−Y) signal input
SECref 31 48 SECAM reference output
XTAL1 32 49 3.58 MHz crystal connection
XTAL2 33 50 4.43/3.58 MHz crystal connection
DET 34 52 loop filter phase detector
VP2 35 54 horizontal oscillator supply voltage (+8 V)
CVBS/TXT 36 55 CVBS/TXT output
SCO 37 56 sandcastle output
HOUT 38 57 horizontal output

January 1995 5
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

PIN
SYMBOL DESCRIPTION
SDIP52 QFP64
FBI 39 58 flyback input
PH2LF 40 59 phase-2 filter
PH1LF 41 60 phase-1 filter
GND2 42 26 ground 2
EWD 43 63 east-west drive output
VDR(pos) 44 64 vertical drive 1 positive output
VDR(neg) 45 1 vertical drive 2 negative output
IFIN1 46 2 IF input 1
IFIN2 47 3 IF input 2
EHTO 48 4 EHT/overvoltage protection input
VSC 49 5 vertical sawtooth capacitor
Iref 50 6 reference current input
DECAGC 51 7 AGC decoupling capacitor
AGCOUT 52 8 tuner AGC output
n.c. − 9 not connected
n.c. − 10 not connected
n.c. − 15 not connected
n.c. − 19 not connected
n.c. − 34 not connected
n.c. − 36 not connected
n.c. − 41 not connected
n.c. − 51 not connected
n.c. − 53 not connected
VP3 − 23 supply voltage 3 (+8 V)
GND3 − 61 ground 3
GND4 − 62 ground 4

The pin numbers mentioned in the rest of this document are referenced to the SDIP52 (SOT247-1) package.

January 1995 6
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

handbook, halfpage
IFDEM1 1 52 AGCOUT

IFDEM2 2 51 DEC AGC

DEC DIG 3 50 I ref

IFVO 4 49 VSC

SCL 5 48 EHTO

SDA 6 47 IFIN2

DEC BG 7 46 IFIN1

CHROMA 8 45 VDR (neg)

CVBS/Y 9 44 VDR(pos)

V P1 10 43 EWD

CVBS INT 11 42 GND2

GND1 12 41 PH1LF

PIPO 13 40 PH2LF
TDA8366
DEC FT 14 39 FBI

CVBS EXT 15 38 HOUT

BLKIN 16 37 SCO

BO 17 36 CVBS/TXT

GO 18 35 VP2

RO 19 34 DET

BCLIN 20 33 XTAL2

RI 21 32 XTAL1

GI 22 31 SEC ref

BI 23 30 RYI

RGBIN 24 29 BYI

LUMIN 25 28 RYO

LUMOUT 26 27 BYO

MLA737 - 1

Fig.2 Pin configuration (SDIP52).

January 1995 7
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

55 CVBS/TXT
64 VDR(pos)

60 PH1LF

59 PH2LF

57 HOUT
62 GND4

61 GND3
63 EWD

56 SCO

52 DET
handbook, full pagewidth

54 VP2

53 n.c.
58 FBI
VDR (neg) 1 51 n.c.

IFIN1 2 50 XTAL2

IFIN2 3 49 XTAL1

EHTO 4 48 SEC ref

VSC 5 47 RYI

I ref 6 46 BYI

DECAGC 7 45 RYO

AGCOUT 8 44 BYO

n.c. 9 43 LUMOUT

n.c. 10 TDA8366H 42 LUMIN

IFDEM1 11 41 n.c.

IFDEM2 12 40 RGBIN

DEC DIG 13 39 BI

IFVO 14 38 GI

n.c. 15 37 RI

SCL 16 36 n.c.

SDA 17 35 BCLIN

DEC BG 18 34 n.c.

n.c. 19 33 RO
CHROMA 20

CVBS/Y 21

V P1 22

VP3 23

CVBS EXT 24

GND1 25

GND2 26

PIPO 27

DEC FT 28

CVBS INT 29

BLKIN 30

BO 31

GO 32

MLC756

Fig.3 Pin configuration (QFP64).

January 1995 8
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

FUNCTIONAL DESCRIPTION Synchronization circuit

Vision IF amplifier The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
The IF-amplifier contains 3 AC-coupled control stages with
These pulses are fed to the slicing stage which is operating
a total gain control range which is in excess of 66 dB. The
at 50% of the amplitude.
sensitivity of the circuit is comparable with that of modern
IF-ICs. The reference carrier for the video demodulator is The separated sync pulses are fed to the first phase
obtained by means of passive regeneration of the picture detector and to the coincidence detector. This coincidence
carrier. The external reference tuned circuit is the only detector is only used to detect whether the line oscillator is
remaining adjustment of the IC. synchronized and not for transmitter identification. The first
Phase-Locked Loop (PLL) has a very high-statical
The polarity of the demodulator can be switched via the
steepness so that the phase of the picture is independent
I2C-bus in such a way that the circuit is suitable for both
of the line frequency.
positive and negative modulated signals.
The line oscillator is running at twice the line frequency.
The AFC-circuit is driven with the same reference signal as
The oscillator capacitor is internal. Because of the spreads
the video demodulator. To avoid that the video content
of internal components an automatic adjustment circuit
disturbs the AFC operation a sample-and-hold circuit is
has been added to the IC. It compares the oscillator
applied for signals with negative modulation. The capacitor
frequency with that of the crystal oscillator in the colour
for this function is internal. The AFC information is supplied
decoder.
to the tuning system via the I2C-bus.
To protect the horizontal output transistor the horizontal
The AGC-detector operates on top-sync or top white-level
drive is switched-off when a power-on-reset is detected.
depending on the polarity of the demodulator. The
The frequency of the oscillator is calibrated again when all
demodulation polarity is switched via the I2C-bus. The
subaddress bytes have been sent. When the oscillator has
AGC detector time-constant capacitor is connected
the right frequency the calibration stops and the horizontal
externally (this mainly because of the flexibility of the
drive is switched-on again via the soft start procedure
application). The time-constant of the AGC system during
(standby bit in normal mode). When the IC is switched-on
positive modulation is rather long to avoid visible variations
the same procedure is followed.
of the signal amplitude. To obtain an acceptable speed of
the AGC system a circuit has been included which detects When the coincidence detector indicates an out-of-lock
whether the AGC detector is activated every frame period. situation the calibration procedure is repeated.
When during 3 frame periods no action is detected the
The circuit has a second control loop to generate the drive
speed of the system is increased.
pulses for the horizontal driver stage. During the start-up
The circuit contains a video identification circuit which is procedure the duty cycle of the horizontal output pulse
independent of the synchronization circuit. Therefore increases from 0 to 50% in approximately 100 lines.
search tuning is possible when the display section of the
The vertical sawtooth generator drives the vertical output
receiver is used as a monitor. The identification output is
and EW correction drive circuits. The geometry processing
supplied to the tuning system via the I2C-bus. The
circuits provide control of horizontal shift, EW width, EW
information of this identification circuit can also be used to
parabola/width ratio, EW corner/parabola ratio, trapezium
switch the phase-1 (ϕ1) loop to a low gain when no signal
correction, vertical shift, vertical slope, vertical amplitude,
is received so that a stable OSD display is obtained. The
and the S-correction. All these controls can be set via the
coupling of the video identification circuit with the ϕ1 loop
I2C-bus. The geometry processor has a differential current
can be switched on and off via the I2C-bus.

January 1995 9
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

output for the vertical drive signal and a single-ended Video switches
output for the EW drive. Both the vertical drive and the EW
The circuit has two CVBS inputs and an Super-Video
drive outputs can be modulated for EHT compensation.
Home System (S-VHS) input. The input can be chosen by
The EHT compensation pin is also used for overvoltage
the I2C-bus. The input selector also has a position in which
protection.
CVBSEXT is processed, unless there is a signal on the
The geometry processor also offers the possibilities for S-VHS input. When the input selector is in this position it
vertical compression (for display of 16 : 9 pictures on a switches to the S-VHS input if the S-VHS detector detects
4 : 3 screen) and vertical expansion (for display of sync pulses on the S-VHS luminance input. The S-VHS
4 : 3 pictures on a 16 : 9 screen with full picture width, or detector output can be read by the I2C-bus. When the
for display of ‘letter-box’ transmissions on a 4 : 3 screen S-VHS option is not used the luminance input can be used
with full picture height). For the expand mode it is possible as a second input for external CVBS signals. The choice is
to shift the picture vertically (only one fixed position). made via the CVS-bit (see Table 1).
Also the de-interlace of the vertical output can be set via The video switch circuit has two outputs which can be
the I2C-bus. programmed in a different way. The input signal for the
decoder is also available on the TXT output. Therefore this
To avoid damage of the picture tube when the vertical
signal can be used to drive the teletext decoder and the
deflection fails the guard output current of the TDA8350
SECAM add-on decoder. The signal on the PIP output can
can be supplied to the sandcastle output. When a failure is
be chosen independent of the TXT output. If S-VHS is
detected the RGB-outputs are blanked and a bit is set
selected for one of the outputs the luminance and
(NDF) in the status byte of the I2C-bus. When no vertical
chrominance signals are added so that a CVBS signal is
deflection output stage is connected this guard circuit will
obtained again.
also blank the output signals. This can be overruled by
means of the EVG bit of subaddress 0A (see Table 1).
Colour decoder
Integrated video filters The colour decoder contains an alignment-free crystal
oscillator, a killer circuit and the colour difference
The circuit contains a chrominance bandpass and trap
demodulators. The 90° phase shift for the reference signal
circuit. The chrominance trap filter in the luminance path is
is made internally. The demodulation angle and gain ratio
designed for a symmetrical step response behaviour. The
for the colour difference signals for PAL and NTSC are
filters are realized by means of gyrator circuits and they
adapted to the standard.
are automatically tuned by comparing the tuning frequency
with the crystal frequency of the decoder. The luminance The colour decoder is very flexible. Together with the
delay line and the delay for the peaking circuit are also SECAM decoder TDA8395 an automatic multistandard
realized by means of gyrator circuits. decoder can be designed.
It is possible to connect a Colour Transient Improvement Which standard the IC can decode depends on the
(CTI) or Picture Signal Improvement (PSI) IC to the external crystals. If a 4.4 MHz and a 3.5 MHz crystal are
TDA8366. Therefore the luminance signal which has used PAL 4.4, NTSC 4.4, NTSC 3.5 and PAL 3.5 can be
passed the filter and delay line circuit is externally decoded. If two 3.5 MHz crystals are used PAL N and M
available. The output signal of the transient improvement can be decoded. If one crystal is connected only
circuit must be supplied to the luminance input circuit. PAL/NTSC 4.4 or PAL/NTSC 3.5 can be decoded. The
When the CTI function is not required the two pins must be crystal frequency of the decoder is used to tune the line
AC-coupled. oscillator. Therefore the value of the crystal frequency
must be given to the IC via the I2C-bus.

January 1995 10
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

RGB output circuit and black-current stabilization visible on the screen. As soon as the current supplied to
the measuring input exceeds a value of 190 µA the
The colour-difference signals are matrixed with the
stabilization circuit is activated. After a waiting time of
luminance signal to obtain the RGB-signals. For the
approximately 0.8 s the blanking and the beam current
RGB-inputs linear amplifiers have been chosen so that the
limiting input pin are released. The remaining switch-on
circuit is suited for signals coming from the SCART
behaviour of the picture is determined by the external time
connector. The contrast and brightness control operate on
constant of the beam current limiting network.
internal and external signals.
The output signal has an amplitude of approximately 2 V
I2C-BUS SPECIFICATION
black-to-white at nominal input signals and nominal
settings of the controls.
The black current stabilization is realized by means of a handbook, halfpage
A6 A5 A4 A3 A2 A1 A0 R/W
feedback from the video output amplifiers to the RGB
control circuit. The ‘black current’ of the 3 guns of the 1 0 0 0 1 0 1 1/0
picture tube is internally measured and stabilized. The
MLA743
black level control is active during 4 lines at the end of the
vertical blanking. During the first line the leakage current is X = don’t care.
measured and the following 3 lines the 3 guns are
Fig.4 Slave address (8A).
adjusted to the required level. The maximum acceptable
leakage current is ±100 µA. The nominal value of the
‘black current’ is 10 µA. The ratio of the currents for the
various guns automatically tracks with the white point Valid subaddresses: 00 to 13; subaddress FE is reserved
adjustment so that the back-ground colour is the same as for test purposes. Auto-increment mode is available for
the adjusted white point. subaddresses.

The input impedance of the ‘black-current’ measuring pin Start-up procedure

is 15 kΩ. Therefore the beam current during scan will
cause the input voltage to exceed the supply voltage. The Read the status bytes until POR = 0 and send all
internal protection will start conducting so that the subaddress bytes. The horizontal output signal is
excessive current is bypassed. switched-on when the oscillator is calibrated. It is possible
to have the horizontal output signal available before
When the TV receiver is switched-on the black current calibration. Then the SFM bit must be set to logic 0.
stabilization circuit is not active, the RGB outputs are
blanked and beam current limiting input pin is Each time before the data in the IC is refreshed, the status
short-circuited. Only during the measuring lines will the bytes must be read. If POR = 1, the procedure mentioned
outputs supply a voltage of 5 V to the video output stage above must be carried out to restart the IC.
so that it can be detected if the picture tube is warming up. When this procedure is not followed the horizontal
These pulses are switched-on after a waiting time of frequency may be incorrect after power-up or after a
approximately 0.5 s. This ensures that the vertical power dip.
deflection is activated so that the measuring pulses are not

January 1995 11
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

Inputs
Table 1 Input status bits; note 1

SUBADDRESS DATA BYTE

FUNCTION
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Source select 00 INA INB INC IND FOA FOB XA XB
Decoder mode 01 FORF FORS DL STB POC CM2 CM1 CM0
Hue 02 X X A5 A4 A3 A2 A1 A0
Horizontal shift (HS) 03 X X A5 A4 A3 A2 A1 A0
EW width (EW) 04 X X A5 A4 A3 A2 A1 A0
EW parabola/width (PW) 05 X X A5 A4 A3 A2 A1 A0
EW corner parabola (CP) 06 X X A5 A4 A3 A2 A1 A0
EW trapezium (TC) 07 X X A5 A4 A3 A2 A1 A0
Vertical slope (VS) 08 NCIN X A5 A4 A3 A2 A1 A0
Vertical amplitude (VA) 09 VID LBM A5 A4 A3 A2 A1 A0
S-correction (SC) 0A HCO EVG A5 A4 A3 A2 A1 A0
Vertical shift (VSH) 0B SBL PRD A5 A4 A3 A2 A1 A0
White point R 0C EXP CL A5 A4 A3 A2 A1 A0
White point G 0D SFM CVS A5 A4 A3 A2 A1 A0
White point B 0E MAT PHL A5 A4 A3 A2 A1 A0
Peaking 0F YD3 YD2 YD1 YD0 A3 A2 A1 A0
Brightness 10 RBL COR A5 A4 A3 A2 A1 A0
Saturation 11 IE1 X A5 A4 A3 A2 A1 A0
Contrast 12 AFW IFS A5 A4 A3 A2 A1 A0
AGC take-over 13 MOD VSW A5 A4 A3 A2 A1 A0

Note
1. X = don’t care.

Table 2 Output status bits; note 1

SUBADDRESS DATA BYTE

FUNCTION
(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Output status bytes 00 POR FSI STS SL XPR CD2 CD1 CD0
01 NDF IN1 X IFI AFA AFB X X

Note
1. X = don’t care.

January 1995 12
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

INPUT CONTROL BITS Table 7 Forced field frequency

Table 3 Source select 1 FORF FORS FIELD FREQUENCY
INA INB DECODER AND TXT 0 0 auto (60 Hz when line not
synchronized)
0 0 CVBSINT
0 1 60 Hz; note 1
0 1 CVBSEXT
1 0 50 Hz; note 1
1 0 S-VHS
1 1 auto (50 Hz when line not
1 1 S-VHS (CVBSEXT)
synchronized)

Table 4 Source select 2 Note

INC IND PIP 1. When the forced mode is selected the divider will only
switch to that position when the horizontal oscillator is
0 0 CVBSINT not synchronized.
0 1 CVBSEXT
1 0 S-VHS Table 8 Interlace
1 1 S-VHS (CVBSEXT) DL STATUS
0 interlace
Table 5 Phase 1 (ϕ1) time constant
1 de-interlace
FOA FOB(1) MODE
0 0 normal Table 9 Standby
0 1 slow STB MODE
1 X fast 0 standby
Note 1 normal
1. X = don’t care.
Table 10 Synchronization mode
Table 6 Crystal indication POC MODE
XA XB CRYSTAL 0 active
0 0 two 3.6 MHz 1 not active
0 1 one 3.6 MHz (pin 32)
Table 11 Colour decoder mode
1 0 one 4.4 MHz (pin 33)
1 1 3.6 MHz (pin 32) and 4.4 MHz CM2 CM1 CM0 DECODER MODE
(pin 33) 0 0 0 not forced, own intelligence
0 0 1 forced NTSC 3.6 MHz
0 1 0 forced PAL 4.4 MHz
0 1 1 forced SECAM
1 0 0 forced NTSC 4.4 MHz
1 0 1 forced PAL 3.6 MHz (pin 32)
1 1 0 forced PAL 3.6 MHz (pin 33)
1 1 1 no function

January 1995 13
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

Table 12 Vertical divider mode Table 20 Horizontal frequency during switch-on

NCIN VERTICAL DIVIDER MODE SFM START-UP FREQUENCY

0 normal operation 0 maximum
1 switched to search window 1 nominal

Table 13 Video ident mode Table 21 Condition Y/C input

VID VIDEO IDENT MODE CVS Y-INPUT MODE

0 ϕ1 loop switched on and off 0 switched to Y/C mode
1 not active 1 switched to CVBS mode

Table 14 Long blanking mode Table 22 PAL/NTSC matrix

LBM BLANKING MODE MAT MATRIX
0 adapted to standard (50 or 60 Hz) 0 adapted to standard
1 fixed in accordance with 50 Hz standard 1 PAL

Table 15 EHT tracking mode Table 23 Colour crystal PLL

HCO TRACKING MODE PHL STATE
0 EHT tracking only on vertical 0 PLL closed
1 EHT tracking on vertical and EW 1 oscillator free-running

Table 16 Enable vertical guard (RGB blanking) Table 24 Y-delay adjustment; note 1
EVG VERTICAL GUARD MODE YD0 to YD3 Y-DELAY
0 not active YD3 YD3 ∗ 160 ns +
1 active YD2 YD2 ∗ 80 ns +
YD1 YD1 ∗ 40 ns +
Table 17 Service blanking YD0 YD0 ∗ 40 ns
SBL SERVICE BLANKING MODE
Note
0 off 1. For an equal delay of the luminance and chrominance
1 on signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
Table 18 Overvoltage input mode delay distortions.

PRD OVERVOLTAGE MODE

Table 25 RGB blanking
0 detection mode
RBL RGB BLANKING
1 protection mode
0 not active
Table 19 Vertical deflection mode 1 active

EXP CL VERTICAL DEFLECTION MODE

Table 26 Noise coring (peaking)
0 0 normal
COR NOISE CORING
0 1 compress
0 off
1 0 expand
1 on
1 1 expand and lift

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

Table 27 Enable fast blanking Table 35 Phase 1 (ϕ1) lock indication

IE1 FAST BLANKING SL INDICATION
0 not active 0 not locked
1 active 1 locked

Table 28 AFC window Table 36 X-ray protection

AFW AFC WINDOW XPR OVERVOLTAGE
0 normal 0 no overvoltage detected
1 enlarged 1 overvoltage detected

Table 29 IF sensitivity Table 37 Colour decoder mode

IFS IF SENSITIVITY CD2 CD1 CD0 STANDARD
0 normal 0 0 0 no colour standard identified
1 reduced 0 0 1 NTSC 3.6 MHz
0 1 0 PAL 4.4 MHz
Table 30 Modulation standard
0 1 1 SECAM
MOD MODULATION 1 0 0 NTSC 4.4 MHz
0 negative 1 0 1 PAL 3.6 MHz (pin 32)
1 positive 1 1 0 PAL 3.6 MHz (pin 33)
1 1 1 spare
Table 31 Video mute
VSW STATE Table 38 Output vertical guard

0 normal operation NDF VERTICAL OUTPUT STAGE

1 IF-video signal switched off 0 OK
1 failure
OUTPUT CONTROL BITS
Table 32 Power-on-reset Table 39 Indication RGB insertion

POR MODE IN1 RGB INSERTION

0 normal 0 no (pin 24 LOW)

1 power-down 1 yes (pin 24 HIGH)

Table 33 Field frequency indication Table 40 Output video identification

FSI FREQUENCY IFI VIDEO SIGNAL

0 50 Hz 0 no video signal identified

1 60 Hz 1 video signal identified

Table 34 S-VHS status

STS S-VHS INPUT

0 no signal
1 signal

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

Table 41 AFC output

AFA AFB CONDITION

0 0 outside window; too low
0 1 outside window; too high
1 0 in window; below reference
1 1 in window; above reference

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VP supply voltage − 9.0 V
Tstg storage temperature −25 +150 °C
Tamb operating ambient temperature 0 70 °C
Tsol soldering temperature for 5 s − 260 °C
Tj operating junction temperature − 150 °C
Ves electrostatic handling HBM; all pins; notes 1 and 2 −2000 +2000 V
MM; all pins; notes 1 and 3 −200 +200 V

Notes
1. All pins are protected against ESD by means of internal clamping diodes.
2. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.
3. Machine Model (MM): R = 0 Ω; C = 200 pF.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air
SDIP52 40 K/W
QFP64 50 K/W

QUALITY SPECIFICATION Following pins do not meet the above specification:

In accordance with “SNW-FQ-611E”. The number of the Pin 7: −90 mA
quality specification can be found in the “Quality Pin 17: 90 mA
Reference Handbook”. The handbook can be ordered Pin 18: 90 mA
using the code 9398 510 63011.
Pin 19: 90 mA
Latch-up Pin 24: −90 mA
• Itrigger ≥ 100 mA or ≥1.5VDD(max) Pin 34: 60 mA
• Itrigger ≤ −100 mA or ≤−0.5VDD(max). Pin 49: −90 mA
Pin 50: ±90 mA.

January 1995 16
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

CHARACTERISTICS
VP = 8 V; Tamb = 25 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies
MAIN SUPPLY (PIN 10)
VP1 supply voltage 7.2 8.0 8.8 V
IP1 supply current − 100 − mA
Ptot total power dissipation − 850 − W
HORIZONTAL OSCILLATOR SUPPLY (PIN 35)
VP2 supply voltage 7.2 8.0 8.8 V
IP2 supply current − 6 − mA
IF circuit
VISION IF AMPLIFIER INPUTS (PINS 46 AND 47)
Vi(rms) input sensitivity (RMS value) note 1
fi = 38.90 MHz − 70 100 µV
fi = 45.75 MHz − 70 100 µV
fi = 58.75 MHz − 70 100 µV
RI input resistance (differential) note 2 − 2 − kΩ
CI input capacitance (differential) note 2 − 3 − pF
Gcr gain control range 64 − − dB
Vi max(rms) maximum input signal 100 150 − mV
(RMS value)
VIDEO AMPLIFIER OUTPUT (PIN 4); note 3
Vo zero signal output level negative modulation; note 4 − 4.7 − V
positive modulation; note 4 − 2.0 − V
V4 top sync level negative modulation 1.9 2.0 2.1 V
V4 white level positive modulation − 4.5 − V
∆V4 difference in amplitude between − 0 15 %
negative and positive
modulation
Zo video output impedance − 50 − Ω
Ibias internal bias current of NPN 1.0 − − mA
emitter follower output transistor
Isource(max) maximum source current − − 5 mA
B bandwidth of demodulated at −3 dB 6 9 − MHz
output signal
Gdiff differential gain note 5 − 2 5 %
ϕdiff differential phase notes 5 and 6 − − 5 deg
NLvid video non-linearity note 7 − − 5 %
Vth white spot threshold level − 5.0 − V
Vins white spot insertion level − 3.3 − V

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VIDEO AMPLIFIER OUTPUT (CONTINUED)
Nclamp noise inverter clamping level − 1.4 − V
Nins noise inverter insertion level − 2.6 − V
(identical to black level)
δmod intermodulation notes 6 and 8
blue Vo = 0.92 or 1.1 MHz 60 66 − dB
Vo = 2.66 or 3.3 MHz 60 66 − dB
yellow Vo = 0.92 or 1.1 MHz 56 62 − dB
Vo = 2.66 or 3.3 MHz 60 66 − dB
S/N signal-to-noise ratio notes 6 and 9
Vi = 10 mV 52 60 − dB
end of control range 52 61 − dB
V4 residual carrier signal note 6 − 5.5 − mV
V4 residual 2nd harmonic of carrier note 6 − 2.5 − mV
signal
IF AND TUNER AGC; note 10
timing of IF-AGC with a 2.2 µF capacitor (pin 51)
modulated video interference 30% AM for 1 mV to 100 mV; − − 10 %
0 to 200 Hz (system B/G)
tinc response time to an IF input positive and negative − 2 − ms
signal amplitude increase of modulation
52 dB
tdec response to an IF input signal negative modulation − 50 − ms
amplitude decrease of 52 dB positive modulation − 100 − ms
IL allowed leakage current of the negative modulation − − 10 µA
AGC capacitor positive modulation − − 200 nA
Tuner take-over adjustment (via I2C-bus)
V51min(rms) minimum starting level for tuner − 0.4 0.8 mV
take-over (RMS value)
V51max(rms) maximum starting level for tuner 40 80 − mV
take-over (RMS value)
Tuner control output (pin 52)
V52max maximum tuner AGC output maximum tuner gain; note 2 − − VP + 1 V
voltage
V52(sat) output saturation voltage minimum tuner gain; − − 300 mV
I47 = 2 mA
I52max maximum tuner AGC output 5 − − mA
swing
IL leakage current RF AGC − − 1 µA
∆Vi input signal variation for 0.5 2 4 dB
complete tuner control

January 1995 18
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

AFC OUTPUT (VIA I2C-BUS); note 11
RES AFC resolution − 2 − bits
Wsen window sensitivity 65 80 100 kHz
WsenL window sensitivity in large 195 240 300 kHz
window mode
fos AFC offset note 6 − − 50 kHz
VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS)
td delay time of identification after − − 10 ms
the AGC has stabilized on a
new transmitter
CVBS and S-VHS input switch
INTERNAL AND EXTERNAL CVBS INPUTS (PINS 11 AND 15)
V11(p-p) CVBS input voltage note 12 − 1.0 1.4 V
(peak-to-peak value)
I11 CVBS input current − 4 − µA
SSCVBS suppression of non-selected notes 6 and 13 50 − − dB
CVBS input signal
S-VHS INPUT (PINS 8 AND 9)
V9(p-p) luminance input voltage − 1.0 1.4 V
(peak-to-peak value)
I9(p-p) luminance input current − 4 − µA
V8 chrominance input voltage note 14 − 0.3 0.45 V
(burst amplitude)
I8 chrominance input current − 4 − µA
TXT AND PIP OUTPUT SIGNALS (PINS 36 AND 13)
Vo(p-p) output signal amplitude − 1.0 − V
(peak-to-peak value)
Zo output impedance − − 250 Ω
VTS top sync level − 2.5 − V

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

RGB inputs, colour difference inputs, luminance inputs and outputs
RGB INPUTS (PINS 21, 22 AND 23)
V21,22,23(p-p) input signal amplitude for an note 15 − 0.7 0.8 V
output signal of 2 V
(black-to-white) (peak-to-peak
value)
V21,22,23(p-p) input signal amplitude before note 6 1.0 − − V
clipping occurs (peak-to-peak
value)
∆Vo difference between black level − − 20 mV
of internal and external signals
at the outputs
I21,22,23 input currents no clamping; note 2 − − 0.5 µA
∆td delay difference for the three note 6 − 0 20 ns
channels
FAST BLANKING (PIN 24)
Vi input voltage no data insertion − − 0.4 V
data insertion 0.9 − − V
V24(max) maximum input pulse insertion − − 3.0 V
td delay time from RGB in to data insertion; note 6 − 100 − ns
RGB out
∆td delay difference between data insertion; note 6 − 50 − ns
insertion to RGB out and
RGB in to RGB out
I24 input current − − 0.2 mA
SSint suppression of internal RGB notes 6 and 12; insertion; 55 − − dB
signals fi = 0 to 5 MHz
SSext suppression of external RGB notes 6 and 12; no insertion; 55 − − dB
signals fi = 0 to 5 MHz
VI input voltage to blank the RGB 4 − − V
outputs to facilitate ‘On Screen
Display’ signals being applied to
the outputs
COLOUR DIFFERENCE INPUT SIGNALS (PINS 29 AND 30)
V30(p-p) input signal amplitude (R−Y) note 2 − 1.05 − V
(peak-to-peak value)
V29(p-p) input signal amplitude (B−Y) note 2 − 1.35 − V
(peak-to-peak value)
I29,30 input current for both inputs note 2 − 0.1 1.0 µA

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

LUMINANCE INPUTS AND OUTPUTS (PINS 25 AND 26)
V26(p-p) output signal amplitude top sync-white − 0.45 0.63 V
(peak-to-peak value)
VTS top sync level − 2.5 − V
Zo output impedance − 250 − Ω
V25(p-p) input signal amplitude − 0.45 − V
(peak-to-peak value)
Iclamp clamp current during burst key pulse − 200 − µA
Ii input current no clamp − − 0.5 µA
Chrominance filters
CHROMINANCE TRAP CIRCUIT
ftrap trap frequency − fosc − MHz
QF trap quality factor note 16 − 2 −
SR colour subcarrier rejection 20 − − dB
CHROMINANCE BANDPASS CIRCUIT
fc centre frequency − fosc − MHz
QBP bandpass quality factor − 3 −
Delay line and peaking circuit
Y DELAY LINE
td delay time note 6 − 480 − ns
td1 tuning range delay time 8 steps −160 − +160 ns
B bandwidth of internal delay line note 6 5 − − MHz
PEAKING CONTROL; note 17
fc(p) peaking centre frequency − 3 − MHz
tW width of preshoot or overshoot note 2 − 160 − ns
OS overshoot positive − 20 − %
negative − 36 − %
peaking control curve 16 steps see Fig.5
CORING STAGE
S coring range − 15 − IRE
GW wave gain negative half wave gain − 1.8 −
--------------------------------------------------------------
positive half wave gain
Horizontal synchronization circuits
SYNC VIDEO INPUT (PINS 9, 11 AND 15)
V9,11,15 sync pulse amplitude note 2 50 300 − mV
SLHS slicing level for horizontal sync note 18 − 50 − %
SLVS slicing level for vertical sync − 30 − %

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

HORIZONTAL OSCILLATOR
ffr free running frequency − 15625 − Hz
∆ffr spread on free running − − ±2 %
frequency
∆f/∆VP frequency variation with respect VP = 8.0 V ±10%; note 6 − 0.2 0.5 %
to the supply voltage
∆f(max) frequency variation with Tamb = 0 to 70 °C; note 6 − − 80 Hz
temperature
∆fosc(max) maximum frequency deviation − − 75 %
at the start of the horizontal
output
FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 41); note 19
fHR holding range PLL − ±0.9 ±1.2 kHz
fCR catching range PLL note 6 ±0.6 ±0.9 − kHz
S/N signal-to-noise ratio of the video − 20 − dB
input signal at which the time
constant is switched
HYS hysteresis at the switching point − 1 − dB
SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 40)
∆ϕi/∆ϕo control sensitivity − 150 − µs/µs
tcr control range from start of 11 12 − µs
horizontal output to flyback at
nominal shift position
tshift horizontal shift range 63 steps ±2 − − µs
control sensitivity for dynamic − 5.3 − µs/V
compensation
HORIZONTAL OUTPUT (PIN 38); note 20
VOL LOW level output voltage IO = 10 mA − − 0.3 V
IO(max) maximum allowed output 10 − − mA
current
VO(max) maximum allowed output − − VP V
voltage
δ duty factor note 6 − 50 − %
FLYBACK PULSE INPUT (PIN 39)
VHSW switching level for horizontal − 0.4 − V
blanking
Vϕ2(SW) switching level for phase-2 loop − 4.0 − V
V39(max) maximum input voltage note 2 − 8.0 − V
Zi input impedance note 2 − 10 − MΩ

January 1995 22
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SANDCASTLE PULSE OUTPUT (PIN 37)
V37 output voltage during burst key 4.8 5.3 5.8 V
during blanking 1.8 2.0 2.2 V
tW pulse width burst key pulse 3.3 3.5 3.7 µs
vertical blanking (50 Hz) − 25 − lines
vertical blanking (60 Hz) − 21 − lines
Vclamp clamp level for vertical guard − 2.7 − V
detection
I37(min) minimum input current to − − 0.5 mA
activate guard detection
I37(max) maximum allowable input 2.5 − − mA
current
td delay of start of burst key to − 5.4 − µs
start of sync
SOFT START; note 21
δdf duty factor control range 0 − 50 %
tss soft start time − 100 − lines
Vertical synchronization and geometry correction
VERTICAL OSCILLATOR; note 22
ffr free running frequency − 50/60 − Hz
flock locking range 45 − 64.5 Hz
divider value not locked − 625/525 − lines
locking range 488 − 722 lines/
frame
VERTICAL RAMP GENERATOR (PIN 49)
V49(p-p) sawtooth amplitude VS = 1FH; − 3.5 − V
(peak-to-peak value) C = 100 nF; R = 39 kΩ
Idis discharge current − 1 − mA
Icharge charge current set by external note 23 − 19 − µA
resistor
VS vertical slope control range (63 steps) −14 − +14 %
compress mode − 75 − %
expand mode − 133 − %
∆I49 charge current increase f = 60 Hz − 20 − %
V49L LOW level of ramp normal or expand mode − 2.07 − V
compress mode − 2.55 − V
VERTICAL DRIVE OUTPUTS (PINS 44 AND 45)
Idiff(p-p) differential output current VA = 1FH − 1 − mA
(peak-to-peak value)
ICM common mode current − 400 − µA
Vo output voltage range 0 − 4.0 V

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 48)
∆V48 input voltage 1.2 − 2.8 V
SMR scan modulation range −6 − +6 %
ϕvert vertical sensitivity − 7.5 − %/V
ϕEW EW sensitivity when switched-on − −7.5 − %/V
Ieq EW equivalent output current +120 − −120 µA
V48 overvoltage detection level − 3.9 − V
DE-INTERLACE
first field delay − 0.5H −
EW WIDTH
CR control range 63 steps 100 − 80 %
Ieq equivalent output current 0 − 400 µA
Vo EW output voltage range 1.0 − 8.0 V
Io EW output current range 0 − 900 µA
EW PARABOLA/WIDTH
CR control range 63 steps 0 − 24 %
Ieq equivalent output current EW = 3FH 0 − 480 µA
EW CORNER/PARABOLA
CR control range 63 steps −44 − 0 %
Ieq equivalent output current PW = 3FH; EW = 3FH −210 − 0 µA
EW TRAPEZIUM
CR control range 63 steps −4 − +4 %
Ieq equivalent output current −80 − +80 µA
VERTICAL AMPLITUDE
CR control range 63 steps; SC = 00H 80 − 120 %
63 steps; SC = 3FH 86 − 112 %
Ieqdiff(p-p) equivalent differential vertical SC = 00H 800 − 1200 µA
drive output current
(peak-to-peak value)
VERTICAL SHIFT
CR control range 63 steps −4 − +4 %
Ieqdiff(p-p) equivalent differential vertical −40 − +40 µA
drive output current
(peak-to-peak value)
S-CORRECTION
CR control range 63 steps 0 − 25 %

January 1995 24
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Colour demodulation part
CHROMINANCE AMPLIFIER
ACCcr ACC control range note 24 26 − − dB
∆V change in amplitude of the − − 2 dB
output signals over the ACC
range
THRon threshold colour killer ON −23 −26 −29 dB
HYSoff hysteresis colour killer OFF strong signal conditions; − +3 − dB
S/N ≥ 40 dB; note 6
noisy input signals; note 6 − +1 − dB
ACL CIRCUIT
chrominance burst ratio at 2.3 − 2.7
which the ACL starts to operate
REFERENCE PART
Phase-locked loop; note 25
fCR catching range 300 500 − Hz
∆ϕ phase shift for a ±400 Hz note 6 − − 2 deg
deviation of the oscillator
frequency
Oscillator
TCosc temperature coefficient of the note 6 − 2.0 2.5 Hz/K
oscillator frequency
∆fosc oscillator frequency deviation note 6; VP = 8 V ±10% − − 250 Hz
with respect to the supply
Ri input resistance pin 32; f = 3.58 MHz; note 2 − 1.5 − kΩ
pin 33; f = 4.43 MHz; note 2 − 1.0 − kΩ
Ci input capacitance pins 32 and 33; note 2 − − 10 pF
HUE CONTROL
HUEcr hue control range 63 steps; see Fig.6 ±35 ±40 − deg
∆HUE hue variation for ±10% VP note 6 − 0 − deg
∆HUE/∆T hue variation with temperature Tamb = 0 to 70 °C; note 6 − 0 − deg

January 1995 25
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DEMODULATORS (PINS 27 AND 28)
V28(p-p) (R−Y) output signal amplitude note 26 − 0.525 − V
(peak-to-peak value)
V27(p-p) (B−Y) output signal amplitude note 26 − 0.675 − V
(peak-to-peak value)
G gain between both 1.60 1.78 1.96
demodulators G(B−Y) and
G(R−Y)
∆V spread of signal amplitude ratio note 6 −1 − +1 dB
PAL/NTSC
Zo output impedance (R−Y)/(B−Y) note 6 − 500 − Ω
output
B bandwidth of demodulators −3 dB; note 27 − 650 − kHz
V27,28(p-p) residual carrier output f = fosc; (R−Y) output 5 mV
(peak-to-peak value) f = fosc; (B−Y) output − − 5 mV
f = 2fosc; (R−Y) output 5 mV
f = 2fosc; (B−Y) output − − 5 mV
V28(p-p) H/2 ripple at (R−Y) output − − 25 mV
(peak-to-peak value)
∆Vo/∆T change of output signal note 6 − 0.1 − %/K
amplitude with temperature
∆Vo/∆VP change of output signal note 6 − − ±0.1 dB
amplitude with supply voltage
ϕe phase error in the demodulated − − ±5 deg
signals
COLOUR DIFFERENCE MATRICES IN CONTROL CIRCUIT
PAL or (SECAM mode with TDA8395); (R−Y) and (B−Y) not affected
(G−Y)/(R−Y) ratio of demodulated signals − −0.51 −
±10%
(G−Y)/(B−Y) ratio of demodulated signals − −0.19 −
±25%
NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting)
(B−Y) (B−Y) signal (B−Y)
(R−Y) (R−Y) signal 1.39(R−Y) − 0.07(B−Y)
(G−Y) (G−Y) signal −0.46(R−Y) − 0.15(B−Y)

January 1995 26
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

REFERENCE SIGNAL OUTPUT FOR TDA8395 (PIN 31)
fref reference frequency − 4.43 − MHz
V31(p-p) output signal amplitude 0.2 0.25 0.3 V
(peak-to-peak value)
Vo output level PAL/NTSC identified − 1.5 − V
no PAL/NTSC identified; − 5.0 − V
SECAM (by TDA8395)
identified
I31 required current to stop 150 − − µA
PAL/NTSC identification circuit
during SECAM
Control part
SATURATION CONTROL; note 15
SATcr saturation control range 63 steps; see Fig.7 52 − − dB
CONTRAST CONTROL; note 15
CONcr contrast control range 63 steps − 20 − dB
tracking between the three see Fig.8 − − 0.5 dB
channels over a control range of
10 dB
BRIGHTNESS CONTROL
BRIcr brightness control range 63 steps; see Fig.9 − ±0.7 − V
RGB AMPLIFIERS (PINS 17, 18 AND 19)
V17,18,19(p-p) output signal amplitude at nominal luminance input tbf 2.0 tbf V
(peak-to-peak value) signal, nominal contrast and
white-point adjustment;
note 15
at maximum white point − 3.0 − V
setting
VBWmax(p-p) maximum signal amplitude note 28 − 2.6 − V
(black-to-white) at maximum white point − 3.6 − V
setting
VRED(p-p) output signal amplitude for the at nominal settings for tbf 2.1 tbf V
‘red’ channel (peak-to-peak contrast and saturation
value) control and no luminance
signal to the input (R−Y, PAL)
Vblank blanking level at the RGB 0.7 0.8 0.9 V
outputs
Ibias internal bias current of NPN − 1.5 − mA
emitter follower output transistor
Io available output current − 5 − mA
Zo output impedance − 150 − Ω

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Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

RGB AMPLIFIERS (CONTINUED)
CRbl control range of the nominal brightness and − − ±1 V
black-current stabilization white-point adjustment (with
respect to the measuring
pulse); Vblk = 2.5 V
Vbl black level shift with picture note 6 − − 20 mV
content
Vo output voltage of the 4-L pulse − 4.2 − V
after switch-on
∆bl/∆T variation of black level with note 6 − 1.0 − mV/K
temperature
∆bl relative variation in black level note 6
between the three channels
during variations of
supply voltage (±10%) nominal controls − − tbf mV
saturation (50 dB) nominal contrast − − tbf mV
contrast (20 dB) nominal saturation − − tbf mV
brightness (±0.5 V) nominal controls − − tbf mV
temperature (range 40 °C) − − tbf mV
S/N signal-to-noise ratio of the RGB input; note 29 60 − − dB
output signals CVBS input; note 29 50 − − dB
Vres(p-p) residual voltage at the RGB at fosc − − 15 mV
outputs (peak-to-peak value) at 2fosc plus higher − − 15 mV
harmonics in RGB outputs
B bandwidth of output signals RGB input; at −3 dB 8 − − MHz
CVBS input; at −3 dB; − 2.8 − MHz
fosc = 3.58 MHz
CVBS input; at −3 dB; − 3.5 − MHz
fosc = 4.43 MHz
S-VHS input; at −3 dB 5 − − MHz
WHITE-POINT ADJUSTMENT
I2C-bus setting for nominal gain HEX code − 20H −
Ginc(max) maximum increase of the gain HEX code 3FH 40 50 60 %
Gdec(max) maximum decrease of the gain HEX code 00H 40 50 60 %
BLACK-CURRENT STABILIZATION (PIN 16); note 30
Ibias bias current for the picture tube − 10 − µA
cathode
Ileak acceptable leakage current − 100 − µA
Iscan(max) maximum current during scan − 0.3 − mA

January 1995 28
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BEAM CURRENT LIMITING (PIN 20); note 28
VCR contrast reduction starting − 4 − V
voltage
VdiffCR voltage difference for full − 2 − V
contrast reduction
VBR brightness reduction starting − 3 − V
voltage
VdiffBR voltage difference for full − 2 − V
brightness reduction
Vbias internal bias voltage − 4.5 − V
Ich(int) internal charge current − 40 − µA
Idisch discharge current due to − 200 − µA
‘peak-white limiting’
Notes
1. On set AGC.
2. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
3. Measured at 10 mV (RMS) top sync input signal.
4. So called projected zero point, i.e. with switched demodulator.
5. Measured in accordance with the test line given in Fig.10. For the differential phase test the peak white setting is
reduced to 87%.
a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.11.
8. The test set-up and input conditions are given in Fig.12. The figures are measured with an input signal of
10 mV RMS.
9. Measured with a source impedance of 75 Ω, where:
V O (black-to-white)
S/N = 20 log ---------------------------------------------------------
V m ( rms ) ( B = 5 MHz )

10. To obtain a good noise immunity of the AGC circuit the AGC detector is gated during the sync pulse. This gating is
switched-off during the vertical retrace to avoid disturbances of the signal amplitude due to phase errors of the
incoming video signal which are caused by the head-switching of VCRs.

January 1995 29
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

11. The AFC slope is directly related to the Q-factor of the demodulator tuned circuit. The given AFC steepness is
obtained with a Q-factor of 60. The AFC off-set is tested with a double sideband input signal and with the reference
tuned circuit tuned to minimum AGC voltage (optimum tuning for the demodulator).
The tuning information is supplied to the tuning system via the I2C-bus. Two bits have been reserved for this function.
The first bit indicates whether the tuning is within the given window. The second bit indicates the direction of the
tuning. Bit indications:
a) AFA = 1; tuning inside window.
b) AFA = 0; tuning outside window.
c) AFB = 1; tuning too high.
d) AFB = 0; tuning too low.
To improve the speed of search tuning systems the AFC window can be increased to about 240 kHz. The width of
the window can be set by means of the AFW bit in subaddress 03.
12. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
13. This parameter is measured at nominal settings of the various controls.
14. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).
15. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum −10 dB. In the nominal
brightness setting the black level at the outputs is identical to the level of the black-current measuring pulses.
16. The −3 dB bandwidth of the circuit can be calculated by means of the following equation:
1
f –3 dB = f osc  1 – -------- 
2Q
17. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
18. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch).
19. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the I2C-bus. Therefore the circuit contains a
noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’
mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be
automatically or overruled by the I2C-bus.
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification
circuit with the first loop can be defeated via the I2C-bus.
When the horizontal PLL is set to the ‘slow’ mode (via I2C-bus bits FOA and FOB) or during weak signal conditions
in the ‘automatic’ mode the phase detector is gated to obtain a good noise immunity. The width of the gating pulse
is 5.7 µs.
The output current of the phase detector in the various conditions are shown in Table 42.
20. During the start-up period of the oscillator the duty factor of the output pulse rises gradually from 0% to 50% (time
approximately 100 lines).
21. The start-up frequency depends on the SFM bit in the I2C-bus protocol. When SFM = 0 the frequency starts at a high
(non calibrated) value. When SFM = 1 the output signal will only be available after calibration.

January 1995 30
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

22. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This
divider circuit has 3 modes of operation:
a) Search mode ‘large window’.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per
frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode
the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).
b) Standard mode ‘narrow window’.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator
is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch
back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.
c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in
accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the
standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync
pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 08.
23. Conditions: frequency is 50 Hz; normal mode; VS = 1F.
24. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB.
25. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency.
All oscillator specifications are measured with the Philips crystal series 9922 520.
If the spurious response of the 4.43 MHz crystal is lower than −1 dB with respect to the fundamental frequency for a
damping resistance of 1 kΩ, oscillation at the fundamental frequency is guaranteed.
The spurious response of the 3.58 MHz crystal must be lower than −1 dB with respect to the fundamental frequency
for a damping resistance of 1.5 kΩ.
The catching and detuning range are measured for nominal crystal parameters. These are:
a) Load resonance frequency f0 = 4.433619 or 3.579545 MHz; CL = 20 pF.
b) Motional capacitance C1 = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal).
c) Parallel capacitance C0 = 5.5 pF (4.43 MHz crystal) or 4.5 pF (3.58 MHz crystal).
The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and
off chip.
Philips Components has developed a special crystal which is tuned to the correct frequency in an application without
series capacitance (code number 9922 520 0038X; see Table 43). This has the advantage that the tuning (catching)
range is increased with approximately 50% without negative effects on spurious responses. When the catching range
of 300 Hz is considered too low this special crystal is a suitable alternative.
The free-running frequency of the oscillator can be checked by opening the colour PLL via the I2C-bus. In that
condition the colour killer is not active so that the frequency off-set is visible on the screen. When two crystals are
connected to the IC the circuit must be forced to one of the crystals during this test to prevent the oscillator switching
continuously between the two frequencies.

January 1995 31
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

26. The (R−Y) and (B−Y) signals are demodulated with a phase difference of the reference carrier of 90° and a gain ratio
( B – Y)
--------------------- = 1.78. The matrixing to the required signals is achieved in the control part.
( R – Y)
27. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
28. At nominal setting of the gain control. When this amplitude is exceeded the peak-white limiting circuit will reduce the
contrast. The control voltage is generated via the external capacitor connected to the beam-current limiting input.
29. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
30. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain
(white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a
result the ‘black-current’ of each gun is adapted to the white point setting so that the back-ground colour will follow
the white point adjustment.

Table 42 Output current of the phase detector in the various conditions

I2C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE

VID POC FOA FOB IDENT COIN NOISE SCAN V-RETR GATING MODE
− 0 0 0 yes yes yes 30 30 yes auto
− 0 0 0 yes no − 180 270 no auto
− 0 0 1 yes yes − 30 30 yes slow
− 0 0 1 yes no − 180 270 no slow
− 0 1 − yes − − 180 270 no fast
0 0 − − no − − 6 6 no OSD
− 1 − − − − − − − − off

Table 43 Code numbers for special crystals

FREQUENCY
SYSTEM CODE NUMBER
(MHz)
PAL-N 3.582056 9922 520 00381
NTSC-M 3.579545 9922 520 00382
PAL-M 3.575611 9922 520 00383
PAL-B/G 4.433619 9922 520 00384

January 1995 32
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

MLA738 - 1 MLA739 - 1
50 50

(%) (deg)

30 30

10 10

10 10

30 30

50 50
0 4 8 C F 10 0 10 20 30 40
DAC (HEX) DAC (HEX)

Overshoot in direction ‘black’.

Fig.5 Peaking control curve. Fig.6 Hue control curve.

MLA741 - 1
MLA740 - 1
250 100
(%) (%)
225 90

200 80

175 70

150 60

125 50

100 40

75 30

50 20

25 10

0 0 10 20 30 40
0 10 20 30 40
DAC (HEX) DAC (HEX)

Fig.7 Saturation control curve. Fig.8 Contrast control curve.

January 1995 33
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

MLA742 - 1

0.7

(V)
MBC212

0.35 100%
16 % 92%

0.35
30%

for negative modulation

100% = 10% rest carrier
0.7

0
0 10 20 30 40
DAC (HEX)

Relative variation with respect to the measuring pulse.

Fig.9 Brightness control curve. Fig.10 Video output signal.

handbook, full pagewidth MBC211

100%

86%

72%

58%

44%

30%

10 12 22 26 32 36 40 44 48 52 56 60 64 µs

Fig.11 Test signal waveform.

January 1995 34
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

handbook, full pagewidth 3.2 dB

10 dB
13.2 dB 13.2 dB

30 dB 30 dB

SC CC PC SC CC PC
MBC213
BLUE YELLOW

PC

TEST SPECTRUM
SC Σ ATTENUATOR CIRCUIT ANALYZER

gain setting
adjusted for blue
CC
MBC210

Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier.

All amplitudes with respect to top sync level.
V O at 3.58 or 4.4 MHz
Value at 0.92 or 1.1 MHz = 20 log ------------------------------------------------------------ + 3.6 dB
V O at 0.92 or 1.1 MHz

V O at 3.58 or 4.4 MHz

Value at 2.66 or 3.3 MHz = 20 log ------------------------------------------------------------
V O at 2.66 or 3.3 MHz

Fig.12 Test set-up intermodulation.

January 1995 35
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

TEST AND APPLICATION INFORMATION

handbook, full pagewidth BAND

QSS IF PASS L
STEREO AND CONTROL
BAND R
PASS
SCL
from SAW SOUND CVBS/Y
tuner FILTER SDA
TRAP CVBS EXT CHROMA RI GI BI RGBIN
2
11 4 15 9 8 5 6 21 22 23 24
47 and 46 19 RO

18 GO
17 BO

IFDEM2 16 BLKIN
2 20 BCLIN
TDA8366 43 EWD
1 44 VDR (pos)
IFDEM1
45 VDR (neg)

38 HOUT

39 FBI
33 32 36 31 28 27 30 29 37

4.4 3.6 CVBS/ SEC ref RYO BYO RYI BYI SCO
MHz MHz TXT
to text decoder

TDA8395 TDA4661 MLA746 - 1

Fig.13 Application diagram.

East-West output stage The preferred value of Rc is 39 kΩ which results in a

reference current of 100 µA (Vref = 3.9 V).
In order to obtain correct tracking of the vertical and
horizontal EHT-correction, the EW output stage should be The value of REW must be:
dimensioned as illustrated in Fig.14. V scan
R EW = R c × -----------------------
Resistor REW determines the gain of the EW output stage. 18 × V ref
Resistor Rc determines the reference current for both the
vertical sawtooth generator and the geometry processor. Example: With Vref = 3.9 V; Rc = 39 kΩ and Vscan = 120 V
then REW = 68 kΩ.

January 1995 36
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

handbook, full pagewidth VDD

HORIZONTAL
DEFLECTION V scan
STAGE

R ew

TDA8366
DIODE V EW
43
EWD MODULATOR

EW output
50 49 stage
V ref
Rc C saw
39 kΩ
(2%) 100 nF
I ref (5%) MLA744 - 1

Fig.14 East-West output stage.

VA = 0, 31H and 63H; VSH = 31H; SC = 0. VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0.

Fig.15 Control range of vertical amplitude. Fig.16 Control range of vertical slope.

January 1995 37
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

VSH = 0, 31H and 63H; VA = 31H; SC = 0. SC = 0, 31H and 63H; VA = 31H; VHS = 31H.

Fig.17 Control range of vertical shift. Fig.18 Control range of S-correction.

EW = 0, 31H and 63H; PW = 31H; CP = 31H. PW = 0, 31H and 63H; EW = 31H; CP = 31H.

Fig.19 Control range of EW width. Fig.20 Control range of EW parabola/width ratio.

January 1995 38
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

CP = 0, 31H and 63H; EW = 31H; PW = 63H. TC = 0, 31H and 63H; EW = 31H; PW = 31H.

Fig.21 Control range of EW corner/parabola ratio. Fig.22 Control range of EW trapezium correction.

January 1995 39
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

Adjustment of geometry control parameters For adjustment of the vertical shift and vertical slope
independent of each other, a special service blanking
The deflection processor of the TDA8366 offers nine
mode can be entered by setting the SBL bit HIGH. In this
control parameters for picture alignment:
mode the RGB-outputs are blanked during the second half
• Vertical picture alignment of the picture. There are 2 different methods for alignment
– S-correction of the picture in vertical direction. Both methods make use
of the service blanking mode.
– vertical amplitude
– vertical slope The first method is recommended for picture tubes that
have a marking for the middle of the screen. With the
– vertical shift
vertical shift control the last line of the visible picture is
• Horizontal picture alignment positioned exactly in the middle of the screen. After this
– horizontal shift adjustment the vertical shift should not be changed. The
top of the picture is placed by adjustment of the vertical
– EW width
amplitude, and the bottom by adjustment of the vertical
– EW parabola/width slope.
– EW corner/parabola
The second method is recommended for picture tubes that
– EW trapezium correction. have no marking for the middle of the screen. For this
It is important to notice that the TDA8366 is designed for method a video signal is required in which the middle of the
use with a DC-coupled vertical deflection stage. This is the picture is indicated (e.g. the white line in the circle test
reason why a vertical linearity alignment is not necessary pattern). With the vertical slope control the beginning of the
(and therefore not available). blanking is positioned exactly on the middle of the picture.
Then the top and bottom of the picture are placed
For a particular combination of picture tube type, vertical symmetrical with respect to the middle of the screen by
output stage and EW output stage it is determined which adjustment of the vertical amplitude and vertical shift.
are the required values for the settings of S-correction, EW After this adjustment the vertical shift has the right setting
parabola/width ratio and EW corner/parabola ratio. These and should not be changed.
parameters can be preset via the I2C-bus, and do not need
any additional adjustment. The rest of the parameters are If the vertical shift alignment is not required VSH should be
preset with the mid-value of their control range (i.e. 1FH), set to its mid-value (i.e. VSH = 1F). Then the top of the
or with the values obtained by previous TV-set picture is placed by adjustment of the vertical amplitude
adjustments. and the bottom by adjustment of the vertical slope. After
the vertical picture alignment the picture is positioned in
The vertical shift control is meant for compensation of the horizontal direction by adjustment of the EW width and
off-sets in the external vertical output stage or in the the horizontal shift. Finally (if necessary) the left- and
picture tube. It can be shown that without compensation right-hand sides of the picture are aligned in parallel by
these off-sets will result in a certain linearity error, adjusting the EW trapezium control.
especially with picture tubes that need large S-correction.
The total linearity error is in first order approximation After adjustment of the picture for normal vertical
proportional to the value of the off-set, and to the square of deflection as described, no additional adjustment is
the S-correction needed. The necessity to use the vertical necessary for the compress and expand mode. If required
shift alignment depends on the expected off-sets in vertical a small correction of the picture height can be made by
output stage and picture tube, on the required value of the adjusting the vertical slope. This will not effect the linearity.
S-correction, and on the demands upon vertical linearity.

January 1995 40
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

PACKAGE OUTLINES

handbook, full pagewidth 47.92 15.80

seating plane

47.02 15.24

4.57 5.08
max max

3.2
2.8 0.51
min
0.18 M 0.32 max
1.73 1.778 0.53
max (25x) max
15.24
17.15
1.3 max 15.90
MSA267

52 27

14.1
13.7

1 26

Dimensions in mm.

Fig.23 Plastic shrink dual in-line package; 52 leads (600 mil) SDIP52; SOT247-1.

January 1995 41
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

handbook, full pagewidth

seating plane 0.10 S S

18.2
17.6 B

64 52

1 51

1.2
pin 1 index (4x)
0.8

1.0

20.1 24.2
0.20 M B

19.9 23.6

0.50
0.35

19 33

20 32

0.50 1.2
0.20 M A (4x)
0.35 0.8 X
1.0
14.1
13.9
A

1.4
1.2
2.90
3.2
2.65 0.25 2.7
0.25
0.05 0.14

1.0
0.6 0 to 7 o

detail X MSA327

Dimensions in mm.

Fig.24 Plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm.

January 1995 42
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

SOLDERING A modified wave soldering technique is recommended

using two solder waves (dual-wave), in which a turbulent
Plastic dual in-line packages
wave with high upward pressure is followed by a smooth
BY DIP OR WAVE laminar wave. Using a mildly-activated flux eliminates the
need for removal of corrosive residues in most
The maximum permissible temperature of the solder is applications.
260 °C; this temperature must not be in contact with the
joint for more than 5 s. The total contact time of successive
BY SOLDER PASTE REFLOW
solder waves must not exceed 5 s.
Reflow soldering requires the solder paste (a suspension
The device may be mounted up to the seating plane, but
of fine solder particles, flux and binding agent) to be
the temperature of the plastic body must not exceed the
applied to the substrate by screen printing, stencilling or
specified storage maximum. If the printed-circuit board has
pressure-syringe dispensing before device placement.
been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within Several techniques exist for reflowing; for example,
the permissible limit. thermal conduction by heated belt, infrared, and
vapour-phase reflow. Dwell times vary between 50 and
REPAIRING SOLDERED JOINTS 300 s according to method. Typical reflow temperatures
range from 215 to 250 °C.
Apply a low voltage soldering iron below the seating plane
(or not more than 2 mm above it). If its temperature is Preheating is necessary to dry the paste and evaporate
below 300 °C, it must not be in contact for more than 10 s; the binding agent. Preheating duration: 45 min at 45 °C.
if between 300 and 400 °C, for not more than 5 s.
REPAIRING SOLDERED JOINTS (BY HAND-HELD SOLDERING
Plastic quad flat-packs IRON OR PULSE-HEATED SOLDER TOOL)

BY WAVE Fix the component by first soldering two, diagonally

opposite, end pins. Apply the heating tool to the flat part of
During placement and before soldering, the component the pin only. Contact time must be limited to 10 s at up to
must be fixed with a droplet of adhesive. After curing the 300 °C. When using proper tools, all other pins can be
adhesive, the component can be soldered. The adhesive soldered in one operation within 2 to 5 s at between 270
can be applied by screen printing, pin transfer or syringe and 320 °C. (Pulse-heated soldering is not recommended
dispensing. for SO packages.)
Maximum permissible solder temperature is 260 °C, and For pulse-heated solder tool (resistance) soldering of VSO
maximum duration of package immersion in solder bath is packages, solder is applied to the substrate by dipping or
10 s, if allowed to cool to less than 150 °C within 6 s. by an extra thick tin/lead plating before package
Typical dwell time is 4 s at 250 °C. placement.

January 1995 43
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

PURCHASE OF PHILIPS I2C COMPONENTS

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

January 1995 44
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

NOTES

January 1995 45
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

NOTES

January 1995 46
Philips Semiconductors Objective specification

I2C-bus controlled PAL/NTSC TV

TDA8366
processor

NOTES

January 1995 47
 Philips Semiconductors – a worldwide company
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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For all other countries apply to: Philips Semiconductors,
Italy: PHILIPS SEMICONDUCTORS S.r.l.,
International Marketing and Sales, Building BE-p,
Piazza IV Novembre 3, 20124 MILANO, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands,
Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557 Telex 35000 phtcnl, Fax. +31-40-724825
Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108,
Tel. (03)3740 5028, Fax. (03)3740 0580 SCD36 © Philips Electronics N.V. 1994
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SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 or contract, is believed to be accurate and reliable and may be changed without
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Tel. 9-5(800)234-7381, Fax. (708)296-8556 use. Publication thereof does not convey nor imply any license under patent- or
other industrial or intellectual property rights.
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB
Tel. (040)783749, Fax. (040)788399
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Tel. (09)849-4160, Fax. (09)849-7811
Norway: Box 1, Manglerud 0612, OSLO, 533061/1500/01/pp48 Date of release: January 1995
Tel. (022)74 8000, Fax. (022)74 8341 Document order number: 9397 745 80011

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