The 8051 Assembly Language

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Overview
Assembler directives Data transfer instructions Addressing modes Data processing (arithmetic and logic) Program flow instructions

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Instructions vs. Directives

Assembler Directives
Instructions for the ASSEMBLER NOT 8051 instructions

Examples:
;cseg stands for code segment cseg at 1000h ;address of next instruction is 1000h GREEN_LED equ P1.6 ;symbol for Port 1, bit 6

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Assembler Directives
DATA
Used to define a name for memory locations
SP DATA 0x81 ;special function registers MY_VAL DATA 0x44 ;RAM location

Addres s

EQU Used to create symbols that can be used to represent registers, numbers, and addresses
LIMIT EQU 2000 VALUE EQU LIMIT 200 + 'A' SERIAL EQU SBUF COUNT EQU R5 MY_VAL EQU 0x44

Registers, numbers, addresses

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Prof. Cherrice Traver

Data Transfer Instructions

MOV dest, source dest 6 basic types: source

MOV a, byte ;move byte to accumulator MOV byte, a ;move accumulator to byte MOV Rn, byte ;move byte to register of ;current bank MOV direct, byte ;move byte to internal RAM MOV @Rn, byte ;move byte to internal RAM ;with address contained in Rn MOV DPTR, data16 ;move 16-bit data into data ;pointer

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EE/CS-152: Microprocessors and Microcontrollers

Other Data Transfer Instructions

Stack instructions
PUSH byte ;increment stack pointer, ;move byte on stack POP byte ;move from stack to byte, ;decrement stack pointer

Exchange instructions
XCH a, byte ;exchange accumulator and ;byte XCHD a, byte ;exchange low nibbles of ; accumulator and byte

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EE/CS-152: Microprocessors and Microcontrollers

Addressing Modes
Immediate Mode specify data by its value
mov a, #0 ;put 0 in the accumulator a = 00000000 mov a, #0x11 ; put 11hex in the accumulator a = 00010001 mov a, #11 ; put 11 decimal in accumulator a = 00001011 mov a, #77h ; put 77 hex in accumulator a = 01110111

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EE/CS-152: Microprocessors and Microcontrollers

Addressing Modes
Direct Mode specify data by its 8-bit address
mov a, 0x70 ; copy contents of RAM at 70h to a mov 0xD0, a ; put contents of a into PSW

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EE/CS-152: Microprocessors and Microcontrollers

Addressing Modes
Register Addressing either source or destination is one of R0-R7
mov R0, a mov a, R0

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EE/CS-152: Microprocessors and Microcontrollers

Play with the Register Banks

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EE/CS-152: Microprocessors and Microcontrollers

Addressing Modes
Register Indirect the address of the source or destination is specified in registers Uses registers R0 or R1 for 8-bit address:
mov 0xD0, #0 ; use register bank 0 mov r0, #0x3C mov @r0, #3 ; memory at 3C gets #3 ; M[3C] 3

Uses DPTR register for 16-bit addresses:

mov dptr, #0x9000 ; dptr 9000h mov a, @dptr ; a M[9000] Note that 9000 is an address in external memory

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EE/CS-152: Microprocessors and Microcontrollers

Exercise: Use Register Indirect to access upper RAM block

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EE/CS-152: Microprocessors and Microcontrollers

Learn about Include Files

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EE/CS-152: Microprocessors and Microcontrollers

Addressing Modes
Register Indexed Mode source or destination address is the sum of the base address and the accumulator. Base address can be DPTR or PC
mov dptr, #4000h mov a, #5 movc a, @a + dptr ;a M[4005]

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EE/CS-152: Microprocessors and Microcontrollers

Addressing Modes
Register Indexed Mode Base address can be DPTR or PC
Addr cseg at 0x1000h 1000 mov a, #5 1. movc a, @a + PC ;a M[1008] 1003 nop
P C

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EE/CS-152: Microprocessors and Microcontrollers

Table Lookup

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EE/CS-152: Microprocessors and Microcontrollers

A and B Registers
A and B are accumulators for arithmetic instructions They can be accessed by direct mode as special function registers: B address 0F0h A address 0E0h - use ACC for direct mode
Prof. Cherrice Traver EE/CS-152: Microprocessors and Microcontrollers

Address Modes
Stack-oriented data transfer another form of register indirect addressing, but using SP
mov sp, #0x40 ; Initialize SP push 0x55 ; SP SP+1, M[SP] ; M[41] M[55] pop b ; b M[55]

M[55]

Note: can only specify RAM or SFRs (direct mode) to push or pop. Therefore, to push/pop the accumulator, must use acc, not a: push acc push a
Prof. Cherrice Traver EE/CS-152: Microprocessors and Microcontrollers

Stacks
pus h stack pointer stac k po p

Go do the stack exercise..

Prof. Cherrice Traver EE/CS-152: Microprocessors and Microcontrollers

Address Modes
Exchange Instructions two way data transfer
XCH a, 0x30 ; a M[30] XCH a, R0 ; a R0 XCH a, @R0 ; a M[R0] XCHD a, R0 ; exchange digit
a[7..4] a[3..0] R0[7..4] R0[3..0]
Only 4 bits exchanged
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Address Modes
Bit-Oriented Data Transfer transfers between individual bits. SFRs with addresses ending in 0 or 8 are bit-addressable. (80, 88, 90, 98, etc) Carry flag (C) (bit 7 in the PSW) is used as a single-bit accumulator RAM bits in addresses 20-2F are bit addressable

Examples of bit transfers of special function register bits:

mov C, P0.0 ; C
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bit 0 of P0
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Bit Addressable Memory

2F 7F 2E 2 D 2 C 2B 2A 29 28 78

20h 2Fh (16 locations X 8-bits = 128 bits) Bit addressing: mov C, 1Ah or mov C, 23h.2

2 7 2 6 2 5 2 4 2 0F 3 2 07 06 05 04 2 2 1 Prof. Cherrice Traver 2

1A 10 08 03 02 01 00

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SPRs that are Bit Addressable

Address Register SPI0CN B ADC0CN ACC PCA0CN PSW T2CON SMB0CN IP P3 IE P2 SCON P1 TCON P0

SPRs with addresses of multiples of 0 and 8 are bit addressable. Notice that all 4 parallel I/O ports are bit addressable.
SFRs
Pink are implemented in enhanced C8051F020

0xF8 0xF0 0xE8 0xE0 0xD8 0xD0 0xC8 0xC0 0xB8 0xB0 0xA8 0xA0 0x98 0x90 0x88 0x80

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Go Access the Port Bits.

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Part II
The 8051 Assembly Language

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Program Template
Use this template as a starting point for future programs.

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EE/CS-152: Microprocessors and Microcontrollers

Data Processing Instructions

Arithmetic Instructions Logic Instructions

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EE/CS-152: Microprocessors and Microcontrollers

Arithmetic Instructions
Add Subtract Increment Decrement Multiply Divide Decimal adjust

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EE/CS-152: Microprocessors and Microcontrollers

Arithmetic Instructions
Mnemonic ADD A, byte ADDC A, byte SUBB A, byte INC A INC byte INC DPTR DEC A DEC byte MUL AB DIV AB DA A
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Description add A to byte, put result in A add with carry subtract with borrow increment A increment byte in memory increment data pointer decrement accumulator decrement byte multiply accumulator by b register divide accumulator by b register decimal adjust the accumulator
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ADD Instructions
add a, byte ; a a + byte addc a, byte ; a a + byte + C These instructions affect 3 bits in PSW: C = 1 if result of add is greater than FF AC = 1 if there is a carry out of bit 3 OV = 1 if there is a carry out of bit 7, but not from bit 6, or visa versa.

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

Instructions that Affect PSW bits

Prof. Cherrice Traver

EE/CS-152: Microprocessors and Microcontrollers

ADD Examples
mov a, #0x3F add a, #0xD3
0011 1111 1101 0011 0001 0010

What is the value of the C, AC, OV flags after the second instruction is executed? C=1 AC = 1 OV = 0

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EE/CS-152: Microprocessors and Microcontrollers

Signed Addition and Overflow

2s complement: 0000 0000 00 0 0111 1111 7F 127 1000 0000 80 -128 1111 1111 FF -1
0111 1111 (positive 127) 0111 0011 (positive 115) 1111 0010 (overflow cannot represent 242 in 8 bits 2s complement) 1000 1111 (negative 113) 1101 0011 (negative 45) 0110 0010 (overflow)

0011 1111 (positive) 1101 0011 (negative) 0001 0010 (never overflows)

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EE/CS-152: Microprocessors and Microcontrollers

Addition Example
; Computes Z = X + Y; Adds values at locations 0x78 and 0x79 and puts them in location 0x7A $INCLUDE (C8051F020.inc) ; EQUATES ;----------------------------------------------------------------------------X equ 0x78 Y equ 0x79 Z equ 0x7A ; RESET and INTERRUPT VECTORS ;----------------------------------------------------------------------------cseg at 0 ljmp Main ; CODE SEGMENT ;----------------------------------------------------------------------------cseg at 100h Main: mov 0xFF, #0DEh ; Disable watchdog timer mov 0xFF, #0ADh mov a, X add a, Y mov Z, a Prof. Cherrice Traver EE/CS-152: Microprocessors and Microcontrollers nop

The 16-bit ADD example..

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EE/CS-152: Microprocessors and Microcontrollers

Subtract
SUBB A, byte subtract with borrow

Example:
SUBB A, #0x4F ; A A 4F C

Notice that there is no subtraction WITHOUT borrow. Therefore, if a subtraction without borrow is desired, it is necessary to clear the C flag.

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EE/CS-152: Microprocessors and Microcontrollers

Increment and Decrement

INC A INC byte INC DPTR DEC A DEC byte increment A increment byte in memory increment data pointer decrement accumulator decrement byte

The increment and decrement instructions do NOT affect the C flag. Notice we can only INCREMENT the data pointer, not decrement.
Prof. Cherrice Traver EE/CS-152: Microprocessors and Microcontrollers

Example: Increment 16-bit Word

Assume 16-bit word in R3:R2
mov a, r2 add a, #1 ; use add rather than increment to affect C mov r2, a mov a, r3 addc a, #0 ; add C to most significant byte mov r3, a

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Multiply
When multiplying two 8-bit numbers, the size of the maximum product is 16-bits FF x FF = FE01 (255 x 255 = 65025)
MUL AB ; BA A*B

Note: B gets the HIGH byte, A gets the LOW byte

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Go forth and multiply

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Division
Integer Division
DIV AB ; divide A by B A Quotient(A/B), B Remainder(A/B)

OV - used to indicate a divide by zero condition. C set to zero

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EE/CS-152: Microprocessors and Microcontrollers

Decimal Adjust
DA a ; decimal adjust a Used to facilitate BCD addition. Adds 6 to either high or low nibble after an addition to create a valid BCD number. Example:
mov a, #0x23 mov b, #0x29 add a, b ; a 23 + 29 = 4C (wanted 52) DA a ; a a + 6 = 52
Note: This instruction does NOT convert binary to BCD!

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EE/CS-152: Microprocessors and Microcontrollers

Logic Instructions
Bitwise logic operations (AND, OR, XOR, NOT) Clear Rotate Swap Logic instructions do NOT affect the flags in PSW

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EE/CS-152: Microprocessors and Microcontrollers

Bitwise Logic
ANL AND ORL OR XRL eXclusive OR CPL Complement
Example s: ANL 0000111 1 1010110 0000110 0 0000111 1 1010110 1010111 0 1 0000111 1 1010001 1010110 1 0 1010110 0101001 0 1

OR L

XRL

CP L
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EE/CS-152: Microprocessors and Microcontrollers

Address Modes with Logic

ANL AND ORL OR XRL eXclusive oR a, byte
direct, reg. indirect, reg, immediate

byte, a
direct

byte, #constant CPL Complement

a ex: cpl a

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EE/CS-152: Microprocessors and Microcontrollers

Uses of Logic Instructions

Force individual bits low, without affecting other bits.
anl PSW, #0xE7 ;PSW AND 11100111 anl PSW, #11100111b ; can use binary

Force individual bits high.

orl PSW, #0x18 ;PSW OR 00011000

Complement individual bits

xrl P1, #0x40 ;P1 XRL 01000000
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A bit part for you.

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EE/CS-152: Microprocessors and Microcontrollers

Other Logic Instructions

CLR - clear RL rotate left RLC rotate left through Carry RR rotate right RRC rotate right through Carry SWAP swap accumulator nibbles

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CLR Set all bits to 0

CLR A CLR byte (direct mode) CLR Ri (register mode) CLR @Ri (register indirect mode)

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Rotate
Rotate instructions operate only on a rl a mov a, #0xF0 ; a 11110000 rl a ; a 11100001

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Rotate through Carry

rrc a
C

mov a, #0A9h ; a A9 add a, #14h ; a BD (10111101), C 0 rrc a ; a 01011110, C 1

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EE/CS-152: Microprocessors and Microcontrollers

Swap
swap a

mov a, #72h swap a ; a 27h

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Bit Logic Operations

Some logic operations can be used with single bit operands
ANL C, bit ANL C, /bit ORL C, bit ORL C, /bit CLR C CLR bit bit can be any of the bit-addressable CPL C RAM locations or SFRs. CPL bit SETB C SETB bit
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Rotate and Multiplication/Division

Note that a shift left is the same as multiplying by 2, shift right is divide by 2
mov a, #3 ; A 00000011 (3) clr C ; C 0 rlc a ; A 00000110 (6) rlc a ; A 00001100 (12) rrc a ; A 00000110 (6)
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Shift/Multiply Example
Program segment to multiply by 2 and add 1 clr c rl a ;multiply by 2 inc a ;and add one

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EE/CS-152: Microprocessors and Microcontrollers

Be Logical..
Logical Operations Exercise Part 2

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Program Flow Control

Unconditional jumps (go to) Conditional jumps Call and return

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Unconditional Jumps
SJMP <rel addr> ; Short jump, relative
address is 8-bit 2s complement number, so jump can be up to 127 locations forward, or 128 locations back. LJMP <address 16> ; Long jump

AJMP <address 11> ; Absolute jump to

anywhere within 2K block of program memory JMP @A + DPTR ; Long indexed jump

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Infinite Loops

Start: mov C, p3.7 mov p1.6, C sjmp Start

Microcontroller application programs are almost always infinite loops!

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EE/CS-152: Microprocessors and Microcontrollers

Re-locatable Code
Memory specific (NOT Relocatable) cseg at 8000h mov C, p1.6 mov p3.7, C ljmp 8000h end Relocatable cseg at 8000h Start: mov C, p1.6 mov p3.7, C sjmp Start end

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Conditional Jumps
These instructions cause a jump to occur only if a condition is true. Otherwise, program execution continues with the next instruction. loop: mov a, P1 jz loop ; if a=0, goto loop, ; else goto next ; instruction mov b, a

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EE/CS-152: Microprocessors and Microcontrollers

Conditional jumps
Mnemonic
JZ <rel addr> JNZ <rel addr> JC <rel addr> JNC <rel addr> JB <bit>, <rel addr> JNB <bit>,<rel addr> JBC <bit>, <rel addr> CJNE A, direct, <rel addr>
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Description Jump if a = 0 Jump if a != 0 Jump if C = 1 Jump if C != 1 Jump if bit = 1 Jump if bit != 1 Jump if bit =1, clear bit Compare A and memory, jump if not EE/CS-152: equal Microprocessors and
Microcontrollers

Conditional Jumps for Branching

if condition is true
goto label
conditio fals n
tru e labe l e

else
goto next instruction

if a = 0 is true
send a 0 to LED

else
send a 1 to LED

led_off: skipover:

jz led_off setb C mov P1.6, C sjmp skipover clr C mov P1.6, C mov A, P0

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EE/CS-152: Microprocessors and Microcontrollers

More Conditional Jumps

Mnemonic
CJNE A, #data <rel addr> CJNE Rn, #data <rel addr> CJNE @Rn, #data <rel addr> DJNZ Rn, <rel addr>

Description Compare A and data, jump if not equal Compare Rn and data, jump if not equal Compare Rn and memory, jump if not equal Decrement Rn and then jump if not zero Decrement memory and then jump if not zero
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DJNZ direct, <rel addr>

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Iterative Loops
For A = 0 to 4 do {}
clr a loop: ... inc a cjne a, #4, loop

For A = 4 to 0 do {}
mov R0, #4 loop: ... ... djnz R0, loop

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EE/CS-152: Microprocessors and Microcontrollers

Branch and Jump

Fun with the LED

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Call and Return

Call is similar to a jump, but
Call instruction pushes PC on stack before branching Allows RETURN back to main program Absolute call
acall <address ll>

; PC

; stack address 11

PC

Long call
lcall <address 16> ; stack ; PC Cherrice Traver 16 address Prof. PC
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Return
Return is also similar to a jump, but
Return instruction pops PC from stack to get address to jump to
ret ; PC stack

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Subroutines
call to the subroutine

Main: ... acall sublabel ... ... sublabel:... ... ret

the subroutine

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Initializing Stack Pointer

The Stack Pointer (SP) is initialized to 0x07. (Same address as R7) When using subroutines, the stack will be used to store the PC, so it is very important to initialize the stack pointer. Location 2F is often used.

mov SP, #0x2F

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Subroutine - Example
$include (c8051f020.inc) GREEN_LED equ P1.6 cseg at 0 ljmp Main cseg at 0x100 Main: mov WDTCN, #0DEh mov WDTCN, #0ADh orl P1MDOUT,#40h mov XBR2, #40h clr GREEN_LED Again: acall Delay cpl GREEN_LED sjmp Again Delay: mov R7, #02 Loop1: mov R6, #00h Loop0: mov R5, #00h djnz R5, $ djnz R6, Loop0 djnz R7, Loop1 ret END Prof. Cherrice Traver

reset vector

main program

subroutin e

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Subroutine another example

; Program to compute square root of value on Port 3 (bits 3-0) and ; output on Port 1. $INCLUDE (C8051F020.inc) cseg at 0 reset ljmp Main Main: mov P3MDOUT, #0 ; Set open-drain mode vector mov P3, #0xFF ; Port 3 is an input mov P1MDOUT, #0xFF ; Port 1 is an output mov XBR2, #40h ; Enable crossbar loop: mov a, P3 anl a, #0x0F ; Clear bits 7..4 of A lcall sqrt mov P1, a sjmp loop sqrt: inc a movc a, @a + PC ret squares: db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3 end

main program

subroutin e dat a

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EE/CS-152: Microprocessors and Microcontrollers

Why Subroutines?
Subroutines allow us to have "structured" assembly language programs. This is useful for breaking a large design into manageable parts. It saves code space when subroutines can be called many times in the same program.

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EE/CS-152: Microprocessors and Microcontrollers

Timeout for Subroutines....

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Interrupts
mov a, #2 mov b, #16 mul ab mov R0, a mov R1, b mov a, #12 mov b, #20 mul ab add a, R0 mov R0, a mov a, R1 addc a, b mov R1, a end

interrup t

ogram xecution

ISR: orl P1MDIN, #40h orl P1MDOUT,#40h setb P1.6 here: sjmp here cpl P1.6 reti

retur n

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EE/CS-152: Microprocessors and Microcontrollers

Interrupt Sources
Original 8051 has 5 sources of interrupts
Timer 1 overflow Timer 2 overflow External Interrupt 0 External Interrupt 1 Serial Port events (buffer full, buffer empty, etc)

Enhanced version has 22 sources

More timers, programmable counter array, ADC, more external interrupts, another serial port (UART)
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Interrupt Process
If interrupt event occurs AND interrupt flag for that event is enabled, AND interrupts are enabled, then: 1. Current PC is pushed on stack. 2. Program execution continues at the interrupt vector address for that interrupt. 3. When a RETI instruction is encountered, the PC is popped from the stack and program execution resumes where it left off.

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Interrupt Priorities
What if two interrupt sources interrupt at the same time? The interrupt with the highest PRIORITY gets serviced first. All interrupts have a default priority order. (see page 117 of datasheet) Priority can also be set to high or low.

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Interrupt SFRs

Interrupt enables for the 5 original 8051 interrupts: Timer 2 Serial (UART0) Global Interrupt Enable 1 Timer must be set to 1 for External 1 any interrupt to be Timer 0 1 = enabled External Enable 0 0= Disable
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Another Interrupt SFR

Comparator 1 rising edge Comparator 1 falling edge

Program Counter Array ADC0 Window Comparison System Management Bus SPI Interface
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Comparator 0 rising edge Comparator 0 falling edge

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Another Interrupt SFR

External ADC Clock 1 source Serial Valid (UART) 1 External 7 External 6

Timer 4

ADC 0 Timer 3

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External Interrupts
/INT0 (Interrupt 0) and /INT1 (Interrupt 1) are external input pins. Interrupt 6 and Interrupt 7 use Port 3 pins 6 and 7:
INT 6 = P3.6 INT 7 = P3.7

These interrupts can be configured to be

rising edge-triggered falling edge-triggered
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External Interrupts

Interrupt flags: 0 = no falling edges detected since bit cleared 1 = falling edge detected

Interrupt Edge Configuration: 0 = interrupt on falling edge 1 = interrupt on rising edge

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EE/CS-152: Microprocessors and Microcontrollers

Example Configuration
Configure Port 3, bit 7 (the pushbutton switch) to interrupt when it goes low.
anl P3MDOUT, #0x7F ; Set P3.7 to be an input setb P3.7 mov XBR2, #40h ; Enable crossbar switch mov P3IF, #0 ; Interrupt on falling edge mov EIE2, #020h ; Enable EX7 interrupt mov IE #80h ; Enable global interrupts

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Interrupt Vectors
Each interrupt has a specific place in code memory (a vector) where program execution (interrupt service routine) begins (p17). Examples:
External Interrupt 0: 0x0003 Timer 0 overflow: 0x000B External Interrupt 6: 0x0093 External Interrupt 7: 0x009B
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Note that there are only 8 memory locations between vectors.

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Interrupt Vectors
To avoid overlapping Interrupt Service routines, it is common to put JUMP instructions at the vector address. This is similar to the reset vector.
cseg at 009B ; at EX7 vector ljmp EX7ISR cseg at 0x100 ; at Main program Main: ... ; Main program ... EX7ISR:... ; Interrupt service routine ... ; Can go after main program reti ; and subroutines.
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Example Interrupt Service Routine

; EX7 ISR to blink the LED 5 times.
; Modifies R0, R5-R7, bank 3. ;----------------------------------------------------

ISRBLK: push PSW ; save state of status word mov PSW, #18h ; select register bank 3 mov R0, #10 ; initialize counter Loop2: mov R7, #02h ; delay a while Loop1: mov R6, #00h Loop0: mov R5, #00h djnz R5, $ djnz R6, Loop0 djnz R7, Loop1 cpl P1.6 ; complement LED value djnz R0, Loop2 ; go on then off 10 times pop PSW mov P3IF, #0 ; clear interrupt flag reti Cherrice Traver Prof. EE/CS-152: Microprocessors and
Microcontrollers

Key Thinks for ISRs

Put the ISR vector in the proper space using a CSEG assembler directive and long jump Save any registers/locations that you use in the routine (the stack is useful here) Clear the interrupt flag (unless it is cleared by hardware) Dont forget to restore any saved registers/locations and to put the RETI Prof. Cherrice Traver EE/CS-152: Microprocessors and at the end! Microcontrollers

Practice Interrupting

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EE/CS-152: Microprocessors and Microcontrollers