SL NO.

QUESTION
Why excess 3 code is known as self-complementing
1
code?
2 Find the decimal equivalent for (101101.10101)2
Perform the following conversion: Binary to gray code:
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Binary: (101011)2.
Perform the following conversion: Decimal (432)10 to
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BCD code
Perform the following conversion: Decimal (234)10 to
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Excess 3
6 What is BCD code? Write the full form of EBCDIC.
7 Subtract 10001002 from 10101002 using 2’s Complement method.
8 Find the 2’s complement of 1101001.
9 Perform the BCD addition for (57)10 and (26)10.
10 Find the 9’s & 10’s complement of 6423
11 Convert 62.04 to binary, decimal and hexadecimal
12 Subtract using 1’s complement subtraction: (13)10 - (11)10
13 Subtract using 2’s complement subtraction: (12)10 - (3)10
14 State De-Morgan’s law and verify it with the truth table.
15 Why is Gray code called a unit distance code.
Minimize the expression using k-map method
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F(A,B,C)= m(1,2,3,5,7)
17 What is prime implicant & essential prime implicant?
Draw the basic block diagram of a 4:1 Multiplexer (with
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all notations available)
19 Why demultiplexer is also called as a data distributor?
Draw the basic block diagram of a 2 bit magnitude
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comparator
21 What do you understand by microoperation?
22 Define single precision format with example.
23 Define addressing mode.
24 Differentiate RISC and CISC architecture.
25 The number of bits required to represent 128 different numbers is
 Reduce the following expressions using Boolean
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algebra:(A+B+C) (A+B’+C) (A+B+C’)
Reduce the following expressions using Boolean
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algebra: XY+XZ+YZ’
Prove the following expressions using Boolean algebra
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rules/theorem: (A+B) (A+B’) (A’+B) (A’+B’) = 0
Solve using K-map: Y (A,B,C,D) = C’ (A’B’D’+D) +
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AB’C + D’
. Suppose only one multiplexer and one inverter are allowed to be
5 used to implement any Boolean function of n variables. What is the
minimum size of the multiplexer needed?
6 Let f(w, x, y, z) = ∑ (0, 4, 5, 7, 8, 9, 13, 15).Minimize it.
Consider a Boolean function f(w, x, y, z). Suppose that exactly one of
its inputs is allowed to change at a time. If the function happens to be
true for two input vectors i1 = (w1, x1, y1, z1) and i2 = (w2, x2, y2,
7 z2), we would like the function to remain true as the input changes
from i1 to i2 (i1 and i2 differ in exactly 1 bit position), without
becoming false momentarily. Let f(w, x, y, z) = (5, 7, 11, 12, 13, 15).
Which covers of f will ensure that the required property is satisfied?
Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2’s complement
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numbers. Their product in 2’s complement is
A 4-bit carry look-ahead adder, which adds two 4-bit numbers, is
designed using AND, OR, NOT, NAND, NOR gates only. Assuming
that all the inputs are available in both complemented and
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uncomplemented forms and the delay of each gate is one time unit,
what is the overall propagation delay of the adder? Assume that the
carry network has been implemented using two-level AND-OR logic.
A circuit outputs a digit in the form of 4 bits, where 0 is represented
by 0000, 1 by 0001, …, 9 by 1001. A combinational circuit is to be
10 designed which takes these 4 bits as input and output 1 if the digit ≥5,
and 0 otherwise. If only AND, OR and NOT gates are used, what is
the minimum number of gates required?
. Consider a multiplexer with X and Y as data inputs and Z as control
input. Z = 0 selects input X, and Z = 1 selects input Y. What are the
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connections required to realize the 2-variable Boolean function f = T
+ R, without using any additional hardware?
How many 3-to-8 line decoders with an enable input are needed to
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construct a 6-to-64 line decoder without using any other logic gates?
How many 32 K × 1 RAM chips are needed to provide a memory
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capacity of 256 K-bytes?
14 Write short notes on : CLA,ENCODER
15 P is a 16-bit signed integer. The 2’s complement representation of P
is (F87B)16. The 2’s complement representation of 8×P is
 What is the minimum number of 2-input NOR gates
required to implement 4-variable function expressed in sum-of-
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minterms from as f = (0, 2, 5, 7, 8,
10, 13, 15)?
Draw a NAND logic diagram that implements the
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complement of the following function F(A,B,C,D)= (0,1,2,3,4,8,9,12)
Design a combinational circuit which performs
3 EXCESS-3 code to BCD code conversion using minimum number of
logic gates.
Draw and explain the logic diagram of a half adder
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using only NOR gates.
Simplify the Boolean function using K-map
5 F (A, B, C, D) =m(4,5,6,7,8)
d (A, B, C, D) = m(11,12,13,14,15)
In a look-ahead carry generator, the carry generate function Gi and
the carry propagate function Pi for inputs Ai and Bi are given by Pi =
Ai ⊕ Bi and Gi = Ai Bi The expressions for the sum bit Si and the
carry bit Ci+1 of the look-ahead carry adder are given by Si = Pi ⊕ Ci
and Ci + 1 = Gi + Pi Ci , where C0 is the input carry. Consider a two-
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level logic implementation of the look-ahead carry generator. Assume
that all Pi and Gi are available for the carry generator circuit and that
the AND and OR gates can have any number of inputs. The number
of AND gates and OR gates needed to implement the look-ahead
carry generator for a 4-bit adder with S3
If all the flip-flops were reset to 0 at power on, what is the total
number of distinct outputs (states) represented by PQR generated by
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the counter? . The minimum number of D flip-flops needed to
design a Mod-258 counter is
A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8).
The number of 2 × 4 decoders with enable line needed to construct a
8 16K × 16 RAM from 1K × 8 RAM is? How many 3 × 8 decoders are
needed to construct
4 × 16 decoder?
9 Design a Full Adder circuit using NAND Gate only.
10 Design 4X6 Decoder using 3X8 Decoder