See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/346720334

FinFET technology considerations for circuit design

(invited short course)

Conference Paper · November 2020

CITATIONS READS

0 3,837

1 author:

Alvin Leng Sun Loke

Intel
102 PUBLICATIONS 906 CITATIONS

SEE PROFILE

All content following this page was uploaded by Alvin Leng Sun Loke on 10 December 2020.

The user has requested enhancement of the downloaded file.

 Short Course

FinFET Technology Considerations

for Circuit Design
Alvin L.S. Loke
NXP Semiconductors
San Diego, CA

11/16/20 BCICTS 2020 Monterey, CA Slide 1

 Semiconductor Demand
Product Units
(millions) Ubiquitous Mobile
100,000
Computing HPC
Mobile Auto
10,000 Computing
Personal IoT
1000
Computing
100
10
Mainframe
1
Computing Hou, TSMC [1]
0.1
0.01
Node

1960 1970 1980 1990 2000 2010 2020 2030

11/16/20 BCICTS 2020 Monterey, CA Slide 2

 Moore’s Law – Scaling Reduces Cost

Dennard Scaling Strain+HKMG FinFET+DTCO

10M
Inverter
1M
Relative Density

SRAM
100k
Logic gates
10k
Transistors
1k (microprocessors)
100
10
1
1970 1980 1990 2000 2010 2020
Wong, TSMC [2]
11/16/20 BCICTS 2020 Monterey, CA Slide 3
 Outline
 Evolution to FinFET
 Technology Scaling Enablers
 Design Realities
 Design Strategies
 What’s Ahead
 Conclusion

11/16/20 BCICTS 2020 Monterey, CA Slide 4

 Outline
 Evolution to FinFET
• Dennard Scaling
• Extending Dennard Scaling – Mechanical Strain & HKMG
• Fully Depleted Device
 Technology Scaling Enablers
 Design Realities
 Design Strategies
 What’s Ahead
 Conclusion

11/16/20 BCICTS 2020 Monterey, CA Slide 5

 Short-Channel Effects (SCEs)
 Area scaling ➜ smaller Contacted Gate Pitch (CGP) ➜ smaller Lgate
 Scaling Lgate weakens gate control of body depletion & channel formation
• More S/D junction control of body depletion ➜ VT rolloff
• VDS increases drain-side depletion ➜ drain-induced barrier lowering (DIBL)
CGP
Lgate contact
VT VT
gate
DIBL
source drain

body (well) Lgate VDS

11/16/20 BCICTS 2020 Monterey, CA Slide 6
 Dennard Scaling Recipe
Original Device Scaled Device
(Factor of α)

Lg ⇩ ➜ xD ⇩ ➜ NA ⇧ ➜ tox ⇩ ➜ V ⇩
Dennard et al., IBM [3] / Frank et al., IBM [4]

11/16/20 BCICTS 2020 Monterey, CA Slide 7

 Not Bad for 3 Decades
 10+ nodes: 10µm to 0.13µm
gate
 Almost 100x reduction in Lgate & tox spacer
 Innovations to extend short-channel control S/D
extension
1. Optimized body doping profile halo poly
• Lateral halo implants for higher local gate
doping under gate edge
• Vertical retrograded well with shallow S/D
surface VT implant STI
retrograded well
2. Gate spacer for self-aligned halo,
S/D extension & S/D
• Shallow junction with extension
• Short extension to reduce resistance STI = Shallow Trench Isolation

11/16/20 BCICTS 2020 Monterey, CA Slide 8

 Obstacles to Continued Dennard Scaling
 Higher body doping
• Dopant scattering ➜ channel mobility µ ⇩
 Thinner gate dielectric Igate
• Severe tunneling leakage through nitrided oxide
• High-ρ poly-Si gate depletion & channel quantum
confinement limited further tox scaling quantum
confinement
 Innovations
poly
1. Channel strain
depletion
2. High-K (HK) Gate Dielectric & Metal Gate (MG)

Wong, IBM [5]

11/16/20 BCICTS 2020 Monterey, CA Slide 9

 Mechanical Strain for Mobility Boost
 Exploit silicon’s piezoresistivity  Works for short channel only,
 1% channel strain can increase µ (reduce not effective for long channel
carrier m*) several times  Techniques
 Surround channel with several-GPa • SiGe & SiC/SiP source/drain
stressors (steel yields at 0.8GPa) • Stress memorization
 Increase Ion for same Ioff & Cox • Dielectric stress liners
 NMOS & PMOS want opposite stress along • Strained gate & contact
Lgate, but desired stress is anisotropic
tension  faster NMOS compression  faster PMOS

Chan et al., IBM [6]

11/16/20 BCICTS 2020 Monterey, CA Slide 10
 High-K Gate Dielectric & Metal Gate
 Extends Cox or EOT scaling N metal P metal
• Thicker HfO2 HK gate dielectric ➜ less Igate fill fill
• Conductive MG work function (𝜙𝜙M) layer & HK 𝜙𝜙MN 𝜙𝜙MP
more conductive metal fill ➜ less gate depletion
 Different 𝜙𝜙M needed to replace n+ & p+ poly
 Multiple VT still tuned through body doping
 Lots of integration challenges
• Replacement metal gate (RMG) for stable VT NMOS PMOS
with thermally delicate HK-MG interface
• Silicide-last (after contact etch) to accommodate silicide in
HK post-deposition anneal for reliability trench contact
EOT = Equivalent Oxide Thickness Auth et al., Intel [7] / Packan et al., Intel [8] / Kirsch et al., IBM [9]
11/16/20 BCICTS 2020 Monterey, CA Slide 11
 End of Dennard Scaling
 Subthreshold FET = BJT with base (𝜙𝜙s) controlled by COX vs. (CB+CD)
 Scaling mandates higher body doping & shorter Lgate ➜ higher CB & CD
 Higher subthreshold swing (mV/decade) incongruent with VT & VDD scaling
 Performance with Lgate scaling comes with high leakage
VGS gate gate control DIBL
(what we want)
Cox VDS
body
𝜙𝜙s drain
source source effect
CB CD
VGS drain
VDS
body VBS |VBS|
11/16/20 BCICTS 2020 Monterey, CA Slide 12
 Turning to Fully Depleted Devices
 Body dopants mirror gate charge ➜ dipoles, electric fields ➜ surface inversion
 Surface dopants not fundamental to field-effect action
 Move dopants away from surface to create extremely retrograded well
 Undoped surface has no charge to offer ➜ becomes fully depleted
• Less channel scattering ➜ µ ⇧
fully
• Fewer field lines from drain ➜ DIBL ⇩
depleted
• Geometry-based vs. dopant-based undoped
(analogous to parallel-plate capacitor) gate
surface
+++++++++++ +++++++++++
 Implementation options
• Planar on bulk (not easy)
• Planar on SOI (FD-SOI)
• 3-D on bulk (finFET)
• 3-D on SOI (not needed) Yan et al., Bell Labs [10] / Fujita et al., Fujitsu [11] / Cheng et al., IBM [12]
11/16/20 BCICTS 2020 Monterey, CA Slide 13
 Enabling Disruptive VT & VDD Scaling

VGS gate log (ID) log (ID)

IDsat IDsat
Cox VDS SS IDlin SS IDlin
ϕs drain
source
CB CD Ioff Ioff

DIBL DIBL
body VBS VGS V
VTsat VTlin VDD VTsat VTlin VDD GS

 Fully depleted device reduces CB & CD ➜ SS, DIBL, body effect ⇩

 VT & VDD can scale for lower power at given Ion & Ioff
11/16/20 BCICTS 2020 Monterey, CA Slide 14
 Less DIBL  Better Analog & Digital
2
2 Vin
IDsatVGS
Vin Vout
IHI (no-DIBL) Vout 3
VDD 1
Drain Current, ID

Ieff (no-DIBL)
IHI  IDsat underestimates CV/I switching delay
Ieff ILO ILO + IHI
 Use Ieff =
½VDD 2
inverter
switching trajectory 1 ILO @ VGS=½VDD, VDS=VDD
IHI @ VGS=VDD, VDS=½VDD
3 ½VDD VDD
Drain Voltage, VDS  Less DIBL ➜ Ieff ⇧, not just rout
Na et al., IBM [13] / Wei et al., Stanford [14]
11/16/20 BCICTS 2020 Monterey, CA Slide 15
 Outline
 Evolution to FinFET
 Technology Scaling Enablers
• FinFET Device
• Lithography & Self-Aligned Patterning
• Mechanical Stressors & HKMG for FinFET
• Middle-End-Of-Line (MEOL) & Self-Aligned Contacts
• Other Design/Technology Co-Optimization (DTCO) Innovations
 Design Realities
 Design Strategies
 What’s Ahead
 Conclusion
11/16/20 BCICTS 2020 Monterey, CA Slide 16
 Planar FET  Tri-Gate FinFET
p-well fully depleted p-well
channel tie n+ drain
n+ drain body tie
gate
NMOS
n+ source n+ source
STI STI
p-well p-well
p-substrate p-substrate
n-well n-well
p+ drain tie
p+ drain tie
PMOS
p+ source p+ source
n-well n-well
p-substrate p-substrate
STI = Shallow Trench Isolation Huang et al., UC Berkeley [15] / Auth et al., Intel [16]
11/16/20 BCICTS 2020 Monterey, CA Slide 17
 Properties of Fully Depleted FinFET
 More Ion & gm per area with Weff ~ 3-4x fin pitch
fully  Quantized channel width
depleted • Challenge for SRAM & logic
body
drain well tie • Not big issue for analog (low gm per fin)
 Less DIBL ➜ higher rout & intrinsic gain
 Negligible body effect (ΔVT < 10mV)
source  Less mismatch ➜ no RDF
STI • Variation depends on area & geometry
well
 Parasitics
p-substrate • High S/D resistance & coupling to gate
• Fin width ≪ fin pitch ➜ low Cj, high Rwell
 1/f noise comparable to much worse
Hsueh et al., TSMC [17] /
Loke et al., Qualcomm [18]
 Higher self-heating density ➜ reliability concerns

11/16/20 BCICTS 2020 Monterey, CA Slide 18

 Analog/Mixed-Signal (AMS) Dashboard
1.2x 1.2x 5x
planar finFET
1.0x
planar finFET  Lower power
1.0x 4x Lower leakage
VDDmax 0.8x rout 
3x  Better switches
0.8x 0.6x
0.4x 2x gm  Higher intrinsic gain
VDDnom
0.6x
0.2x Ioff 1x  Better mismatch
planar finFET
0.4x 0.0x 0x Smaller area
28nm 16nm 7nm 28nm 16nm 7nm 28nm 16nm 7nm 
1.2x 1.2x 1.2x
planar finFET planar finFET  Good PPA story,
1.0x
1.0x
0.8x
1.0x
mismatch if you only use FETs
VT
0.8x 0.6x 0.8x  AMS scaling benefits
0.4x Ron saturating after first
0.6x 0.6x
0.2x planar finFET migration to finFET
0.4x 0.0x 0.4x
28nm 16nm 7nm 28nm 16nm 7nm 28nm 16nm 7nm Loh, Mediatek [19]

11/16/20 BCICTS 2020 Monterey, CA Slide 19

 Foundry Pitch Scaling
40 28 20 16/14 10 7nm  Physical scaling rate slower than 0.7x
200 per node ➜ getting incremental
Minimum Pitch (nm)

10 metal gate  Node name tied to area scaling,

80
0 no longer linked to Lgate
60
193i single  13.5nm Extreme Ultra-Violet (EUV)
40 exposure limit
fin only started in production at 7nm
20 0.7x  Process complexity & cost for sub-76nm
per 2 years pitch without EUV
Yang, Qualcomm [20] / Wu et al., TSMC [21] /
Wu et al., TSMC [22] / Cho et al., Samsung [23]

11/16/20 BCICTS 2020 Monterey, CA Slide 20

 Lithography Innovations
Pitch Splitting Orthogonal Cutting
 Interleave two or more exposures  Extra mask(s) to break line patterns
 Mask color decomposition & balance  Reduced end-to-end spacing
 Limited by overlay between masks  Limited by cut mask overlay
(X direction) (Y direction)
cut mask
Mask pattern
A

Mask
B

Arnold et al., ASML [24] Auth et al., Intel [7]

11/16/20 BCICTS 2020 Monterey, CA Slide 21

 Spacer-Based Self-Aligned Patterning
 Pattern fins, short-channel gates, MEOL & lower BEOL (Back-End-Of-Line)
 Results in sea of spacers with single feature width
 Conformal spacer ➜ correlated line edge roughness ➜ less width variation
sacrificial Spacer 1
mandrel SADP

Spacer 2 SAQP
top
view

mandrel = shape for forming sidewall spacers Choi et al., UC Berkeley [25]
11/16/20 BCICTS 2020 Monterey, CA Slide 22
 Variations of Spacer-Based Patterning
Spacer Trim Mask SADP/SAQP + Block Mask
 Extra mask to trim spacers for extra  Extra mask to bridge spacers prior to
feature width prior to etch etch for more flexible metal space
 Example: Lmin & Lmin+Δ gates  Adjust mandrel width/space for more
trim mask
flexible metal width/space

block mask

Lmin+Δ Lmin

Loke et al., Qualcomm [18] Woo et al., Globalfoundries [26]

11/16/20 BCICTS 2020 Monterey, CA Slide 23
 Extreme Ultra-Violet (EUV) Lithography
Entry in 7nm production Many 193i masks (pitch-split, cut,
 High source power & sensitive resist block masks) ➜ one EUV mask
for high throughput  Process simplicity, fewer defects
 13.5nm λ ➜ reflective mask/optics  Simpler OPC & DRC, better overlay
reflective  Reduced cycle time  cost saving
mask
reflective Five 193i masks
illuminator One EUV mask
optics (mirrors)
reflective
EUV source projection
optics (mirrors)

Chang et al., NTU [27]

wafer
Yeap et al., TSMC [28]

11/16/20 BCICTS 2020 Monterey, CA Slide 24

 Mechanical Stressors in FinFET
 Same basic idea
• Tensile for NMOS, compressive for PMOS
• 3D very complex – (110) sidewall vs. (100) top
• Limited options: S/D fin recess & epitaxy
NMOS
• Limited stressor volume with CGP scaling
 Far more effective for PMOS ➜ β ratio ➞ 1
 Stress (hence µ) depends on OD length/width/space
& S/D volume
• Layout-Dependent Effects (LDEs)
• Pre/post-layout simulation gap PMOS

OD = Oxide Definition (active area)

11/16/20 BCICTS 2020 Monterey, CA Slide 25
 HKMG in FinFET
 Small fin volume & severe RDF
gate HKMG
➜ doping-based VT tuning not S/D
cap over gate
feasible beyond 14nm trench
fin spacer
contact
• VT tuning through VFB
(MG composition & HK dipole)
 MG layer(s) very resistive
• Effective gate 𝜙𝜙M influenced by
metal fill composition & thickness
• Complex VT vs. Lgate silicide fins with S/D
 High Rgate in short Lgate only at metal fill epitaxial fill
bottom of 𝜙𝜙M metal
 High S/D resistance with silicide last contact HK dielectric
RDF = Random Dopant Fluctuation
VFB = flatband voltage
11/16/20 BCICTS 2020 Monterey, CA Slide 26
 Refresher on VFB (Flatband Voltage)
Energy Band Diagram inversion
layer
silicon
surface
𝑉𝑉𝑇𝑇 = 𝑉𝑉𝐹𝐹𝐹𝐹 + ∆𝑉𝑉𝐺𝐺𝐺𝐺,𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓→𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖𝑖 EC φ
EF Ei s
EF
EV
“offset” flatband inversion

𝑄𝑄𝑓𝑓 1 𝑡𝑡𝑜𝑜𝑜𝑜 MG 𝜙𝜙M

𝑉𝑉𝐹𝐹𝐹𝐹 = 𝜙𝜙𝑀𝑀 − 𝜙𝜙𝑆𝑆 − − ∫ 𝑥𝑥𝜌𝜌 𝑥𝑥 𝑑𝑑𝑑𝑑
𝐶𝐶𝑜𝑜𝑜𝑜 𝜖𝜖𝑜𝑜𝑜𝑜 0 −𝑄𝑄𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑
𝑡𝑡𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑
𝑡𝑡𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑 𝑡𝑡𝑜𝑜𝑜𝑜 HK ++++++ +𝑄𝑄𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑
≈ 𝜙𝜙𝑀𝑀 − 𝜙𝜙𝑆𝑆 − 𝑄𝑄𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑
𝜖𝜖𝑜𝑜𝑜𝑜
Pierret, Purdue [29]
silicon
11/16/20 BCICTS 2020 Monterey, CA Slide 27
 Complex Middle-End-Of-Line (MEOL)
 Tight CGP ➜ tough to land diffusion & gate contacts without shorts
 Dielectric caps protect gate & contact to prevent gate-to-diffusion shorts
➜ self-aligned diffusion contacts (SACs) & self-aligned gate contacts
 More via/contact interfaces from metal to FET ➜ higher FET access resistance

metal contact metal

dielectric
diffusion gate cap self-aligned self-aligned
contact contact S/D via gate contact
gate
dielectric self-
gate cap aligned
contact
CGP = Contacted Gate Pitch Yang, Qualcomm [20]

11/16/20 BCICTS 2020 Monterey, CA Slide 28

 Self-Aligned Contact (SAC)
 Allows misaligned contact to overlap with gate without contact-to-gate short
 Recess gate after RMG CMP, then inlay insulator on top of gate
➜ protects gate during contact etch
nitride 100%
misalignment cap

Dies Passing
80%

contact 60%
40%
20%
gate
S/D 0%
-20 -10 0 +10 +20
Contact-to-Gate (CTG) Shift (nm)
Auth et al., Intel [16]

11/16/20 BCICTS 2020 Monterey, CA Slide 29

 Self-Aligned Gate Contact
 Land gate contact directly on top of gate on active, not on gate overhang
 Less space between OD rows ➜ shorter standard cell height
 Reduces Rgate ➜ less non-quasistatic (NQS) effect
S/D
gate contact self-aligned
contact
on overhang gate contact
self-aligned
gate contact

S/D
gate
S/D via Yeap et al., TSMC [28] Auth et al., Intel [30]

11/16/20 BCICTS 2020 Monterey, CA Slide 30

 Gate-Cut Last for Reduced Cell Height
 Gate conventionally cut prior to RMG module
 Sidewall HK & 𝜙𝜙M metal at gate ends requires more gate overhang
 Cut gate after RMG to eliminate sidewall HKMG ➜ reduce overhang
sidewall reduced
N metal fill gate cut P metal fill
HKMG fin-to-fin spacing
𝜙𝜙MN metal 𝜙𝜙MP metal
HK

gate reduced
overhang overhang
gate cut before RMG module gate cut after RMG module
Greene et al., IBM [31]
11/16/20 BCICTS 2020 Monterey, CA Slide 31
 Single vs. Double Diffusion Break
 Dummy gates terminate OD to block epitaxy on fin ends & induce strain
 SDB eliminates dummy gate waste ➜ saves 10–20% logic area
 Aggressive isolation in SDB ➜ process/model risk, stress LDE

dummy
gates DDB SDB

OD = Oxide Definition (active area) Yang et al., Qualcomm [32]

11/16/20 BCICTS 2020 Monterey, CA Slide 32

 Fin Depopulation for Logic Density
 Fin depopulation can increase speed & power efficiency
 More fins ➜ highest speed at highest power
 Fewer fins ➜ highest speed for given power, lowest power for given speed

4-fin cell 3-fin cell 2-fin cell

4-fin

3-fin

Power
2-fin

Lu, TSMC [33] Frequency

11/16/20 BCICTS 2020 Monterey, CA Slide 33
 Outline
 Evolution to FinFET
 Technology Scaling Enablers
 Design Realities
• Analog/Mixed-Signal Device Palette
• Parasitics & Layout-Dependent Effects (LDEs)
• Layout Considerations
• Design Concurrent with Technology Development
 Design Strategies
 What’s Ahead
 Conclusion

11/16/20 BCICTS 2020 Monterey, CA Slide 34

 Stacked FET for Higher rout
 Maximum Lgate limited by HKMG CMP
 More process, model & DRC friendly than long Lgate
 µ boost in short Lgate ➜ may use less area with fewer fingers despite S/D overhead
 Intermediate diffusions degrade HF rout (gain, CMRR, …)
1.2
DC iac HF iac 240nm
1.0

Normalized rout
0.8
0.6
0.4
Lmin stack
0.2
0.0
0.01 0.10 1.00 10.00
Normalized Frequency
CMP = Chemical-Mechanical Polishing
Loke et al., Qualcomm [18]
11/16/20 BCICTS 2020 Monterey, CA Slide 35
 Thick-Oxide I/O FET
 General-Purpose I/Os still use 1.8V swing despite lower core VDD
• Peripheral ICs still made in lower cost nodes
 Challenging to keep 1.8V I/O devices
• Tighter fin pitch ➜ tough HKMG fill
• Complex level shifters to protect gate oxide & handle larger ΔVDD
• Some I/Os stopped supporting backward compatibility to enable
higher data rate & lower power
• Thinner I/O oxide, e.g., 1.2V ➜ power & area ⇩, Igate ⇧
• Challenging with nanosheet integration
tighter
 System impact fin pitch
• Chipset (SoC) / chiplet (SiP) partitioning
• More options with more system ownership
Wei et al., Globalfoundries [34]

11/16/20 BCICTS 2020 Monterey, CA Slide 36

 Resistors
Thin Film Precision Resistor Metal Gate Resistor
 HKMG made poly resistor obsolete  Free “poly” resistor
 Low temperature coefficient  Small area but higher variation
 Ends not well defined ➜ current spreading from gate density & limited Wmax
 Inserted in MEOL or above lower BEOL  Higher temperature coefficient
➜ decouples resistor integration from FEOL  Coupled to MG stack tuning of VT
 No area scaling in new node (variation-limited)

metal fill
𝝓𝝓M metal
HK dielectric
11/16/20 BCICTS 2020 Monterey, CA Slide 37
 Capacitors
MOM (Metal-Oxide-Metal) Planar MIM (Metal-Insulator-Metal)
 Pitch scaling ➜ higher cap density  Intended for supply decoupling
 Reduced AC coupling efficiency  Inserted near top of BEOL stack
(worse parasitics)  Extra process cost
 Beware of dielectric TDDB reliability  Contacted from top or via sidewall
dictating minimum metal space  High plate ESR ➜ bandwidth limitation

TDDB = Time-Dependent Dielectric Breakdown ESR = Equivalent Series Resistance

11/16/20 BCICTS 2020 Monterey, CA Slide 38
 Varactors & Inductors
Accumulation-Mode Varactor Inductor
 Fully depleted ➜ steeper C-V transition  Low-Rs thick upper Cu layer & Al RDL
 Tougher circuit biasing to use narrower  Upper BEOL unchanged node-to-node
high-slope region ➜ no area scaling
Cg  More restrictive dummy fill rules
g
finFET  Use much smaller active inductors
where noise & low Q can be tolerated
n+ n+
planar
n-well desired
p-substrate
VG
Chang et al., Xilinx [35]
Z
11/16/20 BCICTS 2020 Monterey, CA Slide 39
 Diodes & PNP-BJTs
 Ubiquitous in ESD, bandgap references & thermal sensors
 High Rwell ➜ high diode/BJT series resistance
 Stricter well tie density, guard ring & latch-up rules
 Current limited by junction area ➜ limited node-to-node scaling
emitter base collector Ideality higher
p+ n+ p+ Factor, η series RD
usable
Io/N & Io
range
Rwell
n-well p-well 1
p-substrate
Loke et al., Qualcomm [18] log(ID)
11/16/20 BCICTS 2020 Monterey, CA Slide 40
 Interconnect Resistance
 Resistance is arguably the
C
defining agony of finFET era u
design 75 2.0

Mx Capacitance (vs. 40nm)

Mx Resistance (vs. 40nm)
• High-ρ Cu barrier line not scaling 60 1.8
• High R in MEOL & lower BEOL 1.6
• C-only post-layout sims useless 45
1.4
 FET performance greatly 30
compromised by source 1.2
degeneration 15 1.0
• Every mV of source-side IR
drop matters with aggressive 0 0.8
40nm 28nm 16nm 7nm 5nm
VDD scaling
Hou, TSMC [1]

11/16/20 BCICTS 2020 Monterey, CA Slide 41

 Gate Resistance
 Rgate increases with Lgate scaling
Rgate
 Distributed RC (NQS effect) has
increasing impact on FET delay gate
 Rgate has complex horizontal & drain contact
vertical components gate
 Mitigation source
• Generally fewer fins
• Double-sided gate contact
• Self-aligned gate contacts

Wu & Chan, HKUST [36] / Lee, Intel [37]

11/16/20 BCICTS 2020 Monterey, CA Slide 42

 Gate-to-Contact Capacitance
 S/D epi & SAC form vertical plate capacitors with gate sidewall
 Worse noise coupling in many analog circuits (2 examples below)
• Adding capacitance increases area & wake-up time (burst-mode)

Worse PSRR in Kickback noise

SAC LDO regulator in LPDDR RX
Vref Vbias CGS
CGD
epi Vout Vin Vref

Vout
SAC = Self-Aligned (diffusion) Contact

11/16/20 BCICTS 2020 Monterey, CA Slide 43

 Flicker (1/f) Noise
 16nm finFET 1/f noise on par to much worse than 20nm planar
 Factors affecting surface charge trapping/detrapping
• Interfacial oxide, channel & HK material, channel orientation
• NMOS vs. PMOS, VT type, core vs. I/O, Lgate
 Very bias-dependent ➜ worse at low gate overdrive
 Cumbersome but not showstopper ➜ overcome with more area & circuit topology
Device Type Noise Ratio (FinFET:Planar)
Lgate Oxide NMOS PMOS
Minimum Core 1.1x 6.8x
72nm Core 2.4x 25.7x
200nm I/O 3.8x 9.7x Chang, Xilinx [38]

11/16/20 BCICTS 2020 Monterey, CA Slide 44

 Basic Stress LDEs
 Stronger FET stressors & interaction with surrounding STI/ILD
 Stronger layout effects ➜ more pre/post-layout simulation gap
 Models capture Δµ & ΔVT (some effects as early as 130nm)
Length of OD

Gate
OD Pitch
Width Oxide
Space

Faricelli, AMD [39] / Garcia Bardon et al., imec [40] / Bianchi et al., STMicroelectronics [41]

11/16/20 BCICTS 2020 Monterey, CA Slide 45

 Gate-Cut Stress LDE in FinFETs
 Gate cut disrupts mechanical support of continuous gate & stress near cut
 Models capture Δµ & ΔVT starting in 16/14nm

gate no gate cut with gate cut

cut impacted
device

fins

gate
compressive tensile
Yang et al., Qualcomm [32]

11/16/20 BCICTS 2020 Monterey, CA Slide 46

 HKMG LDEs
Metal Boundary Effect Density Gradient Effect (DGE)
 ΔVT near border of different 𝜙𝜙M due to  Gate density gradients ➜ ΔVT &
interdiffusion of 𝜙𝜙M variation from RMG CMP dishing
 Mitigated with gate cut but costs area  Effective 𝜙𝜙M influenced by metal fill &
 Models capture Δµ & ΔVT sidewall 𝜙𝜙M metal
 Difficult to capture in models
PMOS 𝜙𝜙M1 𝜙𝜙M metal metal fill
fins gate

NMOS 𝜙𝜙M2
fins gate

Hamaguchi et al., Toshiba [42] Yang et al., Qualcomm [43]

11/16/20 BCICTS 2020 Monterey, CA Slide 47
 Density & Floorplan Considerations
 Critical process steps are extremely sensitive to pattern density & loading
 1000s of DRCs, many very tough to pass, increasingly restrictive & foreign
 DRCs reduce unmodeled long-range systematic & random variation
➜ iterative rework of smaller cells
ADPLL partial floorplan
• Area, perimeter, gradient
• Contacts, vias, cuts, tight-pitch metal Synthesized Digital
• Larger checking windows
Transition
• Density union of multiple metal levels
Decoupling
 Floorplanning more tedious & bloated Capacitance Custom Digital
• More dummy gates, well taps, guard rings
Transition
• Wasteful transitions between different
device types & pattern densities AMS AMS

11/16/20 BCICTS 2020 Monterey, CA Slide 48

 Process Loading-Related Variation
 Local pattern density modulates deposition rate, etch rate/profile & CD
 Extremely tough to correctly capture variation in models
Deposition loading Epitaxy loading Etch loading
• Spacer width variation • S/D volume variation • Depth/profile variation
(e.g., SADP/SAQP) • Impacts S/D resistance • Impacts Lgate, fin &
• Impacts gate & metal CD & channel stress metal height

CD = Critical Dimension

11/16/20 BCICTS 2020 Monterey, CA Slide 49

 Long-Range Density-Related Variation
Rapid Thermal Annealing Chemical Mechanical Polishing
 Active & gate densities impact surface  Dishing & erosion causes density-
heat absorption during anneals dependent topography
 Non-uniform density & RTA heating  Electrical variation in STI, poly,
➜ device variation RMG, MEOL & BEOL modules
Pre-optimized Temperature 10 Normalized Metal
1.2
Gate Density Simulation Sheet Resistance

Line Space (µm)

8 1.1
6
1.0
4
0.9
2
0 0.8
0 2 4 6 8 10 Loke & Wee,
Agilent [44]
Auth et al., Intel [7] Line Width (µm)
11/16/20 BCICTS 2020 Monterey, CA Slide 50
 Commentary on FinFET Node Models
 FET models
• BSIM-CMG – based on channel surface potential, less equation fitting
• Target-based for latest nodes, more silicon influence in mature nodes
• Prone to model-vs.-silicon gap from increasing density & loading effects
• Unit cells for RF design – more accurate but more area
 BEOL models
• Electrical information provided, limited to no physical stack-up details
• Less pessimistic corners for relaxed timing closure (customer pressure)
 Usual reliability models (HCI, BTI, TDDB, EM)
• Vague allowable VDD, depends on application
 Foundries extremely paranoid to protect their technology IP from competitors
• Process corner methodologies & many model parameters encrypted
• Limited physical information available – even basic dimensions (e.g., Lgate) not real
• CD bias & mask booleans to conceal process details (e.g., RMG flow for multiple VT)
11/16/20 BCICTS 2020 Monterey, CA Slide 51
 Bleeding-Edge Product Development
 Design concurrently developed with technology to shorten product
time-to-market ➜ initial models are target-based (projections)
 Multiple models & design iterations  earlier design start & finish

Test Chip
Model Uncertainty

Speculative Silicon-Influenced Silicon-Based

Models Models Models

Initial Updated Final

Design Design Design Bair, AMD [45]

Time
11/16/20 BCICTS 2020 Monterey, CA Slide 52
 FET Modeling for Analog vs. Digital
 Technology & modeling prioritized 1.5
VGS
28nm example
to logic & SRAM core FETs VDD=1.0V IDsat
IHI 1.0V
 Lower priority for long-channel & 1.0

ID (mA)
I/O devices
Ieff 0.7V
 Device targeting & model 0.5
correlation at limited number of I-V ILO
IDlin 0.5V
& C-V points at limited VDD range Ioff
0.0
 Analog also needs accurate slope 0.0 0.2 0.4 0.6 0.8 1.0
modeling (gm, gds) which gets some VDS (V)
attention but not priority typical analog biasing
VGS =VT to VT +0.1V Feng et al., Globalfoundries [46] /
McAndrew et al., Freescale [47]
11/16/20 BCICTS 2020 Monterey, CA Slide 53
 Process Corner Model Limitations
 Corners are digital-centric
• Don’t necessarily correlate to AMS

PMOS Parameter (e.g., Ieff)

worst-case corners FF
SF
 Systematic within-die process SFG FFG
gradients typically not modeled
 Within-die random variation typically TT
captures side-by-side local mismatch FSG
• Not distance-dependent SSG
FS
SS
 Model quality only as good as
fab understanding of design usage
NMOS Parameter (e.g., Ieff)

11/16/20 BCICTS 2020 Monterey, CA Slide 54

 Pre- vs. Post-Layout Simulation Gaps
 Accept more iterations in each new node – c’est la vie!
• Never too early to start layout
 Sources of Δ
• LDEs (layout-extracted vs. schematic defaults)
• MEOL & BEOL parasitics not anticipated in schematics
 Estimated parasitics typically in pre-layout netlist
• S/D contact resistance (big help!)
• Gate resistance
• Gate-to-contact capacitance
 Making schematic more layout aware will reduce gap
• Back-annotate key parasitics into schematic
• Specify FET schematic options that estimate LDEs & parasitics

11/16/20 BCICTS 2020 Monterey, CA Slide 55

 Outline
 Evolution to FinFET
 Technology Scaling Enablers
 Design Realities
 Design Strategies
• Pattern Density, Parasitics & LDEs
• Target-Based Model Uncertainty
• Analog Cells
 What’s Ahead
 Conclusion

11/16/20 BCICTS 2020 Monterey, CA Slide 56

 Avoid Mixing Short & Long Channels
 Short Lgate patterned by SADP;
long Lgate with conventional 2nd mask
 SADP prone to spacer deposition & etch
loading with surrounding long channels
 Mixed Lgate prone to DGE from
RMG CMP preferred
 Example:
current mirror with enable devices
RMG = Replacement Metal Gate
CMP = Chemical Mechanical Polishing

Loke et al., Qualcomm [18]

11/16/20 BCICTS 2020 Monterey, CA Slide 57

 Mitigate MEOL Resistance
 Challenging for high-current circuits, e.g., I/O drivers, clock buffers
 Examples of R mitigation (despite higher C)

Double-source layout halves S/D Rcontact Extend SAC to land extra diffusion via
short together extended SAC extra S/D via
gate

fins

diffusion contact (SAC)

Loke et al., Qualcomm [18]
11/16/20 BCICTS 2020 Monterey, CA Slide 58
 Mitigate BEOL Resistance – Via Pillar
 MEOL & lower BEOL DPT layers & vias are very resistive
 Be careful to not block routing tracks with unnecessary via pillars
Connection through Layer promotion to Via pillar
DPT layer non-DPT layer

standard 20µm wire

cell

DPT wire resistance Source via Best combination of

dominates resistance increases metal & source via
DPT = Double-Patterning Technology
resistance
Hou, TSMC [1]
11/16/20 BCICTS 2020 Monterey, CA Slide 59
 Continuous OD for Performance & Matching
 µ variation in short OD
 Build up stress plateau for higher µ µ variation in constant µ in
short OD continuous OD
 Affects shortest Lgate most
(strongest LDE) OD
stress
 Pay area tax of dummy gates
in each OD
 Matched FETs also need matched
spacing to surrounding devices
dummy stress dummy
gates plateau for gates
active gates
OD = Oxide Definition (active area) Loke et al., Qualcomm [18]

11/16/20 BCICTS 2020 Monterey, CA Slide 60

 Avoid Resistors
 Precision resistor area not scaling ➜ more costly in each new node
 Migrate to resistorless topologies wherever possible
• LPDDR4 TX controlled-impedance driver (example below)
• Less CML, more CMOS

Lu et al., TSMC [48]

11/16/20 BCICTS 2020 Monterey, CA Slide 61

 Avoid BJTs & Diodes If Possible
 Bandgap references & thermal sensors
not friendly in advanced nodes
• PNP/diode & resistor area not scaling Io Io AIo
• High PNP/diode resistance ➜ smaller
diode ratios & higher variation sensitivity
• High VD from high well doping
➜ higher VDD
• Output variation dominated by mismatch N
➜ trimming, dynamic element matching
• OTA mismatch ➜ offset cancellation
 Lots of research in non-diode-based alternatives but
challenges with accuracy and single-temp calibration Banba et al., Toshiba [49]

11/16/20 BCICTS 2020 Monterey, CA Slide 62

 Mitigate Self-Heating
 Reliability concerns
• Devices (HCI, BTI, gate dielectric TDDB)
• Overlying metal (electromigration, interconnect TDDB)
 Sink heat away to substrate & metal simulated
• Insert dummies to spread devices out temperature
• Funnel heat to stacked vias & well taps rise profile
• Fewer fins (narrower OD) better
than fewer fingers (shorter OD)

FET well tap FET Liu et al., TSMC [50]

11/16/20 BCICTS 2020 Monterey, CA Slide 63

 Dealing with Target-Based Uncertainty
 Process at tapeout more immature in each new node
• More masks & longer fab cycle time (some relief from EUV)
➜ fewer cycles of silicon learning
 Process development areas, even after tapeout
• HKMG stack & RMG optimization to tune multiple VT
• S/D epitaxy, MEOL modules (contacts, vias & metal)
• Logic & SRAM area-saving constructs (SDB, S/D jumper)
 Most vulnerable (unstable) model parameters
• FET VT, µ, LDEs
• Long L & I/O FETs not top priority
• RC parasitics in S/D & MEOL
 Incorporate more design margin, but don’t overdo it

11/16/20 BCICTS 2020 Monterey, CA Slide 64

 Template-Based Analog Cells
 Technology aware for fast design closure & productivity
 Layout considerations
• Incorporate process-friendly layout guidelines
• Anticipate density concerns
• Short-channel stack to emulate long-channel FET
• Pre-defined routing tracks
• Include MEOL & lower BEOL for easier assembly
 Schematic considerations
to reduce pre/post-layout simulation gap
• Anticipate LDEs with continuous OD placement
(e.g., SA/SB override)
• Disable Rcontact in stacked FET
• Back-annotate MEOL & BEOL parasitic estimates Loke et al., Qualcomm [51]
11/16/20 BCICTS 2020 Monterey, CA Slide 65
 Outline
 Evolution to FinFET
 Technology Scaling Enablers
 Design Realities
 Design Strategies
 What’s Ahead
• FinFET Improvements
• Beyond the FinFET
 Conclusion

11/16/20 BCICTS 2020 Monterey, CA Slide 66

 Squeezing Out What’s Left in FinFETs
 Really tough after 4 finFET generations
• Realistically, never been any low hanging fruit with each new node
• Process innovations & complexity for only incremental gain
• +5% ring oscillator frequency is a big deal
 Areas of development (no stones unturned)
• Short-channel control ➜ narrower fins, tradeoff vs. µ reduction
• Channel mobility ➜ high-µ fin material, e.g., TSMC 5nm
• EOT ➜ higher K, thinner & reliable gate dielectrics
• Device variation ➜ fin uniformity & geometry control
• Volumeless VT tuning using only HK dipoles
• Rcontact ➜ contact resistivity (interface quality) & area
• Rgate ➜ selective bottom-up HKMG deposition
• CGS & CGD ➜ gate spacer K, air gap spacers
• MEOL & BEOL resistance ➜ metal resistivity, Rvia Yeap et al., TSMC [28] / Cai, TSMC [52]

11/16/20 BCICTS 2020 Monterey, CA Slide 67

 Migrating to Gate-All-Around (GAA)
 FinFET has poor short-channel control with further Lgate scaling
 Need better short-channel control & more Weff per die area
 Stacked GAA nanowires & nanosheets are promising
 Nanowires offer better SCE, nanosheets offer better area scaling
FinFET Nanowire Nanosheet stacked
nanosheet
demonstration

Cai, TSMC [52] /

Loubet et al., IBM [53]
11/16/20 BCICTS 2020 Monterey, CA Slide 68
 FinFET ➜ Nanosheet
FinFET Nanosheet Y cut X cut
W
PMOS W
S/D S/D

NMOS X cut
inner
spacer
Y cut
Gate  Current mostly flows along (100) surface (electrons , holes )
Silicon  Need inner spacers to reduce gate-to-S/D capacitance
Contact  Disable parasitic planar FET below nanosheets
Cai, TSMC [52]

11/16/20 BCICTS 2020 Monterey, CA Slide 69

 2D/1D Materials for Shorter Gate Control
 Geometry scaling requires thinner channels for shorter Lgate
 Mobility falls rapidly in very thin Si channels from surface scattering
 Intense R&D on naturally thin, atomically smooth 2D & 1D materials
10,000 2D TMD (MoS2, WSe2, WS2…)
CNT
Mobility (cm2/V-s)

1,000 WSe2 Si < 1 nm

WS2
100 TMD = Transition Metal Dichalcogenide
MoS2
10 Ge 1D carbon nanotube (CNT)

1
0 1 2 3 4
Channel thickness (nm)
Wong, TSMC [2] / Radisavljevic et al., EPFL [54]

11/16/20 BCICTS 2020 Monterey, CA Slide 70

 Conclusion
 “Moore’s Law is well and alive, it’s not even sick”
 SoC area scaling now driven primarily by device innovation & DTCO,
less by feature size reduction
 FinFET area scaling prioritizes logic & memory, not classic analog
 Design implementation needs a lot more perspiration for incremental
inspiration
 Understand & exploit technology for maximum PPA benefit &
efficient design productivity

Wong, TSMC [2]

11/16/20 BCICTS 2020 Monterey, CA Slide 71

 Acknowledgments
My friends and former colleagues at Qualcomm and TSMC
 Behnam Amelifard  Lixin Ge  Chulkyu Lee  Jacob Schneider
 Jin Cai  Baptiste Grave  Szu-Lin Liu  Eric Soenen
 Min Cao  Jonathan Holland  Lee-Chung Lu  Ray Stephany
 Mark Chen  Cliff Hou  Shih-Lien Linus Lu  Esin Terzioglu
 Alan Cheng  Kenny Hsieh  Betty McGovern  Tin Tin Wee
 Vincent Chou  Patrick Isakanian  Giri Nallapati  Philip Wong
 Patrick Drennan  Reza Jalilizeinali  Keith O’Donoghue  Da Yang
 Sreeker Dundigal  Xiaohua Kong  Dirk Pfaff  Sam Yang
 Stefano Facchin  Albert Kumar  Kern Rim  Geoffrey Yeap
 Emily Fan  Mike Leary  Alan Roth  Bo Yu

11/16/20 BCICTS 2020 Monterey, CA Slide 72

 References (1/4)
[1] C. Hou, “A smart design paradigm for smart chips,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, San Francisco, CA, USA, Feb. 5–9, 2017, pp.
8–13.
[2] H.-S. P. Wong, “IC technology – what will the next node offer us?” in HotChips, Stanford, CA, USA, Aug. 18–20, 2019, Keynote.
[3] R. H. Dennard et al., “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. 9, no. 5, pp. 256–268, Oct.
1974.
[4] D. J. Frank et al., “Device scaling limits of silicon MOSFETs and their application dependencies,” Proc. IEEE, vol. 89, no. 3, pp. 259–288, Mar. 2001.
[5] H.-S. P. Wong, “Beyond the conventional transistor,” IBM J. Research & Development, vol. 2-3, no. 46, pp. 133–168, Mar. 2002.
[6] V. Chan et al., “Strain for CMOS performance improvement,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, Sep. 18–21, 2005, pp.
667–674.
[7] C. Auth et al., “45nm high-k + metal-gate strain-enhanced transistors,” in IEEE Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, USA, Jun. 17–19,
2008, pp. 128–129.
[8] P. Packan et al., “High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors,” in IEEE Int. Electron Devices Meeting
Tech. Dig., Baltimore, MD, USA, Dec. 7–9, 2009, pp. 659–662.
[9] P. D. Kirsch et al., “Band edge n-MOSFETs with high-k/metal gate stacks scaled to EOT=0.9nm with excellent carrier mobility and high temperature
stability,” in IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, USA, Dec. 11–13, 2006, pp. 639–642.
[10] R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: from bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704–1710,
Jul. 1992.
[11] K. Fujita et al., “Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low power applications,” in IEEE Int. Electron
Devices Meeting Tech. Dig., Washington, DC, USA, Dec. 5–7, 2011, pp. 749–752.
[12] K. Cheng et al., “Fully depleted extremely thin SOI technology fabricate by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted
raised source/drain,” in IEEE Symp. VLSI Technology Dig. Tech. Papers, Kyoto, Japan, Jun. 15–18, 2009, pp. 212–213.
[13] M. Na et al., “The effective drive current in CMOS inverters,” in IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, USA, Dec. 8–11, 2002,
pp. 121–124.
[14] L. Wei et al., “Exploration of device design space to meet circuit speed targeting 22nm and beyond,” in Int. Conf. Solid State Devices and Materials, Miyagi,
Japan, Oct. 7–9, 2009, pp. 808–809.

11/16/20 BCICTS 2020 Monterey, CA Slide 73

 References (2/4)
[15] X. Huang et al., “Sub-50nm finFET: PMOS,” in IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, USA, Dec. 5–8, 1999, pp. 67–70.
[16] C. Auth et al., “A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high
density MIM capacitors,” in IEEE Symp. VLSI Technology Dig. Tech. Papers, Honolulu, HI, USA, Jun. 12–15, 2012, pp. 131–132.
[17] F.-L. Hsueh et al., “Analog/RF wonderland: circuit and technology co-optimization in advanced finFET technology,” in IEEE Symp. VLSI Technology Dig.
Tech. Papers, Honolulu, HI, USA, Jun. 13–17, 2016, pp. 114–115.
[18] A. L. S. Loke et al., “Analog/mixed-signal design challenges in 7-nm CMOS and beyond,” in Proc. IEEE Custom Integrated Circuits Conf., San Diego, CA,
USA, Apr. 8–11, 2018.
[19] K. L. Loh, “FinFETs for analog & mixed-signal designs,” in IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, Feb. 11–15, 2018, Forum F2.
[20] D. Yang, “SoC scaling challenges in the era of the single digit technology nodes,” in Int. Workshop Advanced Patterning Solutions, Beijing, China, Oct. 12–
13, 2017.
[21] S.-Y. Wu et al., “A 16nm finFET CMOS technology for mobile SoC and computing applications,” in IEEE Int. Electron Devices Meeting Tech. Dig.,
Washington, DC, USA, Dec. 9–11, 2013, pp. 224–227.
[22] S.-Y. Wu et al., “A 7nm CMOS platform technology featuring 4th generation finFET transistors with a 0.027um2 high-density 6-T SRAM cell for mobile SoC
applications,” in IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, USA, Dec. 3–7, 2016, pp. 43–46.
[23] H.-J. Cho et al., “Si finFET based 10nm technology with multi Vt gate stack for low power and high performance applications,” in IEEE Symp. VLSI
Technology Dig. Tech. Papers, Honolulu, HI, USA, Jun. 13–17, 2016, pp. 12–13.
[24] W. Arnold, M. Dusa, and J. Finders, “Manufacturing challenges in double patterning lithography,” in IEEE Int. Symp. Semiconductor Manufacturing, Tokyo,
Japan, Sep. 25–27, 2006, pp. 283–286.
[25] Y.-K. Choi, T.-J. King, and C. Hu, “A spacer patterning technology for nanoscale CMOS,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 436–441, Mar.
2002.
[26] Y. Woo et al., “Design and process technology co-optimization with SADP BEOL in sub-10nm SRAM bitcell,” in IEEE Int. Electron Devices Meeting Tech.
Dig., Washington, DC, Dec. 7–9, 2015, pp. 273–276.
[27] Y.-W. Chang, R.-G. Liu, and S.-Y. Fang, “EUV and e-beam manufacturability: challenges and solutions,” in ACM/EDAC/IEEE Design Automation Conf.,
San Francisco, CA, USA, Jun. 7–11, 2015.

11/16/20 BCICTS 2020 Monterey, CA Slide 74

 References (3/4)
[28] G. Yeap et al., “5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel finFETs with densest 0.021μm2 SRAM
cells for mobile SoC and high performance computing applications,” in IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, USA, Dec. 7–11,
2019.
[29] R.F. Pierret, “Nonideal MOS,” in Semiconductor Device Fundamentals, Reading, MA, USA: Addison-Wesley, 1996, ch. 18, pp. 645–690.
[30] C. Auth et al., “A 10nm high performance and low-power CMOS technology featuring 3rd generation finFET transistors, self-aligned quad patterning,
contact over active gate and cobalt local interconnects,” in IEEE Int. Electron Devices Meeting Tech. Dig., San Francisco, CA, Dec. 2–6, 2017, pp. 673–
676.
[31] A. K. Greene et al., “Gate-cut-last in RMG to enable gate extension scaling and parasitic capacitance reduction,” in IEEE Symp. VLSI Technology Dig.
Tech. Papers, Kyoto, Japan, Jun. 9–14, 2019.
[32] S. Yang et al., “10 nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling,” in IEEE Symp. VLSI
Technology Dig. Tech. Papers, Kyoto, Japan, Jun. 5–8, 2017.
[33] L. C. Lu, “Physical design challenges and innovations to meet power, speed, and area scaling trend,” in ACM Int. Symp. Physical Design, Keynote, Lake
Oswego, OR, USA, Mar. 19–22, 2017, Keynote.
[34] A. Wei et al., “Challenges of analog and I/O scaling in 10nm SoC technology and beyond,” in IEEE Int. Electron Devices Meeting Tech. Dig., San
Francisco, CA, USA, Dec. 15–17, 2014, pp. 462–465.
[35] K. Chang et al., “Device aware high-speed transceiver design in planar and finFET technologies,” in IEEE Int. Electron Devices Meeting Tech. Dig., San
Francisco, CA, USA, Dec. 15–17, 2014, pp. 454–457.
[36] W. Wu and M. Chan, “Gate resistance modeling of multifin MOS devices,” IEEE Electron Device Lett., vol. 27, no. 1, pp. 68–70, Jan. 2006.
[37] H.-J. Lee, “The hitchhiker’s guide to save Moore’s law in 5G era,” in IEEE Symp. VLSI Circuits, Kyoto, Japan, Jun. 9–14, 2019, Circuits Short Course.
[38] K. Chang, “High-speed wireline transceivers in finFET,” in IEEE Int. Solid-State Circuits Conf., San Francisco, CA, USA, Feb. 11–15, 2018, Forum F2.
[39] J. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, Sep. 19–
22, 2010.
[40] M. Garcia Bardon et al., “Layout-induced stress effects in 14nm & 10nm finFETs and their impact on performance,” in IEEE Symp. VLSI Technology Dig.
Tech. Papers, Kyoto, Japan, Jun. 12–14, 2013, pp. 114–115.

11/16/20 BCICTS 2020 Monterey, CA Slide 75

 References (4/4)
[41] R. A. Bianchi et al., “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance,” in IEEE Int. Electron
Devices Meeting Tech. Dig., San Francisco, CA, USA, Dec. 8–11, 2002, pp. 117–120.
[42] M. Hamaguchi et al., “New layout dependency in high-K/metal gate MOSFETs,” in IEEE Int. Electron Devices Meeting Tech. Dig., Washington, DC, USA,
Dec. 5–7, 2011, pp. 579–582.
[43] S. Yang et al., “High-performance mobile SoC design and technology co-optimization to mitigate high-K metal gate process variations,” in IEEE Symp.
VLSI Technology Dig. Tech. Papers, Honolulu, HI, USA, Jun. 9–12, 2014.
[44] A. L. S. Loke and T.T. Wee, “Introduction to copper/low-K interconnects and electromigration fundamentals,” in IEEE Solid-State Circuits Soc. Chapter
Seminar, Fort Collins, CO, USA, Sep. 12, 2003.
[45] L. Bair, “Process/product interactions in a concurrent design environment,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA, Sep. 16–
19, 2007, pp. 779–782.
[46] J. Feng et al., “Bridging design and manufacture of analog/mixed-signal circuits in advanced CMOS,” in IEEE Symp. VLSI Technology Dig. Tech. Papers,
Kyoto, Japan, Jun. 14–16, 2011, pp. 226–227.
[47] C. McAndrew et al., “Corner models: inaccurate at best, and it only gets worst…,” in Proc. IEEE Custom Integrated Circuits Conf., San Jose, CA, USA,
Sep. 22–25, 2013.
[48] T.-C. Lu et al., “A resistor-free 4.266 Gbps LPDDR4 I/O in 10nm finFET CMOS technology,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Kyoto, Japan,
Jun. 5–8, 2017 pp. 192–193.
[49] H. Banba et al., “A CMOS bandgap reference circuit with sub-1-V operation,” IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999.
[50] S.-L. Liu et al., “Self-heating temperature behavior analysis for DC-GHz design optimization in advanced finFETs,” in IEEE Symp. VLSI Technology Dig.
Tech. Papers, Kyoto, Japan, Jun. 9–14, 2019.
[51] A. L. S. Loke, C. K. Lee, and B. M. Leary, “Nanoscale CMOS implications on analog/mixed-signal design,” in IEEE Custom Integrated Circuits Conf.,
Austin, TX, USA, Apr. 14–17, 2019, Educational Session ES2-2.
[52] J. Cai, “Device Technology for 3nm Node and Beyond,” in IEEE Int. Electron Devices Meeting, San Francisco, CA, USA, Dec. 7–11, 2019, Short Course 1.
[53] N. Loubet et al., “Stacked nanosheet gate-all-around transistor to enable scaling beyond finFET,” in IEEE Symp. VLSI Technology Dig. Tech. Papers,
Kyoto, Japan, Jun. 5–8, 2017, pp. 230–231.
[54] B. Radisavljevic et al., ”Single-layer MoS2 transistors,” Nature Nanotech., vol. 6, no. 3, pp. 147–150, Jan. 2011.

11/16/20 View publication stats

BCICTS 2020 Monterey, CA Slide 76