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9:31 AM 9/25/2023 Chapter 1

Course
ME4162: Microprocessor Introduction
Semester 1, 2023 Number Representation
Lecturer: Dr. Duong Van Lac Dr. Duong Van Lac
Department of Mechatronics, HUST
Email: [email protected]

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Number Representation Decimal Numbers: Base 10

• Number Base B => B symbols per digit: • Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
• Base 10 (Decimal): 0, 1, 2, 3, 4, 5, 6, 7, 8, 9
• Example:
• Base 2 (Binary): 0, 1
3271 = (3x10^3) + (2x10^2) + (7x10^1) + (1x10^0)
• Number representation:
• dpdp-1 ... d2d1d0 is a p digit number
• value = dpx Bp + dp-1 x Bp-1 + ... + d2 x B2 + d1 x B1 + d0 x B0

• Binary: 0,1
• 1011010 = 1x26 + 0x25 + 1x24 + 1x23 + 0x22 + 1x2 + 0x1 = 64 + 16
+ 8 + 2 = 90

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Hexadecimal Numbers: Base 16 Hexadecimal Numbers: Base 16

• Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F • Example (convert hex to decimal):
B28F0DD = (Bx166) + (2x165) + (8x164) + (Fx163) + (0x162) + (Dx161)
• Normal digits have expected values + (Dx160)
= (11x166) + (2x165) + (8x164) + (15x163) + (0x162) + (13x161) +
• In addition: (13x160)
• A ➔ 10 = 187232477 decimal
• B ➔ 11
• C ➔ 12 • Notice that a 7 digit hex number turns out to be a
• D ➔ 13
9 digit decimal number
• E ➔ 14
• F ➔ 15

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Decimal vs. Hexadecimal vs. Binary Problems

1. Convert 2510 to binary.
• Examples: 00 0 0000
01 1 0001 2. Convert 110012 to decimal.
• 1010 1100 0101 (binary) 02 2 0010
= ? (hex) 3. Represent binary 100111110101 in hex.
03 3 0011
04 4 0100 4. Convert hex 29B to binary.
05 5 0101
• 10111 (binary) 06 6 0110
07 7 0111
= 0001 0111 (binary) 08 8 1000
= ? (hex) 09 9 1001
10 A 1010
11 B 1011
• 3F9(hex) 12 C 1100
13 D 1101
= ? (binary) 14 E 1110
15 F 1111

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Solutions Problems
1. Perform binary addition: 0b1101 + 0b1001. Check
against their decimal equivalents
2. Perform hex addition: 23D9 + 94BE
3. Perform hex subtraction: 59F – 2B8.
4. Convert hex 29B to binary.

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Solutions Chapter 1

Introduction
Computer Architecture
Dr. Duong Van Lac
Department of Mechatronics, HUST

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Topics Internal organization of computers

• Internal organization of computers • CPU
– The different parts of a computer • Memory
• I/O • I/O
• Memory – Input
• CPU • E.g. Keyboard, Mouse, Sensor
– Connecting the different parts – Output
• Connecting memory to CPU • E.g. LCD, printer, hands of a robot
• Connecting I/Os to CPU
– How computers work

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Memory Memory characteristics

• Everything that can store, retain, and recall • Capacity
information. – The number of bits that a memory can store.
– E.g. hard disk, a piece of paper, etc. • E.g. 128 Kbits, 256 Mbits
• Organization
– How the locations are organized 4 bits
• E.g. a 128 x 4 memory has 128 locations, 0

128 locations
1
2
4 bits each

…
• Access time 127

– How long it takes to get data from memory

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Problems Solutions
1. A given memory chip has 12 address pins and 4
data pins. Find:
(a) the organization, and (b) the capacity.

2. A 512K memory chip has 8 pins for data. Find:

(a) the organization, and (b) the number of address
pins for this memory chip.

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Memory Semiconductor memories

• Semiconductors
• ROM (Read-Only RAM (Random Access •
Memory) Memory)
– Mask ROM )Static RAM( SRAM –
– PROM (Programmable )Dynamic RAM( DRAM –
ROM) Nonvolatile ( NV-RAM –
• Non-semiconductors – EPROM (Erasable )RAM
The pictures are copied from http://www.wikipedia.org/
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM

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Memory\ROM\ Mask ROM Memory\ROM\ PROM (Programmable ROM)

• Programmed by the IC manufacturer • OTP (One-Time Programmable)
– You can program it only once

Texas TMS27PC256-20NL One time Programmable ROM

Intel 1301 Integrated Circuit (Mask ROM)

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Memory\ROM\ EPROM (Erasable Programmable ROM) Memory\ROM\ EEPROM (Electrically Erasable

Programmable ROM)
• UV-EPROM
– You can shine ultraviolet (UV) radiation to erase it • Erased Electrically RDY/BSY VCC
A12 WE
– Erasing takes up to 20 minutes A7 NC
– Erased instantly A6 8K x 8 A8
– The entire contents of ROM are erased A5 A9

– Each byte can be erased separately A4

A3
A11
OE
A2 A10
A1 CE
A0 I/O7
I/O0 I/O6
I/O1 I/O5
I/O2 I/O4
VSS I/O3

2764

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Memory\ROM\ Flash ROM Semiconductor memories

• Erased in a Flash
• the entire device is erased at once • ROM RAM •
– Mask ROM )Static RAM( SRAM –
– PROM (Programmable )Dynamic RAM( DRAM –
ROM) Nonvolatile ( NV-RAM –
– EPROM (Erasable )RAM
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM

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Memory\RAM\ SRAM (Static RAM) Memory\RAM\ DRAM (Dynamic RAM)

• Made of flip-flops (Transistors) • Made of capacitors
• Advantages: • Advantages:
– Faster 2K x 8
– Less power consumption
SRAM
– No need for refreshing – Cheaper
• Disadvantages: – High capacity
– High power consumption • Disadvantages:
– Expensive – Slower
– Refresh needed

A six-transistor CMOS SRAM cell

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Memory\RAM\ NV-RAM (Nonvolatile RAM) Internal parts of computers\CPU

• Made of SRAM, Battery, control circuitry • Tasks:

• Advantages: – It should execute instructions
– Very fast • It should recall the instructions one after another
and execute them
– Infinite program/erase cycle
– Non-volatile
• Disadvantage:
– Expensive

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Connecting memory to CPU Connecting memory to CPU

Writing
Reading to memory
from memory
• Memory pin out
VCC Address
Address
CS
CS
GND VCC OE
Data
Data
8
D0-D7 WE
n WE
A0-An-1 active low Time
Time
WE
VCC
OE
CS
GND VCC

8
- A0–An-1 are for address inputs D0-D7
- WE (write enable) is for writing data into memory (active low).
- OE (output enable) is for reading data out of memory (active low). CPU n
A0-An-1

- CS (chip select) is used to select the memory chip. WE

- D0–D7 are for data I/O OE
CS

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Connecting I/Os to CPU Connecting I/Os to CPU using bus

• CPU should have lots of pins!

Mouse

Address bus

Data bus
Write

Network
CPU Keyboard
Control bus Read

CPU
I/O 0 I/O 1 I/O 2 I/O n

Sound Card
Graphic Card

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Connecting I/Os and Memory to CPU Connecting I/Os and memory to CPU using bus
Address bus

VCC
0
1
Data bus How could we manage it? 2
3

A0-An-1
Write

GND

D0-D7
Control bus Read

WE

OE
CS
0
Address bus

Data bus
CPU I/O 0 I/O 1 I/O 2 I/O n
Write
Control bus Read
VCC

n
GND VCC
CPU
A0-An-1
8
D0-D7

I/O 0 I/O 1 I/O 2 I/O n

WE

OE
CS

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Connecting I/Os and Memory to CPU using bus Connecting I/Os and Memory to CPU using bus
(Peripheral I/O) (Memory Mapped I/O)
The logic circuit

VCC
0

VCC
0
1
1 enables CS
.. How could we make the logic ..
when address is
15

A0-An-1
GND

D0-D7
63 circuit? between 0 and

A0-An-1
GND

D0-D7

WE

OE
CS
15

WE

OE
CS
Logic circuit
Address bus
Address bus
Data bus
Solution
Data bus
Control 1.
bus Write
Write the address range in binary
Write Read
Control bus Read 2. Separate the fixed part of address
IO/MEM
3. Using a NAND, design a logic circuit whose output
CPU CPU
activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0 ➔ 0 0 0 0 0 0 0 0 a4

I/O 0 I/O 1 I/O n I/O 16 I/O 17 I/O a5

18 I/OCS
n
I/O 2 To address15 ➔ 0 0 0 0 1 1 1 1 a6
a7

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Another example for address decoder Examples

• Design an address decoder for address of 300H • Four 8K  8 memories are used together to provide a
to 3FFH. 32K  8 memory
Memory Map of System
D0
Address Range

Data
Bus
...
D7 0000H–1FFFH RAM 0
Solution D7 ... D0 D7 ... D0 D7 ... D0 D7 ... D0
2000H–3FFFH RAM 1
MEMR
OE
MEMR MEMR
OE
MEMR 4000H–5FFFH RAM 2
OE OE
MEMW WR MEMW WR MEMW WR MEMW WR 6000H–7FFFH RAM 3
1. Write the address range in binary

8Kx8 RAM2
8Kx8 RAM0

8Kx8 RAM3
8Kx8 RAM1
CPU
A13 A13 A13 A13

2. Separate the fixed part of address A14

A15
CS A14
A15
CS
A14
A15
CS A14
A15
CS

A0 A0 A0 A0 A0 A0 A0 A0

3. Design the logic circuit.

A12 A12 A12 A12 A12 A12 A12 A12

a8 a7 a6 a5 a4 a3 a2 a1 a0
a11 a10 a9 a8 a8 A0
a9
From address 300H ➔ 0 0 1 1 0 0 0 0 0 0 0 0 a10 CS

Address Bus
a11
To address 3FFH ➔ 001111111111 A12
A13
A14
A15

MEMR

Control
Bus
MEMW

An easy way of IOR

IOW

designing

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Examples Inside the CPU

• Redesign the system using 74LS138 • PC (Program Counter)
• Instruction decoder
• ALU (Arithmetic Logic Unit)

.
..
D7 ... D0 D7 ... D0 D7 ... D0 D7 ... D0
• Registers
8Kx8 8Kx8 OE 8Kx8 8Kx8

•
OE OE OE

Transfer Components Bus

WR WR

CPU RAM0 WR
RAM1 RAM2 WR
RAM3
CS A12 ... A0 CS A12 ... A0 CS A12 ... A0 CS A12 ... A0
A12 A0 A12 A0 A12 A0 A12 A0
A0
Address Bus

A12
A13
A14
A15

PC A
Control

MEMR
Bus

MEMW
IOR
IOW A13 Y0

ALU B
A
A14 B Y1
74LS138

A15 C Y2
Y3
VCC
Y4

CPU
G1
Y5
G2A Y6
G2B Y7
C
D
Instruction decoder
registers

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How computers work How computers work

0 31h
31 0 31h
A [17] A [17]
1 C4h BA 1 C4h BA
2 26h A  [6] 2 26h A  [6]
VCC

VCC
3 81h AA+B 3 81h AA+B
4 EAh
[7]A 4 EAh
[7]A
5 0h 5 0h
A0-An-1

A0-An-1
GND

GND
D0-D7

D0-D7
6 5h 6 5h
WE

WE
OE

OE
CS

CS
7 7

Logic circuit Logic circuit

Address bus Address bus 17

Data bus Data bus

Write
Control bus Read Write
Control bus Read

ALU
CPU A
B ALU
CPU A
B
PC: 10 C PC: 1 C 9

D I/O 16 I/O 17 I/O 18 I/O n D I/O 16 I/O 17 I/O 18 I/O n

Inst. Dec. registers
Inst. Dec. registers

31

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How computers work How computers work 0

0 31h 31h
A [17] A [17]
1
1 C4
C4h BA C4h BA
2 26
26h A  [6] 2 26h A  [6]

VCC

VCC
3 81h AA+B 3 81h
81 AA+B
4 EAh
[7]A 4 EA
EAh [7]A
5 0h 5 0h

A0-An-1

A0-An-1
GND

GND
55h 5h

D0-D7

D0-D7
6 6

WE

WE
OE

OE
7

CS

CS
7

Logic circuit 7 Logic circuit

Address bus 17
6 Address bus
Eh
Data bus Data bus
Write
Control bus Read Write
Control bus Read

ALU
CPU 9
A
B
+
ALU
E CPU A
9
B
E
5

PC: 1
2
3 C PC: 4
35 C
D I/O 16 I/O 17 I/O 18 I/O n D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers
Inst. Dec. registers

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How Instruction decoder works Von Neumann vs. Harvard architecture

Opcode Operand Opcode Operand
Data bus Data bus
Code Data
Instruction Memory Address bus CPU Address bus Memory
Control bus Control bus
Instruction

Operation Code Meaning

• Harvard architecture
000 A x
0011 0001 0 31h
1100 0100 1 C4h A [17] 001 A  [x]
BA
0010 0110 2 26h 010 A  A – register (x)
A  [6] Data
1000 0001 3 81h Code
1110 1010 4 EAh
AA+B 011 AA+x Memory Memory
[7]A
0000 0000 5 0h 100 A  A + register (x)
6
0000 0101 5h
101 AA–x
Data bus
7
CPU Address bus
110 Register (xH)  Register (xL)
111 [x]  A Control bus

• Von Neumann architecture

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Von Neumann vs. Harvard architecture Problems

Von Neumann Architecture Harvard architecture
1. Find the address range of the memory design in
the diagram
High level of flexibility as the Limited flexibility as there is only
memory is shared between a certain amount of memory
Flexibility instructions and data so the level that can be used for data and a
assigned to each can fluctuate certain amount for instructions.
depending on task
Speed is limited when compared Two sets of memory and buses
to harvard due to only having mean data can be handled
Speed
one memory location and set of more quickly which would result
buses in decreasing execution time
Typically used in general Typically embedded systems
purpose like washing machines, burglar
Examples Examples computers that will be alarms etc. 2. Using NAND gates and inverters, design
used for many different
purposes.
decoding circuitry for the address range 2000H–
2FFFH.

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