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Shiv PD Resume

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murugeshj55
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9 views2 pages

Shiv PD Resume

Uploaded by

murugeshj55
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Shivani Shetkar

Physical Design Engineer

[email protected] +91-7975534040 www.linkedin.com/in/shetkar-shivani

I am an Enthusiastic individual with strong ASIC/SoC design background, seeking a role to apply EDA tool
expertise in developing innovative chip solutions. Proven academic foundation combined with a passion for
semiconductor technology. Eager to contribute to cutting-edge projects.

Professional Training
Advanced VLSI Physical Design Feb 2024 - Till Date
Maven Silicon VLSI Training center Bangalore

Education
Visvesvaraya Technological University Aug 2017 - Dec 2023
M.Tech in Digital Communication and Networking, Guru Nanak Dev Engineering College, CGPA:
8.56.
B.E in Electronics and Communication, Guru Nanak Dev Engineering College, CGPA: 8.6

Karnataka School Examination and Assessment Board Jun 2015 - Mar 2017
Pre University College, Guru Nanak Ind PU College, CGPA: 8.13

Central Board of Secondary Education Jun 2014 - May 2015


Guru Nanak Public School, CGPA: 8.2

Skills
VLSI Design Skills EDA Tools
Synthesis Tanner EDA (Siemens)
Floor Plan Prime Time (Synopsys)
Placement Fusion Compiler (Synopsys)
Clock Tree synthesis Calibre (Siemens)
Routing Model Sim (Intel)
Static Timing Analysis DC+ICC2 (Synopsys)
Subject Expertise
Digital Electronics
CMOS
Physical Design
Verilog(Basic)
Internship
Embedded System an IoT Jan 2023 - Feb 2023
Technofly Solutions Vijaya Nagar Bangalore
PD Projects
ORCA
Technology : 32nm
Tool : Fusion Compiler
Project Description
> Primary Clock Frequency - 500MHz
> Macros - 40
Responsibilities
> Performed Complete PNR flow.
>Placed Macros based on DFF Analysis.
>Applied keep-out margins for macros for easy routing.
>Placed all the Macros manually following the guidelines.
>Applied partial placement blockages to minimize the congestion.

Router1x3
Technology : 32nm
Tool : Fusion Compiler
Description
> Router 1x3 has one source and three destinations, the router accepts the data packet on a
single 8-bit port and routes the packet (header + payload ) to the respective destination.
Responsibilities
> Designed 1x3 router along with the sub-blocks and implemented RTL using Verilog HDL
Simulated using model sim.
> RTL Synthesis, floor planning and placement implemented at Compile Fusion stage .
>Clock Tree Synthesis and Routing are executed after Compile Fusion.
>Timing verified with prime time tool at pre and post routing stages.

Academic Projects
Joint Secure Transmit Beam forming Designs for ISAC
Co-designed secure transmit beamforming schemes for improved spectral efficiency in an Integrated
Sensing and Communication (ISAC) system.
Social Distancing Detection and Alerting system
Developed a deep learning framework for social distancing detection and alerting system using
computer vision techniques.

Strengths
Leadership
Self Motivated
Active Lisetner

Hobbies
Travelling
Cooking

Declaration:
I hereby declare that all the information shared in the resume is true.

Date:
Place: Bengaluru Shivani Shetkar

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