878 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO.

3, MARCH 2013

A High-Speed 7.2-ns Read-Write Random Access

4-Mb Embedded Resistive RAM (ReRAM) Macro
Using Process-Variation-Tolerant Current-Mode
Read Schemes
Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu,
Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku,
Ming-Jer Kao, and Ming-Jinn Tsai

Abstract—ReRAM is a promising next-generation nonvolatile quenching times; PCRAM also suffers from large write power
memory (NVM) with fast write speed and low-power operation. consumption. MRAM has a fast write speed (10–30 ns) and
However, ReRAM faces two major challenges in read operations: excellent endurance, but suffers read difficulty due to a small
1) low read yield due to wide resistance distribution and 2) the re-
quirement of accurate bitline (BL) bias voltage control to prevent resistance ratio ( -ratio) against process variations. Among
read disturbance. This study proposes two process-variation-tol- these emerging NVMs, ReRAM has a faster write time, a larger
erant schemes for current-mode read operation of ReRAM: par- -ratio, multilevel capability, and relatively low write power
allel-series reference-cell (PSRC) and process-temperature-aware consumption.
dynamic BL-bias (PTADB) schemes. These schemes are meant to Current-mode sensing amplifiers (CSAs) [4]–[7], [37]–[46]
improve the read speed and yield of ReRAM, while taking read dis-
turbance into consideration. PSRC narrows the reference current are commonly used for NVMs with long bitline (BL) and
distribution to achieve high read yield against resistance variation. small cell read current ( ) to achieve a fast read speed
PTADB achieves small fluctuations in BL bias voltage to prevent with immunity to noise [47]. To achieve high sensing yield
read disturbance, while providing rapid BL precharge speeds. This across a wide range of process-voltage-temperature (PVT)
study fabricated a 4-Mb ReRAM macro to confirm the effective- conditions, many NVMs track using reference-cells
ness of the proposed schemes for both SLC and MLC operations.
The fastest sub-8-ns (7.2 ns) read-write random access time among [4]–[7], [37]–[46] to generate the required reference-current
megabit scaled embedded NVM macros has been demonstrated. ( ) for their CSAs. However, resistance change device in-
cluding ReRAM have large cross-die and within-die variations
Index Terms—Multilevel cell (MLC), read disturbance, resistive
RAM (ReRAM), single-level cell (SLC). in resistance ( -variation). -variations in reference-cells [4],
[35], cause wide distribution and low sensing yield for
conventional reference cell schemes.
I. INTRODUCTION Moreover, ReRAM requires a low BL bias voltage for read
operations ( ) to prevent read disturbance [20]–[23], [33].
Thus, the challenge in ReRAM design is determining how to
S EVERAL emerging nonvolatile memories (NVMs) in-
cluding phase-change RAM (PCRAM) [1]–[3], MRAM
[4]–[6], and resistive RAM (ReRAM/Memristor) [7]–[34]
use a higher to induce a larger cell read current (
for faster read speeds and larger sensing margin, while avoiding
)

read disturbance due to variations in process and temperature.

have achieved faster operation speeds and lower write power
To facilitate fast read speeds and high yields, this work pro-
than commonly used embedded Flash (eFlash) macros [35],
poses two schemes that are insensitive to process variation for
[36]. PCRAM has a shorter write time than eFlash, but still
current-mode sensing of ReRAM (Fig. 1): a parallel-series ref-
requires 50–300 ns for write operations owing to the long
erence-cell (PSRC) scheme and a process-temperature-aware
dynamic BL-bias circuit (PTADB). The PSRC scheme sup-
Manuscript received May 07, 2012; revised September 26, 2012; accepted
presses the distribution against wide resistance variation
September 28, 2012. Date of publication December 20, 2012; date of current
version February 20, 2013. This paper was approved by Associate Editor Peter for applications using either single-level cells (SLC) or mul-
Gillingham. tilevel cells (MLC). The PTADB scheme achieves a fast BL
M.-F. Chang, K.-F. Lin, C.-W. Wu, C.-C. Kuo, Y.-S. Yang, and C.-H. Lien
precharge with small fluctuations to prevent read dis-
are with the National Tsing Hua University, Hsinchu 30013, Taiwan (e-mail:
[email protected]). turbance. This paper presents the first instance of an embedded
S.-S. Sheu, H.-Y. Lee, F. T. Chen, K.-L. Su, T.-K. Ku, M.-J. Kao, and M.-J. megabit scale (4 Mb) NVM macro with sub-8-ns (7.2 ns)
Tsai are with the Industrial Technology Research Institute, Hsinchu 30013,
read-write random access time [48]. The proposed ReRAM
Taiwan.
P.-F. Chiu and Y.-S. Chen are with the National Tsing Hua University, design also features MLC read operations, the efficacy of which
Hsinchu 30013, Taiwan, and also with the Industrial Technology Research was demonstrated experimentally.
Institute, Hsinchu 30013, Taiwan.
The remainder of this paper is organized as follows.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. Section II discusses the background of read operations for
Digital Object Identifier 10.1109/JSSC.2012.2230515 ReRAM. Section III describes the proposed PSRC scheme.

0018-9200/$31.00 © 2012 IEEE

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 879

As with SLC, the application of different SET operating con-

ditions enables this ReRAM device to support MLC operations,
as shown in Table II.
The write speed of most NVMs is far slower than the read
speed; however, the proposed ReRAM device has a faster write
speed than read speed, particularly for long BL cell arrays, as
shown in Fig. 4. Thus, read operations are the bottleneck in the
proposed ReRAM device.

B. Sensing Schemes for ReRAM

Two types of sense amplifier (SAs) are commonly used for
memory devices: voltage-mode SA (VSA) and current-mode
SA (CSA).
As mentioned earlier, low is required to prevent read
disturbance in ReRAM. Applying low in VSA limits the
Fig. 1. Proposed read structure for ReRAM.
BL voltage difference (sensing margin) between reading HRS
and LRS cells, thereby making the read operations vulnerable
to BL noise, such as BL crosstalk and WL-to-BL coupling [47],
Section IV describes the proposed PTADB scheme. Section V
[49]. Moreover, because the resistive device of a ReRAM cell
presents the macro structure and experiment results. Section VI
is directly connected to the BL, the BL parasitic load depends
draws conclusions.
on the data pattern of a BL. This causes a large fluctuation in
BL precharge/discharge time for reading an LRS cell across dif-
II. BACKGROUND ferent BL data patterns. For example, for a 256-cell BL (used
in this work), the maximum fluctuations in BL precharge time
A. Employed ReRAM Device of CSA and BL developing/discharge time of VSA across var-
Fig. 2 shows the structure of the 1T1R ReRAM cell used ious BL data patterns are 0.3 and 2.4 ns, respectively. Thus, it
in this study, comprising an NMOS switch transistor and an is difficult to generate a reference voltage for VSAs to achieve
HfO -based (TiN/TiO /HfO /TiN) bipolar resistive memory high-speed read operations for ReRAM.
device (memristor), [20]–[23]. This ReRAM cell uses the Conversely, CSAs usually achieve a faster read speed, with
back-end-of-line (BEOL) process for the resistive device, with superior immunity to BL noise than VSAs for memories with
standard CMOS logic technology for the NMOS switch. a long BL array structure and small . In CSAs, data de-
The ReRAM cell is capable of two direct overwrite oper- pendency affects only the BL precharge speed. After the BL is
ations for SLC: SET (write-0) and RESET (write-1). Table I fully precharged, all of the internal nodes in the unselected cells
shows the operating conditions of this ReRAM device. The are also charged. Fortunately, the BL precharge current is much
SET operation changes the ReRAM device from a high-re- larger than the cell read current and is not susceptible to sig-
sistive state (HRS) to a low-resistive state (LRS) by applying nificant data dependency. Fig. 4 shows the read access time of
a SET-voltage ( ) to the BL and 0 V to the source line VSA and CSA schemes across various BL lengths. In reading
(SL). The RESET operation changes the ReRAM device from a 0.18- m ReRAM LRS cell with 20 A, CSAs
low resistance ( , LRS) to high resistance ( , HRS) by achieve faster read speed than VSA when the BL length exceed
applying a RESET voltage ( ) to the SL and 0 V to the 128 rows. Moreover, unlike the VSA, the sensing margin (cur-
BL. The mean -ratio ( ) of the proposed SLC ReRAM rent difference between reading LRS and HRS) of CSA is in-
device exceeds 100. The write operation consumes only a sensitive to data-pattern-dependent BL parasitic load.
small current ( 25 A) and features rapid switching time, as Considering the sensing margin and read speed, CSAs suit
shown in Fig. 3 [23]. Fig. 3(a) presents the three – -curves ReRAM much better than VSAs do for high-speed and large-
of the proposed ReRAM device, with three different clamping capacity applications.
currents for SET operation under the operating conditions of Fig. 5 shows two commonly used BL voltage bias (clamping)
1.5 V and 1.5 V with a dc voltage sweep. schemes: static BL-clamping and dynamic BL-clamping
However, the must be held at a low voltage to prevent schemes. The static BL-clamping scheme [33], [42], [45] uses
read disturbance. According to the test results shown at [20], fixed voltage to control the BL clamping transistor (NCLP).
when applying a constant voltage stress of 0.5 V for 1000 s to The dynamic BL-clamping scheme [7], [46] uses dynamic
a single ReRAM device, the BL voltage should be kept below voltage to control the NCLP. Generally, dynamic BL-bias
0.5 V to prevent read disturbance. The development of ReRAM schemes achieve better accuracy [6] with a faster set-
is still a work in progress; therefore, the optimized BL bias tling time than a static BL-bias scheme. Moreover, as with the
voltage has yet to be fixed. In this study, we selected 0.3 V issue of variations in BL swing (BL discharge speed) in VSA,
(with 0.2-V margin) for the BL bias voltage to prevent read the data-dependent BL load causes large timing fluctuations
disturbance under megabit coverage. It should be noted that in settling time for static BL-clamping schemes. To
this value may be adjusted according to the performance of the achieve high read speeds for large capacity ReRAM macros,
ReRAM device. this study employs CSA with a dynamic BL-clamping scheme.
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
880 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

Fig. 2. Structure of HfO -based bipolar ReRAM cell used in this study.

TABLE II
MLC OPERATION CONDITIONS

Fig. 3. (a) – curve with three different SET clamping currents (A, B, and
C). (b) Switching behavior of ReRAM device.

Fig. 4. Random read/write access times for ReRAM devices with various BL
TABLE I lengths. The read access time includes the VSA and the CSA using static BL
SLC OPERATION CONDITIONS clamping and dynamic BL clamping.

the same target . However, large cross-die and within-die

-variations in both LRS and HRS reference cells result in
wide distribution and low sensing yield for conventional
single-cell (one-cell) [3], [5], [6], [35], [39]–[43], parallel-cell
(two-cells or -cells), or - -average ( -Avg.)
reference-cell schemes [4], [7], particularly with large -ratio
C. Current-Mode Sensing Scheme Versus Process Variations ReRAM. Fig. 6 shows the simulated distribution of gen-
The CSA scheme requires a reference-current ( ) for erated by conventional reference-cell schemes, compared to the
comparison with the to-be-sensed . As mentioned in measured distribution of the proposed ReRAM device.
Section I, in generating the required for high sensing The LRS cells have wide distribution. LRS reference
yield, many NVMs use reference-cells to ensure the good cells with a smaller resistance generate a larger .
tracking behavior of across various PVT conditions. When the difference between and , is insuffi-
Note that the reference current for an SA is generated by cient to overcome the SA input offset ( ) or –
replica cells and a current-mirror-based current buffer (CB). overlap, sensing failure occurs, as shown in Fig. 6.
Different replica-cell schemes generate different degrees of As mentioned earlier, ReRAM has an upper limit for
resistance and require different current-mirror ratios to achieve to prevent read disturbance. However, ReRAM requires a higher
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 881

III. PSRC SCHEME

To maximize the sensing margin and obtain a better read
yield, the for CSA should be the “mid-point current” ( )
of the of two neighboring memory states. This study pro-
poses a PSRC scheme for SLC/MLC ReRAM to generate an
close to with suppressed fluctuation against variations
in resistance.

A. Circuit Structure and Operation of PSRC

The PSRC scheme comprises a reference cell array (RCA)
and a current-mirror-based CB. Fig. 8 displays the structure
of the proposed PSRC for MLC applications. The RCA com-
prises dummy cells, reference wordlines (RWLs), reference bit-
lines (RBLH and RBLL), reference source lines (RSLs), and
parallel-series reference blocks (PSRBs). For a four-state ( ,
Fig. 5. (a) Static BL-clamping and (b) dynamic BL-clamping schemes.
, , and ) MLC application, three PSRB units are
required to generate three different ( , and
). The CB mirrors the generated from RCA and gen-
erate a mirror voltage ( ) for each SA of the IO block.
A PSRB unit includes subreference-blocks (SRB), con-
nected in series. Each SRB has parallel-connected reference-
cells. In this work, we selected to suppress the current
mismatch between and caused by the body ef-
fect. By applying to RBLH ( ) and ground
voltage to RBLL ( ), each PSRB unit generates an
current ( , , or ). The derivation of
to distinguish between reading the and states in PSRC
is presented as

Fig. 6. Cell read current ( ) and reference current ( ) variations in

ReRAM.

to induce a larger to ensure a sufficient sensing

margin to overcome SA offset while achieving faster sensing (1)
operations. Unfortunately, conventional BL clamping schemes
suffer from large fluctuations in across various PVT con- where and represent two neighboring lower and higher
ditions. Fig. 7 shows the of a conventional dynamic resistance states, respectively.
BL-clamping scheme with variations in the threshold voltage Clearly, the PSRC can generate an that is close to the
of NMOS ( ) and PMOS ( ). Noted, Fig. 7 does not target “mid-point current” .
include the fluctuations from ReRAM cells, because they do Fig. 9 shows two alternative structures of the proposed
not have a significant influence on . Variations in PSRB for SLC application: 1) using both LRS and HRS cells
( ) and ( ) are normalized to the difference and 2) using LRS cells only. Both of these schemes produce
in between Typical(T) and Slow(S)/Fast(F) corners, which similar results in suppressing distribution compared to
is assumed to be - . With SF corners, PMOS is much conventional schemes. In SLC applications, the large -ratio
stronger than NMOS, such that the exceeds the target causes the LRS cell to dominate generation. Moreover,
bias voltage of 0.3 V, causing read disturbance in ReRAM de- the within-die -variation range of is 10 smaller than
vices. With FS corners, NMOS is much stronger than PMOS, in the proposed ReRAM. By replacing the HRS cells with
such that the is significantly lower than the target bias LRS cells, the LRS-cell-only scheme has more LRS cells than
voltage of 0.3 V, which degrades the amount of the induced the “LRS+HRS” scheme, which results in better averaging
. This reduced can result in low sensing yield, par- and provides a slightly narrower distribution than (1).
ticularly for tail bits with higher resistance. In application, LRS-cell-only scheme generates 2 current
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
882 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

Fig. 7. Fluctuations in across various global process corners and temperatures.

B. PSRC Against Resistance Variation (Comparison With

Other Reference Current Generation Schemes)

Fig. 10 displays the reference-cell structures of previous par-

allel-cells, -Avg., and series-parallel (SP) [5] schemes.
In conventional parallel-cell schemes, if the resistance of a
reference cell is significantly lower than that of a typical cell,
the equivalent impedance of the parallel-cell is dominated by
this smaller-resistance cell and generates a larger than
the target . Oppositely, thanks to the serial connections
of SRBs, the minimum equivalent impedance is the sum of
the impedance of SRBs, rather than being dominated by one
ultralow-resistance reference cell (a tail-bit).
Fig. 11 compares the distribution ranges of par-
allel-cells and PSRC schemes for SLC applications using
a 10 000-sample Monte-Carlo simulation. For a four-ref-
erence-cell topology, the proposed PSRC scheme narrows
the SLC distribution range and - by 36.3% and
23.5%, compared with conventional 4-parallel-cells schemes,
respectively. The “16-cell parallel” scheme results in smaller
variations than the “4-cell parallel” scheme, but still produces
a small amount of resistance due to a single tail bit with lower
resistance. In contrast, the resistance of the proposed PSRC
is not dominated by single tail bits due to the serial behavior
of PSRC. Thus, the 4-cell PSRC can achieve a narrower dis-
tribution than the 16-cell parallel scheme. The 4-cell PSRC
also reduces the distribution range and - by 53.3%
and 40.8% compared with conventional 2-cell parallel-cell
schemes, respectively.
Previous SP schemes generate the “mid-point resistance” of
two neighboring resistance states, as derived by

Fig. 8. Structure of PSRC for MLC applications: (a) RCA. (b) PSRB unit
(using and for ).

on reference bitline due to its half effective resistance, the

current-mirror ratio of CB should be adjusted for target
( ).
It should be noted that, by applying the voltage conditions
of the regular cell array to RWL, RSL, and RBLL/RBLH, the
resistance of the reference cells in PSRB can be programmed to
(2)
provide the same resistance as regular ReRAM cells.
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 883

Fig. 9. Two PSRB structures for SLC applications (a) using both LRS and HRS cells and (b) using LRS cells only.

the higher-resistance MLC cells (smaller ). The PSRC

achieved a 99% lower mean- deviation from the com-
pared to the SP approach. The PSRC also achieved 29%–32%
and 27%–56% smaller values in than conventional
- -average and SP schemes, respectively. Clearly, the
proposed PSRC is better able to generate against resistance
variation over previous reference-cell schemes. Thus, the PSRC
scheme is suitable for both SLC and MLC ReRAMs.

IV. PTADB SCHEME

This study proposes a process-temperature-aware dynamic
BL-bias circuit (PTADB) to achieve: 1) small fluctu-
ation for ReRAM taking read disturbance into consideration
Fig. 10. Previous (a) parallel and (b) series-parallel reference cell schemes.
and 2) a fast BL precharge time. Fig. 14 shows the structure of
proposed PTADB scheme, comprising a process-temperature
However, the ( ) derivation from the detector (PTD), a process-temperature compensated feedback
“mid-point resistance ( )” does not yield the “mid-point amplifier (PTFA), and a BL precharge speed enhancement
current ( )” of two neighboring resistance states. (BLPSE) circuit. The PTD circuit detects the global process
Fig. 12 compares the mean- of the series-parallel (SP) corner and operating temperature and then generates a -bit
and the PSRC schemes with various -ratios. The of digital code ( ). The PTFA receives the -bit
the SP scheme achieves only 10% mismatch from the ideal digital code from PTD to adjust the bias voltage ( ) of the
when the -ratio is less than 2. However, the SP scheme BL-clamping NMOS transistor (NCLP) to suppress
suffers large mismatch between and when the -ratio fluctuation across different process corners and temperature
is large. By contrast, the proposed PSRC exhibits consistent conditions. The BLPSE provides dynamic precharge current to
99.9% “mid-point current” behavior across a wide-range of reduce the BL precharge time.
-ratios. Thus, previous SP approaches are appropriate only
for memories with small -ratio devices (i.e., MRAM), and A. Process-Temperature Detector (PTD)
the proposed PSRC scheme is effective for a wide range of Fig. 15 shows the circuit and waveform of a PTD, com-
resistive memory devices, regardless of their -ratios or MLC prising a PMOS–NMOS transistor strength comparator (P-N
range. comparator), and a differential voltage digitizer (DVD). The
Fig. 13 displays the ( , , ) generated P-N comparator comprises a current mirror circuit (PA and
from previous SP, - -average, and the proposed PSRC PA_M) and a pair of PMOS and NMOS transistors (PB and
schemes, based on the measured four-level MLC resistance NB). The PA-PB forms a voltage divider circuit to generate
distribution of the ReRAM devices in this study. The mean voltage at node PP. Because of the current mirror be-
of PSRC and the - -average schemes are both havior, the drain current of PA_M is the same as that of PA/PB.
consistently close to the target across various MLC states. This mirrored charging current then fights with the discharging
However, the SP scheme yielded a 46%~84% lower mean current generated by NB transistor. When PB is stronger than
(mismatch) than the target across various MLC states NB, the voltage at node PN is higher than . When PB
and demonstrated significantly overlap with the of is weaker than NB, is lower than . For example, the
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
884 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

Fig. 11. distribution range of parallel cells and PSRC scheme for SLC applications.

The source voltage of P1, (node voltage at VDDA), is

modulated by the number of conductive PMOS VDDA switches
(SW3~SW1 and SW0). The SW0 transistor is controlled by the
SENB signal, and is on during a read cycle. The SW3~SW1
transistors are controlled by the -bit ( ) digital code from
the PTD.
The PTFA uses a dynamic bias generator (DBG) to control
the gate voltage ( ) of N1 dynamically, rather than using
a fixed . At the beginning of the BL precharge phase
( ), the low and enables to have
a higher voltage (larger voltage swing) than the fixed-
approach to enlarge the BL charging current for faster BL
precharge speed, as shown in Fig. 16(b). With feedback from
(rising), the begins to drop. The P3 transistor then
Fig. 12. Mean- of series-parallel scheme and PSRC schemes across var-
ious -ratios. feedback the status to DBG and increases the .
Thus, the increase in , drops more rapidly, settling
at a static level for the target .
voltage difference between and at “SF corner, 75 C” Fig. 17 shows the simulated of conventional schemes
and “FS corner, 0 C” for a 0.18- m process are 184 mV and and those proposed in this study, across a range of NMOS and
150 mV , respectively. PMOS threshold voltages at 1.8 V and 25 C for a
The DVD employs different current ratios between tran- 0.18- m process node. We divided the current ratios across
sistors to generate different voltages at various global process corners and temperature conditions into
node according to the voltage difference between four segments, (000, 100, 110, and 111), as listed in Table III.
and . The output latches then translate these analog Folding the fluctuation into four segments enables the
voltages ( ) into a -bit digital code ( ). PTADB to reduce the variation in by 45% and 56%,
When the sense enable signal is activated ( ), the compared with conventional (CNV) dynamic BL-bias schemes
signal is output as signal at the PTD output (Fig. 7) and our PTFA without PTD, respectively.
node. The number of and the current ratio between N1 to NK It should be noted that the number of segments in PTDFB
depends on the required accuracy of and the manufac- is not limited to four. It is a design tradeoff between the target
turing technology employed. In this work, we selected variation range, area overhead, and design complexity
and designed the current ratio to meet the design target for a of PTD and PTFA.
0.18- m process, as shown in Table III.
It should be noted that,to prevent speed overhead, the -bit C. BL Precharge Speed Enhancement (BLPSE) Circuit
digital code from the PTD can be generated outside the read This work developed a BLPSE circuit to reduce the BL
cycles, such as during write cycles or immediately after chip precharge time and achieve a faster read speed without af-
power-on. fecting the sensing margin. The BLPSE scheme employs two
charging current paths to achieve faster BL precharge speed: a
B. Process-Temperature Compensated Feedback Amplifier regular BL charger (MP1) and an assist BL charger (MCRG),
(PTFA) as shown in Fig. 18.
Fig. 16 shows the circuit of PTFA, which generates At the beginning of the BL precharge phase, the grounded
to dynamically control the BL bias NMOS transistor (NCLP). BL induces a large BL precharge current ( ) in MP1. The
The is controlled by virtual VDD (VDDA) switches, a MP2 then mirrors the drain current of MP1, which is equal
–controlled common-source amplifier (P1), and a dy- to the sum of and , to charge node NSA1 against
namic current bias (N1). the discharge current provided by MN1. When the BL voltage
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 885

Fig. 14. Structure of proposed PTADB scheme.

MCRG and generates an assist BL charging current to speed up

the BL precharge process. When the BL voltage approaches the
target , the drain current of MP1/MP2 is reduced while
the source voltage of MCRG is increased. The then be-
gins to drop and the drain current of MCRG is reduced. After a
sufficient BL precharge period, the is low and the drain
current of MCRG is small enough to be overlooked. It should
be noted that the implementation of MN1 requires considerable
delicacy. If the transistor width of MN1 is too large, then
would be too low for MCRG to turn on; conversely, if the tran-
sistor width of MN1 is too small, then would be too high
to cut off MCRG when is large. Thus, MN1 should be
kept sufficiently small to ensure that the MCRG can be turned
on during the selective BL precharge period (or ) to im-
prove target speed. In addition, MN1 should be large enough to
turn off MCRG when sensing the maximum .
Because the source voltage of MCRG ( ) is higher than its
body voltage (ground), the body effect increases the threshold
voltage, which suppresses the leakage current of MCRG. To
read a tail bit (with a smaller ), the is lower com-
pared to when reading a nominal cell (with a larger ).
Thus, the BL leakage current from the MCRG is proportional
to the . By designing the transistor size specifically for
MCRG and MN1, the leakage current of MCRG can be below
2% of the , which does not influence the sensing margin
significantly.
Thus MN1 should be small enough to ensure the MCRG can
be turned on during a selective BL precharge period (or )
for a target speed improvement. Also, MN1 should be large
enough to turn off MCRG when sensing the maximum .
Fig. 19 shows the speed breakdown of conventional schemes
and the proposed current-mode sensing schemes for a 0.18- m
Fig. 13. generated from the PSRC, series-parallel, and averaging
ReRAM macro with 256 cells per BL. Using PTFA and BLPSE
schemes for MLC applications. (a) for differing and . (b) schemes, the proposed macro achieved a 36% reduction in BL
for differing and . (c) for differing and . precharge time. Due to the smaller fluctuations in , the
PTFA scheme results in a higher and generates a larger
. This larger improves the sensing speed of CSA.
is low, the large drain current of MP1/MP2, which significant Compared to conventional dynamic BL-bias schemes, the pro-
exceeds the drain current of MN1, causes the voltage at node posed macro achieves a 24% faster macro-level random read
NSA1 ( ) to rise quickly. This high turns on the access time.
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
886 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

Fig. 15. (a) Circuit and (b) simulated waveforms of PTD.

Fig. 16. (a) Circuit and (b) simulated waveform of PTFA.

TABLE III
PTD OUTPUT CODES VERSUS GLOBAL PROCESS CORNERS AND TEMPERATURE
CONDITIONS

V. IMPLEMENTATION AND EXPERIMENTAL RESULTS

A. Macro and Testchip Implementation

We fabricated a testchip with a 4 Mb ReRAM macro using Fig. 17. BL bias voltage across various PMOS–NMOS global corners.
a 0.18- m bulk-CMOS logic process and in-house BEOL
Hf O-based ReRAM device technology. Fig. 20 shows a die
photograph of this testchip. Cell efficiency of this ReRAM circuit was implemented to verify both the SLC and MLC
macro is only 30% due to the large area taken up by the operation of the ReRAM macro. A write-verify test-mode
test-mode circuits. These test-mode circuits are mainly for circuit [48] was implemented in this ReRAM macro to narrow
process development and will not be included in production the distribution of each resistance state for MLC applications.
chips. This ReRAM macro comprised 32 subblocks, with 256 Fig. 21 shows the schematic of the testchip. The access time
rows and 512 columns per subblock. A dual-mode sensing ( ) includes the access time of the embedded ReRAM
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 887

Fig. 18. (a) Circuit and (b) simulated waveform of BLPSE.

Fig. 21. Structure of test chip with dummy path for extraction.

Fig. 19. Improvement in read access time using the proposed PTADB scheme
compared with conventional (CNV) CSA.

Fig. 20. Die photograph of 4-Mb ReRAM macro.

Fig. 22. Measured and single-cell distribution for SLC operation.

macro ( ) and the path delay ( ), which includes

the delay of on-chip and load-board wirings. This work imple- Fig. 23 shows the captured waveform of the 4-Mb SLC read
mented a dummy path to extract the of ReRAM macro by operation. As discussed in Section II, the ReRAM device has
deducing the from . fast write speed; therefore, the read-write access time is dom-
inated by read operations. The measured random-read-access
B. Experimental Results and burst-read of the 4-Mb-SLC ReRAM macro at 1.8 V
Fig. 22 shows the measured distribution. The PSRC is 7.2 and 3.6 ns, respectively.
scheme achieves a narrower distribution than the 2-cell Fig. 24 shows the captured waveform of the MLC operation
-averaging (with single LRS cell) scheme, with in a sub-block after the write-verify operation. Due to smaller
a 44% reduction in - . and , the reading of “11” ( “11”) has a slower
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
888 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

Fig. 25. Shmoo plot of SLC.

with tolerance to process variation. PSRC narrows the refer-

ence current distribution against resistance variation. PTADB
achieves small fluctuations in BL bias voltage with rapid BL
precharge speeds. The fabricated 4 Mb ReRAM macro con-
firms the effectiveness of the proposed schemes for both SLC
and MLC operations. This paper reports the first instance of an
embedded megabit-scale NVM macro with sub-8-ns read-write
Fig. 23. Captured waveform of 4-Mb SLC operation at 1.8 V: (a)
Random read access. (b) Burst-mode access.
random access time.

ACKNOWLEDGMENT
The authors would like to thank EOL of ITRI for ReRAM
manufacturing and testing support.

REFERENCES
[1] S. Hanzawa et al., “A 512 kB embedded Phase Change Memory with
416 kB/s write through at 100 cell write current,” in IEEE Int.
Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 474–475.
[2] G. D. Sandre et al., “A 90 nm 4 Mb embedded Phase-Change memory
with 1.2 V 12 ns read access time and 1 MB/s write throughput,” in
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp.
268–269.
[3] Y. N. Hwang et al., “MLC PRAM with SLC write-speed and robust
Fig. 24. Captured waveform of MLC operation at 1.8 V. read scheme,” in Symp. VLSI Tech. Dig. Tech. Papers, Jun. 2010, pp.
201–202.
[4] K. Tsuchida et al., “A 64 Mb MRAM with clamped-reference and ade-
quate-reference schemes,” in IEEE Int. Solid-State Circuits Conf. Dig.
than reading other data-patterns (“00”, “01”, and “10”). The Tech. Papers, Feb. 2010, pp. 258–259.
[5] M. Durlam et al., “A 1-Mbit MRAM based on 1T1MTJ bit cell inte-
measured worst-case MLC (reading “11”) is 14.2 ns. This grated with copper interconnects,” IEEE J. Solid-State Circuits, vol.
test confirms that the proposed PSRC scheme is also functional 38, no. 5, pp. 769–773, May 2003.
for MLC applications with tight sensing margins ( -ratio) be- [6] Y. Iwata et al., “A 16 Mb MRAM with FORK writing scheme and burst
modes,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
tween neighboring resistance states. 2006, pp. 138–139.
Fig. 25 shows the measured Shmoo plot for the 4-Mb SLC [7] S. Dietrich et al., “A nonvolatile 2-Mbit CBRAM memory core fea-
turing advanced read and program control,” IEEE J. Solid-State Cir-
operation. The PSRC and PTADB circuits are functional from cuits, vol. 42, no. 4, pp. 839–845, Apr. 2007.
1.8 V to 700 mV, across a wide range of WL voltage [8] P. Schrogmeier et al., “Time discrete voltage sensing and iterative pro-
(3.3 to 1.1 V). This test confirmed that the proposed sensing gramming control for a 4F2 multilevel CBRAM,” in Proc. Symp. VLSI
Circuits, Jun. 2007, pp. 186–187.
circuit shows good tracking capability and is scalable [9] L. O. Chua, “Memristor—The missing circuit element,” IEEE Trans.
for a wide range of operating voltages (1x–0.38x of VDD at Circuit Theory, vol. CT-18, no. 5, pp. 507–519, Sep. 1971.
this work). [10] I. G. Baek et al., “Multi-layer cross-point binary oxide resistive
memory (OxRRAM) for post-NAND storage application,” in Int.
Electron Devices Meeting Tech. Dig. Papers, 2005, pp. 750–753.
VI. CONCLUSION [11] A. Chen et al., “Non-volatile resistive switching for advanced memory
applications,” in Int. Electron Devices Meeting Tech. Dig. Papers,
To achieve high sensing yield and fast read speeds with read 2005, pp. 746–749.
[12] Y.-B. Kim et al., “Bi-layered RRAM with unlimited endurance and ex-
disturbance consideration, this paper presents two read schemes tremely uniform switching,” in Symp. VLSI Circuits Dig. Tech. Papers,
(PSRC and PTADB) for ReRAM using current-mode sensing Jun. 2011, pp. 52–53.
Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 889

[13] K. Tsunoda et al., “Low power and high speed switching of Ti-doped [36] J. Tsouhlarakis et al., “A flash memory technology with quasi-virtual
NiO ReRAM under the unipolar voltage source of less than 3 V,” in Int. ground array for low-cost embedded applications,” IEEE J. Solid-State
Electron Devices Meeting Tech. Dig. Papers, Dec. 2007, pp. 767–770. Circuits, vol. 36, no. 6, pp. 969–978, Jun. 2001.
[14] D. B. Strukov et al., “The missing memristor found,” Nature, no. 453, [37] G. D. Sandre et al., “A 90 nm 4 Mb embedded Phase-Change memory
pp. 80–83, May 2008. with 1.2 V 12 ns read access time and 1 MB/s write throughput,” in
[15] Z. Wei et al., “Highly reliable ReRAM and direct evidence of IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp.
redox reaction mechanism,” in Int. Electron Devices Meeting Tech. 268–269.
Dig. Papers, Dec. 2008, pp. 293–296. [38] Y. N. Hwang et al., “MLC PRAM with SLC write-speed and robust
[16] W. C. Chien et al., “A forming-free Wox resistive memory using a read scheme,” in Symp. VLSI Tech. Dig. Tech. Papers, Jun. 2010, pp.
novel self-aligned field enhancement feature with excellent reliability 201–202.
and scalability,” in Int. Electron Devices Meeting Tech. Dig. Papers, [39] D. Elmhust and M. Goldman, “A 1.8-V 128-Mb 125-MHz multilevel
Dec. 2010, pp. 440–443. cell flash memory with flexible read while write,” IEEE J. Solid-State
[17] S. Kawabata et al., “CoO -RRAM memory cell technology using re- Circuits, vol. 38, no. 11, pp. 1929–1933, Nov. 2003.
cess structure for 128 Kbits memory array,” in Proc. Int. Memory Work- [40] M. Bauer et al., “A multilevel-cell 32 Mb flash memory,” in IEEE Int.
shop (IMW), May 2010, pp. 1–2. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 1995, vol. 38, pp.
[18] M. J. Kim et al., “Low power operating bipolar TMO ReRAM for sub 132–133.
10 nm era,” in Int. Electron Devices Meeting Tech. Dig. Papers, Dec. [41] R. Micheloni, L. Crippa, M. Sangalli, and G. Campardo, “The flash
2010, pp. 444–447. memory read path: Building blocks and critical aspects,” Proc. IEEE,
[19] D.-J. Seong et al., “Effect of oxygen migration and interface engi- vol. 91, no. 4, pp. 537–553, Apr. 2003.
neering on resistance switching behavior of reactive metal/polycrys- [42] T. Ogura et al., “A 1.8-V 256-Mb multilevel cell NOR flash memory
talline Pr Ca MnO device for nonvolatile memory applications,” with BGO function,” IEEE J. Solid-State Circuits, vol. 41, no. 11, pp.
in Int. Electron Devices Meeting Tech. Dig. Papers, Dec. 2009, pp. 2589–2600, Nov. 2006.
101–104. [43] C.-C. Chung, H. Lin, and Y.-T. Lin, “A multilevel read and verifying
[20] H.-Y. Lee et al., “Low power and high speed bipolar switching with scheme for Bi-NAND flash memory,” IEEE J. Solid-State Circuits, vol.
a thin reactive ti buffer layer in robust HfO based RRAM,” in Int. 42, no. 5, pp. 1180–1188, May 2007.
Electron Devices Meeting Tech. Dig. Papers, Dec. 2008, pp. 1–4. [44] S. Atsumi et al., “A channel-erasing 1.8-V-only 32-Mb NOR flash
[21] Y. S. Chen et al., “Highly scalable hafnium oxide memory with im- EEPROM with a bitline direct sensing scheme,” IEEE J. Solid-State
provements of resistive distribution and read disturb immunity,” in Int. Circuits, vol. 35, no. 11, pp. 1648–1654, Nov. 2000.
Electron Devices Meeting Tech. Dig. Papers, Dec. 2009, pp. 105–108. [45] T. Tanzawa, Y. Takano, T. Taura, and S. Atsumi, “Design of a sense
[22] H. Lee et al., “Evidence and solution of over-RESET problem for circuit for low-voltage flash memories,” IEEE J. Solid-State Circuits,
HfO based resistive memory with sub-ns switching speed and high vol. 35, no. 10, pp. 1415–1421, Oct. 2000.
endurance,” in Int. Electron Devices Meeting Tech. Dig. Papers, Dec. [46] A. Conte, G. L. Giudice, and A. Signorello, “A high-performance very
2010, pp. 460–463. low-voltage current sense amplifier for nonvolatile memories,” IEEE
[23] H. Y. Lee et al., “Low-power and nanosecond switching in robust J. Solid-State Circuits, vol. 40, no. 2, pp. 507–514, Feb. 2005.
hafnium oxide resistive memory with a thin Ti cap,” IEEE Electron [47] R.-A. Cernea et al., “A 34 MB/s MLC write throughput 16 Gb NAND
Device Lett., vol. 31, no. 1, pp. 44–46, Jan. 2010. with all bit line architecture on 56 nm technology,” IEEE J. Solid-State
[24] M. Terai et al., “High thermal robust ReRAM with a new method for Circuits, vol. 44, no. 1, pp. 186–194, Jan. 2009.
suppressing read disturb,” in IEEE Symp. VLSI Technol. Dig. Tech. Pa- [48] S.-S. Sheu et al., “A 4 Mb embedded SLC resistive-RAM macro with
pers, Jun. 2011, pp. 50–51. 7.2 ns read-write random-access time and 160 ns MLC-access capa-
[25] J. Lee et al., “Diode-less nano-scale ZrO /HfO RRAM device with bility,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb.
excellent switching uniformity and reliability for high-density cross- 2011, pp. 200–201.
point memory applications,” in Int. Electron Devices Meeting Tech. [49] M.-F. Chang, S.-M. Yang, C.-W. Liang, C.-C. Chiang, P.-F. Chiu, and
Dig. Papers, Dec. 2010, pp. 452–455. K.-F. Lin, “Noise-immune embedded NAND-ROM using a dynamic
[26] M. J. Lee et al., “Low power operating bipolar TMO ReRAM for sub split source-line scheme for VDDmin and speed improvements,” IEEE
10 nm era,” in Int. Electron Devices Meeting Tech. Dig. Papers, Dec. J. Solid-State Circuits, vol. 45, no. 10, pp. 2142–2155, Oct. 2010.
2010, pp. 444–447.
[27] C. H. Cheng et al., “Novel ultra-low power RRAM with good en-
durance and retention,” in IEEE Symp. VLSI Technol. Dig. Tech. Pa-
pers, Jun. 2010, pp. 85–86.
[28] J. Hi et al., “Highly reliable and fast nonvolatile hybrid switching
ReRAM memory using thin Al O demonstrated at 54 nm memory
array,” in IEEE Symp. VLSI Technol. Dig. Tech. Papers, Jun. 2011,
pp. 48–49. Meng-Fan Chang received the M.S. degree from
[29] X. A. Tran et al., “High performance unipolar AlO /HfO /Ni based The Pennsylvania State University, University Park,
RRAM compatible with Si diodes for 3D application,” in IEEE Symp. and the Ph.D. degree from the National Chiao Tung
VLSI Technol. Dig. Tech. Papers, Jun. 2011, pp. 44–45. University, Hisnchu, Taiwan, respectively.
[30] W. Kim et al., “Forming-free nitrogen-doped AlO RRAM with Currently, he is an Associate Professor with
sub- A programming current,” in IEEE Symp. VLSI Technol. Dig. National Tsing Hua University (NTHU), Hsinchu,
Tech. Papers, Jun. 2011, pp. 22–23. Taiwan. Before 2006, he worked in industry for
[31] K. Higuchi, K. Miyaji, K. Johguchi, and K. Takeuchi, “50 nm HfO over ten years. From 1996 to 1997, he designed
ReRAM with 50-times endurance enhancement by set/reset turnback memory compilers at Mentor Graphics. From 1997
pulse & verify scheme,” in Proc. Int. Conf. on Solid State Devices and to 2001, he designed embedded SRAMs and Flash
Mater., Sep. 2011, pp. 1011–1012. with the Design Service Division (DSD), TSMC.
[32] C. J. Chevallier et al., “A 0.13 m 64 Mb multi-layered conductive During 2001–2006, he was a Director with IPLib Company, where he de-
metal-oxide memory,” in IEEE Int. Solid-State Circuits Conf. Dig. veloped embedded SRAM and ROM compilers, Flash macros, and Flat-cell
Tech. Papers, Feb. 2010, pp. 260–261. ROM products. He has authored and coauthored several ISSCC and VLSI
[33] W. Otsuka et al., “A 4 Mb conductive-bridge resistive memory with symposia papers.. His research interests include circuit designs for volatile and
2.3 GB/s read-throughput and 216 MB/s program-throughput,” in nonvolatile memory, ultra-low-voltage systems, 3D-memory, and memristor
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2011, pp. logics.
210–211. Prof. Chang received the Academia Sinica Junior Research Investigators
[34] A. Kawahara et al., “An 8 Mb multi-layered cross-point ReRAM macro Award in 2012, and the Ta-You Wu Memorial Award of National Science
with 443 MB/s write throughput,” in IEEE Int. Solid-State Circuits Council (NSC-Taiwan) in 2011. He served a program/organization committee
Conf. Dig. Tech. Papers, Feb. 2012, pp. 432–433. for IEEE MTDT from 2007 through 2009. He has been serving a program
[35] M.-F. Chang et al., “A process variation tolerant embedded split-gate committee for IEEE A-SSCC since 2011. He has been serving as the Asso-
Flash memory using pre-stable current sensing scheme,” IEEE J. Solid- ciate Executive Director for Taiwan’s 5-year National Program of Intelligent
State Circuits, vol. 44, no. 3, pp. 987–994, Mar. 2009. Electronics (NPIE) since 2011.

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
890 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 3, MARCH 2013

Shyh-Shyuan Sheu received the Ph.D. degree from Yu-Sheng Chen is currently working toward the
National Central University, Chungli, Taiwan. Ph.D. degree at the Institute of Electronics Engi-
Currently, he is the Circuit Design Group Manager neering, National Tsing Hua University, Taiwan.
with the Electronics and Optoelectronics Research He is a Device and Testing Engineer with the
Laboratory, Industrial Technology Research In- Industrial Technology Research Institute, Hsinchu,
stitute, Hsinchu, Taiwan. His research involves Taiwan. His research interests include CMOS tech-
memory, display, and CMOS image sensor circuit nology, nonvolatile memory technology, and circuit
design and technology. design for memory.

Ku-Feng Lin received the M.S. degree from Na-

tional Tsing Hua University, Hsinchu, Taiwan, in Heng-Yuan Lee received the Ph.D. degree from the
2010. Institute of Electronics Engineering, National Tsing
He is currently a Memory Circuit Design Engi- Hua University, Hsinchu, Taiwan.
neer with National Tsing Hua University, Hsinchu, He is a Device Engineer with the Industrial Tech-
Taiwan. His research interests include circuit designs nology Research Institute, Hsinchu, Taiwan. His re-
of SRAM, ROM, Flash, and RRAM. search interests include device development of Flash,
DRAM, and emerging memory technologies.

Che-Wei Wu received the B.S. and M.S. degrees in

electrical engineering from National Tsing Hua Uni-
versity, Hsinchu, Taiwan, in 2009 and 2011, respec- Chenhsin Lien received the B.S. degree in physics
tively. from National Tsing Hua University, Hsinchu,
He is currently a Memory Design Engineer with Taiwan, in 1975, and the Ph.D. degree in physics
MediaTek, Hsinchu, Taiwan. from Ohio State University, Columbus, in 1982.
He is a Professor with the Department of Elec-
trical Engineering, National Tsing Hua University
(NTHU), Hsinchu, Taiwan, where he is also the
Director of the Center of the Advanced Power
Technologies. Throughout his career, his research
has primarily focused on solid-state devices, ranging
from the quantum optoelectronic devices, CMOS
Chia-Chen Kuo received the B.S. degrees in elec- devices, nanoelectronic devices to memories. Since 1983, he has been with
trical engineering from National Tsing Hua Univer- the Department of Electrical Engineering, NTHU, where he is currently a
sity, Hsinchu, Taiwan, in 2010, where he is currently Professor. From 2004 to 2006, he was the Director of the Institute of Electronic
working toward the M.S degree. Engineering, NTHU. From 2006 to 2010, he was the Chair of Department of
His research interests include circuit designs of Electrical Engineering, NTHU. During 2010, he was the Acting Dean of the
SRAM and ReRAM. College of Electrical Engineering and Computer Science, NTHU. He served
on memory technology subcommittee of IEDM 2009–2010. He has authored
more than 100 technical papers. His recent research interests include studies on
nonvolatile memory such as resistive random-access memory (ReRAM) and
nanowire Schottky barrier SONOS memory.

Pi-Feng Chiu received the B.S. degree and M.S. Frederick T. Chen received the Ph.D. degree in ap-
degrees in electrical engineering from National plied physics from Cornell University, Ithaca, NY.
Tsing Hua University, Hsinchu, Taiwan, in 2010 and He is the RRAM Group Manager and a Deputy
2011, respectively. She is currently working toward Director of the Nanoelectronic Technology Division,
the Ph.D. degree at the University of California, Industrial Technology Research Institute, Hsinchu,
Berkeley. Taiwan. His research interests include advanced
During 2011 to 2012, she worked on resistive memory technologies, metal-insulator transitions
memory, nonvolatile SRAM, nonvolatile logic, and and nanoscale phenomena.
3DIC design with the Electronics and Optoelec-
tronics Research Laboratories, Industrial Technology
Research Institute, Hsinchu, Taiwan.

Yih-Shan Yang received the B.S. and M.S. degrees

in electronics engineering from National Tsing Hua Keng-Li Su received the M.S. degree from Chung
University, Hsinchu, Taiwan, in 2010 and 2012 re- Hua University, Hsinchu, Taiwan.
spectively. He is a Circuit Design Project Manager with the
In 2012, he joined Macronix International Co., Electronics and Optoelectronics Research Labo-
Ltd., Hsinchu, Taiwan. Since then, he has been ratory, Industrial Technology Research Institute,
working on the research and development of 3-D Hsinchu, Taiwan. His research interests include
vertical gate NAND Flash memory. memory and RF and CIS circuit design.

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.
CHANG et al.: HIGH-SPEED READ-WRITE RERAM MACRO USING PROCESS-VARIATION-TOLERANT CURRENT-MODE READ SCHEMES 891

Tzu-Kun Ku received the Ph.D. degree from Na- Ming-Jinn Tsai received the Ph.D. degree in mate-
tional Chiao Tung University, Hsinchu, Taiwan. rials science and engineering from the Massachusetts
He is a Director with the Electronics and Optoelec- Institute of Technology, Cambridge.
tronics Research Laboratory, Industrial Technology He then joined the Industrial Technology Research
Research Institute, Hsinchu, Taiwan. He is currently Institute (ITRI), Hsinchu, Taiwan, in 1991, where
involved with the development of device and process he has been working mainly on the semiconductor
technologies for new non-volatile memory, 3-D IC, device and process technology, including CCD,
and power electronics. IRCCD, power and RF devices, and high-K capac-
itors. Currently, he is a Senior Principle Engineer
and Research Director of the Electronics and Opto-
electronics Research Laboratory, ITRI, and working
on development of new nonvolatile memory technologies and wide-bandgap
devices for high-power applications. He has published approximately 250
referred journal and conference papers and holds nearly 20 patents.
Ming-Jer Kao received the Ph.D. degree from Na-
tional Cheng Kung University, Hsinchu, Taiwan.
He is a Deputy General Director with the Elec-
tronics and Optoelectronics Research Laboratory,
Industrial Technology Research Institute, Hsinchu,
Taiwan. His research interests include device devel-
opment of Flash, DRAM, MRAM, and emerging
memory technologies.

Authorized licensed use limited to: FUDAN UNIVERSITY. Downloaded on October 17,2024 at 11:35:30 UTC from IEEE Xplore. Restrictions apply.