COA

UNIT-5
Faculty Name:- Mr. Karan Siwach

Input-Output interface

Input-Output interface provides a method for transferring information between internal

storage (such as memory and CPU registers) and external I/O devices.
Peripherals connected to a computer need special communication links for interfacing
them with the central processing unit.
The communication link resolves the following differences between the computer and
peripheral devices.
● Devices and signals
Peripherals - Electromechanical Devices
CPU or Memory - Electronic Device
● Data Transfer Rate
Peripherals - Usually slower
CPU or Memory - Usually faster than peripherals
Some kinds of Synchronization mechanism may be needed
● Unit of
Information
Peripherals - Byte
CPU or Memory - Word
● Operating Modes
Peripherals - Autonomous, Asynchronous
CPU or Memory – Synchronous
To resolve these differences, computer systems include special hardware components
(Interfaces) between the CPU and peripherals to supervise and synchronize all input
and output interfaces.

I/O Bus and Interface Modules

The I/O bus consists of data lines, address lines and control lines.
I/O commands that the interface may receive:

● Control command: issued to activate the peripheral and to inform it what to

do.
● Status command: used to test various status conditions in the interface and
the peripheral.
● Output data: causes the interface to respond by transferring data from the bus
into one of its registers.
● Input data: is the opposite of the data output.

I/O versus Memory Bus

Computer buses can be used to communicate with memory and I/O in three ways:
● Use two separate buses, one for memory and other for I/O. In this method, all
data, address and control lines would be separate for memory and I/O.
● Use one common bus for both memory and I/O but have separate control lines.
There is a separate read and write lines; I/O read and I/O write for I/O and
memory read and memory write for memory.
● Use a common bus for memory and I/O with common control line. This I/O
configuration is called memory mapped.

Isolated I/O versus Memory Mapped I/O

Isolated I/O
● Separate I/O read/write control lines in addition to memory read/write
control lines
● Separate (isolated) memory and I/O address spaces
● Distinct input and output instructions

Memory-mapped I/O
● A single set of read/write control lines (no distinction between memory and
I/O transfer)
● Memory and I/O addresses share the common address space which reduces
memory address range available
● No specific input or output instruction so the same memory reference
instructions can be used for I/O transfers
Asynchronous Data Transfer:
Two units, such as a CPU and an I/O interface, are designed independently of each other.
If the registers in the interface share a common clock with the CPU registers, the
transfer between the two units is said to be synchronous.
In most cases, the internal timing in each unit is independent from the other in that
each uses its own private clock for internal registers. In that case, the two units are said
to be asynchronous to each other. This approach is widely used in most computer
systems.

Asynchronous data transfer between two independent units requires that control
signals be transmitted between the communicating units to indicate the time at which
data is being transmitted.
A strobe pulse supplied by one of the units to indicate to the other unit when the
transfer has to occur.
Another method commonly used is to accompany each data item being transferred with
a control signal that indicates the presence of data in the bus. The unit receiving the
data item responds with another control signal to acknowledge receipt of the data. This
type of agreement between two independent units is referred to as handshaking.

Strobe Control: The strobe may be activated by either the source or the destination
unit. The data bus carries the binary information from source unit to the destination
unit. Typically, the bus has multiple lines to transfer an entire byte or word. The strobe
is a single line that informs the destination unit when a valid data word is available in
the bus.

In this case the destination unit activates the strobe pulse, informing the source to
provide the data. The source unit responds by placing the requested binary information
on the data bus. The data must be valid and remain in the bus long enough for the
destination unit to accept it. The destination unit. Then disables the strobe.

Handshaking:

The disadvantage of the strobe method is that the source unit that initiates the transfer
has no way of knowing whether the destination unit has actually received the data item
that was placed in the bus. The handshake method solves this problem by introducing a
second control signal that provides a reply to the unit that initiates the transfer.
 Fig: Source initiated

Fig: Destination initiated

Modes of transfer
Data Transfer between the central computer and I/O devices may be handled in a variety
of modes.
Data transfer to and from peripherals may be handled in one of three possible modes.
● Programmed I/O
● Interrupt Driven I/O
● Direct Memory Access (DMA)

Programmed I/O
Programmed I/O operations are the result of I/O instructions written in the computer
program.
In programmed I/O, each data transfer in initiated by the instructions in the CPU and
hence the CPU is in the continuous monitoring of the interface.
Input instruction is used to transfer data from I/O device to CPU, store instruction is
used to transfer data from CPU to memory and output instruction is used to transfer
data from CPU to I/O device.
This technique is generally used in very slow speed computer and is not a efficient
method if the speed of the CPU and I/O is different.

Interrupt-driven I/O
In the programmed I/O method, the CPU stays in a program loop until the I/O unit
indicates that it is ready for data transfer. This is a time-consuming process since it
keeps the processor busy needlessly. It can be avoided by using an interrupt facility and
special commands to inform the interface to issue an interrupt request signal when the
data are available from the device. In the meantime the CPU can proceed to execute
another program. The interface meanwhile keeps monitoring the device. When the
interface determines that the device is ready for data transfer, it generates an interrupt
request to the computer. Upon detecting the external interrupt signal, the CPU
momentarily stops the task it is processing, branches to a service program to process
the I/O transfer, and then returns to the task it was originally performing.
DMA (DIRECT MEMORY ACCESS):
Transfer of data under programmed I/O is between CPU and peripheral. In direct
memory access (DMA), the interface transfers data into and out of the memory unit
through the memory bus. The CPU initiates the transfer by supplying the interface with
the starting address and the number of words needed to be transferred and then
proceeds to execute other tasks. When the transfer is made, the DMA requests memory
cycles through the memory bus. When the request is granted by the memory controller,
the DMA transfers the data directly into memory. The CPU merely delays its memory
access operation to allow the direct memory I/O transfer. Since peripheral speed is
usually slower than processor speed, I/O-memory transfers are infrequent compared to
processor access to memory.

DMA controller Interface that provides I/O transfer of data directly to and from the
memory and the I/O device
CPU initializes the DMA controller by sending a memory address and the number of
words to be transferred
Actual transfer of data is done directly between the device and memory through DMA
controller -> Freeing CPU for other tasks

The transfer of data between the peripheral and memory without the interaction of CPU
and letting the peripheral device manage the memory bus directly is termed as Direct
Memory Access (DMA).

The two control signals Bus Request and Bus Grant are used to fascinate the DMA
transfer. The bus request input is used by the DMA controller to request the CPU for the
control of the buses. When BR signal is high, the CPU terminates the execution of the
current instructions and then places the address, data, read and write lines to the high
impedance state and sends the bus grant signal. The DMA controller now takes the
control of the buses and transfers the data directly between memory and I/O without
processor interaction. When the transfer is completed, the bus request signal is made
low by DMA. In response to which CPU disables the bus grant and again CPU takes the
control of address, data, read and write lines.

The transfer of data between the memory and I/O of course facilitates in two ways
which are DMA Burst and Cycle Stealing.
DMA Burst: The block of data consisting a number of memory words is transferred at a
time.
Cycle Stealing: DMA transfers one data word at a time after which it must return
control of the buses to the CPU.
CPU is usually much faster than I/O (DMA), thus CPU uses the most of the memory
cycles.

DMA Controller
The DMA controller communicates with the CPU through the data bus and control lines.
DMA select signal is used for selecting the controller, the register select is for selecting
the register. When the bus grant signal is zero, the CPU communicates through the data
bus to read or write into the DMA register. When bus grant is one, the DMA controller
takes the control of buses and transfers the data between the memory and I/O.

The address register specifies the desired location of the memory which is incremented
after each word is transferred to the memory. The word count register holds the
number of words to be transferred which is decremented after each transfer until it is
zero. When it is zero, it indicates the end of transfer. After which the bus grant signal
from CPU is made low and CPU returns to its normal operation. The control register
specifies the mode of transfer which is Read or Write.

DMA Transfer
DMA request signal is given from I/O device to DMA controller.
DMA sends the bus request signal to CPU in response to which CPU disables its current
instructions and initialize the DMA by sending the following information.
● The starting address of the memory block where the data are available (for
read) and where data to be stored (for write)
● The word count which is the number of words in the memory block
● Control to specify the mode of transfer
● Sends a bust grant as 1 so that DMA controller can take the control of the buses
DMA sends the DMA acknowledge signal in response to which peripheral device puts
the words in the data bus (for write) or receives a word from the data bus (for read).
DMA Operation

CPU tells DMA controller:-

● Read/Write
● Device address
● Starting address of memory block for data
● Amount of data to be transferred
● CPU carries on with other work
● DMA controller deals with transfer
● DMA controller sends interrupt when finished

I/O Processors:

Processor with direct memory access capability that communicates with I/O
devices Channel accesses memory by cycle stealing.
A computer may incorporate one or more external processors and assign them the task
of communicating directly with the I/O devices so that no each interface need to
communicate with the CPU. An I/O processor (IOP) is a processor with direct memory
access capability that communicates with I/O devices. IOP instructions are specifically
designed to facilitate I/O transfer. The IOP can perform other processing tasks such as
arithmetic logic, branching and code translation.
The memory unit occupies a central position and can communicate with each processor
by means of direct memory access. The CPU is responsible for processing data needed
in the solution of computational tasks. The IOP provides a path for transferring data
between various peripheral devices and memory unit.

In most computer systems, the CPU is the master while the IOP is a slave processor. The
CPU initiates the IOP and after which the IOP operates independent of CPU and transfer
data between the peripheral and memory.

CPU – IOP Communication

The memory unit acts as a message centre where each processor leaves information for
the other.

● The CPU sends an instruction to test the IOP path.

● The IOP responds by inserting a status word in memory for the CPU to check.
 ● The bits of the status word indicate the condition of the IOP and I/O device, such
as IOP overload condition, device busy with another transfer or device ready for
I/O transfer.
● The CPU refers to the status word in in memory to decide what to do next.
● If all right up to this, the CPU sends the instruction to start I/O transfer.
● The CPU now continues with another program while IOP is busy with I/O
program.
● When IOP terminates the execution, it sends an interrupt request to CPU.
● CPU responds by issuing an instruction to read the status from the IOP.
● IOP responds by placing the contents to its status report into specified
memory location.
● Status word indicates whether the transfer has been completed or with error.

Interrupts:
An interrupt is a condition that halts the microprocessor temporarily to work on a
different task and then return to its previous task. Interrupt is an event or signal that
request to attention of CPU. This halt allows peripheral devices to access the
microprocessor.
Whenever an interrupt occurs the processor completes the execution of the current
instruction and starts the execution of an Interrupt Service Routine (ISR) or Interrupt
Handler. ISR is a program that tells the processor what to do when the interrupt occurs.
After the execution of ISR, control returns back to the main routine where it was
interrupted.
The different types of interrupts present in processor are given by:
Handling Multiple Devices:

When more than one device raises an interrupt request signal, then additional
information is needed to decide which which device to be considered first. The
following methods are used to decide which device to select: Polling, Vectored
Interrupts, and Interrupt Nesting. These are explained as following below.
1. Polling:
In polling, the first device encountered with with IRQ bit set is the device that is to
be serviced first. Appropriate ISR is called to service the same. It is easy to
implement but a lot of time is wasted by interrogating the IRQ bit of all devices.
2. Vectored Interrupts:

In vectored interrupts, a device requesting an interrupt identifies itself directly by

sending a special code to the processor over the bus. This enables the processor to
identify the device that generated the interrupt. The special code can be the
starting address of the ISR or where the ISR is located in memory, and is called the
interrupt vector.

3. Interrupt Nesting:

In this method, I/O device is organized in a priority structure. Therefore, interrupt

request from a higher priority device is recognized where as request from a lower
priority device is not. To implement this each process/device (even the processor).
Processor accepts interrupts only from devices/processes having priority more
 than it.

A program interrupt refers to the transfer of program control from a currently running
program to another service program as a result of an external or internal generated
request.
There are mainly three types of interrupts:

1. External interrupts: It arises due to external call from I/O devices. For e.g. I/O
devices requesting transfer of data, power failure, etc.
2. Internal interrupts: It arises due to illegal and erroneous use of an instruction
or data. For e.g. stack overflow, division by zero, invalid opcode, etc. These are
also called traps.
3. Software interrupts: It is initiated by executing an instruction. It can be used
by the programmer to initiate an interrupt at the desired point in the program.
External and internal interrupts are initiated from signals that occur in the hardware of
the CPU whereas Software interrupts occur from the instructions.

Hardware Interrupt:
The interrupt signal is coming from a device external to the CPU.
Example: keyboard interrupt, timer interrupt, etc.

• Maskable Interrupt: Hardware interrupts that can be masked or delayed when

a higher priority interrupt request arrives.
There are processor instructions that can selectively mask and unmask the interrupt
request lines of the CPU.

• Non-Maskable Interrupt: Interrupts that cannot be delayed and should be

handled by the CPU immediately.
Examples: power fail interrupts, real time system interrupts, etc.

Software Interrupt: They are caused due to execution of some instructions.

Not caused due to external inputs.

• TRAP: They are special instructions used to request services from the
operating system. Also called system calls.

• Exception: These are unplanned interrupts generated while executing a

program. They are generated from within the system.
Examples: invalid opcode, divide by zero, page fault, invalid memory access, etc.