STUDY GUIDE

FACULTY OF SCIENCE AND TECHNOLOGY

CBCA2103
Computer Architecture

Copyright © Open University Malaysia (OUM)

STU DY GU I DE CB CA2 1 0 3 Computer Architecture

FACULTY OF SCIENCE AND TECHNOLOGY

STUDY GUIDE
CBCA2103
Computer Architecture

Writer: Dr Nor’ashikin Ali

Universiti Tenaga Nasional

Developed by: Centre for Instructional Design and Technology

Open University Malaysia

First Edition, April 2015

Copyright © Open University Malaysia (OUM), April 2015, CBCA2103
All rights reserved. No part of this work may be reproduced in any form or by any means
without the written permission of the President, Open University Malaysia.

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INTRODUCTION TO STUDY GUIDE

This Study Guide is intended for Open University Malaysia's CBCA2103
Computer Architecture course. It comes in TWO parts, as described below:

Part One comprises the Course Introduction, which gives you an overview
of the course. More specifically, it provides you with the course synopsis,
objectives, learning outcomes and study load. There is a brief description of
the main textbook(s), which you must read to fulfil the course requirements.
There is also a list of additional reading references. You are encouraged to
go into myINSPIRE to check out the assessment, assignment and final
examination formats.

Part Two comprises the Learning Guide. This starts with an overview, a
recommended weekly study schedule to guide your learning process and a
brief description of the various elements in the Learning Guide. There is also
a list of topics to be covered. For each topic, you are given the specific
learning outcomes, a topic overview and a listing of the focus areas, together
with assigned readings and the pages where information on the focus areas
is found. To consolidate your learning and test your understanding, a
summary of the main content covered and study questions are provided at
the end of each topic.

Finally, there are two appendices, Learning Support and Study Tips, to
help you walk through the course successfully.

Please read through this Study Guide before you commence your course.
We wish you a pleasant study experience.

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Contents
Part One: Course Introduction ................................................................... 5
Synopsis ............................................................................................ 5
Objectives .......................................................................................... 5
Learning Outcomes ........................................................................... 5
Study Load ......................................................................................... 6
Main Textbook(s) .............................................................................. 6
Additional Recommended Readings.................................................. 7
Assessment ....................................................................................... 7

Part Two: Learning Guide ........................................................................... 8

Overview ............................................................................................ 8
Topic 1: Central Processing Unit (CPU) Organisation .................. 10
Topic 2: Pipelining and Parallel Processing ................................. 16
Topic 3: Microprogrammed Control Unit ....................................... 21
Topic 4: Memory Organisation ..................................................... 27
Topic 5: Input-Output Organisation .............................................. 32
Topic 6: Elements of Assembly Language ................................... 37
Topic 7: Basic Instructions ............................................................ 40
Topic 8: Multiprocessor ................................................................ 45
Topic 9: Case Study 8085 Processor ........................................... 52

Appendices ................................................................................................ 59
Appendix A: Learning Support ......................................................... 59
Appendix B: Study Tips ................................................................... 60

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PART ONE: COURSE INTRODUCTION

Synopsis

This course explores the design of computer systems and provides a

foundation for learners to understand modern computer system architecture.
This course includes a topic on understanding the components of computer
systems and the organisation of the Central Processing Unit (CPU). Several
other relevant topics covered are pipelining and parallel processing,
microprogrammed control unit, memory organisation and input-output
organisation. The concept of a multiprocessing environment, which includes
the design of multiprocessors, is also introduced in this course.

Objectives

The general aims of this course are to:

1. Expose learners to the components of a computer system and the main

concepts of computer architecture and organisation;

2. Introduce learners to assembly language statements; and

3. Provide learners with knowledge of a multiprocessing system and

enable learners to acquire skills related to the design of a
multiprocessor.

Learning Outcomes

By the completion of this course, you should be able to:

1. Explain the organisation of a Central Processing Unit (CPU);

2. Describe computer components, which include functions and the

interconnection of a computer system, pipelining and parallel
processing, microprogrammed control unit, memory organisation and
input-output organisation;

3. Identify assembly language statements; and

4. Illustrate the design of multiprocessors.

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Study Load

It is a standard OUM practice that learners accumulate 40 study hours for

every credit hour. As such, for a three-credit hour course, you are expected
to spend at least 120 hours of learning. Table 1 gives an estimation of how
the 120 hours can be accumulated.

Table 1: Allocation of Study Hours

Activities No. of Hours

Reading course materials and completing exercises 60
Attending 5 seminar sessions (3 hours for each session) 15
Engaging in online discussions 15
Completing assignment(s) 20
Revision 15
Total 120

Main Textbook(s)

Access through OUM Tan Sri Abdullah Sanusi Digital Library portal:

Detmer, R. C. (2012). Essentials of 8086 assembly language (2nd ed.).

Burlington, MA: Jones & Bartlett Learning.

Null, L., & Lobur, J. (2003). The essentials of computer organization and
architecture. Sudbury, MA: Jones & Bartlett Publishers.

Sharma, N. (2009). Computer architecture. New Delhi, India: University

Science Press.

Yadav, A. (2008). Microprocessor 8085, 8086. New Delhi, India: University

Science Press/Laxmi Publications.

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Additional Recommended Readings

Hennessy, J. L., & Patterson, D. A. (2000). Computer architecture: A

quantitative approach. San Diego, CA: Elsevier Science & Technology
Books.

Assessment

Please refer to myINSPIRE for information on the assessment format and

requirements.

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PART TWO: LEARNING GUIDE

Overview

This Learning Guide is arranged by topic. It covers essential content in the

main textbook and is organised to stretch over TEN study weeks, before
the examination period begins. Use this Learning Guide to plan your
engagement with the course content. You may follow the recommended
weekly study schedule in Table 2 to help you progress in a linear fashion,
starting with Week 1.

Table 2: Recommended Weekly Study Schedule

Topic Week
Topic 1: Central Processing Unit (CPU) Organisation 1
Topic 2: Pipelining and Parallel Processing 2
Topic 3: Microprogrammed Control Unit 3
Topic 4: Memory Organisation 4
Topic 5: Input-Output Organisation 5
Topic 6: Elements of Assembly Language 6
Topic 7: Basic Instructions 7
Topic 8: Multiprocessor 8
Topic 9: Case Study on 8085 processor 9 to 10

Each topic in the Learning Guide comprises the following sections (refer to
Figure 1):

 Learning Outcomes: Outline the specific tasks to be accomplished;

 Topic Overview: Briefly explains what the topic touches on so as to

provide a general interpretative framework for understanding the topic
content;

 Focus Areas: Identify the main and sub areas to be covered;

 Assigned Readings: Help you to navigate the main textbook and reading
materials;

 Content Summary: Provides an interpretative framework for understanding

the core content; and

 Study Questions: Help you to focus on key subject areas.

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Figure 1: Organisation of the Learning Guide

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Topic 1: Central Processing Unit (CPU) Organisation

Learning Outcomes

By the end of this topic, you should be able to:

1. Identify the main components of the Central Processing Unit (CPU)

and their functions;

2. Describe the organisation and architecture of the CPU; and

3. Explain how the CPU works by elaborating on the concepts of

instruction format, addressing modes, data transfer and manipulation,
status bit condition and program interrupt.

Topic Overview

This topic discusses the main components of the Central Processing Unit
(CPU), which includes describing the functions of each component. It
explains the various types of CPU organisations as well. This topic also
explains instruction format, addressing modes, data manipulation and
transfer, status bit condition and program interrupt, which are important
functions of the CPU.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Sharma, N. (2009). Computer
architecture. New Delhi, India:
University Science Press.

1.1 What is CPU? Chapter 3, Section 3.1.

1.2 CPU Organisation Chapter 3, Section 3.2.
1.3 Instructions Format Chapter 3, Section 3.3.
1.4 Addressing Modes Chapter 3, Section 3.4.
1.5 Data Transfer and Manipulation Chapter 3, Section 3.5.
1.6 Status Bit Conditions Chapter 3, Section 3.6.
1.7 Subroutine Call and Return Chapter 3, Section 3.7.
1.8 Program Interrupt Chapter 3, Section 3.8.

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Content Summary

1.1 The Control Processing Unit (CPU) can be defined as the brain of a
computer, as it handles all instructions to perform a specific task.

1.2 Three major parts of a CPU include:

 Arithmetic and Logic Unit (ALU) – Used to perform arithmetic and

logic microoperations when executing instructions;

 Control Unit – Consists of control input devices, output devices

and other components of a computer; and

 Register Set – This part stores data temporarily during the

execution of a program.

1.3 Figure 1.1 illustrates the components of a CPU and how they interact
with one another.

Figure 1.1: Components of a CPU

Source: Sharma (2009)

1.4 The primary function of a CPU is to execute the programs that reside
in the memory unit, which consists of a sequence of instructions.

1.5 A program is executed in the computer by going through a cycle for

each instruction, which in turn is divided into a sequence of phases.

1.6 The phases in each instruction cycle are as follows:

 Fetch the instruction from the memory unit;

 Decode the instruction;

 Fetch the operand; and

 Execute the instruction.

These phases will be repeated until they are interrupted.

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1.7 There are three types of CPU organisations as shown in Figure 1.2.

Figure 1.2: Three types of CPU organisations

1.8 A computer has three types of instructions and they are:

 Memory reference instructions;

 Register reference instructions; and

 Input-output instructions.

1.9 There are also three fields in an instruction:

 An operation code field which specifies the operation that is to be

performed;

 An address field which designates a memory address or a

processor register; and

 A mode field which specifies the way the operand or the effective
address is determined.

1.10 The instructions can be in zero, one, two or three address

instructions.

1.11 Addressing modes is a rule or a way by which the value of the

operand is referenced.

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1.12 The terms used in the addressing modes are:

 Address (A) – Contents of an address field in the instruction that

refers to a memory location;

 Register (R) – Contents of an address field that refers to a

register in the instruction;

 Program Counter (PC) – Keeps track of the instructions in the

program stored in the memory. It also holds the address of the
instruction that is to be executed and is incremented every time
an instruction is fetched from the memory; and

 Effective Address (EA) – the address of the operand when the

operand is actually stored. It is defined as the memory address
obtained from the computation dictated by the given addressing
mode.

1.13 Addressing modes can be divided into the following types:

 Implied Addressing – Operands are defined implicitly as a part of

the definition of the instruction itself.

 Immediate Addressing – Immediate addressing is the simplest

form of addressing mode. The operand itself is a part of the
instruction. An immediate mode instruction contains an operand
field.

 Direct Addressing – The operand is present in memory. When

accessing effective address (EA), the value of the operand will be
obtained immediately.

 Indirect Addressing – Overcomes the limitation of direct

addressing, which provides limited address space. The address
field of the instruction gives the address where the EA is stored in
the memory.

 Register Addressing – The operands are in registers that reside

within the CPU. The address fields refer to a register rather than a
main memory address.

 Register Indirect Addressing – An address field refers to a

register, whose contents give the address of the operand in
memory.

 Relative Addressing – The contents of the Program Counter is

used as a base address.

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 Indexed Addressing – The contents of an index register is added

with the address part of the instruction to obtain the effective
address (EA). An index register is a special CPU register that
contains an index value.

 Based Register Addressing – The contents of the base register is

added with the address part of the instruction to obtain the
effective address (EA).

 Auto Increment and Auto Decrement Addressing – A special

addressing mode that automatically increases or decreases the
index register.

1.14 The instructional set of a computer determines the machine’s

computational capabilities. The three fields of instructions include
Opcode, Address Field and Mode Field.

1.15 The Opcode instruction can be further categorised into three parts, as
summarised in Figure 1.3.

Figure 1.3: Categories of Opcode

1.16 Status bits are also called condition-code bits or flag bits. It is
convenient to check the status bits after an ALU operation.

1.17 A subroutine is a self-contained sequence of instructions which

performs a given computational task.

1.18 A program interrupt is used to handle a variety of problems that arise

out of a normal program sequence.

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Study Questions

1. Describe each component of a CPU and their respective functions.

2. List the phases in each instruction cycle for the instructions executed in
a CPU.

3. Describe briefly three types of CPU organisations.

4. What are the three types of instructions in a computer?

5. Describe the function of each field in an instruction.

6. What do you understand by the following terms of addressing modes?

(a) Address (A);
(b) Register (R);
(c) Program Counter (PC); and
(d) Effective Address (EA).

7. Explain each type of addressing mode.

8. What are the three categories of Opcode?

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Topic 2: Pipelining and Parallel Processing

Learning Outcomes

By the end of this topic, you should be able to:

1. Explain the concepts of pipelining and parallel processing; and

2. Differentiate between Reduced Instruction Set Computing (RISC) and

Complex Instruction Set Computers (CISC) architectures.

Topic Overview

This topic introduces the concepts of pipelining and parallel processing. It

also discusses the trends that lead towards parallel processing, by using
Flynn’s taxonomy. The concepts of pipelining and types of pipelining are also
elaborated in detail. This topic also identifies and explains RISC and CISC
architectures.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Sharma, N. (2009). Computer
architecture. New Delhi, India:
University Science Press.

2.1 Parallel Processing Chapter 4, Section 4.1 and 4.2.

2.2 Flynn’s Classification Chapter 4. Section 4.3.
2.3 Pipelining Chapter 4, Section 4.4.
2.4 RISC and CISC Architecture Chapter 4, Section 4.5.

Content Summary

2.1 The concept of parallel processing came about to improve the speed
of CPU performance. Parallel processing implies the simultaneous
processing of information. It is used to provide simultaneous data
processing tasks for the purpose of increasing the computational
speed of a computer system.

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2.2 The purpose of parallel processing is to speed up the processing

capability of computers and increase their throughput, that is, the
amount of processing that can be accomplished during a given
interval of time.

2.3 Parallel processing can be achieved by:

 Multiplicity of functional units;

 Parallelism and pipelining within the CPU;

 Overlapped CPU and input /output operations;

 The use of a hierarchical memory system;

 Balancing of subsystem bandwidths; and

 Multiprogramming and time sharing.

2.4 Parallel computers are those which emphasise parallel processing.

They can be divided into three architectural configurations, which are
pipeline computers, array processors and multiprocessor system.

2.5 Parallel processing can be classified from the internal organisation

of the processors, from the interconnection structure between
processors or the flow of information through the system.

2.6 One of the most used classifications is the Flynn’s classification.

Parallel processing may occur in the instruction stream, in the data
stream or in both. An instruction stream is a set of sequential
instructions to be executed by a single processor and the data stream
is the sequential flow of data required by the instruction stream.

Flynn’s classification divides computers into four major groups:

 Single Instruction Single Data Stream (SISD);

 Single Instruction Multiple Data Stream (SIMD);

 Multiple Instruction Single Data Stream (MISD); and

 Multiple Instruction Multiple Data Stream (MIMD).

2.7 Pipelining is a technique of overlapping the execution of several

instructions to reduce the execution time of a set of instructions.

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2.8 A pipeline can be described as a collection of processing segments

through which binary information flows.

2.9 The process of executing an instruction in a digital computer involves

four major steps as described in Figure 2.1.

Figure 2.1: Four steps of executing an instruction in a digital computer

2.10 There are two classes of pipeline, which are:

 Arithmetic Pipeline

 It divides an arithmetic operation into suboperations for

execution in the pipeline segments;

 It is used to implement complex arithmetic functions like

floating point addition, multiplication and addition; and

 It is found in very high speed computers.

 Instruction Pipeline

 It increases the performance of a processor by overlapping

the fetch, decode and execute phases of the instruction cycle.

 Issues regarding the instruction pipeline are data

dependency, branch difficulties and resource conflicts.

 An instruction pipeline consists of five stages, as shown in

Figure 2.2:

Figure 2.2: Five stages of an instruction pipeline

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2.11 An important aspect of computer architectures is the design of the

instruction set for the processor. The instruction set chosen for a
particular computer determines the way the machine’s language
programs are constructed. The evolution in computer architecture is
to maximise the speed of operation or minimise execution time, which
will in turn minimise development cost and sale price.

2.12 A computer with a large number of instructions is classified as a

Complex Instruction Set Computer (CISC).

2.13 The purpose of a CISC is to simplify the compilation and improve the
overall performance of a computer.

2.14 The essential goal of CISC architecture is to attempt to provide single

machine instructions for each statement that is written in a high level
language.

2.15 Examples of CISC include digital equipment corporation Virtual

Address Extension (VAX) computers and IBM 370 computers.

2.16 Major characteristics of CISC are as follows:

 A large number of instructions – Typically from 100 to 250

instructions;

 Some instructions perform specialised tasks and are used

frequently;

 A large variety of addressing modes – Typically from five to 20

different modes;

 Variable length instruction formats; and

 Instructions that manipulate operands in the memory.

2.17 The RISC architecture is an attempt to reduce execution time by

simplifying the instruction set of a computer.

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2.18 Major characteristics of RISC include:

 Relatively few instructions;

 Relatively few addressing modes;

 Memory access limited to load and store instructions;

 All operations are done within the register of the CPU;

 Fixed-length, easily decoded instruction format;

 Single cycle instruction execution; and

 Hardwired rather than microprogrammed control.

Study Questions

1. Explain the concept of parallel processing. How does it improve the

performance of the CPU?

2. What are the methods to achieve parallel processing?

3. Name three architectural configurations of parallel computers.

4. Explain four major groups of Flynn’s classification.

5. What are the four steps in executing an instruction?

6. Describe each class of pipeline.

7. Differentiate the major characteristics between CISC and RISC

architectures. Give examples for each architectures.

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Topic 3: Microprogrammed Control Unit

Learning Outcomes

By the end of this topic, you should be able to:

1. Describe the architecture of a computer control unit and its function;

2. Compare the two major types of control units; and

3. Explain the concepts of address sequencing capabilities and

microinstruction format.

Topic Overview

This topic begins by explaining the basic parts of a digital computer system
and their functions. This topic also describes the function of control units
including the function of two major types of control units. The terms and
concepts used such as address sequencing capabilities and microinstruction
format are also introduced in this topic.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Sharma, N. (2009). Computer
architecture. New Delhi, India:
University Science Press.

3.1 The Concept of a Digital Chapter 6, Section 6.1.

Computer
3.2 Control Unit Chapter 6. Section 6.2.
3.3 Address Sequencing Capabilities Chapter 6, Section 6.3.
3.3 Microinstruction Format Chapter 6, Section 6.4.

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Content Summary

3.1 A digital computer can be divided into two parts which are:

 Execution unit; and

 Control unit.

3.2 The Execution Unit (EU) and Control Unit (CU) in a processor are as
illustrated in Figure 3.1.

Figure 3.1: Block diagram of a processor (EU + CU)

Source: Sharma (2009)

3.3 The execution unit is a network of functional units that perform

certain microoperations on data. The execution unit of the processor
contains circuits to perform arithmetic and logical operations on data
and a storage unit where the data is stored.

3.4 A control unit is one of the components of a CPU apart from the
register set and ALU.

3.5 The function of the control unit in a digital computer is to initiate

sequences of microoperations that comprise instructions. The control
unit issues control signals to the execution unit.

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3.6 In general, there are two major approaches of control units:

 Hardwired control unit; and

 Microprogrammed control unit.

3.7 The hardwired control unit and microprogrammed control unit are
explained in detail in Table 3.1.

Table 3.1: The Hardwired Control Unit and Microprogrammed Control Unit

Hardwired Control Unit Microprogrammed Control Unit

When the control signals are When the control signals originate
generated by hardware, the control from data stored in a special unit
unit is hardwired. and constitute a program on the
small scale, the control unit is
microprogrammed.
The hardwired approach to The microprogramme is a sequence
implement a control unit views the of microinstructions. It has two
controller as a sequential circuit memories – a main memory and a
based on different states in a control memory. The main memory
machine. is for storing user program and the
control memory is for storing
microprogramme.
The drawback of the hardwired Microprogramming makes the
control unit is that once the unit control unit design more systematic,
is constructed, it is difficult to making it easy to change.
implement changes.
The RISC architecture concept uses The CISC architecture concept uses
hardwired control. the microprogrammed control unit
approach.

3.8 Address sequencing is a selection of address for control memory.

3.9 Address sequencing capabilities are required in these four situations:

 Incrementing of the control address register;

 Unconditional branch or conditional branch, depending on status

bit conditions;

 Mapping process (bits of the instruction for control memory); and

 A facility for subroutine return.

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3.10 Figure 3.2 illustrates the address selection for control memory.

Figure 3.2: Address selection for control memory

Source: Sharma (2009)

3.11 The status bits control the conditional branch decisions generated in
the branch logic.

3.12 The branch logic hardware may be implemented in a variety of ways.

First, test the specified condition and branch to the indicated address
to determine if the condition is met; otherwise the control address
register is just incremented.

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3.13 Figure 3.3 has an operation code of four bits which can specify up to
16 distinct instructions. A simple mapping process that converts the
four bit operation code to a six bit address for control memory is
shown in Figure 3.3.

Figure 3.3: Mapping from instruction code to microinstruction address

Source: Sharma (2009)

3.14 Subroutines are programs that are used by other routines. A

subroutine can be called from any point within the main body of the
microprogramme.

3.15 Microinstructions can be saved by subroutines that use a common

section of microcode.

3.16 Subroutines must have provision for:

 Storing the return address during a subroutine call; and

 Restoring the address during a subroutine return.

3.17 Two types of microinstruction formats include:

 Horizontal Format – Long format, it has the ability to express a

high degree of parallelism and little encoding of control
information; and

 Vertical Format – Short format, has a limited ability to express

parallelism and considerable encoding of control information.

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Study Questions

1. Explain the basic parts of a digital computer. Draw a diagram to show

the position of these parts in a computer.

2. What is the function of a control unit?

3. What are the two major types of control unit? Describe each one in
detail.

4. What is address sequencing?

5. In what situations are address sequencing capabilities required?

6. Explain the processes involved in address sequencing.

7. What are the two types of microinstruction formats?

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Topic 4: Memory Organisation

Learning Outcomes
By the end of this topic, you should be able to:

1. Explain the basic function of a memory unit and the criteria needed for
choosing the memory unit;

2. Describe the memory hierarchy components and the function of each

component; and

3. Identify the function of virtual memory.

Topic Overview

This topic discusses various memory device organisations. The topic begins
with discussion on the basic function of a memory unit and the criteria
needed when choosing the memory, followed by an explanation of each level
in the memory unit. This topic also discusses Random Access Memory
(RAM) and Read Only Memory (ROM) and its respective functions. The
function of associative memory and details on the operation of this type of
memory, followed by the functions of cache memory are also presented in
this topic. Lastly, this topic discusses the function of virtual memory and
explains the memory and address space functions.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Sharma, N. (2009). Computer
architecture. New Delhi, India:
University Science Press.

4.1 Memory Unit Chapter 7, Section 7.1.

4.2 Memory Hierarchy Chapter 7, Section 7.2.
4.3 Main Memory Chapter 7, Section 7.3.
4.4 Associative Memory Chapter 7, Section 7.4.
4.5 Cache Memory Chapter 7, Section 7.5.
4.6 Virtual Memory Chapter 7, Section 7.6.

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Content Summary

4.1 A memory unit is an essential component in digital computers and is

needed for storing programs and data.

4.2 The criteria in deciding which memory unit to use are:

 Cost;

 Speed;

 Memory access time;

 Data transfer rate;

 Reliability; and

 Memory cycle time.

4.3 The components of a memory system (memory hierarchy) are

illustrated in Figure 4.1:

Figure 4.1: Four components of a memory system

4.4 The main memory is the control storage device of a computer

system. It has a large and fast memory to store the data and
programs needed by the CPU.

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4.5 Main memory uses semiconductor integrated circuits. It is made up of

RAM (Random Access Memory) and ROM (Read Only Memory)
chips. The RAM is for storing programs and data that can be
changed (permanent programs). ROM is a bootstrap loader that is
used to start the computer software operating when power is on.

4.6 The integrated RAM chips have the following criteria:

 The capacity of a RAM chip is 128  8 RAM = 27 = 128 (7 bit

address lines);

 It has two operating modes which are static and dynamic; and

 The dynamic RAM provides reduced power consumption and

larger storage capacity while the static RAM is easier to use and
has shorter read and write cycles.

4.7 ROM chips have the following criteria:

 It has the capacity of 512  8 ROM = 29 = 512 (9 bit address

lines); and

 The contents of ROM remain constant regardless of whether or

not the power is turned on or off.

4.8 Associative memory is also known as Content Addressable Memory

(CAM). It is an expensive memory unit accessed by content.

4.9 Associative memory provides parallel searching.

4.10 Cache memory is generally the top level and also the fastest
component in the memory hierarchy. It has the memory of 512K  12
bit word.

4.11 As displayed in Figure 4.2, cache memory is a small high speed

memory, placed between the CPU and the main memory. It stores
the most frequently accessed instructions and data in the fast cache
memory and reduces references to the main memory.

Figure 4.2: Cache memory

Source: Sharma (2009)

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4.12 The references to the main memory tend to be confined within a few
localised areas in memory.

4.13 The basic operations of the cache is that when the CPU needs to
access the memory, first the cache is examined:

 Cache hit: Data is found in the cache, results in data transfer at

maximum speed; and

 Cache miss: Data not found in the cache. Processor loads data
from the main memory and copies it into the cache.

4.14 The performance of the cache memory is measured by a hit ratio.

4.15 A hit ratio is defined as the number of hits divided by the total number
of CPU references to memory (hits + misses).

4.16 An important aspect of cache organisation is memory write requests.

There are two methods that the hardware may employ in memory
write requests, which are write-through and write-back methods.

4.17 The transformation of data from the main memory to cache memory
is called a mapping process.

4.18 Based on the mapping process, cache organisation is categorised

into three types:

 Associative mapping cache;

 Direct mapping cache; and

 Set-associative mapping cache.

4.19 Virtual memory is a technique that is used to both allow memory

storage to serve as a level in the memory system and to provide
protection between programs running on the same system.

4.20 Virtual memory allows translating auxiliary memory into the location
of the main memory. It maps memory addresses used by a program,
called virtual addresses, into physical addresses in the computer
memory.

4.21 Address space is defined as a virtual address that is used by a

programmer.

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4.22 Memory space is the physical address, which is an address in the

main memory. It is stored in the memory address register.

4.23 The memory map translates virtual addresses into physical

addresses.

4.24 Paging is a hardware-oriented technique for mapping physical

memory.

4.25 Page replacement policies include:

 Page fault: The page referenced by the CPU is not in the main
memory;

 A new page should be transferred from the auxiliary memory to

the main memory; and

 Replacement algorithm: First In, First Out (FIFO) and Least

Recently Used (LRU).

Study Questions

1. What is a memory unit?

2. What are the criteria for choosing a memory unit?

3. What are the components that make up a memory hierarchy?

4. Describe the function of the main memory.

5. What is the difference between the RAM and ROM chips?

6. What is associative memory?

7. Describe how cache memory is different from other memory units.

8. What is the difference between cache hit and cache miss?

9. What are the mapping processes in cache memory organisation?

10. Explain the concept of virtual memory. What are the functions of
address space and memory space that are used in virtual memory?

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Topic 5: Input-Output Organisation

Learning Outcomes

By the end of this topic, you should be able to:

1. Identify the functions of peripheral devices of a computer system;

2. Explain the input-output interface and the commands used in the

interface; and

3. Describe various methods of data transfer and the function of I/O

processor and serial communication.

Topic Overview

This topic introduces the peripheral devices that are attached to a computer,
followed by an explanation of input-output interface and the commands
received by the interface. This topic also explores various methods of data
transfer and their respective functions. Lastly, the topic elaborates the
function of the input-output processor and serial communication.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Sharma, N. (2009). Computer
architecture. New Delhi, India:
University Science Press.

5.1 Peripheral Devices Chapter 8, Section 8.1 and 8.2.

5.2 Input-Output Interface Chapter 8,Section 8.3.
5.3 Asynchronous Data Transfer Chapter 8, Section 8.4.
5.4 Direct Memory Access Chapter 8, Section 8.5.
5.5 Input-Output Processor Chapter 8,Section 8.6.
5.6 Serial Communication Chapter 8, Section 8.7.

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Content Summary

5.1 The input-output (I/O) subsystem provides an efficient communication

mode between the central system and the outside environment.

5.2 Input-output devices that are attached to the computer are also called
peripherals. Among the most commonly used peripherals are:

 Monitor (visual output device): Cathode Ray Tube (CRT) or

Liquid-crystal Display (LCD);

 Input device: Light pen, mouse, touch screen, joy stick or digitiser;
and

 Printer (hardcopy device): Dot matrix (impact), thermal, ink jet or

laser jet (non-impact).

5.3 Input-output interface circuits are special hardware components

between the CPU and the peripherals.

5.4 Computer systems include the communication link to supervise and

synchronise all input and output transfers.

5.5 The I/O bus connects data lines, address lines and control lines.

5.6 Four commands received by an interface are as follows:

 Control command;

 Status command;

 Data input command; and

 Data output command.

5.7 Synchronous data transfer is said to occur when the data is

transferred simultaneously and the registers in the interface share a
common clock with CPU registers.

5.8 Asynchronous data transfer occurs when the internal timing in each
unit (CPU and interface) is independent from one another.

5.9 Each unit uses its own private clock for internal registers.

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5.10 Methods for asynchronous data transfer:

 Strobe base: Control signal to indicate the time at which data is

being transmitted; and

 Handshaking: Agreement between two independent units.

5.11 Direct Memory Access (DMA) is implemented using a DMA

controller. It is a data transfer technique that takes over the buses to
manage the transfer directly between the I/O device and memory.

5.12 Figure 5.1 illustrates the position of the DMA controller in a computer
system.

Figure 5.1: DMA transfer

Source: Sharma (2009)

5.13 The Input-Output Processor (IOP) has a DMA capability that

communicates with I/O devices. It functions like a CPU but is
designed to handle the details of I/O processing.

5.14 The IOP is a specialised processor that can load, store and execute
instructions.

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5.15 Figure 5.2 shows the working of a computer with IOP. The
communication between the IOP and CPU can take on different
forms, depending on the particular computer used.

Figure 5.2: Block diagram of a computer with IOP

Source: Sharma (2009)

5.16 In an I/O based system, I/O devices can directly access the memory
without intervention by the processor.

5.17 Serial communication is a standard device communication protocol. It

is commonly found in almost every computer.

5.18 There are three modes of data transmission, which are:

 Simplex: Transmitted in one direction only;

 Half-duplex: Transmitted in both directions but only in one

direction at a time; and

 Full-duplex: Transmitted in both directions simultaneously.

5.19 Data link is the communication lines, modems and other equipment
used in the transmission of information between two or more stations.

5.20 Data link protocol includes character-oriented protocol and bit-

oriented protocol.

5.21 Data transparency uses Data Link Escape (DLE) character which is
inefficient and complicated to implement.

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Study Questions

1. List the peripheral devices (I/O) that are attached to a computer.

2. What is the function of an I/O interface?

3. What are the commands that should be received by the interface for
the interface to activate?

4. What is the difference between asynchronous and synchronous data

transfer?

5. Describe how Direct Memory Access (DMA) works as a data transfer

technique.

6. What is the function of an input-output processor to I/O devices?

7. Describe three modes of data transmission in serial communication.

8. Explain the following terms:

(a) Data link; and
(b) Data transparency.

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Topic 6: Elements of Assembly Language

Learning Outcomes

By the end of this topic, you should be able to:

1. Execute assembly language programs; and

2. Apply the operands for data definition directives and executable

instructions.

Topic Overview

This topic begins with an explanation on assembly language statements,

which includes three types of statements. This is followed by the format of
assembly language statements as well as the list of identifiers used in them.
This topic also presents types of data declaration, followed by types of
instructions operands as well as the types of addressing modes used in Intel
80  86 processors.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Detmer, R. C. (2012). Essentials of
8086 assembly language (2nd ed.).
Burlington, MA: Jones & Bartlett
Learning.

6.1 Assembly Language Statements Chapter 2, Section 2.1.

6.2 Data Declaration Chapter 2, Section 2.3.
6.3 Instructions Operands Chapter 2, Section 2.4.

Content Summary

6.1 An assembly language source code file consists of a collection of

statements.

6.2 Comments are used to describe the source code and they always
start with a semicolon. These comments are ignored and are not
executed during assembly.

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6.3 The three types of assembly language statements are:

 Instructions: Each corresponds to a CPU instruction;

 Directives: Tells the assembler what to do; and

 Macros: Expands into additional statements.

6.4 Other statements have the format as shown in Figure 6.1.

Figure 6.1: The format of other statements

6.5 Based on Figure 6.1, the name field ends with a colon (:) when used
with an instruction and has no colon when issued with a directive.

6.6 The mnemonic in a statement indicates a specific instruction,

directive or macro. If there is more than one operand, they are
separated by commas.

6.7 Names and other identifiers used in assembly language are formed
from letters, digits and special characters. Special characters include
underscore (_), question mark (?), dollar symbol ($) and alias symbol
(@).

6.8 A name may not begin with a digit. An identifier may have up to
247 characters.

6.9 Numeric operands can be expressed in decimal, hexadecimal, binary

or octal notations.

6.10 BYTE, DWORD or WORD directives reserve bytes, doublewords or

word of storage and optionally assign initial values.

6.11 Instructions operands have three types:

 Constants;

 CPU register designations; and

 References to memory locations.

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6.12 Many instructions have two operands. The first operand gives the
destination of the operation while the second operand identifies a
source for the operation, never the destination.

6.13 The addressing modes used by Intel 8086 microprocessors are as

summarised in Table 6.1.

Table 6.1: Addressing Modes

Mode Location of Data

Immediate Data built into the instruction
Register Data in a register
Memory Data in storage

6.14 Memory mode operands come in several formats, two of which are:

 Direct; and

 Register indirect.

6.15 The 64-bit environment uses RIP-relative addressing instead of direct

memory addressing.

Study Questions

1. Name and describe the three types of assembly language statements.

2. What are the identifiers that are allowed in assembly language

statements?

3. In what form can numeric operands be expressed?

4. What do BYTE, DWORD or WORD directives mean?

5. What are the three types of instructions operands?

6. Explain the addressing modes used by Intel 8086 microprocessors.

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Topic 7: Basic Instructions

Learning Outcomes

By the end of this topic, you should be able to:

1. Demonstrate ways to copy data between memory and CPU registers

and between two registers;

2. Summarise the use of 8086 addition, subtraction, multiplication and

division instructions; and

3. Discuss how the execution of these instructions affects flags.

Topic Overview

This topic covers instructions to copy data from one location to another and
instructions used for integer arithmetic. It specifies the types of operands that
are allowed for various instructions. This topic also explains the instructions
on the integer addition and subtraction, followed by multiplication instructions
and division instructions.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Detmer, R. C. (2012). Essentials of
8086 assembly language (2nd ed.).
Burlington, MA: Jones & Bartlett
Learning.

7.1 Copying Data Chapter 3, Section 3.1.

7.2 Integer Addition and Subtraction Chapter 3, Section 3.2.
Instruction
7.3 Multiplication Instruction Chapter 3, Section 3.3.
7.4 Division Instruction Chapter 3, Section 3.4.

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Content Summary

7.1 Instructions to copy data in 8086 architectures are done using mov
(“move”) in a form of mov destination, source where the destination
must either be a register or memory location and source may be a
constant, another register or a memory location.

7.2 This instruction copies a byte, word or doubleword value from the
source operand location to the destination operand location.

7.3 The value stored at the source location is not changed.

7.4 The destination location must be the same size as the source.

7.5 In this language, combinations of both source and destination are

not allowed to be in the memory.

For example:
count: = number

Mov count, number is considered illegal for two memory operands if

both count and number reference memory locations.

It requires multiple instructions instead. For example:

move ax, number
mov count, eax

7.6 The length of time an instruction takes to execute is measured in

clock cycles. The actual time is determined by the clock speed of the
processor.

For example:

The Intel 8088 in IBM PC had a clock speed of 4.77 MHz that is
4,770,000 cycles per second.

Now computer systems have exceeded 200 MHz that is 200,000,000

cycles per second (210ns; ns = nanosecond).

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7.7 Exchanges of data in one location with data from another location in
a single instruction can be done using xchg.

For example, suppose value1 and value2 are being exchanged.

Assuming that value1 is stored in the EAX register and value2 is

stored in the EBX register, the code is:
xchg eax, ebx; swap value1 and value2

The xchg instruction makes the code shorter and clearer.

If using mov, the codes for swapping are:

mov ax, eax
ove ax, ebx
mov ebx, ecx

7.8 The Intel 8086 microprocessor has add and sub instructions to
perform addition and subtraction using byte, word or doubleword
length operands.

7.9 Each add instruction has the form:

add destination, source

When an add instruction is executed, the integer at the source is

added to the integer at the destination and the sum replaces the
original value at the destination.

7.10 Each sub instruction has the form:

sub destination, source

When a sub instruction is executed, the integer at the source is

subtracted from the integer at the destination and the difference
replaces the old value at the destination.

With both add and sub instructions, the source (second) operand is
unchanged.

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7.11 The Intel 8086 microprocessor has inc and dec instructions to
increment (add one to) and decrement (subtract one from) a single
operand and a neg instruction that negates a single operand.
inc destination
dec destination

7.12 Writing an assembly language program requires planning on how

registers and memory will be used.

7.13 Two multiplication instruction mnemonics are as follows:

 imul instruction treats its operands as signed numbers; while

 mul instruction treats its operands as unsigned binary numbers.

7.14 There are fewer variants of mul than of imul. The mul instruction has
a single operand and its format is:

mulsource

7.15 The source operand can be byte-, word-, doubleword- or quadword-

length (quadword in 64-bit mode only). It can be in a register or in the
memory, but cannot be immediate.

7.16 The signed multiplication instructions use mnemonic imul. There are
three formats, each with a different number of operands. They are:

 imul source;

 imul destination register, source; and

 imul register, source, immediate.

7.17 The division instructions have formats such as:

 idiv source; and

 div source.

7.18 The source operand identifies the divisor. The divisor can be in a
register or the memory but not immediate.

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Study Questions

1. Write an instruction to copy data from one location to another location

in 8086 machines.

2. Describe how the data is moved from one location to another.

3. How can the length of time an instruction takes to execute be

measured and how can the actual time be determined?

4. If the Intel 8088 in IBM PC had a clock speed of 4.77 MHz, what is a
clock speed in cycles per second?

5. Write a single instruction to exchange data in one location with data

from another location.

6. What are the operands used for add and sub instructions?

7. Write a statement for addition and subtraction.

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Topic 8: Multiprocessor
Learning Outcomes

By the end of this topic, you should be able to:

1. Explain the concept of a multiprocessing system;

2. Discuss the categories and characteristics of various designs of

multiprocessors; and

3. Recommend other advanced computing architectures.

Topic Overview

This topic starts by explaining the concept of a multiprocessing system

and the characteristics of multiprocessor systems. This topic also includes
discussions on categories and characteristics of various designs of
multiprocessors. Finally, other advanced computing architectures are
introduced and discussed.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Null, L., & Lobur, J. (2003). The
essentials of computer organization and
architecture. Sudbury, MA: Jones &
Bartlett Publishers.

8.1 Multiprocessing Environment Chapter 9, Section 9.4.3.

8.2 Multiple Instruction Streams and Chapter 9, Section 9.4.3.
Multiple Data Streams (MIMD)
8.3 Classification of Multiprocessors Chapter 9, Section 9.4.4.
8.4 Shared Memory or Tightly Chapter 9, Section 9.4.4.
Coupled Systems
8.5 Shared Memory MIMD Chapter 9, Section 9.4.4.
8.6 Distributed Computing Chapter 9, Section 9.4.5.
8.7 Remote Procedure Calls Chapter 9, Section 9.4.5.
8.8 Alternative Approaches to Chapter 9, Section 9.5.
Parallelism

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Content Summary

8.1 In a multiprocessing environment, the CPUs cooperate with one

another to solve problems, working in parallel to achieve a common
goal. A machine can have either one or multiple streams of data and
can have either one or multiple processors working on this data.

8.2 Machines use Multiple Instruction Streams and Multiple Data

Streams (MIMD) which have a number of processors that function
asynchronously and independently.

8.3 At any one time, different processors may be executing different

instructions on different pieces of data.

8.4 Multiprocessors are classified by the memory organisation, shown in

Figure 8.1.

Figure 8.1: Classification of multiprocessors

8.5 Shared memory or a tightly-coupled system has the following criteria:

 It uses the same memory and is thus known as shared memory

processors. This does not mean all processors must share one
large memory;

 Each processor could have a local memory but which must be

shared with other processors; and

 It is also possible that local caches could be used with a single

global memory.

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8.6 The three criteria are illustrated in Figure 8.2.

Figure 8.2: Shared memory configurations

Source: Null & Lobur (2003)

8.7 The global shared memory can be divided equally among the
processors.

8.8 Shared memory MIMD machines can be divided into two categories
according to how they synchronise their memory operations, which
are:

 Bus-based shared-memory architecture; and

 Switch-based architecture.

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8.9 In Uniform Memory Access (UMA) systems, all memory accesses

take the same amount of time.

8.10 A UMA machine has one pool of shared memory that is connected to
a group of processors through a bus or switched network.

8.11 All processors have equal access to memory, according to the

established protocol of the interconnection network.

8.12 The drawback is the scalability of UMA machines which is limited by

the properties of interconnection networks.

8.13 Non-Uniform Memory Access (NUMA) machines provide each

processor with its own piece of memory.

8.14 The memory space of a NUMA machine is distributed across all of

the processors.

8.15 The drawback of NUMA is that the memory access time is

inconsistent across the address space of the machine.

8.16 Distributed computing is another form of multiprocessing. All

multiprocessor systems are also distributed systems because the
processing load is divided among a group of processors that work
collectively to solve a problem.

8.17 When most people use the term distributed system, they are referring
to a loosely-coupled system. Loosely-coupled distributed computers
depend on a network for communication among processors.

8.18 Multiprocessors can be connected through a network (Figure 8.3).

Figure 8.3: Multiprocessors connected by a network

Source: Null & Lobur (2003)

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8.19 Distributed computing use Network of Workstations (NOWs). These

systems allow idle PC processors to work on small pieces of large
problems.

8.20 Remote Procedure Calls (RPCs) extend the concept of distributed

computing and provide necessary transparency for resource sharing.

8.21 RPCs enable a computer to invoke a procedure to use the resources

available on another computer.

8.22 The procedure itself resides on the remote machine but the
invocation is done as if the procedure were local to the calling
system.

8.23 In dataflow computing, the control of the program is directly tied to

the data itself.

8.24 An instruction is executed when the data is available.

8.25 Execution flow is completely determined by data dependencies.

8.26 Data flows continuously and is available to multiple instructions at the

same time.

8.27 Each instruction is considered to be a separate process, not by

referring to memory but by referring to other instructions.

8.28 There is no concept of share data storage in these systems and there
are no program counters to control execution.

8.29 The advantages of dataflow computing are that data flow

multiprocessors do not suffer from the contention and cache
coherency problems.

8.30 Neural network is an alternative form of multiprocessor computing

with a high degree of connectivity.

8.31 Neural networks are useful in dynamic situations where there is no

exact algorithmic solution and where processing is based on an
accumulation of previous behaviour.

8.32 Neural networks are based on the parallel architecture of human

brains.

8.33 They can deal with imprecise and probabilistic information and they
allow adaptive interaction between the processing elements to occur.

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8.34 Neural network computers are composed of a large number of

processing elements that can handle one piece of larger problems.

8.35 Other names of neural networks include:

 Connectionist systems;

 Adaptive systems; and

 Parallel distributed processing systems.

8.36 Neural networks have been applied extensively in many areas, as

illustrated in Figure 8.4.

Figure 8.4: Ten areas of neural networks application

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8.37 Systolic array computers derive their name based on the analogy of
how the blood flows through a biological heart.

8.38 They are a network of processing elements that compute data by

circulating it through the system.

8.39 Systolic arrays employ a high degree of parallelism (through

pipelining) and can sustain a very high throughput.

8.40 Connections are short and the design is simple and thus highly
scalable.

8.41 The advantages of systolic arrays are that they tend to be robust,
highly compact, efficient and cheap to produce.

8.42 However, the drawbacks are that they are highly specialised and thus
inflexible as to the types of problems that can be solved.

Study Questions

1. How does a computer work in a multiprocessing environment?

2. In your own words, define the MIMD architecture.

3. Differentiate each classification of multiprocessors.

4. Explain the concept of tightly-coupled systems.

5. Discuss two categories of shared memory MIMD machines and how

they are different from each other.

6. Briefly explain the concept of distributed computing and how Remote

Procedure Calls (RPC) is related to distributed computing.

7. Briefly explain the following advanced architectures:

(a) Dataflow computing;
(b) Neural networks; and
(c) Systolic arrays.

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Topic 9: Case Study 8085 Microprocessor

Learning Outcomes

By the end of this topic, you should be able to:

1. Explain the PIN configuration of a 8085 microprocessor;

2. Describe the functional components of a 8085 microprocessor; and

3. Summarise on the various addressing modes, types of instruction,

timing of instructions and interrupt handling of a 8085 microprocessor.

Topic Overview

This topic discusses the 8085 microprocessor in detail. It provides pin

configuration of the 8085. This topic presents the functional description of the
8085, which includes functions such as interrupt, clock inputs, the ALU,
general purpose register and program counter, followed by basic system
timing. This topic also presents other essential functional capabilities of the
microprocessor such as instruction format, addressing modes, stack,
interrupt, memory interfacing, machine cycles and bus timings.

Focus Areas and Assigned Readings

Focus Areas Assigned Readings

Yadav, A. (2008). Microprocessor 8085,
8086. New Delhi, India: University
Science Press/Laxmi Publications.

9.1 PIN Description Chapter 3, Section 3.1.

9.2 Functional Description Chapter 3, Section 3.2.
9.3 Basic System Timing Chapter 3, Section 3.3.
9.4 Instruction Format Chapter 3, Section 3.4.
9.5 Addressing Modes Chapter 3, Section 3.5.
9.6 Stack of 8085 Chapter 3, Section 3.6.
9.7 Interrupt of 8085 Chapter 3, Section 3.7.
9.8 Memory Interfacing Chapter 3, Section 3.8.

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Content Summary

9.1 The Intel 8085AH is a complete 8-bit parallel Central Processing Unit
(CPU).

9.2 It is designed with an N-channel, depletion load, silicon gate

technology (HMOS) and requires a single +5V supply.

9.3 Its basic clock speed is 3MHz (8085AH), 5HZ (8085AH-2) or 6MHz
(8085-AH-1).

9.4 It is also designed to fit into a minimum system of three integrated

circuits (IC), which are:

 The CPU (8085AH);

 A RAM/IO (8156H); and

 An EPROM/IO chip (8755A).

9.5 The 8085AH has 12 addressable 8-bit registers. Four of them can
function only as two 16-bit register pairs. Six others can be used
interchangeably as 8-bit registers or as 16-bit register pairs.

9.6 The 8085AH uses a multiplexed data bus. The address is split
between the higher 8-bit address bus and the lower 8-bit address or
data bus.

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9.7 Figure 9.1 illustrates the PIN configuration for 8085AH.

Figure 9.1: 8085AH PIN configuration

Source: Yadav (2008)

9.8 The description and function of each component in Figure 9.1 is

described further in Table 3.1 on page 38 in Yadav (2008).

9.9 Apart from the features of the 8085AH explained previously, the
8085AH has three maskable vector interrupt pins, one non-maskable
TRAP interrupt and a bus vectored interrupt, INTR.

9.10 The 8085AH has five interrupt inputs, which are:

 INTR;

 RST 5.5;

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 RST 6.5;

 RST 7.5; and

 TRAP.

9.11 The TRAP input is recognised just as any other interrupt but has the
highest priority, while INTR has the lowest priority.

9.12 The TRAP interrupt is useful for catastrophic events such as power
failure or bus error.

9.13 The TRAP is not affected by any flag or mask.

9.14 The Arithmetic and Logic Unit (ALU) performs all arithmetic and
logical operation, including accumulators and fine flags with the
temporary register.

9.15 Flags are used sometimes to perform certain conditional operation on

the basis of conditions that are caused due to operations done by an
execution of instruction.

9.16 The 8085 has 8-bit flag register with five active flags. The
explanations of flags are given in Table 9.1.

Table 9.1: Five Active Flags

Type of Flags Description

1. S-Sign flag Sign bit is used to show the status of a
number; If it is set “1” this means the number
is negative; if it is set “0” this means the
number is positive.
2. Z-Zero flag If the result of an arithmetic operation is
“zero”, then it is set “1”.
3. AC-Auxiliary carry flag If in an arithmetic operation, a carry is
generated at the fourth bit and passed to the
fifth bit, then it is set. This is generally used
for Binary-Coded Decimal (BCD) operations.
4. P-Parity flag If after the execution of an arithmetic
operation, the result has even number of one
(called even party) the flag is set; it is
otherwise for odd number of ones (called odd
parity).
5. CY-Carry flag If an arithmetic operation generates a carry,
then it is set.

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9.17 Other features are considered as part of a general purpose register,

which has eight general purpose registers and a program counter
that contains the address of the next instruction to be executed.

9.18 The timing for microprocessors is based on a clock timing for a

machine cycle. A machine cycle is the time required to complete an
operation of accessing memory, I/O or acknowledging external
request.

9.19 The 8085AH machine cycle consists of Opcode, Fetch, Memory

Read, Memory Write, I/O Read, I/O Write, Acknowledge, INTR and
Bus Idle.

9.20 ALE is an output status signal. It indicates that data and address
are present on the multiplexed address/data lines when ALE = 1 it
means address is present), when ALE = 0 (it means data is
present on multiplexed lines).

9.21 An instruction is a command to the microprocessor to perform a given

task on specified data.

9.22 Each instruction has two parts, which are:

 The task to be performed called opcode; and

 The data to be operated on called operand.

9.23 The data can be specified in various ways, called addressing mode.
This can be the data itself or the address of that particular data.

9.24 Addressing mode is defined as various ways for a multiprocessor to

access data.

9.25 The types of addressing modes are divided into four, which are:

 Immediate addressing mode;

 Register addressing mode;

 Direct addressing mode; and

 Indirect addressing mode.

9.26 In 8085, the stack is defined as a set of memory locations in the R/W
memory, specified by the programmer in the main memory.

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9.27 Meanwhile, interrupt of 8085 is a process by which an external device

can inform the processor that the device needs the service of the
processor.

9.28 8085 has a total of “5” interrupt, as shown in Figure 9.2.

Figure 9.2: Interrupt classification of 8085

Source: Yadav (2008)

9.29 Memory is an integrated part of a microcomputer system. The

interfacing circuit enables the microprocessor to access the memory
to read instruction codes and data stored in the memory.

9.30 The interfacing process involves designing a circuit that will match
the memory requirements with microprocessor signals.

Study Questions

1. Draw the PIN diagram and describe its functional description.

2. Explain the functions of interrupt, ALU, register and program counter.

3. List the machine cycles in a microprocessor.

4. Explain the function of ALE.

5. Explain the instructions opcode and operand.

6. What are the various addressing modes of 8085?

7. What is the function of stack in microprocessor?

8. Classify the interrupts of 8085.

9. Explain the function of memory interfacing.

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Appendices
Appendix A: Learning Support

Tutorials

There are eight hours of face-to-face facilitation, in the form of FOUR

tutorials of two hours each. You will be notified of the date, time and location
of these tutorials, together with the name and e-mail address of your
facilitator, as soon as you are allocated a group.

Discussion and Participation

Besides the face-to-face tutorials, you have the support of online

discussions in myINSPIRE with your facilitator and coursemates. Your
contributions to online discussions will greatly enhance your understanding
of the course content, and help you do the assignment(s) and prepare for
the examination.
Feedback and Input from Facilitator

As you work on the activities and the assigned text(s), your facilitator will
provide assistance to you throughout the duration of the course. Should you
need assistance at any time, do not hesitate to contact your facilitator and
discuss your problems with him/her.

Bear in mind that communication is important for you to be able to get the
most out of this course. Therefore, you should, at all times, be in touch with
your facilitator, e-facilitator and coursemates, and be aware of all the
requirements for successful completion of the course.

Tan Sri Dr Abdullah Sanusi (TSDAS) Digital Library

The TSDAS Digital Library has a wide range of print and online resources for
the use of its learners. This comprehensive digital library, which is accessible
through the OUM portal, provides access to more than 30 online databases
comprising e-journals, e-theses, e-books and more. Examples of databases
available are EBSCOhost, ProQuest, SpringerLink, Books247, InfoSci
Books, Emerald Management Plus and Ebrary Electronic Books. As an OUM
learner, you are encouraged to make full use of the resources available
through this library.

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Appendix B: Study Tips

Time Commitments for Study

You should plan to spend about eight hours of study time on each topic,
which includes doing all assigned readings and activities. You must also set
aside time to discuss work online. It is often more effective to distribute the
study hours over a number of days rather than spend a whole day studying
one topic.

Study Strategy

The following is a proposed strategy for working through the course. If you
have difficulty following this strategy, discuss your problems with your
facilitator either through the online forum or during the tutorials.

(i) The most important step is to read the contents of this Study Guide
thoroughly.

(ii) Organise a study schedule (as recommended in Table 2). Take note of
the amount of time you spend on each topic as well as the dates for
submission of assignment(s), tutorials and examination.

(iii) Once you have created a study schedule, make every effort to stick to
it. One reason learners are unable to cope with postgraduate courses
is that they procrastinate and delay completing their coursework.

(iv) You are encouraged to do the following:

 Read the Study Guide carefully and look through the list of topics
covered. Try to examine each topic in relation to other topics.

 Complete all assigned readings and go through as many

supplementary texts as possible to get a broader understanding of
the course content.

 Go through all the activities and study questions to better

understand the various concepts and facts presented in a topic.

 Draw ideas from a large number of readings as you work on the

assignments. Work regularly on the assignments as the semester
progresses so that you are able to systematically produce a
commendable paper.

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(v) When you have completed a topic, review the Learning Outcomes for
the topic to confirm that you have achieved them and are able to do
what is required.

(vi) After completing all topics, review the Learning Outcomes of the course
to see if you have achieved them.

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