PIC18(L)F2X/4XK22

25.0 INSTRUCTION SET SUMMARY The literal instructions may use some of the following
operands:
PIC18(L)F2X/4XK22 devices incorporate the standard
set of 75 PIC18 core instructions, as well as an extended
set of eight new instructions, for the optimization of code
that is recursive or that utilizes a software stack. The
extended set is discussed later in this section.

25.1 Standard Instruction Set

The control instructions may use some of the following
The standard PIC18 instruction set adds many
operands:
enhancements to the previous PIC® MCU instruction
sets, while maintaining an easy migration from these
PIC® MCU instruction sets. Most instructions are a CALL or RETURN instructions
single program memory word (16 bits), but there are
four instructions that require two program memory
locations.
Each single-word instruction is a 16-bit word divided
into an opcode, which specifies the instruction type and
one or more operands, which further specify the All instructions are a single word, except for four
operation of the instruction. double-word instructions. These instructions were
The instruction set is highly orthogonal and is grouped made double-word to contain the required information
into four basic categories: 1
Byte-oriented operations this second word is executed as an instruction (by
itself), it will execute as a NOP.
Bit-oriented operations
Literal operations All single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Control operations
program counter is changed as a result of the instruc
The PIC18 instruction set summary in Table 25-2 lists tion. In these cases, the execution takes two instruction
byte-oriented, bit-oriented, literal and control cycles, with the additional instruction cycle(s) executed
operations. Table 25-1 shows the opcode field as a NOP.
descriptions.
The double-word instructions execute in two instruction
Most byte-oriented instructions have three operands: cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
register is to be used by the instruction. The destination Two-word branch instructions (if true) would take 3 s.
Figure 25-1 shows the general formats that the
instructions can have. All examples use the convention
the file register specified in the instruction.
All bit-oriented instructions have three operands: The Instruction Set Summary, shown in Table 25-2,
lists the standard instructions recognized by the
Microchip Assembler (MPASMTM).
provides
a description of each instruction.

affected by the operation, while the file register

the bit is located.

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 PIC18(L)F2X/4XK22
TABLE 25-1: OPCODE FIELD DESCRIPTIONS
Field Description
a RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register
bbb Bit address within an 8-bit file register (0 to 7).
BSR Bank Select Register. Used to select the current RAM bank.
C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
d Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f
dest Destination: either the WREG register or the specified register file location.
f 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).
fs 12-bit Register file address (000h to FFFh). This is the source address.
fd 12-bit Register file address (000h to FFFh). This is the destination address.
GIE Global Interrupt Enable bit.
k Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).
label Label name.
mm The mode of the TBLPTR register for the table read and table write instructions.
Only used with table read and table write instructions:
* No change to register (such as TBLPTR with table reads and writes)
*+ Post-Increment register (such as TBLPTR with table reads and writes)
*- Post-Decrement register (such as TBLPTR with table reads and writes)
+* Pre-Increment register (such as TBLPTR with table reads and writes)
n tive branch instructions or the direct address for
CALL/BRANCH and RETURN instructions.
PC Program Counter.
PCL Program Counter Low Byte.
PCH Program Counter High Byte.
PCLATH Program Counter High Byte Latch.
PCLATU Program Counter Upper Byte Latch.
PD Power-down bit.
PRODH Product of Multiply High Byte.
PRODL Product of Multiply Low Byte.
s Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)
TBLPTR 21-bit Table Pointer (points to a Program Memory location).
TABLAT 8-bit Table Latch.
TO Time-out bit.
TOS Top-of-Stack.
u Unused or unchanged.
WDT Watchdog Timer.
WREG Working register (accumulator).
x 0 1 0. It is the recommended form of use for
compatibility with all Microchip software tools.
zs 7-bit offset value for indirect addressing of register files (source).
zd 7-bit offset value for indirect addressing of register files (destination).
{ } Optional argument.
[text] Indicates an indexed address.
(text) The contents of text.
[expr]<n> Specifies bit n of the register indicated by the pointer expr.
Assigned to.
< > Register bit field.
In the set of.
italics User defined term (font is Courier).

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PIC18(L)F2X/4XK22
FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS

Byte-oriented file register operations Example Instruction

15 10 9 8 7 0
OPCODE d a f (FILE #) ADDWF MYREG, W, B
d = 0 for result destination to be WREG register
d = 1 for result destination to be file register (f)
a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address

Byte to Byte move operations (2-word)

15 12 11 0
OPCODE f (Source FILE #) MOVFF MYREG1, MYREG2
15 12 11 0
1111 f (Destination FILE #)

f = 12-bit file register address

Bit-oriented file register operations

15 12 11 9 8 7 0
OPCODE b (BIT #) a f (FILE #) BSF MYREG, bit, B

b = 3-bit position of bit in file register (f)

a = 0 to force Access Bank
a = 1 for BSR to select bank
f = 8-bit file register address

Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh

k = 8-bit immediate value

Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)

n = 20-bit immediate value

15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC

15 12 11 0
1111 n<19:8> (literal)
S = Fast bit

15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC

15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC

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 PIC18(L)F2X/4XK22

TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET

Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
borrow
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For 1
0
2: If this instruction is executed on the TM 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem
ory locations have a valid instruction.

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PIC18(L)F2X/4XK22
TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET (CONTINUED)
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL k, s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO k Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP No Operation 1 0000 0000 0000 0000 None
NOP No Operation 1 1111 xxxx xxxx xxxx None 4
POP Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For 1
0
2: If this instruction is executed on the TM 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem
ory locations have a valid instruction.

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 PIC18(L)F2X/4XK22
TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET (CONTINUED)
Mnemonic, 16-Bit Instruction Word Status
Description Cycles Notes
Operands MSb LSb Affected

LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For 1
0
2: If this instruction is executed on the TM 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem
ory locations have a valid instruction.

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PIC18(L)F2X/4XK22
25.1.1 STANDARD INSTRUCTION SET

ADDLW ADD literal to W ADDWF ADD W to f

Syntax: ADDLW k Syntax: ADDWF f {,d {,a}}
Operands: 0 k 255 Operands: 0 f 255
d [0,1]
Operation: (W) + k W
a [0,1]
Status Affected: N, OV, C, DC, Z
Operation: (W) + (f) dest
Encoding: 0000 1111 kkkk kkkk
Status Affected: N, OV, C, DC, Z
Description: The contents of W are added to the
Encoding: 0010 01da ffff ffff
W. 0
1
Words: 1
Cycles: 1 (default).
Q Cycle Activity: 0
1
Q1 Q2 Q3 Q4
GPR bank.
Decode Read Process Write to W 0
Data set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Example: ADDLW 15h
Before Instruction Bit-Oriented Instructions in Indexed
W = 10h for details.
After Instruction Words: 1
W = 25h Cycles: 1

Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
Data destination

Example: ADDWF REG, 0, 0

Before Instruction
W = 17h
REG = 0C2h
After Instruction
W = 0D9h
REG = 0C2h

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).

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 PIC18(L)F2X/4XK22

ADDWFC ADD W and CARRY bit to f ANDLW AND literal with W

Syntax: ADDWFC f {,d {,a}} Syntax: ANDLW k
Operands: 0 f 255 Operands: 0 k 255
d [0,1]
Operation: (W) .AND. k W
a [0,1]
Status Affected: N, Z
Operation: (W) + (f) + (C) dest
Encoding: 0000 1011 kkkk kkkk
Status Affected: N,OV, C, DC, Z
Encoding: 0010 00da ffff ffff
Description: Add W, the CARRY flag and data mem
Words: 1
0
1 Cycles: 1
Q Cycle Activity:
0
Q1 Q2 Q3 Q4
1
GPR bank. Decode Read literal Process Write to W
0 Data
set is enabled, this instruction operates
in Indexed Literal Offset Addressing Example: ANDLW 05Fh
mode whenever f 95 (5Fh). See
Before Instruction
Bit-Oriented Instructions in Indexed W = A3h
for details. After Instruction
Words: 1 W = 03h
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
Data destination

Example: ADDWFC REG, 0, 1

Before Instruction
CARRY bit = 1
REG = 02h
W = 4Dh
After Instruction
CARRY bit = 0
REG = 02h
W = 50h

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PIC18(L)F2X/4XK22

ANDWF AND W with f BC Branch if Carry

Syntax: ANDWF f {,d {,a}} Syntax: BC n
Operands: 0 f 255 Operands: -128 n 127
d [0,1]
1
a [0,1]
(PC) + 2 + 2n PC
Operation: (W) .AND. (f) dest
Status Affected: None
Status Affected: N, Z
Encoding: 1110 0010 nnnn nnnn
Encoding: 0001 01da ffff ffff
1
will branch.
0
1 added to the PC. Since the PC will have
incremented to fetch the next
0 instruction, the new address will be
1 PC + 2 + 2n. This instruction is then a
GPR bank. 2-cycle instruction.
0
Words: 1
set is enabled, this instruction operates
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f 95 (5Fh). See Q Cycle Activity:
If Jump:
Bit-Oriented Instructions in Indexed
Q1 Q2 Q3 Q4
for details.
Decode Read literal Process Write to PC
Words: 1 Data
Cycles: 1 No No No No
operation operation operation operation
Q Cycle Activity:
If No Jump:
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Decode Read Process Write to
Decode Read literal Process No
Data destination
Data operation

Example: ANDWF REG, 0, 0

Example: HERE BC 5
Before Instruction
Before Instruction
W = 17h PC = address (HERE)
REG = C2h
After Instruction
After Instruction
If CARRY = 1;
W = 02h PC = address (HERE + 12)
REG = C2h If CARRY = 0;
PC = address (HERE + 2)

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 PIC18(L)F2X/4XK22

BCF Bit Clear f BN Branch if Negative

Syntax: BCF f, b {,a} Syntax: BN n
Operands: 0 f 255 Operands: -128 n 127
0 b 7
1
a [0,1]
(PC) + 2 + 2n PC
Operation: 0 f<b>
Status Affected: None
Status Affected: None
Encoding: 1110 0110 nnnn nnnn
Encoding: 1001 bbba ffff ffff
1
program will branch.
0
1 added to the PC. Since the PC will have
GPR bank. incremented to fetch the next
0 instruction, the new address will be
set is enabled, this instruction operates PC + 2 + 2n. This instruction is then a
in Indexed Literal Offset Addressing 2-cycle instruction.
mode whenever f 95 (5Fh). See
Words: 1

Bit-Oriented Instructions in Indexed Cycles: 1(2)

for details. Q Cycle Activity:
Words: 1 If Jump:
Q1 Q2 Q3 Q4
Cycles: 1
Decode Read literal Process Write to PC
Q Cycle Activity:
Data
Q1 Q2 Q3 Q4 No No No No
Decode Read Process Write operation operation operation operation
Data If No Jump:
Q1 Q2 Q3 Q4
Example: BCF FLAG_REG, 7, 0 Decode Read literal Process No
Before Instruction Data operation
FLAG_REG = C7h
After Instruction Example: HERE BN Jump
FLAG_REG = 47h
Before Instruction
PC = address (HERE)
After Instruction
If NEGATIVE = 1;
PC = address (Jump)
If NEGATIVE = 0;
PC = address (HERE + 2)

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PIC18(L)F2X/4XK22

BNC Branch if Not Carry BNN Branch if Not Negative

Syntax: BNC n Syntax: BNN n
Operands: -128 n 127 Operands: -128 n 127
0 0
(PC) + 2 + 2n PC (PC) + 2 + 2n PC
Status Affected: None Status Affected: None
Encoding: 1110 0011 nnnn nnnn Encoding: 1110 0111 nnnn nnnn
0 0
will branch. program will branch.

added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
2-cycle instruction. 2-cycle instruction.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Q Cycle Activity: Q Cycle Activity:
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Decode Read literal Process Write to PC
Data Data
No No No No No No No No
operation operation operation operation operation operation operation operation
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
Data operation Data operation

Example: HERE BNC Jump Example: HERE BNN Jump

Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
After Instruction After Instruction
If CARRY = 0; If NEGATIVE = 0;
PC = address (Jump) PC = address (Jump)
If CARRY = 1; If NEGATIVE = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

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 PIC18(L)F2X/4XK22

BNOV Branch if Not Overflow BNZ Branch if Not Zero

Syntax: BNOV n Syntax: BNZ n
Operands: -128 n 127 Operands: -128 n 127
0 0
(PC) + 2 + 2n PC (PC) + 2 + 2n PC
Status Affected: None Status Affected: None
Encoding: 1110 0101 nnnn nnnn Encoding: 1110 0001 nnnn nnnn
0 0
program will branch. will branch.

added to the PC. Since the PC will have added to the PC. Since the PC will have
incremented to fetch the next incremented to fetch the next
instruction, the new address will be instruction, the new address will be
PC + 2 + 2n. This instruction is then a PC + 2 + 2n. This instruction is then a
2-cycle instruction. 2-cycle instruction.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Q Cycle Activity: Q Cycle Activity:
If Jump: If Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Decode Read literal Process Write to PC
Data Data
No No No No No No No No
operation operation operation operation operation operation operation operation
If No Jump: If No Jump:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read literal Process No Decode Read literal Process No
Data operation Data operation

Example: HERE BNOV Jump Example: HERE BNZ Jump

Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
After Instruction After Instruction
If OVERFLOW = 0; If ZERO = 0;
PC = address (Jump) PC = address (Jump)
If OVERFLOW = 1; If ZERO = 1;
PC = address (HERE + 2) PC = address (HERE + 2)

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PIC18(L)F2X/4XK22

BRA Unconditional Branch BSF Bit Set f

Syntax: BRA n Syntax: BSF f, b {,a}
Operands: -1024 n 1023 Operands: 0 f 255
0 b 7
Operation: (PC) + 2 + 2n PC
a [0,1]
Status Affected: None
Operation: 1 f<b>
Encoding: 1101 0nnn nnnn nnnn
Status Affected: None
Encoding: 1000 bbba ffff ffff
the PC. Since the PC will have incre
mented to fetch the next instruction, the
new address will be PC + 2 + 2n. This 0
instruction is a 2-cycle instruction. 1
GPR bank.
Words: 1
0
Cycles: 2 set is enabled, this instruction operates
Q Cycle Activity: in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Q1 Q2 Q3 Q4
Decode Read literal Process Write to PC Bit-Oriented Instructions in Indexed
Data for details.
No No No No
Words: 1
operation operation operation operation
Cycles: 1
Q Cycle Activity:
Example: HERE BRA Jump
Q1 Q2 Q3 Q4
Before Instruction
Decode Read Process Write
PC = address (HERE)
Data
After Instruction
PC = address (Jump)
Example: BSF FLAG_REG, 7, 1
Before Instruction
FLAG_REG = 0Ah
After Instruction
FLAG_REG = 8Ah

DS40001412H-page 372 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a}
Operands: 0 f 255 Operands: 0 f 255
0 b 7 0 b<7
a [0,1] a [0,1]
Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
0 1
0 1
the next instruction fetched during the the next instruction fetched during the
current instruction execution is discarded current instruction execution is discarded
and a NOP is executed instead, making and a NOP is executed instead, making
this a 2-cycle instruction. this a 2-cycle instruction.
0 0
1 1
GPR bank. GPR bank.
0 0
set is enabled, this instruction operates in set is enabled, this instruction operates
Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). mode whenever f 95 (5Fh).
See See
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
for details. for details.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
Data operation Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation

Example: HERE BTFSC FLAG, 1, 0 Example: HERE BTFSS FLAG, 1, 0

FALSE : FALSE :
TRUE : TRUE :
Before Instruction Before Instruction
PC = address (HERE) PC = address (HERE)
After Instruction After Instruction
If FLAG<1> = 0; If FLAG<1> = 0;
PC = address (TRUE) PC = address (FALSE)
If FLAG<1> = 1; If FLAG<1> = 1;
PC = address (FALSE) PC = address (TRUE)

2010-2021 Microchip Technology Inc. DS40001412H-page 373

PIC18(L)F2X/4XK22

BTG Bit Toggle f BOV Branch if Overflow

Syntax: BTG f, b {,a} Syntax: BOV n
Operands: 0 f 255 Operands: -128 n 127
0 b<7
1
a [0,1]
(PC) + 2 + 2n PC
Operation: (f<b>) f<b>
Status Affected: None
Status Affected: None
Encoding: 1110 0100 nnnn nnnn
Encoding: 0111 bbba ffff ffff
1
program will branch.
inverted.
0 added to the PC. Since the PC will have
1 incremented to fetch the next
GPR bank. instruction, the new address will be
0 PC + 2 + 2n. This instruction is then a
set is enabled, this instruction operates 2-cycle instruction.
in Indexed Literal Offset Addressing
Words: 1
mode whenever f 95 (5Fh). See
Cycles: 1(2)
Bit-Oriented Instructions in Indexed Q Cycle Activity:
for details. If Jump:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1 Decode Read literal Process Write to PC
Data
Q Cycle Activity:
No No No No
Q1 Q2 Q3 Q4 operation operation operation operation
Decode Read Process Write If No Jump:
Data
Q1 Q2 Q3 Q4
Decode Read literal Process No
Example: BTG PORTC, 4, 0 Data operation
Before Instruction:
PORTC = 0111 0101 [75h]
Example: HERE BOV Jump
After Instruction:
PORTC = 0110 0101 [65h] Before Instruction
PC = address (HERE)
After Instruction
If OVERFLOW = 1;
PC = address (Jump)
If OVERFLOW = 0;
PC = address (HERE + 2)

DS40001412H-page 374 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

BZ Branch if Zero CALL Subroutine Call

Syntax: BZ n Syntax: CALL k {,s}
Operands: -128 n 127 Operands: 0 k 1048575
s [0,1]
1
(PC) + 2 + 2n PC Operation: (PC) + 4 TOS,
k PC<20:1>,
Status Affected: None
if s = 1
Encoding: 1110 0000 nnnn nnnn (W) WS,
1 (Status) STATUSS,
will branch. (BSR) BSRS
Status Affected: None
added to the PC. Since the PC will
Encoding:
have incremented to fetch the next
1st word (k<7:0>) 1110 110s k7kkk kkkk0
instruction, the new address will be
2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8
PC + 2 + 2n. This instruction is then a
2-cycle instruction. Description: Subroutine call of entire 2-Mbyte
memory range. First, return address
Words: 1
(PC + 4) is pushed onto the return
Cycles: 1(2) 1, the W, STATUS and
Q Cycle Activity: BSR registers are also pushed into their
If Jump: respective shadow registers, WS,
0, no
Q1 Q2 Q3 Q4
update occurs (default). Then, the
Decode Read literal Process Write to PC
Data
CALL is a 2-cycle instruction.
No No No No
Words: 2
operation operation operation operation
If No Jump: Cycles: 2
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read literal Process No Q1 Q2 Q3 Q4
Data operation Decode Read literal PUSH PC to Read literal
stack
Example: HERE BZ Jump Write to PC
No No No No
Before Instruction
operation operation operation operation
PC = address (HERE)
After Instruction
If ZERO = 1; Example: HERE CALL THERE, 1
PC = address (Jump)
If ZERO = 0; Before Instruction
PC = address (HERE + 2) PC = address (HERE)
After Instruction
PC = address (THERE)
TOS = address (HERE + 4)
WS = W
BSRS = BSR
STATUSS = Status

2010-2021 Microchip Technology Inc. DS40001412H-page 375

PIC18(L)F2X/4XK22

CLRF Clear f CLRWDT Clear Watchdog Timer

Syntax: CLRF f {,a} Syntax: CLRWDT
Operands: 0 f 255 Operands: None
a [0,1]
Operation: 000h WDT,
Operation: 000h f 000h WDT postscaler,
1 Z 1 TO,
1 PD
Status Affected: Z
Status Affected: TO, PD
Encoding: 0110 101a ffff ffff
Encoding: 0000 0000 0000 0100
Description: Clears the contents of the specified
register. Description: CLRWDT instruction resets the
0 Watchdog Timer. It also resets the post
1 scaler of the WDT. Status bits, TO and
GPR bank. PD, are set.
0
Words: 1
set is enabled, this instruction operates
in Indexed Literal Offset Addressing Cycles: 1
mode whenever f 95 (5Fh). See Q Cycle Activity:
Q1 Q2 Q3 Q4
Bit-Oriented Instructions in Indexed
for details. Decode No Process No
operation Data operation
Words: 1
Cycles: 1
Example: CLRWDT
Q Cycle Activity:
Before Instruction
Q1 Q2 Q3 Q4 WDT Counter = ?
Decode Read Process Write After Instruction
Data WDT Counter = 00h
WDT Postscaler = 0
TO = 1
Example: CLRF FLAG_REG, 1 PD = 1
Before Instruction
FLAG_REG = 5Ah
After Instruction
FLAG_REG = 00h

DS40001412H-page 376 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

COMF Complement f CPFSEQ Compare f with W, skip if f = W

Syntax: COMF f {,d {,a}} Syntax: CPFSEQ f {,a}

Operands: 0 f 255 Operands: 0 f 255

d [0,1] a [0,1]
a [0,1]
skip if (f) = (W)
Operation: (f) dest
(unsigned comparison)
Status Affected: N, Z
Status Affected: None
Encoding: 0001 11da ffff ffff
Encoding: 0110 001a ffff ffff
Description: Compares the contents of data memory
0
1 performing an unsigned subtraction.

0 discarded and a NOP is executed

1 instead, making this a 2-cycle
GPR bank. instruction.
0 0
set is enabled, this instruction operates 1
in Indexed Literal Offset Addressing GPR bank.
mode whenever f 95 (5Fh). See 0
set is enabled, this instruction operates
Bit-Oriented Instructions in Indexed in Indexed Literal Offset Addressing
for details. mode whenever f 95 (5Fh). See
Words: 1
Bit-Oriented Instructions in Indexed
Cycles: 1
for details.
Q Cycle Activity:
Words: 1
Q1 Q2 Q3 Q4
Cycles: 1(2)
Decode Read Process Write to Note: 3 cycles if skip and followed
Data destination by a 2-word instruction.
Q Cycle Activity:
Example: COMF REG, 0, 0 Q1 Q2 Q3 Q4
Before Instruction Decode Read Process No
REG = 13h Data operation
After Instruction If skip:
REG = 13h Q1 Q2 Q3 Q4
W = ECh No No No No
operation operation operation operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
No No No No
operation operation operation operation

Example: HERE CPFSEQ REG, 0

NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
W = ?
REG = ?
After Instruction
If REG = W;
PC = Address (EQUAL)
If REG W;
PC = Address (NEQUAL)

2010-2021 Microchip Technology Inc. DS40001412H-page 377

PIC18(L)F2X/4XK22

CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
Operands: 0 f 255 Operands: 0 f 255
a [0,1] a [0,1]
W), W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None
Status Affected: None
Encoding: 0110 010a ffff ffff
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
Description: Compares the contents of data memory
performing an unsigned subtraction.
performing an unsigned subtraction.
contents of WREG, then the fetched
contents of W, then the fetched
instruction is discarded and a NOP is
instruction is discarded and a NOP is
executed instead, making this a
executed instead, making this a
2-cycle instruction.
2-cycle instruction.
0
0
1
1
GPR bank.
GPR bank.
0
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing
Cycles: 1(2)
mode whenever f 95 (5Fh). See
Note: 3 cycles if skip and followed
by a 2-word instruction.
Bit-Oriented Instructions in Indexed
for details. Q Cycle Activity:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1(2) Decode Read Process No
Note: 3 cycles if skip and followed Data operation
by a 2-word instruction. If skip:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
Decode Read Process No operation operation operation operation
Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No
Example: HERE CPFSLT REG, 1
operation operation operation operation
NLESS :
No No No No LESS :
operation operation operation operation
Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER :
If REG < W;
Before Instruction PC = Address (LESS)
PC = Address (HERE) If REG W;
W = ? PC = Address (NLESS)
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)

DS40001412H-page 378 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

DAW Decimal Adjust W Register DECF Decrement f

Syntax: DAW Syntax: DECF f {,d {,a}}
Operands: None Operands: 0 f 255
d [0,1]
Operation: If [W<3:0> > 9] or [DC = 1] then
a [0,1]
(W<3:0>) + 6 W<3:0>;
else dest
(W<3:0>) W<3:0>; Status Affected: C, DC, N, OV, Z

If [W<7:4> + DC > 9] or [C = 1] then Encoding: 0000 01da ffff ffff

(W<7:4>) + 6 + DC W<7:4> ; 0
else 1
(W<7:4>) + DC W<7:4>
Status Affected: C (default).
0
Encoding: 0000 0000 0000 0111
1
Description: DAW adjusts the 8-bit value in W, result GPR bank.
ing from the earlier addition of two vari 0
ables (each in packed BCD format) and set is enabled, this instruction operates
produces a correct packed BCD result. in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Words: 1
Cycles: 1 Bit-Oriented Instructions in Indexed
Q Cycle Activity: for details.
Q1 Q2 Q3 Q4 Words: 1
Decode Read Process Write Cycles: 1
register W Data W
Q Cycle Activity:
Example1:
Q1 Q2 Q3 Q4
DAW
Decode Read Process Write to
Before Instruction Data destination
W = A5h
C = 0
DC = 0 Example: DECF CNT, 1, 0
After Instruction Before Instruction
W = 05h CNT = 01h
C = 1 Z = 0
DC = 0 After Instruction
Example 2: CNT = 00h
Before Instruction Z = 1
W = CEh
C = 0
DC = 0
After Instruction
W = 34h
C = 1
DC = 0

2010-2021 Microchip Technology Inc. DS40001412H-page 379

PIC18(L)F2X/4XK22

DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0

Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ f {,d {,a}}
Operands: 0 f 255 Operands: 0 f 255
d [0,1] d [0,1]
a [0,1] a [0,1]
dest, dest,
skip if result = 0 skip if result 0
Status Affected: None Status Affected: None
Encoding: 0010 11da ffff ffff Encoding: 0100 11da ffff ffff

0 0
1 1

0 0
which is already fetched, is discarded instruction, which is already fetched, is
and a NOP is executed instead, making discarded and a NOP is executed
it a 2-cycle instruction. instead, making it a 2-cycle
0 instruction.
1 0
GPR bank. 1
0 GPR bank.
set is enabled, this instruction operates 0
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Bit-Oriented Instructions in Indexed
for details. Bit-Oriented Instructions in Indexed
for details.
Words: 1
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed Cycles: 1(2)
by a 2-word instruction. Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
Data destination Decode Read Process Write to
If skip: Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT - 1 After Instruction
If CNT = 0;
PC = Address (CONTINUE) If TEMP = 0;
If CNT 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP 0;
PC = Address (NZERO)

DS40001412H-page 380 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

GOTO Unconditional Branch INCF Increment f

Syntax: GOTO k Syntax: INCF f {,d {,a}}
Operands: 0 k 1048575 Operands: 0 f 255
d [0,1]
Operation: k PC<20:1>
a [0,1]
Status Affected: None
Operation: (f) + 1 dest
Encoding:
Status Affected: C, DC, N, OV, Z
1st word (k<7:0>) 1110 1111 k7kkk kkkk0
2nd word(k<19:8>) 1111 k19kkk kkkk kkkk8 Encoding: 0010 10da ffff ffff
Description: GOTO allows an unconditional branch
anywhere within entire 0
2-Mbyte memory range. The 20-bit 1

GOTO is always a 2-cycle 0

instruction. 1
GPR bank.
Words: 2
0
Cycles: 2 set is enabled, this instruction operates
Q Cycle Activity: in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Q1 Q2 Q3 Q4
Decode Read literal No Read literal Bit-Oriented Instructions in Indexed
operation for details.
Write to PC
Words: 1
No No No No
operation operation operation operation Cycles: 1
Q Cycle Activity:
Example: GOTO THERE Q1 Q2 Q3 Q4
After Instruction Decode Read Process Write to
PC = Address (THERE) Data destination

Example: INCF CNT, 1, 0

Before Instruction
CNT = FFh
Z = 0
C = ?
DC = ?
After Instruction
CNT = 00h
Z = 1
C = 1
DC = 1

2010-2021 Microchip Technology Inc. DS40001412H-page 381

PIC18(L)F2X/4XK22

INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0

Syntax: INCFSZ f {,d {,a}} Syntax: INFSNZ f {,d {,a}}

Operands: 0 f 255 Operands: 0 f 255

d [0,1] d [0,1]
a [0,1] a [0,1]
Operation: (f) + 1 dest,
Operation: (f) + 1 dest,
skip if result 0
skip if result = 0
Status Affected: None
Status Affected: None
Encoding: 0100 10da ffff ffff
Encoding: 0011 11da ffff ffff

0
0 1
1
0
0 instruction, which is already fetched, is
which is already fetched, is discarded discarded and a NOP is executed
and a NOP is executed instead, making instead, making it a 2-cycle
it a 2-cycle instruction. instruction.
0 0
1 1
GPR bank. GPR bank.
0 0
set is enabled, this instruction operates set is enabled, this instruction operates
in Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See mode whenever f 95 (5Fh). See

Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed

for details. for details.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process Write to Decode Read Process Write to
Data destination Data destination
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation

Example: HERE INCFSZ CNT, 1, 0 Example: HERE INFSNZ REG, 1, 0

NZERO : ZERO
ZERO : NZERO
Before Instruction Before Instruction
PC = Address (HERE) PC = Address (HERE)
After Instruction After Instruction
CNT = CNT + 1 REG = REG + 1
If CNT = 0; If REG 0;
PC = Address (ZERO) PC = Address (NZERO)
If CNT 0; If REG = 0;
PC = Address (NZERO) PC = Address (ZERO)

DS40001412H-page 382 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

IORLW Inclusive OR literal with W IORWF Inclusive OR W with f

Syntax: IORLW k Syntax: IORWF f {,d {,a}}
Operands: 0 k 255 Operands: 0 f 255
d [0,1]
Operation: (W) .OR. k W
a [0,1]
Status Affected: N, Z
Operation: (W) .OR. (f) dest
Encoding: 0000 1001 kkkk kkkk
Status Affected: N, Z
Description: The contents of W are ORed with the
Encoding: 0001 00da ffff ffff

Words: 1
0 1
Cycles: 1
Q Cycle Activity: (default).
0
Q1 Q2 Q3 Q4
1
Decode Read Process Write to W GPR bank.
Data 0
set is enabled, this instruction operates
Example: IORLW 35h in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Before Instruction
W = 9Ah Bit-Oriented Instructions in Indexed
After Instruction for details.
W = BFh Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
Data destination

Example: IORWF RESULT, 0, 1

Before Instruction
RESULT = 13h
W = 91h
After Instruction
RESULT = 13h
W = 93h

2010-2021 Microchip Technology Inc. DS40001412H-page 383

PIC18(L)F2X/4XK22

LFSR Load FSR MOVF Move f

Syntax: LFSR f, k Syntax: MOVF f {,d {,a}}
Operands: 0 f 2 Operands: 0 f 255
0 k 4095 d [0,1]
a [0,1]
Operation: k FSRf
Operation: f dest
Status Affected: None
Status Affected: N, Z
Encoding: 1110 1110 00ff k11kkk
1111 0000 k7kkk kkkk Encoding: 0101 00da ffff ffff

a destination dependent upon the

0
Words: 2
1
Cycles: 2
Q Cycle Activity:
256-byte bank.
Q1 Q2 Q3 Q4
0
Decode Read literal Process Write 1
Data GPR bank.
MSB to 0
FSRfH set is enabled, this instruction operates
Decode Read literal Process Write literal in Indexed Literal Offset Addressing
Data mode whenever f 95 (5Fh). See

Bit-Oriented Instructions in Indexed

Example: LFSR 2, 3ABh
for details.
After Instruction
Words: 1
FSR2H = 03h
FSR2L = ABh Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write W
Data

Example: MOVF REG, 0, 0

Before Instruction
REG = 22h
W = FFh
After Instruction
REG = 22h
W = 22h

DS40001412H-page 384 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

MOVFF Move f to f MOVLB Move literal to low nibble in BSR

Syntax: MOVFF fs,fd Syntax: MOVLW k
Operands: 0 fs 4095 Operands: 0 k 255
0 fd 4095
Operation: k BSR
Operation: (fs) fd
Status Affected: None
Status Affected: None
Encoding: 0000 0001 kkkk kkkk
Encoding:
1st word (source) 1100 ffff ffff ffffs
Bank Select Register (BSR). The value
2nd word (destin.) 1111 ffff ffff ffffd
0
s regardless of the value of k7:k4.
d Words: 1
s
in the 4096-byte data space (000h to Cycles: 1
d Q Cycle Activity:
can also be anywhere from 000h to
Q1 Q2 Q3 Q4
FFFh.
Either source or destination can be W Decode Read Process Write literal
(a useful special situation). Data
MOVFF is particularly useful for
transferring a data memory location to a Example: MOVLB 5
peripheral register (such as the transmit
Before Instruction
buffer or an I/O port).
BSR Register = 02h
The MOVFF instruction cannot use the
After Instruction
PCL, TOSU, TOSH or TOSL as the
BSR Register = 05h
destination register.
Words: 2
Cycles: 2 (3)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
Data operation
(src)
Decode No No Write
operation operation
No dummy (dest)
read

Example: MOVFF REG1, REG2

Before Instruction
REG1 = 33h
REG2 = 11h
After Instruction
REG1 = 33h
REG2 = 33h

2010-2021 Microchip Technology Inc. DS40001412H-page 385

PIC18(L)F2X/4XK22

MOVLW Move literal to W MOVWF Move W to f

Syntax: MOVLW k Syntax: MOVWF f {,a}
Operands: 0 k 255 Operands: 0 f 255
a [0,1]
Operation: k W
Operation: (W) f
Status Affected: None
Status Affected: None
Encoding: 0000 1110 kkkk kkkk
Encoding: 0110 111a ffff ffff

Words: 1
Cycles: 1 256-byte bank.
Q Cycle Activity: 0
1
Q1 Q2 Q3 Q4
GPR bank.
Decode Read Process Write to W 0
Data set is enabled, this instruction operates
in Indexed Literal Offset Addressing
Example: MOVLW 5Ah mode whenever f 95 (5Fh). See

After Instruction
Bit-Oriented Instructions in Indexed
W = 5Ah for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write
Data

Example: MOVWF REG, 0

Before Instruction
W = 4Fh
REG = FFh
After Instruction
W = 4Fh
REG = 4Fh

DS40001412H-page 386 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

MULLW Multiply literal with W MULWF Multiply W with f

Syntax: MULLW k Syntax: MULWF f {,a}
Operands: 0 k 255 Operands: 0 f 255
a [0,1]
Operation: (W) x k PRODH:PRODL
Operation: (W) x (f) PRODH:PRODL
Status Affected: None
Status Affected: None
Encoding: 0000 1101 kkkk kkkk
Encoding: 0000 001a ffff ffff
Description: An unsigned multiplication is carried
out between the contents of W and the Description: An unsigned multiplication is carried
out between the contents of W and the
placed in the PRODH:PRODL register
pair. PRODH contains the high byte. result is stored in the PRODH:PRODL
W is unchanged. register pair. PRODH contains the
None of the Status flags are affected.
Note that neither overflow nor carry is unchanged.
possible in this operation. A zero result None of the Status flags are affected.
is possible but not detected. Note that neither overflow nor carry is
possible in this operation. A zero
Words: 1
result is possible but not detected.
Cycles: 1 0
Q Cycle Activity: 1
to select the GPR bank.
Q1 Q2 Q3 Q4
0
Decode Read Process Write set is enabled, this instruction
Data registers operates in Indexed Literal Offset
PRODH: Addressing mode whenever
PRODL f 95 (5Fh). See Section 25.2.3

Example: MULLW 0C4h Instructions in Indexed Literal Offset

for details.
Before Instruction
Words: 1
W = E2h
PRODH = ? Cycles: 1
PRODL = ?
Q Cycle Activity:
After Instruction
W = E2h Q1 Q2 Q3 Q4
PRODH = ADh Decode Read Process Write
PRODL = 08h Data registers
PRODH:
PRODL

Example: MULWF REG, 1

Before Instruction
W = C4h
REG = B5h
PRODH = ?
PRODL = ?
After Instruction
W = C4h
REG = B5h
PRODH = 8Ah
PRODL = 94h

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PIC18(L)F2X/4XK22

NEGF Negate f NOP No Operation

Syntax: NEGF f {,a} Syntax: NOP
Operands: 0 f 255 Operands: None
a [0,1]
Operation: No operation
Operation: (f)+1 f
Status Affected: None
Status Affected: N, OV, C, DC, Z
Encoding: 0000 0000 0000 0000
Encoding: 0110 110a ffff ffff 1111 xxxx xxxx xxxx
Description: No operation.
complement. The result is placed in the
Words: 1

0 Cycles: 1
1 Q Cycle Activity:
GPR bank.
Q1 Q2 Q3 Q4
0
set is enabled, this instruction operates Decode No No No
in Indexed Literal Offset Addressing operation operation operation
mode whenever f 95 (5Fh). See
Example:
Bit-Oriented Instructions in Indexed
None.
for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write
Data

Example: NEGF REG, 1

Before Instruction
REG = 0011 1010 [3Ah]
After Instruction
REG = 1100 0110 [C6h]

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 PIC18(L)F2X/4XK22

POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: POP Syntax: PUSH
Operands: None Operands: None
Operation: (TOS) bit bucket Operation: (PC + 2) TOS
Status Affected: None Status Affected: None
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of
stack and is discarded. The TOS value the return stack. The previous TOS
then becomes the previous value that value is pushed down on the stack.
was pushed onto the return stack. This instruction allows implementing a
This instruction is provided to enable software stack by modifying TOS and
the user to properly manage the return then pushing it onto the return stack.
stack to incorporate a software stack.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode PUSH No No
Decode No POP TOS No PC + 2 onto operation operation
operation value operation return stack

Example: POP Example: PUSH

GOTO NEW
Before Instruction
Before Instruction TOS = 345Ah
TOS = 0031A2h PC = 0124h
Stack (1 level down) = 014332h
After Instruction
After Instruction PC = 0126h
TOS = 014332h TOS = 0126h
PC = NEW Stack (1 level down) = 345Ah

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PIC18(L)F2X/4XK22

RCALL Relative Call RESET Reset

Syntax: RCALL n Syntax: RESET
Operands: -1024 n 1023 Operands: None
Operation: (PC) + 2 TOS, Operation: Reset all registers and flags that are
(PC) + 2 + 2n PC affected by a MCLR Reset.
Status Affected: None Status Affected: All
Encoding: 1101 1nnn nnnn nnnn Encoding: 0000 0000 1111 1111
Description: Subroutine call with a jump up to 1K Description: This instruction provides a way to
from the current location. First, return execute a MCLR Reset by software.
address (PC + 2) is pushed onto the
Words: 1
Cycles: 1
have incremented to fetch the next Q Cycle Activity:
instruction, the new address will be
Q1 Q2 Q3 Q4
PC + 2 + 2n. This instruction is a
2-cycle instruction. Decode Start No No
Reset operation operation
Words: 1
Cycles: 2
Example: RESET
Q Cycle Activity:
After Instruction
Q1 Q2 Q3 Q4 Registers = Reset Value
Decode Read literal Process Write to PC Flags* = Reset Value
Data
PUSH PC to
stack
No No No No
operation operation operation operation

Example: HERE RCALL Jump

Before Instruction
PC = Address (HERE)
After Instruction
PC = Address (Jump)
TOS = Address (HERE + 2)

DS40001412H-page 390 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

RETFIE Return from Interrupt RETLW Return literal to W

Syntax: RETFIE {s} Syntax: RETLW k
Operands: s [0,1] Operands: 0 k 255
Operation: (TOS) PC, Operation: k W,
1 GIE/GIEH or PEIE/GIEL, (TOS) PC,
if s = 1 PCLATU, PCLATH are unchanged
(WS) W,
Status Affected: None
(STATUSS) Status,
(BSRS) BSR, Encoding: 0000 1100 kkkk kkkk
PCLATU, PCLATH are unchanged.
Status Affected: GIE/GIEH, PEIE/GIEL. program counter is loaded from the top
of the stack (the return address). The
Encoding: 0000 0000 0001 000s
high address latch (PCLATH) remains
Description: Return from interrupt. Stack is popped unchanged.
and Top-of-Stack (TOS) is loaded into
Words: 1
the PC. Interrupts are enabled by
setting either the high or low priority Cycles: 2
1, the Q Cycle Activity:
contents of the shadow registers, WS,
Q1 Q2 Q3 Q4
STATUSS and BSRS, are loaded into
their corresponding registers, W, Decode Read Process POP PC
0, no update Data from stack,
of these registers occurs (default). Write to W
No No No No
Words: 1
operation operation operation operation
Cycles: 2
Q Cycle Activity: Example:
Q1 Q2 Q3 Q4
Decode No No POP PC CALL TABLE ; W contains table
operation operation from stack ; offset value
; W now has
Set GIEH or
; table value
GIEL
:
No No No No
TABLE
operation operation operation operation
ADDWF PCL ; W = offset
RETLW k0 ; Begin table
Example: RETFIE 1 RETLW k1 ;
:
After Interrupt
:
PC = TOS
W = WS RETLW kn ; End of table
BSR = BSRS
Status = STATUSS
GIE/GIEH, PEIE/GIEL = 1 Before Instruction
W = 07h
After Instruction
W = value of kn

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PIC18(L)F2X/4XK22

RETURN Return from Subroutine RLCF Rotate Left f through Carry

Syntax: RETURN {s} Syntax: RLCF f {,d {,a}}
Operands: s [0,1] Operands: 0 f 255
d [0,1]
Operation: (TOS) PC,
a [0,1]
if s = 1
(WS) W, Operation: (f<n>) dest<n + 1>,
(STATUSS) Status, (f<7>) C,
(BSRS) BSR, (C) dest<0>
PCLATU, PCLATH are unchanged
Status Affected: C, N, Z
Status Affected: None
Encoding: 0011 01da ffff ffff
Encoding: 0000 0000 0001 001s
Description: Return from subroutine. The stack is one bit to the left through the CARRY
popped and the top of the stack (TOS) 0
is loaded into the program counter. If 1
1, the contents of the shadow
registers, WS, STATUSS and BSRS, 0
are loaded into their corresponding 1
registers, W, STATUS and BSR. If select the GPR bank.
0, no update of these registers 0
occurs (default). set is enabled, this instruction
operates in Indexed Literal Offset
Words: 1
Addressing mode whenever
Cycles: 2 f 95 (5Fh). See Section 25.2.3
Q Cycle Activity:
Instructions in Indexed Literal Offset
Q1 Q2 Q3 Q4
for details.
Decode No Process POP PC
operation Data from stack C register f
No No No No
operation operation operation operation Words: 1
Cycles: 1
Q Cycle Activity:
Example: RETURN Q1 Q2 Q3 Q4
After Instruction: Decode Read Process Write to
PC = TOS Data destination

Example: RLCF REG, 0, 0

Before Instruction
REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1

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 PIC18(L)F2X/4XK22

RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}}
Operands: 0 f 255 Operands: 0 f 255
d [0,1] d [0,1]
a [0,1] a [0,1]
Operation: (f<n>) dest<n + 1>, Operation: (f<n>)
(f<7>) dest<0> (f<0>) C,
(C) dest<7>
Status Affected: N, Z
Status Affected: C, N, Z
Encoding: 0100 01da ffff ffff
Encoding: 0011 00da ffff ffff
0
1 one bit to the right through the CARRY
0
0 1
1
GPR bank. 0
0 1
set is enabled, this instruction operates GPR bank.
in Indexed Literal Offset Addressing 0
mode whenever f 95 (5Fh). See set is enabled, this instruction operates
in Indexed Literal Offset Addressing
Bit-Oriented Instructions in Indexed mode whenever f 95 (5Fh). See
for details.
Bit-Oriented Instructions in Indexed
register f
for details.

Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 Data destination

Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0

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PIC18(L)F2X/4XK22

RRNCF Rotate Right f (No Carry) SETF Set f

Syntax: RRNCF f {,d {,a}} Syntax: SETF f {,a}
Operands: 0 f 255 Operands: 0 f 255
d [0,1] a [0,1]
a [0,1]
Operation: FFh f
Operation: (f<n>)
Status Affected: None
(f<0>) dest<7>
Encoding: 0110 100a ffff ffff
Status Affected: N, Z
Description: The contents of the specified register
Encoding: 0100 00da ffff ffff
are set to FFh.
0
0 1
1 GPR bank.
0
0 set is enabled, this instruction operates
selected (default), overriding the BSR in Indexed Literal Offset Addressing
1 mode whenever f 95 (5Fh). See
selected as per the BSR value.
0 Bit-Oriented Instructions in Indexed
set is enabled, this instruction operates for details.
in Indexed Literal Offset Addressing
Words: 1
mode whenever f 95 (5Fh). See
Cycles: 1
Bit-Oriented Instructions in Indexed Q Cycle Activity:
for details.
Q1 Q2 Q3 Q4
register f Decode Read Process Write
Data
Words: 1
Cycles: 1 Example: SETF REG, 1
Q Cycle Activity: Before Instruction
Q1 Q2 Q3 Q4 REG = 5Ah
After Instruction
Decode Read Process Write to
REG = FFh
Data destination

Example 1: RRNCF REG, 1, 0

Before Instruction
REG = 1101 0111
After Instruction
REG = 1110 1011

Example 2: RRNCF REG, 0, 0

Before Instruction
W = ?
REG = 1101 0111
After Instruction
W = 1110 1011
REG = 1101 0111

DS40001412H-page 394 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

SLEEP Enter Sleep mode SUBFWB Subtract f from W with borrow

Syntax: SLEEP Syntax: SUBFWB f {,d {,a}}
Operands: None Operands: 0 f 255
d [0,1]
Operation: 00h WDT,
a [0,1]
0 WDT postscaler,
1 TO, ) dest
0 PD
Status Affected: N, OV, C, DC, Z
Status Affected: TO, PD
Encoding: 0101 01da ffff ffff
Encoding: 0000 0000 0000 0011
Description: The Power-down Status bit (PD) is
cleared. The Time-out Status bit (TO) 0
is set. Watchdog Timer and its posts 1
caler are cleared.
The processor is put into Sleep mode 0
with the oscillator stopped. 1
to select the GPR bank.
Words: 1
0
Cycles: 1 set is enabled, this instruction
Q Cycle Activity: operates in Indexed Literal Offset
Addressing mode whenever
Q1 Q2 Q3 Q4
f 95 (5Fh). See Section 25.2.3
Decode No Process Go to
operation Data Sleep Instructions in Indexed Literal Offset
for details.
Example: SLEEP Words: 1
Before Instruction Cycles: 1
TO = ?
Q Cycle Activity:
PD = ?
After Instruction Q1 Q2 Q3 Q4
TO Decode Read Process Write to
PD = 0 Data destination
Example 1: SUBFWB REG, 1, 0
Before Instruction
REG = 3
W = 2
C = 1
After Instruction
REG = FF
W = 2
C = 0
Z = 0
N = 1 ; result is negative
Example 2: SUBFWB REG, 0, 0
Before Instruction
REG = 2
W = 5
C = 1
After Instruction
REG = 2
W = 3
C = 1
Z = 0
N = 0 ; result is positive
Example 3: SUBFWB REG, 1, 0
Before Instruction
REG = 1
W = 2
C = 0
After Instruction
REG = 0
W = 2
C = 1
Z = 1 ; result is zero
N = 0

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PIC18(L)F2X/4XK22

SUBLW Subtract W from literal SUBWF Subtract W from f

Syntax: SUBLW k Syntax: SUBWF f {,d {,a}}
Operands: 0 k 255 Operands: 0 f 255
d [0,1]
W
a [0,1]
Status Affected: N, OV, C, DC, Z
dest
Encoding: 0000 1000 kkkk kkkk
Status Affected: N, OV, C, DC, Z
Description W is subtracted from the 8-bit
Encoding: 0101 11da ffff ffff

Words: 1
0
Cycles: 1 1
Q Cycle Activity:
(default).
Q1 Q2 Q3 Q4
0
Decode Read Process Write to W 1
Data to select the GPR bank.
0
Example 1: SUBLW 02h
set is enabled, this instruction
Before Instruction operates in Indexed Literal Offset
W = 01h Addressing mode whenever
C = ?
f 95 (5Fh). See Section 25.2.3
After Instruction
W = 01h
C = 1 ; result is positive Instructions in Indexed Literal Offset
Z = 0 for details.
N = 0
Words: 1
Example 2: SUBLW 02h
Cycles: 1
Before Instruction
W = 02h Q Cycle Activity:
C = ?
Q1 Q2 Q3 Q4
After Instruction
W = 00h Decode Read Process Write to
C = 1 ; result is zero Data destination
Z = 1
N = 0 Example 1: SUBWF REG, 1, 0
Example 3: SUBLW 02h Before Instruction
REG = 3
Before Instruction W = 2
W = 03h C = ?
C = ? After Instruction
After Instruction REG = 1
W = 2
C = 0 ; result is negative C = 1 ; result is positive
Z = 0 Z = 0
N = 1 N = 0
Example 2: SUBWF REG, 0, 0
Before Instruction
REG = 2
W = 2
C = ?
After Instruction
REG = 2
W = 0
C = 1 ; result is zero
Z = 1
N = 0
Example 3: SUBWF REG, 1, 0
Before Instruction
REG = 1
W = 2
C = ?
After Instruction

W = 2
C = 0 ; result is negative
Z = 0
N = 1

DS40001412H-page 396 2010-2021 Microchip Technology Inc.

 PIC18(L)F2X/4XK22

SUBWFB Subtract W from f with Borrow SWAPF Swap f

Syntax: SUBWFB f {,d {,a}} Syntax: SWAPF f {,d {,a}}
Operands: 0 f 255 Operands: 0 f 255
d [0,1] d [0,1]
a [0,1] a [0,1]
) dest Operation: (f<3:0>) dest<7:4>,
Status Affected: N, OV, C, DC, Z (f<7:4>) dest<3:0>
Encoding: 0101 10da ffff ffff Status Affected: None
Description: Subtract W and the CARRY flag Encoding: 0011 10da ffff ffff

0 Description: The upper and lower nibbles of register

1 0
1
0
1 0
GPR bank. 1
0 GPR bank.
set is enabled, this instruction operates 0
in Indexed Literal Offset Addressing set is enabled, this instruction operates
mode whenever f 95 (5Fh). See in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Bit-Oriented Instructions in Indexed
for details. Bit-Oriented Instructions in Indexed
for details.
Words: 1
Words: 1
Cycles: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
Data destination Decode Read Process Write to
Example 1: SUBWFB REG, 1, 0 Data destination
Before Instruction
REG = 19h (0001 1001) Example: SWAPF REG, 1, 0
W = 0Dh (0000 1101)
C = 1 Before Instruction
After Instruction REG = 53h
REG = 0Ch (0000 1100) After Instruction
W = 0Dh (0000 1101)
C = 1 REG = 35h
Z = 0
N = 0 ; result is positive
Example 2: SUBWFB REG, 0, 0
Before Instruction
REG = 1Bh (0001 1011)
W = 1Ah (0001 1010)
C = 0
After Instruction
REG = 1Bh (0001 1011)
W = 00h
C = 1
Z = 1 ; result is zero
N = 0
Example 3: SUBWFB REG, 1, 0
Before Instruction
REG = 03h (0000 0011)
W = 0Eh (0000 1110)
C = 1
After Instruction
REG = F5h (1111 0101)

W = 0Eh (0000 1110)

C = 0
Z = 0
N = 1 ; result is negative

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PIC18(L)F2X/4XK22

TBLRD Table Read TBLRD Table Read (Continued)

Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD *+ ;
Operands: None Before Instruction
TABLAT = 55h
Operation: if TBLRD *,
TBLPTR = 00A356h
(Prog Mem (TBLPTR)) TABLAT; MEMORY (00A356h) = 34h
After Instruction
if TBLRD *+, TABLAT = 34h
(Prog Mem (TBLPTR)) TABLAT; TBLPTR = 00A357h
(TBLPTR) + 1 TBLPTR;
Example2: TBLRD +* ;
if TBLRD *-,
(Prog Mem (TBLPTR)) TABLAT; Before Instruction
TBLPTR; TABLAT = AAh
TBLPTR = 01A357h
if TBLRD +*,
MEMORY (01A357h) = 12h
(TBLPTR) + 1 TBLPTR; MEMORY (01A358h) = 34h
(Prog Mem (TBLPTR)) TABLAT; After Instruction
Status Affected: None TABLAT = 34h
TBLPTR = 01A358h
Encoding: 0000 0000 0000 10nn
nn=0 *
=1 *+
=2 *-
=3 +*
Description: This instruction is used to read the contents
of Program Memory (P.M.). To address the
program memory, a pointer called Table
Pointer (TBLPTR) is used.
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory. TBLPTR
has a 2-Mbyte address range.
TBLPTR[0] = 0: Least Significant Byte
of Program Memory
Word
TBLPTR[0] = 1: Most Significant Byte
of Program Memory
Word
The TBLRD instruction can modify the value
of TBLPTR as follows:

Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No operation No No operation
operation (Read Program operation (Write TABLAT)
Memory)

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 PIC18(L)F2X/4XK22

TBLWT Table Write TBLWT Table Write (Continued)

Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+;
Operands: None
Before Instruction
Operation: if TBLWT*, TABLAT = 55h
(TABLAT) Holding Register; TBLPTR = 00A356h
HOLDING REGISTER
(00A356h) = FFh
if TBLWT*+,
After Instructions (table write completion)
(TABLAT) Holding Register;
TABLAT = 55h
(TBLPTR) + 1 TBLPTR; TBLPTR = 00A357h
if TBLWT*-, HOLDING REGISTER
(TABLAT) Holding Register; (00A356h) = 55h
TBLPTR; Example 2: TBLWT +*;
if TBLWT+*,
(TBLPTR) + 1 TBLPTR; Before Instruction
(TABLAT) Holding Register; TABLAT = 34h
TBLPTR = 01389Ah
Status Affected: None HOLDING REGISTER
(01389Ah) = FFh
Encoding: 0000 0000 0000 11nn
HOLDING REGISTER
nn=0 * (01389Bh) = FFh
=1 *+ After Instruction (table write completion)
=2 *- TABLAT = 34h
=3 +* TBLPTR = 01389Bh
HOLDING REGISTER
Description: This instruction uses the three LSBs of (01389Ah) = FFh
TBLPTR to determine which of the eight HOLDING REGISTER
holding registers the TABLAT is written to. (01389Bh) = 34h
The holding registers are used to program
the contents of Program Memory (P.M.).
(Refer to
for additional details on
programming Flash memory.)
The TBLPTR (a 21-bit pointer) points to
each byte in the program memory.
TBLPTR has a 2-MByte address range.
The LSb of the TBLPTR selects which
byte of the program memory location to
access.
TBLPTR[0] = 0: Least Significant
Byte of Program
Memory Word
TBLPTR[0] = 1: Most Significant
Byte of Program
Memory Word
The TBLWT instruction can modify the
value of TBLPTR as follows:

Words: 1
Cycles: 2
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode No No No
operation operation operation
No No No No
operation operation operation operation
(Read (Write to
TABLAT) Holding
Register )

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PIC18(L)F2X/4XK22

TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with W

Syntax: TSTFSZ f {,a} Syntax: XORLW k
Operands: 0 f 255 Operands: 0 k 255
a [0,1]
Operation: (W) .XOR. k W
Operation: skip if f = 0
Status Affected: N, Z
Status Affected: None
Encoding: 0000 1010 kkkk kkkk
Encoding: 0110 011a ffff ffff
Description: The contents of W are XORed with
0, the next instruction fetched
during the current instruction execution in W.
is discarded and a NOP is executed,
Words: 1
making this a 2-cycle instruction.
0 Cycles: 1
1 Q Cycle Activity:
GPR bank.
Q1 Q2 Q3 Q4
0
set is enabled, this instruction operates Decode Read Process Write to W
in Indexed Literal Offset Addressing Data
mode whenever f 95 (5Fh). See
Example: XORLW 0AFh
Bit-Oriented Instructions in Indexed
for details. Before Instruction
W = B5h
Words: 1
After Instruction
Cycles: 1(2)
W = 1Ah
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process No
Data operation
If skip:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No No No No
operation operation operation operation
No No No No
operation operation operation operation

Example: HERE TSTFSZ CNT, 1

NZERO :
ZERO :
Before Instruction
PC = Address (HERE)
After Instruction
If CNT = 00h,
PC = Address (ZERO)
If CNT 00h,
PC = Address (NZERO)

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 PIC18(L)F2X/4XK22

XORWF Exclusive OR W with f

Syntax: XORWF f {,d {,a}}
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: (W) .XOR. (f) dest
Status Affected: N, Z
Encoding: 0001 10da ffff ffff
Description: Exclusive OR the contents of W with
0
1

0
1
GPR bank.
0
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See

Bit-Oriented Instructions in Indexed

for details.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
Data destination

Example: XORWF REG, 1, 0

Before Instruction
REG = AFh
W = B5h
After Instruction
REG = 1Ah
W = B5h

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PIC18(L)F2X/4XK22
25.2 Extended Instruction Set A summary of the instructions in the extended
instruction set is provided in Table 25-3. Detailed
In addition to the standard 75 instructions of the PIC18 descriptions are provided in Section 25.2.2
instruction set, PIC18(L)F2X/4XK22 devices also . The opcode field
provide an optional extension to the core CPU descriptions in Table 25-1 apply to both the standard
functionality. The added features include eight and extended PIC18 instruction sets.
additional instructions that augment indirect and
indexed addressing operations and the implementation
of Indexed Literal Offset Addressing mode for many of Note: The instruction set extension and the
the standard PIC18 instructions. Indexed Literal Offset Addressing mode
The additional features of the extended instruction set were designed for optimizing applications
are disabled by default. To enable them, users must set written in C; the user may likely never use
the XINST Configuration bit. these instructions directly in assembler.
The syntax for these commands is pro
The instructions in the extended set can all be
vided as a reference for users who may be
classified as literal operations, which either manipulate
reviewing code that has been generated
the File Select Registers, or use them for indexed
by a compiler.
addressing. Two of the instructions, ADDFSR and
SUBFSR, each have an additional special instantiation
25.2.1 EXTENDED INSTRUCTION SYNTAX
for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution. Most of the extended instructions use indexed
arguments, using one of the File Select Registers and
The extended instructions are specifically implemented
some offset to specify a source or destination register.
to optimize re-entrant program code (that is, code that
When an argument for an instruction serves as part of
is recursive or that uses a software stack) written in
indexed addressing, it is enclosed in square brackets
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
error if it determines that an index or offset value is not
structures more efficiently. These include:
bracketed.
When the extended instruction set is enabled, brackets
stack space when entering and leaving
are also used to indicate index arguments in byte-
subroutines
oriented and bit-oriented instructions. This is in addition
to other changes in their syntax. For more details, see

.
stack

Note: In the past, square brackets have been

used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text and going forward, optional

TABLE 25-3: EXTENSIONS TO THE PIC18 INSTRUCTION SET

Mnemonic, 16-Bit Instruction Word Status
Description Cycles
Operands MSb LSb Affected

ADDFSR f, k Add literal to FSR 1 1110 1000 ffkk kkkk None

ADDULNK k Add literal to FSR2 and return 2 1110 1000 11kk kkkk None
CALLW Call subroutine using WREG 2 0000 0000 0001 0100 None
MOVSF zs, fd Move zs (source) to 1st word 2 1110 1011 0zzz zzzz None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVSS zs, zd Move zs (source) to 1st word 2 1110 1011 1zzz zzzz None
zd (destination) 2nd word 1111 xxxx xzzz zzzz
PUSHL k Store literal at FSR2, 1 1110 1010 kkkk kkkk None
decrement FSR2
SUBFSR f, k Subtract literal from FSR 1 1110 1001 ffkk kkkk None
SUBULNK k Subtract literal from FSR2 and 2 1110 1001 11kk kkkk None
return

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 PIC18(L)F2X/4XK22
25.2.2 EXTENDED INSTRUCTION SET

ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 + k FSR2,
Operation: FSR(f) + k FSR(f) (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk

contents of FSR2. A RETURN is then

Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
The instruction takes two cycles to
Q Cycle Activity:
execute; a NOP is performed during
Q1 Q2 Q3 Q4
the second cycle.
Decode Read Process Write to This may be thought of as a special
Data FSR case of the ADDFSR instruction,
11
only on FSR2.
Example: ADDFSR 2, 23h Words: 1
Before Instruction Cycles: 2
FSR2 = 03FFh
After Instruction
Q Cycle Activity:
FSR2 = 0422h
Q1 Q2 Q3 Q4
Decode Read Process Write to
Data FSR
No No No No
Operation Operation Operation Operation

Example: ADDULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 0422h
PC = (TOS)

Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).

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PIC18(L)F2X/4XK22

CALLW Subroutine Call Using WREG MOVSF Move Indexed to f

Syntax: CALLW Syntax: MOVSF [zs], fd
Operands: None Operands: 0 zs 127
0 fd 4095
Operation: (PC + 2) TOS,
(W) PCL, Operation: ((FSR2) + zs) fd
(PCLATH) PCH,
Status Affected: None
(PCLATU) PCU
Encoding:
Status Affected: None
1st word (source) 1110 1011 0zzz zzzzs
Encoding: 0000 0000 0001 0100 2nd word (destin.) 1111 ffff ffff ffffd
Description First, the return address (PC + 2) is Description: The contents of the source register are
pushed onto the return stack. Next, the d
contents of W are written to PCL; the actual address of the source register is
existing value is discarded. Then, the determined by adding the 7-bit literal
contents of PCLATH and PCLATU are s
latched into PCH and PCU, FSR2. The address of the destination
respectively. The second cycle is register is specified by the 12-bit literal
executed as a NOP instruction while the d
new next instruction is fetched. can be anywhere in the 4096-byte data
Unlike CALL, there is no option to space (000h to FFFh).
update W, Status or BSR. The MOVSF instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
Words: 1
destination register.
Cycles: 2 If the resultant source address points to
Q Cycle Activity: an indirect addressing register, the
value returned will be 00h.
Q1 Q2 Q3 Q4
Decode Read PUSH PC to No Words: 2
WREG stack operation Cycles: 2
No No No No Q Cycle Activity:
operation operation operation operation
Q1 Q2 Q3 Q4
Decode Determine Determine Read
Example: HERE CALLW source addr source addr source reg
Decode No No Write
Before Instruction
operation operation
PC = address (HERE)
PCLATH = 10h No dummy (dest)
PCLATU = 00h read
W = 06h
After Instruction
PC = 001006h
Example: MOVSF [05h], REG2
TOS = address (HERE + 2)
PCLATH = 10h Before Instruction
PCLATU = 00h
FSR2 = 80h
W = 06h
Contents
of 85h = 33h
REG2 = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
REG2 = 33h

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 PIC18(L)F2X/4XK22

MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 zs 127 Operands: 0 k 255
0 zd 127
Operation: k (FSR2),
Operation: ((FSR2) + zs) ((FSR2) + zd) FSR2
Status Affected: None
Status Affected: None
Encoding:
Encoding: 1111 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd
memory address specified by FSR2. FSR2
Description The contents of the source register are
is decremented by 1 after the operation.
moved to the destination register. The
This instruction allows users to push values
addresses of the source and destination
onto a software stack.
registers are determined by adding the
s d Words: 1
respectively, to the value of FSR2. Both
Cycles: 1
registers can be located anywhere in
the 4096-byte data memory space Q Cycle Activity:
(000h to FFFh). Q1 Q2 Q3 Q4
The MOVSS instruction cannot use the Write to
PCL, TOSU, TOSH or TOSL as the data destination
destination register.
If the resultant source address points to
an indirect addressing register, the Example: PUSHL 08h
value returned will be 00h. If the
resultant destination address points to Before Instruction
an indirect addressing register, the FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
instruction will execute as a NOP.
Words: 2 After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg

Example: MOVSS [05h], [06h]

Before Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 11h
After Instruction
FSR2 = 80h
Contents
of 85h = 33h
Contents
of 86h = 33h

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PIC18(L)F2X/4XK22

SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] FSR2
FSRf (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk

the contents of the FSR specified by contents of the FSR2. A RETURN is then
executed by loading the PC with the TOS.
Words: 1 The instruction takes two cycles to
execute; a NOP is performed during the
Cycles: 1
second cycle.
Q Cycle Activity:
This may be thought of as a special case of
Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary
Decode Read Process Write to 11
Data destination Words: 1
Cycles: 2
Q Cycle Activity:
Example: SUBFSR 2, 23h
Q1 Q2 Q3 Q4
Before Instruction
FSR2 = 03FFh Decode Read Process Write to
Data destination
After Instruction
FSR2 = 03DCh No No No No
Operation Operation Operation Operation

Example: SUBULNK 23h

Before Instruction
FSR2 = 03FFh
PC = 0100h
After Instruction
FSR2 = 03DCh
PC = (TOS)

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 PIC18(L)F2X/4XK22
25.2.3 BYTE-ORIENTED AND 25.2.3.1 Extended Instruction Syntax with
BIT-ORIENTED INSTRUCTIONS IN Standard PIC18 Commands
INDEXED LITERAL OFFSET MODE When the extended instruction set is enabled, the file

bit-oriented commands is replaced with the literal offset

Note: Enabling the PIC18 instruction set
extension may cause legacy applications less than or equal to 5Fh. When an offset value is used,
to behave erratically or fail entirely.
the extended instructions, the use of brackets indicates
In addition to eight new commands in the extended set, to the compiler that the value is to be interpreted as an
enabling the extended instruction set also enables index or an offset. Omitting the brackets, or using a
Indexed Literal Offset Addressing mode (Section 5.7.1 value greater than 5Fh within brackets, will generate an
). This has error in the MPASM assembler.
a significant impact on the way that many commands of
the standard PIC18 instruction set are interpreted. If the index argument is properly bracketed for Indexed
Literal Offset Addressing, the Access RAM argument is
When the extended set is disabled, addresses never specified; it will automatically be assumed to be
embedded in opcodes are treated as literal memory 0

0 1). the target address. Declaring the Access RAM bit in

this mode will also generate an error in the MPASM
0, however, a file register argument of 5Fh or less is assembler.
interpreted as an offset from the pointer value in FSR2
and not as a literal address. For practical purposes, this
means that all instructions that use the Access RAM bit
language support for the extended instruction set must
oriented instructions, or almost half of the core PIC18 be explicitly invoked. This is done with either the
command line option, /y, or the PE directive in the
extended instruction set is enabled. source listing.
When the content of FSR2 is 00h, the boundaries of the
25.2.4 CONSIDERATIONS WHEN
Access RAM are essentially remapped to their original
values. This may be useful in creating backward ENABLING THE EXTENDED
compatible code. If this technique is used, it may be INSTRUCTION SET
necessary to save the value of FSR2 and restore it It is important to note that the extensions to the instruc
when moving back and forth between C and assembly tion set may not be beneficial to all users. In particular,
routines in order to preserve the Stack Pointer. Users users who are not writing code that uses a software
must also keep in mind the syntax requirements of the stack may not benefit from using the extensions to the
extended instruction set (see Section 25.2.3.1 instruction set.
Additionally, the Indexed Literal Offset Addressing
).
mode may create issues with legacy applications
Although the Indexed Literal Offset Addressing mode written to the PIC18 assembler. This is because
can be very useful for dynamic stack and pointer instructions in the legacy code may attempt to address
manipulation, it can also be very annoying if a simple registers in the Access Bank below 5Fh. Since these
arithmetic operation is carried out on the wrong addresses are interpreted as literal offsets to FSR2
register. Users who are accustomed to the PIC18 when the instruction set extension is enabled, the
programming must keep in mind that, when the application may read or write to the wrong data
extended instruction set is enabled, register addresses addresses.
of 5Fh or less are used for Indexed Literal Offset
When porting an application to the PIC18(L)F2X/
Addressing.
4XK22, it is very important to consider the type of code.
Representative examples of typical byte-oriented and
bit-oriented instructions in the Indexed Literal Offset would benefit from efficient compilation will do well
Addressing mode are provided on the following page to when using the instruction set extensions. Legacy
show how execution is affected. The operand condi applications that heavily use the Access Bank will most
tions shown in the examples are applicable to all likely not benefit from using the extended instruction
instructions of these types. set.

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PIC18(L)F2X/4XK22

ADD W to Indexed Bit Set Indexed

ADDWF BSF
(Indexed Literal Offset mode) (Indexed Literal Offset mode)
Syntax: ADDWF [k] {,d} Syntax: BSF [k], b
Operands: 0 k 95 Operands: 0 f 95
d [0,1] 0 b 7
Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k)<b>
Status Affected: N, OV, C, DC, Z Status Affected: None
Encoding: 0010 01d0 kkkk kkkk Encoding: 1000 bbb0 kkkk kkkk
Description: The contents of W are added to the
contents of the register indicated by
Words: 1
0
1 Cycles: 1
Q Cycle Activity:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1 Decode Read Process Write to
Data destination
Q Cycle Activity:
Q1 Q2 Q3 Q4
Example: BSF [FLAG_OFST], 7
Write to
Before Instruction
Data destination
FLAG_OFST = 0Ah
FSR2 = 0A00h
Example: ADDWF [OFST] , 0 Contents
of 0A0Ah = 55h
Before Instruction
After Instruction
W = 17h Contents
OFST = 2Ch of 0A0Ah = D5h
FSR2 = 0A00h
Contents
of 0A2Ch = 20h
After Instruction
W = 37h
Contents
Set Indexed
SETF
of 0A2Ch = 20h (Indexed Literal Offset mode)
Syntax: SETF [k]
Operands: 0 k 95
Operation: FFh ((FSR2) + k)
Status Affected: None
Encoding: 0110 1000 kkkk kkkk
Description: The contents of the register indicated by

Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Write
Data register

Example: SETF [OFST]

Before Instruction
OFST = 2Ch
FSR2 = 0A00h
Contents
of 0A2Ch = 00h
After Instruction
Contents
of 0A2Ch = FFh

DS40001412H-page 408 2010-2021 Microchip Technology Inc.