The International journal of analytical and experimental modal analysis ISSN NO:0886-9367

DESIGN AND IMPLEMENTATION OF RECONFIGURABLE FFT

PROCESSOR USING ERROR DETECTION AND CORRECTION
SYSTEM
1
Y DANIEL MANI RATNA KUMAR, 2RUBIA TASNEEM
1
M.Tech scholar, Dept of ECE, Pragati Engineering College, Surampalem, Andhra Pradesh, India
2
Assistant Professor, Dept of ECE, Pragati Engineering College, Surampalem, Andhra Pradesh,
India

ABSTRACT: In this paper the design and Minimal effort and adaptable HW stages. In
implementation of high speed reconfigurable FFT the OFDM images using the Discrete
processor using error detection and correction
system is done. Basically the FFT supports the bit
Fourier to obtain the high speed operation in
size which is suitable to the system and mostly the system. Here the length of each image is
used in the long term evolution systems. Transport considered as N and these produces complex
triggered architecture is utilized to customize the quantities in the entire system. Hence the
size of fault free FFT processor. Here the both vector image is used with the length of N =
energy-efficiency and performance is evaluated by
using the standard cell technology. Address
128. In the Meantime, the plan eases to be
Generation unit generates the address to access valuable and the primary target gadgets are
the main memory. Adder and multiplier operation compact purchaser Electronics, for example,
is performed very effectively. Error detection and portable (advanced cells,) workstations, and
correction system will detect and correct the so forth. Then again, plans of action require
errors in effective way. Computation is provided
to the obtained output from addition and
adaptable programmable usage [2].
multiplication process. At last from simulation
result it can observe that reconfigurable memory Basically, the main intent of filters is to use
based FFT processor gives effective outcome. partial range of frequency to emphasize the
signals. But here the signals are getting
KEY WORDS: FFT, Computation, Adder,
Multiplier, Computing Address, Generator
rejected because of selection of frequency
Memory Bank. range in alternate way. Coming to the
designing part of circuit, the frequency is
I.INTRODUCTION selected alternatively. Here the frequency
Generally, discrete Fourier transform is range is connected to the electric network.
introduced in 1965. Basically, the discrete This electric network works depending on
Fourier transform is taken from the fast the characteristics of signals. The
Fourier calculation. All things considered, characteristic parameters are amplitude,
after practically 50 years, stays extremely frequency and time [3].
high because of key helpful properties of
DFT. The ongoing increase in such intrigue Depending on these parameters the entire
is because of correspondence applications, electric network works. Here this may come
specifically Long Term Evolution (LTE) and to know that, there will be no change in
Software Defined Radio (SDR) [1]. In these allotted frequency and as well as cannot add
applications, productive usage of DFT are new frequency to the system. Filters are
required so as to help very tight, commonly mainly used in the applications of medical,
negating limitations, for example, hard automotive. There is a unity of region with
ongoing necessities over low-control, some very surprising bases of
characterization channels and these cover in

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The International journal of analytical and experimental modal analysis ISSN NO:0886-9367

some unique ways; there is no direct conditional sequences are using the number
hierarchical grouping. As the social of muliple opeartions units. Here the
properties of the sign change, separation pipeline architectures are designed inside the
strategies will be considered. each unit and the entire operation is
performed sequentially.Next coming to the
FFT is an elective calculation procedure for block butterfly unit, it performs the forward
discrete Fourier change as it registers and inverse operation. In multiple adder
rapidly. FFTs are utilized in countless unit, the component wise multiplication and
applications extending from advanced sign addition operatiions are performed. Now for
preparing and furthermore in the the time domian operations are using the
calculations, for example, understanding the ripple carry adder, subractor and shift
incomplete differential conditions, module units. Control unit is used to
augmentation of enormous esteem whole generate the control signals in the system.
numbers and so forth. FFT processor Coming to memory, it consists of several
working recurrence decides the range for RAM sets which stores the precomputed
which the processor can be utilized. The data and intermidiate results.
processor is intended to figure countless
complex increases both at rapid and with
reliable throughput.
The other design challenges are found in the
way in which, by changing the number of
centers in FFT, the processor can be suitable
for several applications that work both from
the structure and from sensitive applications.
Despite the way in which this is apparently
useful, the fluctuation of the number of
centers emphasizes different changes both at
the registration level and through the change
in the number of bits and the level of
construction based on the variation in the
length of the displacement registers,
analogously to regulation of the meaning of
ROM.
Fig. 1: FFT PROCESSOR
II.FFT PROCESSOR The first and principle significant part in the
The below figure (1) shows the architecture design is multiply and adder unit. This unit
of FFT processor system. In the memory actualizes the segment insightful
based FFT processor architecture is using augmentation and expansion of FFT-RAM.
two modules and this can performs fast To understand the segment savvy increase
opeartions without zero padding. Here radix when operand size isn't bigger than couple
architecture is shown and multipliers are of hundred bits then karatsuba technique is
used. All these componenets combine utilized. The multiplier and adder units
together and gives the specified output. works with pipeline of 3 bit data sources and
one piece yield. Finally to improve the
In this memory based FFT processor system, presentation of increase, karatsuba strategy
for the purpose of modular reduction and is connected recursively. This is about

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The International journal of analytical and experimental modal analysis ISSN NO:0886-9367

duplicate and snake unit and let us examine A Fast Fourier Transform (FFT) is an
about FFT unit. estimate that represents the Discrete Fourier
Transform (DFT) of a meeting or its round
Next it is connected to FFT calculation. The (IDFT). Fourier's examination changes on a
principle correlation of set up and consistent sign of this extraordinary region
geometry FFT is it has same association (occasionally time or space) to a
arrange between each neighboring stages. representation in the space of repetition and
The FFT is structured with six data sources. in a different way. DFT is obtained by
In this the four contributions forward the breaking down a progression of
digits into BFSs for FFT calculation and the characteristics in different frequency
other two contributions forward the pre- portions. This action is important in several
registered upper bound imperatives into fields, but its direct management from the
FSO. definition is as frequent as possible,
III. PROPOSED SYSTEM excessively moderate or possibly
The below figure (2) shows the block conventional.
diagram of proposed system. In this inputs
are taken as input A and input B are used. Accumulation Unit (ACU), is an execution
Twiddle factor is used for multiplication unit inside Control Processing Units (CPUs)
process. Rounding process is performed. that ascertains addresses utilized by the CPU
after rounding process, multiplier will to get to primary memory. By having
multiply the dat. If there are errors in address estimations taken care of by discrete
multiplied data then error detection and hardware that works in parallel with the
correction stage will detect and correct the remainder of the CPU, the quantity of CPU
errors. Address generation stage will cycles required for executing different
generate the address for multiplied data. pre machine directions can be diminished,
processing stage will generate the bringing execution upgrades. While
propagator and generate signals. Carry performing different tasks, CPUs need to
generation stage will generate the carry. Post compute memory tends to required for
processing stage will save the obtained bringing information from the memory; for
output. instance, in-memory places of exhibit
components must be determined before the
CPU can get the information from genuine
memory areas. Those location age
computations include distinctive number-
crunching tasks, for example, expansion,
subtraction, modulo activities, or bit shifts.
The technique that is utilized to exchange
data between inward capacity and outer
gadgets is known as I/O interface. The CPU
is interfaced utilizing unique correspondence
interfaces by the peripherals associated with
any PC framework. These correspondence
connections are utilized to determine the
contrasts among CPU and fringe. There
Fig. 2: PROPOSED SYSTEM exists extraordinary equipment parts among
CPU and peripherals to administer and

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The International journal of analytical and experimental modal analysis ISSN NO:0886-9367

synchronize all the info and yield exchanges

that are called interface units.
Commutators are utilized in direct current
(DC) machines: dynamos (DC generators)
and numerous DC engines just as
widespread engines. In an engine the
commutator applies electric flow to the Fig. 4: TECHNOLOGY SCHEMATIC
windings. By switching the present bearing
in the pivoting windings every half turn, a
consistent pivoting power (torque) is
delivered. At least two electrical contacts
called "brushes" made of a delicate
conductive material like carbon press against
the commutator, reaching progressive
sections of the commutator as it pivots. The Fig. 5: INPUT WAVEFORM
windings (loops of wire) on the armature are
associated with the commutator portions.
IV. RESULTS

Fig. 6:OUTPUT WAVEFORM

V. CONCLUSION
Hence in this paper design and
implementation of high speed reconfigurable
FFT processor using error detection and
correction system was done. In present day
sign preparing circuits, it is entirely expected
to discover a few channels working in
parallel. Reconfigurable memory based FFT
processor framework is a zone productive
system to identify and address single
mistakes. The methodology depends on FFT
yields to identify and address errors. The
commutator checks are utilized to recognize
and find the mistakes and a straightforward
equality FFT is utilized for revision.
Contrasted and past works with comparable
location conspires, this paper underpins
increasingly summed up lengths and
accomplishes progressively adaptable
throughput.
VI. REFERENCES
[1] Yu Xie, Chen Yang, Chuang-An Mao,
Fig. 3: RTL SCHEMATIC He Chen and YiZhuang Xie , “A Novel

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Low-Overhead Fault Tolerant Parallel

Pipelined FFT Design”, 978-1-5386-0362-
8/17/$31.00 ‫׉‬2017 IEEE.
[2] Syed M. A. H. Jafri, Stanisław J.
Piestrak, Kolin Paul, Ahmed Hemani, Juha
Plosila, and Hannu Tenhunen, “Energy-
Aware Fault-Tolerant CGRAs Addressing
Application with Different Reliability
Needs”, `/13 $26.00 © 2013 IEEE.
[3] Abbas BanaiyanMofrad, Houman
Homayoun , Nikil Dutt, “FFT-Cache: A
Flexible Fault-Tolerant Cache Architecture
for Ultra Low Voltage Operation”,
CASES’11, October 9–14, 2011, Taipei,
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[4] C. Radhakrishnan and W. K. Jenkinss,
“Fault Tolerant Adaptive Filters Based on
Modified Discrete Fourier Transform
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3/11/$26.00 ©2011 IEEE.
[5] Hongyi Fu, Xuejun Yang, “Fault
Tolerant Parallel FFT Using Parallel Failure
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2009 IEEE.
[6] Jin-Fu Li, Shyue-Kung Lu, Shih-Arn
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[7] G. Robert Redinbo, Ranjit Manomohan,
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[8] Jin-Fu Li and Cheng-Wen Wu, “Testable
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