USOO6362075B1

(12) United States Patent (10) Patent No.: US 6,362,075 B1

Czagas et al. (45) Date of Patent: Mar. 26, 2002

(54) METHOD FOR MAKING A DIFFUSED 4,923,820 A 5/1990 Beasom

BACK-SIDE LAYER ON A BONDED-WAFER 5,801,084 A * 9/1998 Beasom et al. ............. 438/457
WITHATHICK BOND OXDE 5,882,990 A * 3/1999 DeBusket al. ............. 438/476
6,057,212 A 5/2000 Chan et al. ................. 438/455
(75) Inventors: Joseph A. Czagas, Palm Bay; Dustin 6,118,181 A 9/2000 Merchant et al. ........... 257/757
A. Woodbury, Indian Harbour Beach; 6,140.210 A * 10/2000 Aga et al. ................... 438/458
6,146.979 A * 11/2000 Henley et al. .............. 438/458
James D. Beasom, Melbourne Village, 6,159,824. A * 12/2000 Henley et al. .............. 438/455
all of FL (US) 6,191,006 B1 2/2001 Mori .......................... 438/455
6.211,041 B1 4/2001 Ogura ........................ 438/458
(73) Assignee: Harris Corporation, Melbourne, FL 6,214,701 B1 4/2001 Matsushita et al. ......... 438/458
(US)
OTHER PUBLICATIONS
(*) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35 Joseph A. Czagas, et al. “Method for Making a Diffused
U.S.C. 154(b) by 0 days. Back-Side Layer on a Bonded-Wafer with a Thick Bond
Oxide", pp 1-13, Mar. 2, 1999.
(21) Appl. No.: 09/345,261 * cited by examiner
(22) Filed: Jun. 30, 1999
Primary Examiner Matthew Smith
(51) Int. Cl." ......................... H01L 21/00; H01L 21/30; ASSistant Examiner-Chuong A Lulu
HO1L 21/46 (74) Attorney, Agent, or Firm-Fogg, Slifer & Polglaze,
(52) U.S. Cl. ....................... 438/455; 438/456; 438/408; P.A.; Scott V. Lundberg
438/164; 438/933
(58) Field of Search ................................. 438/455, 456, (57) ABSTRACT
438/406, 404, 430, 407, 203, 422, 164, Integrated circuits, Semiconductor devices and methods for
542, 458, 476, 408, 403,933 making the same are described. Each embodiment Shows a
(56) References Cited diffused, doped backside layer in a device wafer that is oxide
bonded to a handle wafer. The diffused layer may originate
U.S. PATENT DOCUMENTS in the device wafer, in the handle wafer, in the bond oxide
or in an additional Semiconductor layer of polysilicon or
4,127.932 A 12/1978 Hartman et al. .............. 438/58 epitaxial Silicon. The methods use a thermal bond oxide or
4,504,334 A * 3/1985 Schaake et al. ...... ... 438/476 a combination of a thermal and a deposited oxide.
4,554,059 A * 11/1985 Short et al. ................. 438/408
4,807,012 A 2/1989 Beasom
4,897,362 A * 1/1990 Delgado et al. ............ 438/406 26 Claims, 4 Drawing Sheets

HANDLE
P HANDLE
12 20

BOND OXDE ZZZZZZZZZZZ

DEVICE (BULK) DEVICE (BULK)
U.S. Patent Mar. 26, 2002 Sheet 1 of 4 US 6,362,075 B1

- --

DISTRIBUTED
12

P 11

re -
FIG. 2A HANDLE

2/721/////4-12
F-Z2 --
P BOND OXDE 14
DEVICE (BULK) 10
FIG. 2B
FIG. 3A
HANDLE

ZZZZZZZZZZZ
DEVICE (BULK)
FIG. 3B
P
W P DEVICE

FIG. 2D
U.S. Patent Mar. 26, 2002 Sheet 2 of 4 US 6,362,075 B1

P (BORON)
P(BORON)
BOND OXDE
-12
BOND OXDE DEVICE (BULK)
DEVICE (BULK) FIG. 5A
FIG. 4A P (BORON)
P (BORON) BOND OXDE 777 777 7777.
-
ZZZZZ AZ Z Z Z
12
L 14 DEVICE
DEVICE (BULK) 10.

FIG. 4B P2
P (BORON) HANDLE
'YZ
10 DEVICE

16 DEPOSITEDOX P12
14 24
10 DEVICE

FIG 5D
20
16 DEPOSITED OX P
14Y-ZZZZZZZZZZ
16 DEVICE
U.S. Patent Mar. 26, 2002 Sheet 3 of 4 US 6,362,075 B1
BOND OXDE
ZZZZZZZZZZZ
ZZZZ 77777.7 2
P12 HIGH ENERGY 12
14
DEVICE 10 1

FIG. 7A
DOND OXDE POLYSILICON
18.1
14

--1P12 TOBE i?
OXIDIZED
FIG 6B

BOND OXDE
THERMAOX 18.2
7
2 P12 BOND OXDE 14
DEVICE 10 ZZZZZZZZZZN-12
10
FIG. 6C
FIG. 7C
BOND OXIDE
HANDLE 20
HANDLE 20
THERMAlox -182 P12
H. BOND OXEDE 14
ZZZZZZZZZZN-12
10 N-10
U.S. Patent Mar. 26, 2002. Sheet 4 of 4 US 6,362,075 B1
MPLANTED REGION
12

DEVICE 10

FIG. 3A
IMPANTED REGION
EPITAXIALS /1-191
ZZZZZZZZZZZ-12
DEVICE N-10

FIG. 8B
MPLANTED REGION
BOND OXDE | 19.2
//////////
M 12
DEVICE 10

FIG. 8C

BOND OXIDE
//ZZZZZZZZZ
DEVICE
 US 6,362,075 B1
1 2
METHOD FOR MAKING A DIFFUSED Side p-type layer that was not confined to within a few
BACK-SIDE LAYER ON A BONDED-WAFER microns (um) of the bottom of the device island (adjacent to
WITHATHICK BOND OXDE the bond oxide), but that had up-diffused to nearly the
Surface of the lightly-doped p-type device island. This
BACKGROUND OF THE INVENTION reduces the effectiveness of the backside p-type layer in
The High-Voltage Switch (HVS) process technology is enhancing the breakdown of the high-voltage devices.
designed to fabricate a high-voltage relay circuit, and a The device island doping at the bottom needs to be
high-voltage Switch circuit. Both of these types of circuits restricted as closely as possible to the bottom of the device
are used in telecom. (wired telephone) products/ island (the device-Si/bond-oxide interface), so that high
applications. One of the primary devices fabricated in the fields near breakdown are integrated over the greatest pos
HVS technology is a NDMOS with a 400 V breakdown. Sible distance, and thus allow the maximum possible break
One of the features of the 400 V NDMOS is that it down Voltage. This leads to a penalty incurred for any
requires a p-type layer in the bottom of the lightly-doped thermal treatment (Dt) done after the backside p-type layer
p-type device island in which it is formed. The p-type layer has been introduced. This is analogous to the unwanted
15 up-diffusion of a buried layer. However, it should also be
in the bottom of the p-type island is used to provide enough
charge to fully deplete the drain extension layer. The use of noted that the method and structure of this disclosure may be
a p-type bottom layer to control the depletion of a p-type applied to current-carrying buried layerS as well. The nature
island due to substrate bias is described by Beasom, U.S. of bonded-wafer processing entails significant thermal treat
Pat. Nos. 4,923,820 and 4,807,012. This also applies to the ment: device oxidation on the island bottom, bond oxidation
general case of depleting a drain extension, or junction during mating of the device/handle wafers, and trench
termination extension (JTE) layer in a relatively thin, lightly sidewall oxidation to provide lateral device isolation. The
doped island. FIG. 1a shows a conventional drain. FIG. 1b thermal processing required for the front-Side diffused layers
shows a drain with drain extensions. Note the differences in further compounds the problem.
size and shape between the depletion Zone of FIG.1a and the 25
There are Some obvious ways of mitigating the loss of
depletion Zone of FIG. 1b. The drain/junction-termination breakdown due to up-diffusion of the backside p-type layer
extension is used to improve (raise) the breakdown voltage into the lightly-doped p-type device island Si. One is to
of the device by de-focusing the field formed at the edge of lower the dose of the backside p-type (boron) implant. This
the pn junction in the drain region. does not correct the problem with up-diffusion, it just limits
Another purpose for the use of the backside highly-doped the concentration of dopant that is available for up-diffusion.
p-type layer in the HVS proceSS technology, is to provide Another way of keeping the backside p-type layer towards
shielding at the bottom of the device island to protect the the bottom of the device island, is to increase the thickness
devices from Swings in the potential of the handle wafer of the device island. This is problematic for a couple of
under the bond oxide (which can vary in sign, and may be reasons. The trench etch must go through the entire thick
in the magnitude of hundreds of volts), when devices made 35
ness of the device island SL to provide lateral isolation for
in this technology are used in Switching applications. devices. Etching the isolation trench through a thicker
Basically, these voltage Swings can cause the device island device island, will result in more chance of Small dimension
to deplete from the backside. Increasing the doping at the device island geometries being undercut and delaminating
bottom of the device island helps to terminate any depletion from the handle wafer during Subsequent processing. This
field coming from the handle wafer on the backside of the 40
results in an increase in the minimum device island size, and
device island. This allows for the device island to then trench-to-trench minimum space, both of which result in a
deplete the drain extensions fully. die area increase. The increase in trench depth also results in
A p-type layer may be formed in the bottom of a lightly an decrease in equipment throughput at the trench etch
doped p-type device island by doping the bottom of the operation.
device wafer before it is bonded to the handle wafer. See 45 SUMMARY
FIGS. 2a-2d. A disadvantage of this process is that the
bottom p-type layer 12 will up-diffuse into the lightly doped The invention provides silicon on insulator devices with
p-type device wafer 10 during the growth of the bottom diffused device wafer backside layers and methods for
isolation (bond) oxide 14, and during the bonding process manufacturing the Same. Integrated circuits and Semicon
where the device and handle wafer are joined. These pro 50 ductor devices are formed in device islands in a device
cesses may have a large Dt (Diffusivity-time product) result wafer. The device wafer is held to a handle wafer by a bond
ing in a thickening of the bottom p-type layer when boron is oxide. The diffused doped layer is on the backside of the
used as the p-type dopant 12. device wafer between the device islands and the bond oxide.
Generally, in order to make high-voltage devices, junction The dopants in the diffused layer may be initially implanted
depths must be scaled (made deeper) than for an equivalent 55 into either the device wafer or handle wafer. Implantation is
device in a low-voltage process. Increasing junction depth, made directly into the Semiconductor material or through an
entails increasing Dt used in fabricating the devices. This oxide layer. The dopant may be diffused from a deposited or
also causes up-diffusion of a bottom p-type layer into the grown Semiconductor layer that is itself implanted or oth
bulk of the lightly-doped p-type device island. The HVS erwise doped with a diffusing dopant. When boron is the
process originally used a p-type (50 to 150 S2-cm) device 60 diffusing dopant, boron ions may be implanted into a bond
island of about 35 to 40 um thickness. Into this, a p-type oxide layer and then diffused from the bond oxide into the
layer was implanted/diffused into the backside of the device device wafer.
wafer before the bond oxide is grown, after which the device DESCRIPTION OF THE DRAWINGS
wafer is bonded to the handle wafer.
In HVS, the backside p-type layer is put in before the 65 FIGS. 1a and 1b are partial cross sectional views of an
wafer sees any of the Dt of the process. The first HVS n-type well (1a) and an n-type well with a drain extension
fill-process material was found (by SRP) to have the back (1b).
 US 6,362,075 B1
3 4
FIGS. 2a-2d show sequential steps in the formation of a diffusion of boron through an oxide. A handle wafer 20 that
prior art diffused backside layer. is doped to be p-type, or has a p-type layer at the Surface
FIGS. 3a–3b show sequential steps in the formation of the (adjacent to the bond oxide interface), may be used as the
first embodiment of the invention, with a p-Type (Boron) dopant Source. During the wafer bond operation, and the
implant into the handle wafer. Subsequent high-temperature cycles, the p-type (boron)
FIGS. 4a–4c show sequential steps in the formation of the dopant is diffused through the bond oxide 14, and into the
second embodiment of the invention, with a p-Type (Boron) bottom of the device wafer 10, to form the desired p-type
implant directly into the bond oxide. bottom layer 12. This p-type layer 12 will be shallower than
FIGS. 5a-5e show sequential steps in the formation of the the p-type layer formed directly in the bottom of the device
third embodiment of the invention, with the use of a com wafer 10 (FIG. 2), because it must diffuse through the bond
oxide 14 before it enters the backside of the device wafer 10.
posite (thermal/deposited) bond oxide. The concentration of the p-type (boron) dopant introduced
FIGS. 6a–6a show sequential steps in the formation of the into the bottom of the device wafer 10 may be adjusted by
fourth embodiment of the invention, growing a composite choosing, or adjusting the bottom isolation (bond) oxide
bond oxide by using a thermal oxidation of a polysilicon 15 thickness, p-type (boron) dopant concentration (doping
layer. level, and integrated dose/depth, if not done from the bulk of
FIGS. 7a-7d show sequential steps in the formation of the a uniformly-doped handle wafer), and the Dt to which the
fifth embodiment of the invention, using a high-energy composite structure (shown in the last part of FIG.3 on page
implant to place the peak of the backside layer implant into 4) is Subjected.
the device wafer. In addition, the bond oxide 14 may be grown (either
FIGS. 8a–8d show sequential steps in the formation of the partially, or fully) on the p-type handle wafer 20, So as to
Sixth embodiment of the invention, using an epitaxial Silicon incorporate the p-type (boron) dopant into this oxide as it is
deposition to Set the depth of the backside layer implant in grown. This will result in less Dt required to drive the p-type
the device wafer. (boron) dopant into the bottom of the device wafer. For
DETAILED DESCRIPTION OF THE 25 example: Aboron implant of 1.1x10" atoms/cm was done
INVENTION into a boron-doped 3x10" atoms/cm’ p-type wafer. This
wafer had 2 um of oxide grown on it, and was bonded to a
The invention is used in fabricating a DMOS device that 3x10' atoms/cm n-type wafer. A p-type (boron) layer of
is built in a lightly doped P type island using a lateral drain approximately 3.6x10" atoms/cm was formed in the
extension structure as described in U.S. Pat. Nos. 4,823,173 n-type wafer after the wafer bond operation.
and 5,264,719. The island is oxide isolated by the bonded Embodiment 2: p-Type (Boron) Implant Directly Into the
wafer Structure. Bond Oxide as the P-Type Dopant Source
Lateral drain extensions and similarly functioning junc FIGS. 4a–4c show another method of getting a backside
tion termination extension (JTE) layers are used to improve p-type layer which is kept as near the bottom of the device
(increase) breakdown voltage by defocusing the electric 35 island as possible. The method first grows bond oxide 14,
field formed at the edge of a high voltage PN junction (the implants a p-type (boron) ion into the bond oxide 14,
drain body junction in the DMOS). The proper operation of followed by a non-oxidizing diffusion of the boron through
Such extension regions requires that they totally deplete in a the oxide into the bottom of the device wafer 10. The device
controlled way. Controlled depletion requires that the inte wafer 10 may then be bonded to the handle wafer 20. Doing
grated island doping (doping ions per cm) beneath the 40 the implant of the p-type dopant into the bond oxide 14 has
extension be greater than the integrated doping in the the Same benefit as in Embodiment 1, namely using the
extension. This requirement is not met in thin islands of oxide to delay the introduction of the p-type dopant into the
uniform light doping. The problem can be overcome by bottom of the device wafer. (It should be noted that the entire
adding a region of increased doping in the bottom of the p-type implant need not reside Solely in the oxide layer, but
island which increases the integrated doping above the 45 may also partially breach the device-wafer/bond oxide
critical level. interface.) (It should be further noted that the step of
In some applications, the DMOS devices will be operated diffusing can be performed during oxide bonding.)
at bias Voltages which can range hundreds of Volts above and Embodiment 3: Use of a Composite (Thermal/Deposited)
below the voltage on the handle wafer on which the device Bond Oxide to Achieve a Shallow Backside p-Type Layer
island is formed. Such bias can deplete a portion of the 50 with a Thick Bond Oxide
island from the bottom reducing the integrated charge avail See FIGS. 5a-5e. Embodiments 1 and 2 require that the
able to deplete the extension layer. This effect can also be bond oxide 14 thickness be selected such that the p-type
controlled by adding a layer of increased doping to the (boron) dopant may be diffused through it, and into the
bottom of the island which has the same conductivity type backside of the device wafer 10 in a controlled manner. For
as the island. This structure and method are described in U.S. 55 bond oxide 14 thicknesses greater than 1 Lim, it has been
Pat. Nos. 4,923,820 and 4,807,012. shown experimentally that the boron does not move signifi
When an oxide isolated device having a lateral drain cantly from the original as-implanted depth in the oxide,
extension or JTE layer is made in a thin lightly doped island even after significant Dt (1,275 C. for 20 hrs in N). It is
and must operate at large island terminal Voltages with known that when boron is implanted directly into an oxide
respect to the handle wafer (Substrate) Voltage, the integrated 60 layer, damage Sites are formed, which have an affinity for
island doping must be adjusted to accommodate both effects. boron, and thus limit diffusion of boron through the oxide.
This requires a higher integrated doping than is required to This may be mitigated by using hydrogen in the diffusion
Support just one of these conditions. ambient. The hydrogen is said to “passivate” the damage
Embodiment 1: Diffusion of a p-Type Dopant (Boron) from sites, and therefore allow the boron to diffuse more freely
the Handle Wafer Through the Bond Oxide 65 through the oxide layer. Fluorine may also be used as a
The steps shown in FIGS. 3a–3b illustrate a process diffusion enhancer in the diffusion of a boron layer
which provides a thinner p-type backside layer and exploits implanted into an oxide. The fluoride ion (F-) is very mobile
 US 6,362,075 B1
S 6
in oxide, and tunnels through the oxide breaking bonds in non-Oxidizing diffusion using the polysilicon as the dopant
the process, which creates a path for the boron to follow. Of Source, through the thin bond oxide 14, followed by an
course, the resulting oxide will be of poor quality, and will oxidation of the polysilicon to form the remaining bond
require re-densification once the fluorine diffusion ambient oxide required. This also applies to an originally undoped
is removed. polysilicon (as-deposited), which has Subsequently been
In the HVS technology, a 2.0 um bond oxide 14 is doped by doing an implant/diffusion operation.
required for the fabrication of the Solid-state Switch circuit. Embodiment 5: Using a High-Energy Implant to Place the
The requirement for the thick bond oxide 14 is due to the Peak of the Backside Layer Implant Into the Device Wafer
high-voltage requirement (around 500 V) of some of the A high-energy implant may be used to place a backside
devices used in this circuit. AS Stated earlier, diffusing a dopant at Sufficient depth (peak concentration of the
boron layer using either methods of Embodiment 1, or implanted dopant) Such that it is deeper than the portion of
Embodiment 2, through a 2.0 um bond oxide 14 is not device wafer 10 silicon consumed in growing the bond oxide
feasible, without using an enhancer (Such as hydrogen, or 14. Such a method is shown in FIGS. 7a-7d. This method
fluorine) in the diffusion ambient. Implanting the boron into does not eliminate concerns about up-diffusion of the dopant
an oxide layer less than 1.0 um thick, and doing a non 15
into the device wafer, but it does allow for better control of
oxidizing drive, followed by an oxidation to grow the the process to minimize this.
additional thickness of bond oxide 14 required, is not A variation of Embodiment 4 is shown in FIGS. 8a–8d.
feasible. This is because the boron which is diffused into the There a low-energy implant introduces a backside dopant
bottom of the device wafer, will tend to Segregate out into into the surface of a device wafer 10. An epitaxial silicon
the oxide, and the oxidation will consume the backside layer 19.1 is deposited over this implant. (The epitaxial
p-type diffusion layer. silicon deposition would be set to half the thickness of the
One method for controlling a backside p-type (boron) desired bond oxide.) This epitaxial silicon 19.1 could then be
implant while providing a 2.0 um bond oxide 14, is to drive oxidized Such that it becomes the bond oxide 19.2, and the
the boron implant through a thin (less than 1.0 um) bond backside layer 12 remains in the bottom of the device wafer
oxide 14 into the backside of the device wafer, and add the 10. Again, this does not eliminate concerns about
remaining required bond oxide 14 thickness by doing a 25 up-diffusion of the dopant into the device wafer, but it does
plasma enhanced chemical vapor deposition (PECVD) 16. allow for better control of the process to minimize this.
Conversely, the boron implant could be driven through the Embodiment 7: Use of Multiple Backside Layers to Sepa
thin (less than 1.0 um) thermal bond oxide layer, after the rately ASSist in Drain/Junction-Termination Extension
deposited oxide 16 is added. This would serve to not only set Depletion, and to Control Fields from the Handle Wafer
the profile of the backside p-type (boron) layer in the device In the Background the rationale for using backside layers
wafer, but would also serve to density/anneal the deposited was discussed. There were two (2) reasons for using a
oxide portion of the composite bond oxide. backside diffused layer. The first was to provide additional
charge at the bottom of the device island to allow drain/
In the past, it was believed that oxides deposited by junction-termination extensions to deplete fully, thus
PECVD processes would be unsuitable for use as a bond enhancing (increasing) breakdown voltage of the device.
oxide, and that a thermally grown oxide was the only 35 The Second was to provide a shielding layer at the bottom of
Suitable choice. It was conjectured that the quality the device island, to protect the active device from fields
(uniformity; and particulates), bonding, and Surface States in arising from varying Voltages in the handle wafer 20 under
these types of deposited oxides was Such that a good bond the bond oxide. One, or more of the above embodiments
could not be formed at the bond-oxide/handle-wafer may be used to allow for the manufacture of multiple
interface, and that this would result in device islands delami 40 backside layers to Separately control each of these issues
nating from the Substrate during Subsequent processing. We affecting device performance. In this particular case, a
have Since experimentally determined that this is not the shallow heavily-doped p-type layer may be used to control
case with currently available tools and practices in the fields from the handle wafer 20. A deeper more lightly
industry. Wafers have been successfully bonded using a doped p-type layer may be used to assist in depletion of the
composite (thermal/deposited) bond oxide, and have been 45 drain/junction-termination extensions. Note however, that
successfully processed through the remainder of the HVS multiple application of these embodiments is not restricted
process flow, without device island delamination. to these applications, or to just to two (2) backside layers.
The invention is not limited to the detailed embodiments
Embodiment 4: Growing a Composite Bond Oxide by Using shown above. It is intended to include those embodiments as
a Thermal Oxidation of a Polysilicon Layer well as further modifications, changes, improvements and
FIGS. 6a–6a show another way of getting a shallow 50
additions that are in the Spirit and Scope of the appended
backside p-type (boron) layer, while providing for a 2.0 um claims.
bond oxide 14. The method includes depositing a polysilicon We claim:
layer 18.1 over the first layer of thin bond oxide 14, and 1. A method for forming a diffused, doped backside layer
oxidizing this to create the additional bond oxide thickneSS in a device wafer that is oxide bonded to a handle wafer
(18.2 and 14) required to make the aggregate 2.0 um thick 55
comprising the Steps of:
oxide. Polysilicon forms a thermal oxide 18.2 (when com
pletely converted to oxide) of twice the original deposited forming a bond oxide on one Surface of one of the wafers,
polysilicon thickness. Although the quality of a thermal forming a diffusing layer over the bond oxide, Said bond
oxide generated from the oxidation of polysilicon is not as Oxide Situated between Said diffusing layer and Said
good as that generated from the oxidation of Single-crystal 60 device wafer;
Silicon, the particulates, bonding, and Surface States should diffusing dopants from the diffusing layer through the
be superior to those in a PECVD deposited oxide. The bond oxide into the backside Surface of the device
oxidation of the polysilicon could also be incorporated as wafer to provide a diffused, doped backside layer in the
part of the drive used to get the p-type (boron) layer into the device wafer;
backside of the device wafer. 65 forming device islands in the opposite Surface of the
Also, the doped polysilicon 18.1 could be a dopant Source device wafer and above the diffused, doped layer on the
for forming the p-type backside layer. For example, doing a backside thereof.
 US 6,362,075 B1
7 8
2. The method of claim 1 wherein the diffused, doped 15. The method of claim 12 further comprising the step of
backside layer is formed by implanting an oxide layer with forming a Silicon layer on the bond oxide and oxidizing the
dopant and diffusing the implanted ions into the backside Silicon layer to increase the thickness of the bond layer.
Surface of the device wafer. 16. The method of claim 12 wherein the implanted
3. The method of claim 1 wherein the bond oxide is dopants partially extend into the backside Surface of the
formed by thermal oxidation and a layer of oxide is depos device wafer.
ited on the bond oxide. 17. The method of claim 12 in which the implant is made
4. The method of claim 1 wherein the diffused, doped into the bond oxide before the deposited oxide is formed on
backside layer is formed by implanting the handle wafer and the bond oxide.
diffusing the dopant through the bond oxide into the device 1O
18. A method for forming a diffused, doped backside layer
wafer.
5. The method of claim 1 wherein the diffused, doped on a device wafer oxide bonded to a handle wafer compris
backside layer is formed by implanting the backside Surface ing the Steps of:
of the device layer, depositing a Semiconductor layer on the forming an oxide layer on the backside Surface of a device
implanted Surface and oxidizing the deposited layer to form 15 wafer;
a bond oxide. implanting a diffusing dopant into the oxide formed on the
6. The method of claim 1 wherein the diffused, doped backside of the device wafer;
backside layer is formed by implanting the backside Surface forming an oxide layer on the Surface of a handle wafer;
of the device layer, epitaxially growing a Semiconductor
layer on the implanted Surface and oxidizing the epitaxial bonding the oxide coated side of the device wafer to the
layer to form a bond oxide. oxide coated side of the handle wafer;
7. The method of claim 1 wherein the diffused, doped diffusing dopant from the oxide into the backside of the
backside layer is formed by implanting the backside Surface device wafer.
of the device layer and oxidizing the backside Surface of the 19. The method of claim 18 wherein the dopant comprises
device wafer to form a bond oxide. 25 boron.
8. A method for forming a diffused, doped backside layer 20. The method of claim 18 wherein the deposited oxide
on a device wafer oxide bonded to a handle wafer compris is formed on the backside of the device wafer by thermal
ing the Steps of oxidation.
forming a dopant layer of a diffusing dopant in a Surface 21. The method of claim 18 further comprising the step of
of a handle wafer; forming a Silicon layer on the bond oxide and oxidizing the
Oxide bonding the doped Surface of the handle wafer to a Silicon layer to increase the thickness of the bond layer.
backside Surface of a device wafer; (FIG. 6).
diffusing dopant from the surface of the handle wafer 22. A method for forming a diffused, doped backside layer
through the bond oxide to the backside surface of the 35
on a device wafer oxide bonded to a handle wafer compris
device wafer. ing the Steps of:
9. The method of claim 8 wherein the dopant comprises forming a thermal bond oxide layer on a backside Surface
boron. of a device wafer;
10. The method of claim 8 wherein the bond oxide is implanting the bond oxide with a diffusing dopant;
partially grown on the handle wafer. 40 diffusing dopant from the bond oxide into the backside
11. The method of claim 8 wherein the bond oxide is fully Surface of the device wafer;
grown on the handle wafer. depositing a Silicon layer on the bond oxide;
12. A method for forming a diffused, doped backside layer
on a device wafer oxide bonded to a handle wafer compris oxidizing the Silicon layer to increase the thickness of the
ing the Steps of 45
bond layer;
forming a thermal bond oxide layer on a backside Surface bonding the device wafer to the handle wafer.
of a device wafer; 23. The method of claim 22 wherein the dopant comprises
boron.
implanting the bond oxide with a diffusing dopant; 24. The method of claim 22 wherein the bond oxide is
diffusing dopant from the bond oxide into the backside grown on the device wafer.
Surface of the device wafer; 50
25. The method of claim 22 wherein the silicon layer is
depositing an oxide layer on the bond oxide; deposited by chemical vapor deposition.
bonding the deposited oxide layer to a handle wafer. 26. The method of claim 22 in which at least Some of the
13. The method of claim 12 wherein the dopant comprises diffusion occurs after the device wafer is bonded to the
boron. 55
handle wafer.
14. The method of claim 12 wherein the deposited oxide
is deposited by plasma enhanced chemical vapor deposition.