A4987

DMOS Dual Full-Bridge PWM Motor Driver

with Overcurrent Protection

FEATURES AND BENEFITS DESCRIPTION

▪ Low RDS(ON) outputs The A4987 is a dual DMOS full-bridge stepper motor driver
▪ Internal mixed current decay mode with parallel input communication and overcurrent protection.
▪ Synchronous rectification for low power dissipation Each full-bridge output is rated up to 35 V and ±1 A. The A4987
▪ Internal UVLO includes fixed off-time pulse width modulation (PWM) current
▪ Crossover-current protection regulators, along with 2- bit nonlinear DACs (digital-to-analog
▪ 3.3 and 5 V compatible logic supply converters) that allow stepper motors to be controlled in full,
▪ Thin profile QFN and TSSOP packages half, and quarter steps. The PWM current regulator uses the
▪ Thermal shutdown circuitry Allegro™ patented mixed decay mode for reduced audible
▪ Short-to-ground protection motor noise, increased step accuracy, and reduced power
▪ Shorted load protection dissipation.
▪ Low current Sleep mode, < 10 µA
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
PACKAGES:
The outputs are protected from shorted load and short-to-
24-contact QFN ground events, which protect the driver and associated circuitry
Approximate
4 mm × 4 mm × 0.75 mm from thermal damage or flare-ups. Other protection features
footprint
(ES package) include thermal shutdown with hysteresis, undervoltage lockout
(UVLO) and crossover current protection. Special power-up
sequencing is not required.

24-pin TSSOP The A4987 is supplied in two packages, a 24-contact QFN (ES)
with exposed thermal pad and a 24-pin TSSOP (LP). Both packages have exposed thermal
(LP Package) pads for enhanced thermal performance. The 24-contact ES is
4 mm × 4 mm, with a nominal overall package height of 0.75
mm. The 24-pin LP is a TSSOP with 0.65 pitch and an overall
package height of ≤1.2 mm. Both packages are lead (Pb) free,
with 100% matte tin leadframe plating.

Typical Application Diagram

VDD 0.1 µF 0.1 µF

0.22 µF

VREG ROSC CP1 CP2 VCP VBB1

0.22 µF
VDD 100 µF
VBB2

Microcontroller or OUT1A
Controller Logic SLEEP
A4987 OUT1B
IN01
SENSE1
IN02
PH1
IN11
OUT2A
IN12
PH2 OUT2B
SENSE2
VREF GND GND

4987-DS, Rev. 7 April 30, 2021

MCO-0000821
 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Selection Guide
Part Number Package Packing
A4987SESTR-T 24-pin QFN with exposed thermal pad 1500 pieces per 7-in. reel
A4987SLPTR-T 24-pin TSSOP with exposed thermal pad 4000 pieces per 13-in. reel

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 35 V
Output Current IOUT ±1 A
Logic Input Voltage VIN –0.3 to 5.5 V
Logic Supply Voltage VDD –0.3 to 5.5 V
Motor Outputs Voltage –2.0 to 37 V
Sense Voltage VSENSE –0.5 to 0.5 V
Reference Voltage VREF 5.5 V
Operating Ambient Temperature TA Range S –20 to 85 ºC
Maximum Junction TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC

2
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Functional Block Diagram

0.1 µF

Rosc

VCP
CP1

CP2
CHARGE PUMP 0.1 µF
VREG REGULATOR
OSC
0.22 µF
DMOS FULL-BRIDGE 1
To
VBB1
VBB2
Sense2
-

OCP
DAC
+

OUT1A

OSC PWM Latch

VREF BLANKING OUT1B
Mixed Decay

VDD

IN01 GATE
DRIVE SENSE1
IN02

PH1
CONTROL DMOS FULL-BRIDGE 2
LOGIC
IN11 VBB2

IN12

PH2

SLEEP
OCP OUT2A

OUT2B
PWM Latch OSC VCP VREG VREG
BLANKING
Mixed Decay

VREF
DAC
+

REF VREF
Sense2
-

Sense2 SENSE2
GND

GND

3
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

ELECTRICAL CHARACTERISTICS1 at TA = 25°C, VBB = 35 V (unless otherwise noted)

Characteristics Symbol Test Conditions Min. Typ.2 Max. Units
Output Drivers
Operating 8 – 35 V
Load Supply Voltage Range VBB
During Sleep Mode 0 – 35 V
Logic Supply Voltage Range VDD Operating 3.0 – 5.5 V
Source Driver, IOUT = –800 mA – 700 900 mΩ
Output On Resistance RDS(ON)
Sink Driver, IOUT = 800 mA – 700 900 mΩ
Source Diode, IF = –800 mA – – 1.3 V
Body Diode Forward Voltage VF
Sink Diode, IF = 800 mA – – 1.3 V
fPWM < 50 kHz – – 4 mA
Motor Supply Current IBB Operating, outputs disabled – – 2 mA
Sleep Mode – – 10 μA
fPWM < 50 kHz – – 8 mA
Logic Supply Current IDD Outputs off – – 5 mA
Sleep Mode – – 10 μA
Control Logic
VIN(1) VDD×0.7 – – V
Logic Input Voltage
VIN(0) – – VDD×0.3 V
IIN(1) VIN = VDD×0.7 –20 <1.0 20 µA
Logic Input Current
IIN(0) VIN = VDD×0.3 –20 <1.0 20 µA
RIN02 – 100 – kΩ
Logic Input Pull-down
RIN12 – 50 – kΩ
Logic Input Hysteresis VHYS(IN) As a % of VDD 5 11 19 %
Blank Time tBLANK 0.7 1 1.3 μs
OSC = VDD or GND 20 30 40 μs
Fixed Off-Time tOFF
ROSC = 25 kΩ 23 30 37 μs
Reference Input Voltage Range VREF 0 – 4 V
Reference Input Current IREF –3 0 3 μA
VREF = 2 V, %ITripMAX = 33.3% – – ±15 %
Current Trip-Level Error3 errI VREF = 2 V, %ITripMAX = 66.7% – – ±5 %
VREF = 2 V, %ITripMAX = 100.00% – – ±5 %
Crossover Dead Time tDT 100 475 800 ns
Protection
Overcurrent Protection Threshold4 IOCPST 1.1 – – A
Thermal Shutdown Temperature TTSD – 165 – °C
Thermal Shutdown Hysteresis TTSDHYS – 15 – °C
VDD Undervoltage Lockout VDDUVLO VDD rising 2.7 2.8 2.9 V
VDD Undervoltage Hysteresis VDDUVLOHYS – 90 – mV
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Typical data are for initial design estimations only and assume optimum manufacturing and application conditions. Performance may vary for individual
units, within the specified maximum and minimum limits.
3V
ERR = [(VREF/8) – VSENSE] / (VREF/8).
4Overcurrent protection (OCP) is tested at T = 25°C in a restricted range and guaranteed by characterization.
A

4
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

THERMAL CHARACTERISTICS may require derating at maximum conditions

Characteristic Symbol Test Conditions* Value Units
ES package; estimated, on 4-layer PCB, based on JEDEC standard 37 ºC/W
Package Thermal Resistance RθJA
LP package; on 4-layer PCB, based on JEDEC standard 28 ºC/W

*In still air. Additional thermal information available on Allegro Web site.

Maximum Power Dissipation, PD(max)

5.5

5.0

4.5

4.0

3.5 (R
Power Dissipation, PD (W)

θJ
A =
3.0 28
ºC
(R /W
2.5 θJ
)
A =
37
ºC
2.0 /W
)
1.5

1.0

0.5

0.0
20 40 60 80 100 120 140 160 180
Temperature (°C)

5
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Functional Description

Device Operation. The A4987 is designed to operate one DMOS FETs remain off. The off-time, tOFF, is determined by the
stepper motor in full, half, or quarter step mode. The currents in ROSC terminal. The ROSC terminal has two settings:
each of the output full-bridges, all N-channel DMOS, are regu- ▪ ROSC tied to VDD or ground — off-time internally set to 30 µs
lated with fixed off-time pulse width modulated (PWM) control ▪ ROSC through a resistor to ground — off-time is determined by
circuitry. Each full-bridge peak current is set by the value of the following formula:
an external current sense resistor, RSx , and a reference voltage, tOFF ≈ ROSC ⁄  825
VREFx .
Percentages of the peak current are set using a 2-bit nonlinear Blanking. This function blanks the output of the current sense
DAC that programs 33%, 66%, or 100% of the peak current, or comparators when the outputs are switched by the internal current
disables the outputs. control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
Internal PWM Current Control. Each full-bridge is con- clamp diodes, and switching transients related to the capacitance
trolled by a fixed off-time PWM current control circuit that limits of the load. The blank time, tBLANK (µs), is approximately
the load current to a desired value, ITRIP . Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows tBLANK ≈ 1 µs
through the motor winding and the current sense resistor, RSx.
When the voltage across RSx equals the DAC output voltage, the Shorted-Load and Short-to-Ground Protection.
current sense comparator resets the PWM latch. The latch then If the motor leads are shorted together, or if one of the leads is
turns off the appropriate source driver and initiates a fixed off shorted to ground, the driver will protect itself by sensing the
time decay mode. overcurrent event and disabling the driver that is shorted, protect-
The maximum value of current limiting is set by the selection of ing the device from damage. In the case of a short-to-ground, the
¯ Ē
device will remain disabled (latched) until the S̄ L̄ ¯ Ē
¯ P̄¯ input goes
RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting, high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 1.
ITripMAX (A), which is set by
When the two outputs are shorted together, the current path is
ITripMAX = VREF / ( 8 × RS) through the sense resistor. After the blanking time (≈1 µs) expires,
the sense resistor voltage is exceeding its trip value, due to the
where RS is the resistance of the sense resistor (Ω) and VREF is overcurrent condition that exists. This causes the driver to go into
the input voltage on the REF pin (V). a fixed off-time cycle. After the fixed off-time expires the driver
The 2-bit DAC output reduces the VREF output to the current turns on again and the process repeats. In this condition the driver
sense comparator in precise steps, such that is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
Itrip = (%ITripMAX / 100) × ITripMAX This condition is shown in figure 2.

It is critical that the maximum rating (0.5 V) on the SENSE1 and During a shorted load event it is normal to observe both a posi-
SENSE2 pins is not exceeded. tive and negative current spike as shown in figure 3, due to the
direction change implemented by the Mixed decay feature. This
Fixed Off-Time. The internal PWM current control circuitry is shown in figure 3. In both instances the overcurrent circuitry is
uses a one-shot circuit to control the duration of time that the protecting the driver and prevents damage to the device.

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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Charge Pump (CP1 and CP2). The charge pump is used to

generate a gate supply greater than that of VBB for driving the 5 A / div.
source-side FET gates. A 0.1 µF ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 µF ceramic
capacitor is required between VCP and VBB, to act as a reservoir
for operating the high‑side FET gates.
Fault latched
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
VREG (VREG). This internally generated voltage is used to
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled t→
with a 0.22 µF ceramic capacitor to ground. VREG is internally Figure 1. Short-to-ground event
monitored. In the case of a fault condition, the FET outputs of the
A4987 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications. 5 A / div.
Shutdown. In the event of a fault, overtemperature (excess TJ) Fixed off-time
or an undervoltage (on VCP), the FET outputs of the A4987 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.

Sleep Mode ( S̄¯L̄¯Ē¯Ē¯P̄¯ ). To minimize power consumption

when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator, and
¯ Ē
charge pump. A logic low on the S̄ L̄ ¯ Ē
¯ P̄¯ pin puts the A4987 into t→
Sleep mode. When emerging from Sleep mode, in order to allow Figure 2. Shorted load (OUTxA → OUTxB) in
the charge pump to stabilize, provide a delay of 1 ms before issu- Slow decay mode
ing a logic command.

Mixed Decay Operation. The bridge operates in Mixed

Decay mode, as shown in figures 5 through 7. As the trip point 5 A / div.
is reached, the A4987 initially goes into a fast decay mode for
31.25% of the off-time, tOFF. After that, it switches to Slow Decay Fixed off-time
mode for the remainder of tOFF. A timing diagram for this feature
appears in figure 4.

Synchronous Rectification. When a PWM-off cycle is

triggered by an internal fixed-off time cycle, load current recir-
culates in Mixed Decay mode. This synchronous rectification Fast decay portion
feature turns on the appropriate FETs during current decay, and (direction change)
effectively shorts out the body diodes with the low FET RDS(ON).
This reduces power dissipation significantly and can eliminate the t→
need for external Schottky diodes in many applications. Synchro- Figure 3. Shorted load (OUTxA → OUTxB) in Mixed decay mode
nous rectification turns off when the load current approaches zero
(0 A), preventing reversal of the load current.
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

PHx
IN0x
IN1x

100.00

70.71

See Enlargement A

IOUT 0

–70.71

–100.00

Enlargement A

toff

tFD tSD
IPEAK
Slow Decay

Mixed Decay
IOUT

Fa
st
De
ca
y

Symbol Characteristic
toff Device fixed off-time
IPEAK Maximum output current
tSD Slow decay interval
tFD Fast decay interval
IOUT Device output current

Figure 4. Current Decay Modes Timing Chart

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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Application Layout

Layout. The printed circuit board should use a heavy ground- The two input capacitors should be placed in parallel, and as
plane. For optimum electrical and thermal performance, the close to the device supply pins as possible. The ceramic capaci-
A4987 must be soldered directly onto the board. On the under- tor (CIN1) should be closer to the pins than the bulk capacitor
side of the A4987 package is an exposed pad, which provides a (CIN2). This is necessary because the ceramic capacitor will be
path for enhanced thermal dissipation. The thermal pad should be responsible for delivering the high frequency current components.
soldered directly to an exposed surface on the PCB. Thermal vias The sense resistors, RSx , should have a very low impedance
are used to transfer heat to other layers of the PCB. path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point sense comparators. Long ground traces will cause additional
ground, known as a star ground, located very close to the device. voltage drops, adversely affecting the ability of the comparators
By making the connection between the pad and the ground plane to accurately measure the current in the windings. The SENSEx
directly under the A4987, that area becomes an ideal location for pins have very short traces to the RSx resistors and very thick,
a star ground point. A low impedance ground will prevent ground low impedance traces directly to the star ground underneath the
bounce during high current operation and ensure that the supply device. If possible, there should be no other components on the
voltage remains stable at the input terminal. sense circuits.

Solder
A4987
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
OUT2B OUT2A OUT1A OUT1B
Thermal Vias

GND
OUT2B OUT2A OUT1A OUT1B

R4 R5 R4 R5

GND C7
OUT2A
OUT1A
VBB2
SENSE2

SENSE1
VBB1

U1 OUT2B OUT1B
C7
PH2 PH1
PAD
GND GND
C3 CP1 REF
C1 GND

C6
CP2 A4987 IN01

C3 VCP VDD
C4
SLEEP
ROSC
VREG

C4 C1
IN02
IN12

BULK
IN11

ROSC
GND C2

CAPACITANCE
C6 C2
ROSC
VDD VBB

VDD VBB
ES package configuration shown

9
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

OUT2B

C3 C6
GND
U1
A4987 GND
C4 GND CP1
GND C3
CP2 PH2
OUT2A OUT2B
C5 R4 VCP
C4 VBB2
PAD C6
ROSC R5 VREG SENSE2
C5
OUT1A INO2 OUT2A
R4
C1 IN12
GND OUT1A
IN11
SENSE1
ROSC R5
ROSC VBB1
OUT1B SLEEP
OUT1B
VDD
GND GND GND C1 IN01 PH1
BULK
GND REF GND C2
CAPACITANCE
C2 VDD VBB
VDD VBB

LP package typical application and circuit layout

10
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Pin Circuit Diagrams

VDD VBB VBB VCP CP1 CP2

8V 40 V

GND GND GND

PGND GND
8V

GND GND GND

IN01
IN02
VBB IN11 VBB
VREG SENSE VREG IN12 OUT
PH1 DMOS
PH2 Parasitic
DMOS VREF 8V
10 V DMOS
Parasitic ROSC Parasitic
SLEEP
GND GND GND GND GND

11
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Step Sequencing Diagrams

100.0 100.0

66.7
66.7

Phase 1 Phase 1
0 0
(%) (%)

–66.7
–66.7

–100.0 –100.0

100.0 100.0

66.7
66.7

Phase 2 Phase 2
0 0
(%) (%)

–66.7
–66.7

–100.0 –100.0

Full step 2 phase Half step 2 phase

Modified full step 2 phase Modified half step 2 phase

Figure 5. Step Sequencing for Full-Step Increments. Figure 6. Step Sequencing for Half-Step Increments.

12
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

100.0

66.7

33.3

Phase 1
0
(%)

–33.3

–66.7

–100.0

100.0

66.7

33.3

Phase 2 0
(%)

–33.3

–66.7

–100.0

Figure 7. Step Sequence for Quarter-Step Increments

Step Sequencing Settings

Phase 1 Phase 2
Full 1/2 1/4 I01 I11 PHASE I02 I12 PHASE
(%ITripMax) (%ITripMax)
1 1 0 H H x 100 L L 1
2 33 L H 1 100 L L 1
1 2 3 100/66* L/H* L 1 100/66* L/H* L 1
4 100 L L 1 33 L H 1
3 5 100 L L 1 0 H H X
6 100 L L 1 33 L H 0
2 4 7 100/66* L/H* L 1 100/66* L/H* L 0
8 33 L H 1 100 L L 0
5 9 0 H H x 100 L L 0
10 33 L H 0 100 L L 0
3 6 11 100/66* L/H* L 0 100/66* L/H* L 0
12 100 L L 0 33 L H 0
7 13 100 L L 0 0 H H X
14 100 L L 0 33 L H 1
4 8 15 100/66* L/H* L 0 100/66* L/H* L 1
16 33 L H 0 100 L L 1
* Denotes modified step mode

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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Pinout Diagrams
ES Package LP Package

23 SENSE2

20 SENSE1
22 OUT2A
21 OUT1A
24 VBB2

19 VBB1
CP1 1 24 GND
CP2 2 23 PH2
VCP 3 22 OUT2B
OUT2B 1 18 OUT1B VREG 4 21 VBB2
PH2 2 17 PH1 IN02 5 20 SENSE2
GND 3 16 GND IN12 6 PAD 19 OUT2A
PAD
CP1 4 15 REF IN11 7 18 OUT1A
CP2 5 14 IN01 ROSC 8 17 SENSE1

VCP 6 13 VDD SLEEP 9 16 VBB1

VDD 10 15 OUT1B
IN01 11 14 PH1
IN11 10

SLEEP 12
ROSC 11
7
8
9

REF 12 13 GND
VREG
IN02
IN12

Terminal List Table

Number
Name Description
ES LP
CP1 4 1 Charge pump capacitor terminal
CP2 5 2 Charge pump capacitor terminal
PH1 17 14 Logic input
PH2 2 23 Logic input
GND 3, 16 13, 24 Ground*
IN02 8 5 Logic input
IN12 9 6 Logic input
NC – – No connection
OUT1A 21 18 DMOS Full Bridge 1 Output A
OUT1B 18 15 DMOS Full Bridge 1 Output B
OUT2A 22 19 DMOS Full Bridge 2 Output A
OUT2B 1 22 DMOS Full Bridge 2 Output B
REF 15 12 Gm reference voltage input
IN11 10 7 Logic input
ROSC 11 8 Timing set
SENSE1 20 17 Sense resistor terminal for Bridge 1
SENSE2 23 20 Sense resistor terminal for Bridge 2
¯L̄¯Ē
S̄ ¯Ē¯P̄
¯ 12 9 Logic input
IN01 14 11 Logic input
VBB1 19 16 Load supply
VBB2 24 21 Load supply
VCP 6 3 Reservoir capacitor terminal
VDD 13 10 Logic supply
VREG 7 4 Regulator decoupling terminal
PAD – – Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.

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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

ES Package, 24-Pin QFN with Exposed Thermal Pad

For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000222 Rev. 2 or JEDEC MO-220WGGD.)
Dimensions in millimeters – NOT TO SCALE.
Exact case and lead configuration at supplier discretion within limits shown.

4.00 ±0.15 0.30 0.50

24
24
0.95
1
A 1
2
2

4.00 ±0.15 2.70 4.10

2.70
25× D C
4.10
0.08 C 0.75 ±0.05
SEATING
PLANE C PCB Layout Reference View
+0.05
0.25 +0.03
–0.07 0.02 –0.02
0.50 BSC
1
XXXX
Date Code
0.40 ±0.10 Lot Number

B
+0.10
2.70 Standard Branding Reference View
–0.15 E
2 Lines 1, 2, 3 = 6 characters
1
Line 1: Part Number
24 Line 2: 4 digit Date Code
+0.10 Line 3: Characters 5, 6, 7, 8 of
2.70
–0.15 Assembly Lot Number

Pin 1 Dot top left

A Terminal #1 mark area Center align
B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion).
C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M);
all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet
application process requirements and PCB layout tolerances; when mounting on a
multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals

E Branding scale and appearance at supplier discretion.

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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

LP Package, 24-Pin TSSOP with Exposed Thermal Pad

0.65
7.80 ±0.10 0.45
4° ±4
24
+0.05
0.15 –0.06

B
3.00±0.05 4.40 ±0.10 6.40 ±0.20 0.60 ±0.15 3.00 6.10

A (1.00)

1 2
4.32±0.05
0.25
1.65
4.32
24X C SEATING PLANE
SEATING
0.10 C PLANE C PCB Layout Reference View
GAUGE PLANE

+0.05
0.25 –0.06 0.65
1.20 MAX For reference only
0.15 MAX (reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)

16
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 DMOS Dual Full-Bridge PWM Motor Driver
A4987 with Overcurrent Protection

Revision History
Number Date Description
5 March 21, 2012 Update Step Sequence and example layout
6 April 3, 2020 Minor editorial updates
7 April 30, 2021 Updated Package Outline Drawing (page 15)

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