MAHA BARATHI ENGINEERING COLLEGE

NH-79, SALEM-CHENNAI HIGHWAY, A.VASUDEVANUR, CHINNASALEM (TK), KALLAKURICHI (DT) 606 201.
Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai
Accredited by NAAC and Recognized under section 2(f) & 12(B) status of UGC, New Delhi

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Department of Electronics and Communication Engineering

Year/Semester: III/V
EC 3552 – VLSI AND CHIP DESIGN
FOR G2
UNIT 1 MOS TRANSISTOR PRINCIPLE
PART A
1 How does MOSFET acts as switch? Nov/Dec-23
2 Realize the 2:1 multiplexer using transmission gates. Nov/Dec-23
3 What is threshold voltage of MOS transistor? Apr/May-24
4 Show how nMOSFET acts as a switch? Apr/May-24
5 Justify CMOS is the best technology for and digital system. Nov/Dec-21
6 Compare PMOS and NMOS. Nov/Dec-20
7 State the need of scaling. Nov/Dec-20
Apr/May-21
8 Define body bias effect.
Nov/Dec-20
9 State length modulation. Write down the equation for NMOS. Nov/Dec-21
10 Why NMOS device conducts strong zero and weak one? Nov/Dec-18
11 Define threshold voltage of MOSFET. Apr/May-19
12 What is velocity saturation effect? Apr/May-18
13 List the scaling principles. Apr/May-18
By what factor gate capacitance must be scaled if constant electric field scaling is
14 Apr/May-19
Employed?
15 Define Low noise margin and high noise margin of a CMOS inverter? Nov/Dec-21
16 List the sources of Power dissipation in CMOS circuits. Nov/Dec-21
Apr/May-21/
17 Sketch a complementary CMOS gate computing Y= (AB+BC)2.
Nov/Dec-20
PART B&C
Obtain the first order model relating the current and voltage (I-V) for an nMOS transistor
1 Nov/Dec-23
in three regions of operation.
Discuss the velocity saturation and mobility degradation of an nMOS transistor and under non ideal I-
2 Nov/Dec-23
V effects
3 Elucidate the dynamic behavior of MOSFET and discuss each of the component. Nov/Dec-23
Realize the sum of minterms F=∑m(0,1,7,11,15)+∑d(2,3,5) using static CMOS logic and
4 Nov/Dec-23
Clocked CMOS logic
Derive the expression for current in cut off, linear and saturation region in long channel
5 Nov/Dec-21
I-V characteristics.
6 Draw and explain the equivalent RC circuit for an inverter. Nov/Dec-21
7 Describe how dynamic voltage scaling can reduce dynamic power dissipation. Nov/Dec-21
8 Derive an expression for Ids of nMOS in linear and saturated region.(6) Apr/May-19
9 Derive an expression for Ids and gm in the linear and in the saturated region. Nov/Dec-20
 Draw a CMOS inverter. Analyze the switching characteristics during rise time when Vin
10 Apr/May-19
Changes from high to low. (7)
11 Draw the small signal model of device during cut off, saturation region.(5) Nov/Dec-18
12 Explain the dynamic behavior of MOSFET transistor with neat diagram.(6) Apr/May-18

List out the goals of CMOS technology scaling. Explain how common electric field scaling is superior
13 Nov/Dec-18
than constant voltage scaling (7)

Explain the need of scaling, scaling principles, its limits and fundamental units of CMOS Nov/Dec-17
14
Inverter. Apr/May -17
Derive an expression to show the drain current of MOS for various operating regions.
15 Nov/Dec-18
Explain one non-ideality for each operating region that changes the drain current.
UNIT 2 COMBINATIONAL LOGIC CIRCUITS
PART A
1 Draw the stick diagram for 2 input NAND gate. Nov/Dec-23
2 What are the disadvantages of pass transistor logic? Nov/Dec-23
3 What is stick diagram? Draw the stick diagram for two input NAND gates. Apr/May-24
4 Realize the two input NAND gate using Pass transistor logic. Apr/May-24
5 How does a transmission gate produce fully restored logic output? Nov/Dec-21
6 Define propagation delay of a CMOS inverter. Nov/Dec-21
7 State the operations performed during the pre-charge & evaluate phase of dynamic circuits. Nov/Dec-21
8 Realize O1=AB(C+D), O2=B(C+D)and O3= C+D using multiple output domino stages. Nov/Dec-18
9 Draw a 2 input XOR using nMOS pass transistor logic. Apr/May-19
10 Draw the circuit of XOR using transmission gate. Nov/Dec-20
11 What is the use of transmission gates. Apr/May-21
Determine the discharging time of the circuit shown in figure 1 when switch A is closed. Nov/Dec-18
12
Assume CL and internal capacitances C1 and C2 are charged initially. Let CL=C1=C2=C
13 Mention some of the techniques to minimize power dissipation. Nov/Dec-20
PART B&C
1 i).Find the Elmore’s constant of the 4 input NAND Gate. (7)
Apr/May-24
ii).Realize the 4:2 encoder using CMOS logic. (6)
i).Explain the concept of dynamic logic. Realize the3-input NAND gate using Dynamic Logic. (7)
Apr/May-24
2 ii). Describe the disadvantages of dynamic logic. Provide the solution to overcome the
dynamic.
3 logic.((6)
Realize the function of F=∑m(1,5,6,7)using i)Pseudo nMOS logic ii)Static CMOS logic.(8) Apr/May-24
i).Realize the AND gate using pass transistor logic and explain the operation circuit (6)
Nov/Dec-23
4 ii). Discuss the disadvantages of dynamic logic gates. Provide the solution to overcome the
disadvantages.(7)
i)Find the Elmore’s constant for 4-input NAND gate. (6)
5ii What are the types of power dissipation in CMOS circuits? Find the total power dissipation and discuss
Nov/Dec-23
the low power design principles. (7)

Realize the sum of minterms F=∑m(0,1,7,11,15) + ∑d(2,3,5) using i) Static CMOS logic and ii)
6 Nov/Dec-23
Clocked CMOS logic.
7 Draw and explain the equivalent RC circuit for an inverter. Nov/Dec-21
8 Discuss in detail with a neat layout, the design rules for a CMOS inverter. Nov/Dec-21
Compare the circuit implementation of 2-input multiplexer using static CMOS domino and
9 Nov/Dec-21
dual-rail domino logic.
 Apr/May-21
10 Differentiate Static and Dynamic Latches and Registers.
Nov/Dec-20
Sketch a combinational function Y=(A(B+C+D)+E.F.G) 2 using i. Pseudo nMOS logic ii) Apr/May 21
11
Domino Logic iii) Cascode voltage switch logic Nov/Dec-20
Explain the pass transistor logic and show how complementary pass transistor logic are applied for
Apr/May-21
12
2:1 multiplexer. Nov/Dec-20
Draw the circuit of NOR gate using NMOS and using static CMOS logic. Also draw the
13 Nov/Dec-20
corresponding stick diagram.
i).Realize the following Boolean function Z= (A+BC)D+E using static CMOS logic. (6)
14 ii). Realize the 4:1 multiplexer using 2:1 multiplexer. Draw the realization using transmission Nov/Dec-20
gate. (7)
15 Define power dissipation. State the different types of power dissipation. Nov/Dec-20
Realize a 2-input XOR using static CMOS, transmission gate and dynamic CMOS logic.
16 Apr/May-19
Analyze the hardware complexity.
17 Derive an expression for the rise time, fall time and the propagation delay of a CMOS inverter. Nov/Dec-20
i). Differentiate static and dynamic power in CMOS circuits. (7) Apr/May-21
18
ii). Sketch the 4:1 multiplexer using transmission gates. (8) Nov/Dec-20
UNIT 3 SEQUENTIAL CIRCUITS AND CLOCKING STRATEGIES
PART A
Apr/May-24
1 Differentiate latches and registers. Nov/Dec-23
Apr/May 18
Apr/May-24
Nov/Dec-21
2 What is clock skew? How to overcome it?
Apr/May-19
Apr/May 18
3 What are the timing classifications of digital system? Nov/Dec-23
4 What is meant by bistability? Nov/Dec-21
Nov/Dec-20
5 List the timing classification of digital system.
Apr/May-21
Nov/Dec-20
6 Differentiate latches and flipflops.
Apr/May-21
List out the advantage of C2MOS logic based register over pass transistor logic based master
7 Nov/Dec-18
slave register.
Nov/Dec-21
8 What is meant by pipelining? Apr/May -17
Nov/Dec-16
9 Draw the schematic of dynamic edge triggered register Nov/Dec-21
10 Compare and contrast synchronous design and asynchronous design. Apr/May-17
PART B&C
i). Explain the multiplexer based latches and master slave edge triggered register. (7)
1 Nov/Dec-23
ii).Describe the true single phase clock register. (6)
i). Illustrate the combined effect of skew and jitter in sequential logic circuit and find the time
2 period of the clock. (7) Nov/Dec-23
ii).Design the sequential logic circuit based on self-timed approach. (6)
i). Apply the concept of 3-stage pipelining to log (|a n +bn|) and find the number clock period Nov/Dec-23
3
for n=3 to get the output. (7) Apr/May-24
4 Elucidate the static latches and registers suitable for sequential logic circuit design. Apr/May-24
 i).Draw the monostable multivibrator using CMOS transistor and explain the operation. (7)
5 ii).What are the timing classification of digital system? Show how the timing is applied for Apr/May-24
synchronous system. (6)
6 Explain the circuit and working of CMOS implementation of Schmitt trigger. Nov/Dec-21
7 Disscuss the timing parameters and characterize the timing of sequential circuit. Nov/Dec-21
i). Illustrate the circuit designs for basic latches,then build the flip flops and pulsed latches.(7) Nov/Dec-20
8
ii).Design the pulse registers suitable for sequential CMOS circuits. (6) Apr/May-21
Design a D-Latch using transmission gate. Using which realize a two phase non-overlapping master-
Apr/May-19
9
slave negative edge triggered flip flop. Nov/Dec-20
Nov/Dec-21
10 Explain the operation of Master-Slave based edge triggered register.
May/Jun-16
Discuss about CMOS register concept and design master slave triggered register, explain its
11 Apr/May-18
operation with overlapping periods.
12 Discuss in detail various pipelining approaches to optimize sequential circuits. Nov/Dec-21
i).Design a clock distribution network based on H tree model for 16 nodes (7)
13 ii).Design a 4 input NAND gate and obtain its delay during the transistor from high to low (8) Nov/Dec-21

UNIT 4 INTERCONNECT, MEMORY ARCHITECTURE, AND ARITHMETIC

CIRCUITS
PART A
1 List the various interconnect parameters analyzed in VLSI chip design Nov/Dec-23
2 What is the significance of FPGA. Nov/Dec-23

3 Find the propagation delay of n-bit carry select adder. Apr/May-24

4 Write the logic equation for 3 bit Magnitude Comparator. Apr/May-24
The circuit following, shows a carry propagation path in an adder circuit. Let X,Y,C i are the
5 inputs to adder circuit and is the clock signal Փ. Write the logic expressions for the signal Nov/Dec-21
X,Y to generate output carry.
Nov/Dec-21
6 Draw a 4 bit ripple carry adder and find its critical path delay.
Nov/Dec-18
Apr/May-21
7 Draw the dot diagram of Wallace tree multiplier.
Nov/Dec-20
Nov/Dec 20
8 List the categories of memory arrays.
Apr/May-21
9 Compare DRAM and SRAM. Nov/Dec-20
10 Define propagate, generate and kill terms of an adder. Nov/Dec-20
Apr/May-19
11 State the merits of barrel shifter. Nov/Dec-20
12 Draw the circuit diagram of a 1-bit binary shifter using MOS transistor. Nov/Dec-21
13 State the need for a sense amplifier in a memory cell. Nov/Dec-21
14 Draw a 1-transistor Dynamic Ram cell Apr/May-19
15 State Radix-2 booth encoding table Apr/May-19
16 Write the full adder output in terms of propagate and generate. Apr/May-18
17 Draw the structure of 4x4 barrel shifter. Apr/May-18

PART B&C
 i). Write the design techniques in dealing with capacitive cross talk. (6)
1 ii). Describe the design techniques available to the designer to address the voltage drop over Nov/Dec-23
the inductor problem. (7)

2 i).Realize the combinational function with PLA. Y1=∑m(2,3,4,6) Y2=∑m (1,2,3,4) (7) Nov/Dec-23
ii).Elucidate the basic architecture of FPGA. (6)
3 Design a 4-bit binary to excess 3 code converter using ROM. (8) Nov/Dec-23
i).What is the need for carry save adder? Explain the 4-bit carry save adder (6)
4 Apr/May-24
ii).What is an array multiplier? Show how array multiplier uses an array of cells for
computing the result. (7)
5 Illustrate the hierarchical memory architecture and explain the building blocks of memory Apr/May-24
architecture
i). Generate the test vectors for the combinational function F= (AB+BC+CD) using automatic
6 test pattern generation for the stuck at 0 fault at node B. (8) Apr/May-24
ii). Realize the functions F1= X0X1+ X '1 X '2 ;F2= X '0 X '1 +X1X2 using programmable logic array.
(7)
7 i).Explain the concept of carry look ahead adder with neat diagram. (7) Nov/Dec-21
ii). Discuss the details about speed and area trade off (6)
8 Explain the concept of modified Booth multiplier with a suitable example. Nov/Dec-21
i). Explain the carry-Propagate adder and show how the generation and propagation signals
Nov/Dec-20
9 are framed. (6)
Apr/May-21
ii).List the several commonly used shifters. Design the shifter that can perform all the
commonly used shifters (7)
10 Illustrate the building blocks of memory architecture and peripheral circuitry adapted to Nov/Dec-20
operate for non-volatile memory. Apr/May-20
11 Draw the circuit of 6-transistor SRAM cell using NMOS.Explain the read and write operation. Nov/Dec-20
12 State radix-2 booth encoding. Apply radix-2 booth encoding to perform multiplication
Nov/Dec- 20
operation between (-4) and (3). Assume it is a 4 bit multiplier
13 Derive the necessary expressions of a 4 bit carry look ahead adder and realize the carry out
Apr/May-19
expressions using CMOS logic.
14 Design a 4-bit unsigned array multiplier and analyze its hardware complexity. Apr/May-19
Apr/May-18
15 Explain the concept of carry look ahead adder and discuss its types.
Apr/May-17
16 Design an 8-bit Brent-Kung adder. Nov/Dec-18
Nov/Dec-18
17 Construct 4x4 array type multiplier and find its delay.
May/Jun-16
18 Design 4 input and 4 output barrel shift adder using NMOS logic. (5) Nov/Dec-18
19 Design a multiplier for 5 bit by 3 bit. Explain its operation and summarize the number of
adders. Discuss it over Wallace multiplier. Apr/May-18

20 With a neat diagram, describe the architecture of 4x4 unsigned array multiplier. Nov/Dec-20
UNIT 5 ASIC DESIGN AND TESTING
PART A
1 Differentiate FPGA design and ASIC design flow. Nov/Dec-23
2 Write the test bench in Verilog HDL to test the D-flip flop. Nov/Dec-23
3 List the issues in testing microchip design process. Apr/May-24
4 What are the different types of ASIC’s? Apr/May-24
5 Name the elements in a configuration logic block. Apr/May-17
6 Mention the common techniques involved in ad hoc testing?
7 What is known as IDDQ testing?
8 What are the scan based test techniques?
9 What is the purpose of thermal oxidation or deposition in the wafer fabrication process?
10 What is the key step in the masking process during wafer fabrication?
11 What is the purpose of etching in the wafer fabrication process?
12 What is the significance of dielectric deposition and metallization in the fabrication process?
13 What are the characteristics of embedded cores in chip design?
14 What are the characteristics of embedded cores in microchip design?
15 What are some benefits of using embedded cores in chip design?
16 What is SOC?
17 What is ATPG?
18 What is BIST?
PART B&C
1 i). Illustrate the microchip design process and identify the issues in test. (7)
ii). What are common fault models in CMOS design? With a suitable diagram enlighten the Nov/Dec-23
causes of faults. (6)
2 i). Explain the automatic test pattern generation with a suitable example. (7)
Nov/Dec-23
ii). Describe the boundary scan with necessary diagrams. (6)
3 i). What are the faults in ASIC design? Model the faults in ASIC design. (7)
Apr/May-24
ii).Explain the design flow process suitable for ASIC.(6)
4 i). Write the test bench in Verilog HDL for a combinational circuit. (6)
Apr/May-24
ii).Explain the test interface and boundary scan suitable for scan design. (7)
5 Explain the N-Well process for CMOS fabrication, discussing the steps involved and the
advantages of using this process in creating CMOS integrated circuits.
6 Explain the P-Well process for CMOS fabrication, discussing the steps involved and the
advantages of using this process in creating CMOS integrated circuits.
7 Explain the twin-tub CMOS fabrication process, discussing its advantages, challenges, and the
applications for which well suited.
8 Explain the Silicon-on-Insulator (SOI) process, explaining its advantages, limitations, and the
unique characteristics its design and implementation.
9 Explain the ASIC design flow, including the various stages involved and their significance in
achieving a successful ASIC design.
10 Provide an overview of ASIC’s .Discuss their advantages in terms of performance, power
efficiency, and cost.
11 Discuss the concept of system-on Chip (SOC), its advantages, and the challenges associated
with its design and implementation.
12 Explain the concept of full-custom ASICs. Discuss the advantages and challenges associated
with full- custom design methodologies.