LIST OF EXPERIMENTS

1. CMOS logic circuit simulation using any open source software package.

2. Experiments: structural and behavioural modeling based verilog HDL programs.

3. Experiments: Combinational and sequential digital logic implementation with FPGA

4. Implementation of carry look ahead adder with FPGA

5. Implementation of ALU with FPGA

6. Assignment: Low Power VLSI

7.FPGA based Mini Project

XILINX
TOOLS
EXP.NO: 1 a
CMOS logic circuit simulation using any open source
DATE: software package.

AIM:
To study simulation tools using Xilinx software tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

PROCEDURE:
1. Now start the Xilinx ISE Design Suite 12.1
2. Go to file and click new project
3. Enter the project name and click next
4. Select the family name is Spartan 3E, speed is -4 and simulator is verilog click next and
click Finish.
5. Click new source.
6. Select verilog module and type file name and click next.
7. Assign input and output port and click next.
8. Finally the report is shown click finish.
9. Type the program save and click synthesis.
10. To see the output wave form change the source from implementation to simulation and click
simulator behavior model in ISim simulator.
11. Give values to the input variables and then click run
12. In wave window, click run icon and you can see corresponding output.
Steps to use Xilinx tool:
Start the Xilinx Project Navigator by using the desktop shortcut or by using the

 Start  Programs  Xilinx ISE  Project Navigator.

 In the Project Navigator window go to FILE New project Click on new source verilog
module and give the name inverter.v Define portsFinish

 Select devicesGeneral purpose Spartan 3 ISE simulatorverilog

 In the create new source window select source type as verilog module give file name

 assign inputs and outputs  click next finish yesnext  next finish

 Double click on source filecomplete the verilog code for inverter

  Check syntax, and remove errors if present
 Simulate the design using ISE Simulator Highlight inve rter.v file in the Sources in Project
window. To run the Behavioral Simulation, Click on the symbol of FPGA device and then right
clickClick on new sourceClick on verilog text fixtureGive file name with _tb finish
 Generate test bench file after initial begin assign value for inputs Click on simulate behavioral
model see the output.

RESULT:
EXP.NO: 1 b
STUDY OF SYNTHESIZE TOOLS
DATE:

AIM:
To study synthesize tools using Xilinx software tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

THEORY:
Synthesis is an automatic method of converting a higher level abstraction to a lower level
abstraction. The synthesis tool convert Register Transfer Level (RTL) description to gate level netlists.
These gate level netlists consist of interconnected gate level macro cells. These gate level netlists currently
can be optimized for area, speed etc., The analyzed design is synthesized to a library of components,
typically gates, latches, or flipflops. Hierarchical designs are synthesized in bottom up fashion, that is
lower level components are synthesized before higher level components. Once the design is synthesized
we have a gate level netlist. This gate level netlist can be simulated. Delay for the individual components
are available as part of the description of the component libraries. Timing accurate simulation is not
possible at this point because the actual timing characteristics is determined by the physical placement o f
the design within the FPGA chip. However, the functional simulation that is possible at this point is quite a
bit more accurate than simulation based on user specified delays. After run the synthesize in process
window then full adder model is converted to netlist file.

To convert the RTL to gates, three steps typically occur:

* The RTL description is translated to an unoptimized boolean description usually consisting of
primitive gates such as AND and OR gates, flip-flop, and latches. This is a functionally correct but
completely unoptimized description.
* Boolean optimization algorithms are executed on this boolean equivalent description to
produce an optimized boolean equivalent description.
* This optimized boolean equivalent description is mapped to actual logic gate by making use of a
technology library of the target process.

PROCEDURE:
1. Now start the Xilinx ISE Design Suite 12.1
2. Go to file and click new project
3. Enter the project name and click next
4. Select the family name is Spartan 3E, speed is -4 and simulator is verilog click next and
click Finish.
5. Click new source.
6. Select verilog module and type file name and click next.
 7. Assign input and output port and click next.
8. Finally the report is shown click finish.
9. Type the program save and click synthesis.
10. Go to synthesisView RTL schematic

PROGRAM:

module full_adder (a,b,c,sum,carry);

output sum,carry ;
input a,b,c ;
assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);
endmodule

RTL SCHEMATIC:

RESULT:
EXP.NO:1 c
PLACE AND ROOT AND BACK ANNOTATION FOR FPGAS
DATE:

AIM:
To study place and root and back annotation for FPGAs synthesize tools using Xilinx software
tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

THEORY:
To map this Full adder design onto the FPGA. The primitive hardware elements that are available
in Xilinx xc3s500e chip, namely lookup tables and positive-edge-triggered flip-flops are organized as a
two dimensional array of CLBs. The net list from synthesize is composed of gates, latches, and flip-
flops. It is necessary to assign CLB to net list primitives. This is the process of mapping a design. For
example gates will be assigned to look-up tables. This process effectively translates the gate level netlis t
produce by the synthesize compiler into a netlist of FPGA primitive hardware components. Each elements
of this new netlist corresponds to a hardware primitive in the FPGA Chip. The mapped design produces
identifies the set of FPGA hardware primitives and their interconnection. The next step is to assign each of
the components in the netlist to a equivalent physical primitives on the FPGA chip. Once this assignment
or placement is made the interconnection between the components in the netlist must be made within the
chip. This will require routing signals through the switch matrix and other inter connect resources
available on FPGA Chip. This Place and route layout was generated from Xilinx ISE Floor planner. After
place and route the design can be simulated to validate the design. At this point timing is more accurate
because the propagation delays along routed signals and through CLBs can be more accurately estimated.
This is particularly important for designs that are operating under tight timing tolerance.

To convert the RTL to gates, three steps typically occur:

* The RTL description is translated to an unoptimized boolean description usually consisting of
primitive gates such as AND and OR gates, flip-flop, and latches. This is a functionally correct but
completely unoptimized description.
* Boolean optimization algorithms are executed on this boolean equivalent description to
produce an optimized boolean equivalent description.
* This optimized boolean equivalent description is mapped to actual logic gate by making use of a
technology library of the target process.

PROCEDURE:
1. Now start the Xilinx ISE Design Suite 12.1
2. Go to file and click new project
3. Enter the project name and click next
4. Select the family name is Spartan 3E, speed is -4 and simulator is verilog click next and
 click Finish.
5. Click new source.
6. Select verilog module and type file name and click next.
7. Assign input and output port and click next.
8. Finally the report is shown click finish.
9. Types the program saves and clicks synthesis.
10.Choose Implementation user constraints I/O pin planning (plan ahead) pre- synthesis, type the
input /output port.

PROGRAM:

module full_adder (a,b,c,sum,carry);

output sum,carry ;
input a,b,c ;
assign sum = a ^ b ^ c;
assign carry = (a&b) | (b&c) | (c&a);
endmodule

RESULT:
EXP.NO:1 d STUDY OF FPGA BOARD AND ON-BOARD LED’S AND
DATE: SWITCHES

AIM:
To Study Field Programmable Gate Array (FPGA) board and to test the on-board LEDs and
Switches using Xilinx software tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

THEORY:
DIP SWITCHES:
When in the UP or ON position, a switch connects the FPGA pin to V cc, a logic High. When
DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic low. The switches
typically exhibit about 2ms of mechanical bounce and there is no active debouncing circuitry, although
such circuitry could easily be added to the FPGA design programmed on the board.

KEY SWITCHES:
The key switches can provide pulse input to the FPGA. The switches connect to an associated
FPGA pin. Pressing a key generates logic High on the associated FPGA pin. There is no active
debouncing circuitry on the key switches.

LEDS:
Test LEDs are provided for mapping output of FPGA or tracking particular stage in the design. A
series current limiting resistor of 270 ohm is associated with every LED. To turn on an individual LED,
drive the associated FPGA control signal High.

PROCEDURE:
1.Create a new project & create a new Verilog file.
2.Type the program for testing LEDs and Switches and Save it
3.Synthesize the program and view the RTL Model.
4.Create test bench waveform and simulate it.
5.Download the program using the procedure given below into the FPGA.
6.Now test the physical working of the switches and the LED‟s on – board.
DOWNLOADING PROCEDURE:
1. Select “Synthesis/Implementation” in the source window.
2. Select the created module (*.v file) in the source window.
3. Select “user constraint” in the process window, double click “edit constraint” to create user
constraint file (*.UCF).
4. Type the net list to define the I/O pins and save it.
5. Double click “implement design” in the process window.
6. Double click “Generate programming “file and select the respective created bit file (*.bit)
7. Double click “ configure device (iMPACT) ”. In the impact window that appears, select
„configure device using boundary scan‟. Click finish
8. Right click on the created Xilinx model & select „program‟, give OK on the displayed window.

PROGRAM:
module leds(a, b);
input [0:15]a;
output [0:15]b;
reg [0:15]b;
always@(a)begin
b=~a;
end
endmodule
RESULT:
EXP.NO: 2
Experiments: structural and behavioural modeling based verilog HDL programs.
DATE:
AIM:
To write a verilog program for basic logic gates to synthesize and simulate using Xilinx software
tool.

TOOLS REQUIRED:
Software:
1. Xilinx ISE Design Suite 12.1

THEORY:

AND GATE:
An AND gate is a digital logic gate with two or more inputs and one output that performs logical
conjunction. The output of an AND gate is true only when all of the inputs are true. I f one or more of an
AND gate's inputs are false, then the output of the AND gate is false.

EQUATION LOGIC SYMBOL TRUTH TABLE

A B

Y=a& b

OR GATE:
An OR gate is a digital logic gate with two or more inputs and one output that performs logical
disjunction. The output of an OR gate is true when one or more of its inputs are true. If all of an OR gate's
inputs are false, then the output of the OR gate is false
EQUATION LOGIC SYMBOL TRUTH TABLE
A B

Y=a|b
NOT GATE:
A NOT gate, often called an inverter, is a nice digital logic gate to start with because it has only a single
input with simple behavior. A NOT gate performs logical negation on its input. In other words, if the input
is true, then the output will be false. Similarly, a false input results in a true output.
EQUATION LOGIC SYMBOL TRUTH TABLE
A

Y = ~a

NAND GATE:
A NAND gate (sometimes referred to by its extended name, Negated AND gate) is a digital logic gate with
two or more inputs and one output with behavior that is the opposite of an AND gate. The output of a
NAND gate is true when one or more, but not all, of its inputs are false. If all of a NAND gate's inputs are
true, then the output of the NAND gate is false.
EQUATION LOGIC SYMBOL TRUTH TABLE
A B Y

Y = ~(a & b)

NOR GATE:
A NOR gate (sometimes referred to by its extended name, Negated OR gate) is a digital logic gate with
two or more inputs and one output with behavior that is the opposite of an OR gate. The output of a NOR
gate is true all of its inputs arefalse. If one or more of a NOR gate's inputs are true, then the output of the
NOR gate is false.
EQUATION LOGIC SYMBOL TRUTH TABLE
A B Y

Y = ~(a | b)
EX-OR GATE (XOR):
An XOR gate (sometimes referred to by its extended name, Exclusive OR gate) is a digital logic gate with
two or more inputs and one output that performs exclusive disjunction. The output of an XOR gate is true
only when exactly one of its inputs is true. If both of an XOR gate's inputs are false, or if both of its inputs
are true, then the output of the XOR gate is false.
EQUATION LOGIC SYMBOL TRUTH TABLE
A B Y

Y=a^ b

EX-NOR GATE (XNOR):

An XNOR gate (sometimes referred to by its extended name, Exclusive NOR gate) is a digital logic gate
with two or more inputs and one output that performs logical equality. The output of an XNOR gate is true
when all of its inputs are true or when all of its inputs are false. If some of its inputs are true and others are
false, then the output of the XNOR gate is false.
EQUATION LOGIC SYMBOL TRUTH TABLE
A B Y

Y = ~(a ^ b)

BUFFER GATE:
A buffer has only a single input and a single output with behavior that is the opposite of an NOT gate. It
simply passes its input, unchanged, to its output. In a boolean logic simulator, a buffer is mainly used to
increase propagation delay. In a real- world circuit, a buffer can be used to amplify a signal if its current is
too weak.
EQUATION LOGIC SYMBOL TRUTH TABLE
A Y
Y=A
PROCEDURE:
Software part
1. Click on the Xilinx ISE Design Suite 12.1or Xilinx Project navigator icon on the desktop of PC.
2. Write the Verilog code by choosing HDL as top level source module.
3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the
synthesis in the process window.
4. Perform the functional simulation using Xilinx ISE simulator.
5. The output can be observed by using ISIM Simulator.
 PROGRAM:

BASIC GATES:

DATAFLOW BEHAVIORAL STRUCTURAL

NOT GATE

module notgate(a,y); module notgate (a,y); module notgate (a,y)

input a; input a; input a;
output y; output y; output y;
assign y= ~a; reg y; inv a1(y,a);
endmodule always @(a) endmodule
begin
y=~a;
end
endmodule
OR GATE
module orgate(a,b,y); module orgate(a,b,y); module orgate(a,b,y);
inpput a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(a|b); reg y; or a1(y,a,b);
endmodule always @(a,b) endmodule
begin
y=a|b;
end
endmodule
AND GATE
module andgate(a,b,y); module andgate(a,b,y); module andgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(a&b); reg y; and a1(y,a,b);
endmodule always @(a,b) endmodule
begin
y=a&b;
end
endmodule
 NOR GATE
module norgate(a,b,y); module norgate(a,b,y); module norgate(a,b,y);
inpput a,b; input a,b; input a,b;
output y; output y; output y;
assign y=~(a|b); reg y; nor a1(y,a,b);
endmodule always @(a,b) endmodule
begin
y=~(a|b);
end
endmodule
NAND Gate
module nandgate(a,b,y); module nandgate(a,b,y); module nandgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=~(a&b); reg y; nand a1(y,a,b);
endmodule always @(a,b) endmodule
begin
y=~(a&b);
end
endmodule
XOR Gate
module xorgate(a,b,y); module xorgate(a,b,y); module xorgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(a^b); reg y; xor a1(y,a,b);
endmodule always @(a,b) endmodule
begin
y=a^b;
end
endmodule
XNOR GATE
module xnorgate(a,b,y); module xnorgate(a,b,y); module xnorgate(a,b,y);
input a,b; input a,b; input a,b;
output y; output y; output y;
assign y=(~(a^b)); reg y; xnor a1(y,a,b);
endmodule always @(a,b) endmodule
 begin
y=~(a^b);
end
endmodule
BUFFER GATE
module bufgate (a,y); module bufgate (a,y); module bufgate (a,y);
input a; input a; input a;
output y; output y;
output y;
assign y= a; reg y;
endmodule always @(a) buf(y,a);
begin endmodule
y=a;
end
endmodule
BASIC GATES (ALL GATES IN ONE PROGRAM)
module gates(a,b,c,d,e,f,g,h,i,j); module gates(a,b,c,d,e,f,g,h,i,j); module gates(a,b,c,d,e,f,g,h,i,j);
input a,b; input a,b; input a,b;
output c,d,e,f,g,h,i,j; output c,d,e,f,g,h,i,j; output c,d,e,f,g,h,i,j;
assign c=a&b; reg c,d,e,f,g,h,i,j; and (c,a,b);
assign d=a|b; always @(a,b) or(d,a,b);
assign e=~a; begin not(e,a);
assign f=a; c=a&b; buf(f,a);
assign g=~(a|b); d=a|b; nor(g,a,b);
assign h=a^b; e=~a; xor(h,a,b);
assign i=~(a^b); f=a; xnor(i,a,b);
assign j=~(a&b); g=~(a|b); nand(j,a,b);
endmodule h=a^b; endmodule
i=~(a^b);
j=~(a&b);
end
endmodule

RESULT:
EXP NO: 3a Design and FPGA Implementation of Combinational
Date: Circuits

AIM:
To design and implement Carry select Adder in FPGA Spartan 3E Trainer
kit using Xilinx project navigator.

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. XilinxProject navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define ports click next and
finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowSynthesizedouble click check syntax. If
any errors found then remove the errors with proper syntax & coding.
9. Synthesis your design, from the source window select, synthesis/implementation from the
window Now double click the Synthesis -XST.
10. After Synthesis, Click on the symbol of FPGA device and Right click and select New Source,
Select Implementation Constraints File and type file name and click next.
11. Type the Net list and click save.
12. Implement the design by double clicking Implement design in the process window.
13. Then double click Generate Programming File, Double click Configure Target Device and click
OK.
14. Double click Create PROM File in the ISE iMPACT window, Select Storage Target Device as
Xilinx Flash PROM and click forward.
15. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and Location
and click OK.
16. Select the corresponding .bit file and click Open, Click No to Add Another Device and Click
OK.
17. Double click Generate File.
18. Double click Boundary Scan and Right click on the window and select Initialize Chain, Now
Select the corresponding .mcs file and click open.
19. Click OK in the Device Programming Properties window, Download the Program on to the kit
by Right clicking on the device icon and select program.
20. Verify the output in the target device.
CARRY SELECT ADDER:

BLOCK DIAGRAM:
CODING:

module carry_select_adder
( input [3:0] A,B,
input cin,
output [3:0] S,
output cout
);

wire [3:0] temp0,temp1,carry0,carry1;

//for carry 0
fulladder fa00(A[0],B[0],1'b0,temp0[0],carry0[0]);
fulladder fa01(A[1],B[1],carry0[0],temp0[1],carry0[1]);
fulladder fa02(A[2],B[2],carry0[1],temp0[2],carry0[2]);
fulladder fa03(A[3],B[3],carry0[2],temp0[3],carry0[3]);

//for carry 1
fulladder fa10(A[0],B[0],1'b1,temp1[0],carry1[0]);
fulladder fa11(A[1],B[1],carry1[0],temp1[1],carry1[1]);
fulladder fa12(A[2],B[2],carry1[1],temp1[2],carry1[2]);
fulladder fa13(A[3],B[3],carry1[2],temp1[3],carry1[3]);

//mux for carry

multiplexer2 mux_carry(carry0[3],carry1[3],cin,cout);
//mux's for sum
multiplexer2 mux_sum0(temp0[0],temp1[0],cin,S[0]);
multiplexer2 mux_sum1(temp0[1],temp1[1],cin,S[1]);
multiplexer2 mux_sum2(temp0[2],temp1[2],cin,S[2]);
multiplexer2 mux_sum3(temp0[3],temp1[3],cin,S[3]);

endmodule
module fulladder
( input a,b,cin,
output sum,carry
);

assign sum = a ^ b ^ cin;

assign carry = (a & b) | (cin & b) | (a & cin);

endmodule

module multiplexer2
( input i0,i1,sel,
output reg bitout
);

always@(i0,i1,sel)
begin
if(sel == 0)
bitout = i0;
else
bitout = i1;
end

endmodule
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:
PLACE AND ROUTE:
HARDWARE FUSING:

RESULT:

Thus, the Hardware fusing and testing of Carry Select Adder were implemented in
Spartan 3E FPGA trainer kit using Xilinx project navigator.
EXP NO: 3 b Design and FPGA Implementation of Sequential Circuits
Date:

AIM:
To design and implement Counter in FPGA Spartan 3E Trainer kit using Xilinx project
navigator.

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. XilinxProject navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define ports click next and
finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowSynthesizedouble click check syntax. If
any errors found then remove the errors with proper syntax & coding.
9. Synthesis your design, from the source window select, synthesis/implementation from the
window Now double click the Synthesis -XST.
10. After Synthesis, Click on the symbol of FPGA device and Right click and select New Source,
Select Implementation Constraints File and type file name and click next.
11. Type the Net list and click save.
12. Implement the design by double clicking Implement design in the process window.
13. Then double click Generate Programming File, Double click Configure Target Device and click
OK.
14. Double click Create PROM File in the ISE iMPACT window, Select Storage Target Device as
Xilinx Flash PROM and click forward.
15. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and Location
and click OK.
16. Select the corresponding .bit file and click Open, Click No to Add Another Device and Click
OK.
17. Double click Generate File.
18. Double click Boundary Scan and Right click on the window and select Initialize Chain, Now
Select the corresponding .mcs file and click open.
19. Click OK in the Device Programming Properties window, Download the Program on to the kit
by Right clicking on the device icon and select program.
20. Verify the output in the target device.
CODING:

Module ripple counter (A0, A1, A2, A3, Count, Reset)

Output A0,A1, A2,A3;
Input Count,Reset;
ff f0(A0, Count, Reset);
ff f1(A1, A0, Reset);
ff f2(A2, A1, Reset);
ff f3(A3, A2, Reset);
end module
module ff
(Q, CLK, Reset);
output Q;
input CLK, Reset;
reg Q;
always @ (negedge CLK or negedge Reset)
if (~Reset)
Q=1’b0;
else Q=(~Q);
endmodule

RTL SCHEMATIC:
TECHNOLOGY SCHEMATIC:

PLACE AND ROUTE:

RESULT:
EXP NO: 4 Implementation of Carry look ahead adder with FPGA
Date:

AIM:
To design and implement Carry look ahead Adder in FPGA Spartan 3E
kit using Xilinx project navigator.

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. XilinxProject navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define ports click next and
finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowSynthesizedouble click check syntax. If
any errors found then remove the errors with proper syntax & coding.
9. Synthesis your design, from the source window select, synthesis/implementation from the
window Now double click the Synthesis -XST.
10. After Synthesis, Click on the symbol of FPGA device and Right click and select New Source,
Select Implementation Constraints File and type file name and click next.
11. Type the Net list and click save.
12. Implement the design by double clicking Implement design in the process window.
13. Then double click Generate Programming File, Double click Configure Target Device and click
OK.
14. Double click Create PROM File in the ISE iMPACT window, Select Storage Target Device as
Xilinx Flash PROM and click forward.
15. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and Location
and click OK.
16. Select the corresponding .bit file and click Open, Click No to Add Another Device and Click
OK.
17. Double click Generate File.
18. Double click Boundary Scan and Right click on the window and select Initialize Chain, Now
Select the corresponding .mcs file and click open.
19. Click OK in the Device Programming Properties window, Download the Program on to the kit
by Right clicking on the device icon and select program.
20. Verify the output in the target device.
CARRY LOOK AHEAD ADDER:

BLOCK DIAGRAM:
 CODING:

VHDL Code for Partial Full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Partial_Full_Adder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end Partial_Full_Adder;

architecture Behavioral of Partial_Full_Adder is

begin

S <= A xor B xor Cin;

P <= A xor B;
G <= A and B;

end Behavioral;
VHDL Code for Carry Look Ahead Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Carry_Look_Ahead is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Carry_Look_Ahead;
architecture Behavioral of Carry_Look_Ahead is

component Partial_Full_Adder
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
P : out STD_LOGIC;
G : out STD_LOGIC);
end component;

signal c1,c2,c3: STD_LOGIC;

signal P,G: STD_LOGIC_VECTOR(3 downto 0);
begin

PFA1: Partial_Full_Adder port map( A(0), B(0), Cin, S(0), P(0), G(0));
PFA2: Partial_Full_Adder port map( A(1), B(1), c1, S(1), P(1), G(1));
PFA3: Partial_Full_Adder port map( A(2), B(2), c2, S(2), P(2), G(2));
PFA4: Partial_Full_Adder port map( A(3), B(3), c3, S(3), P(3), G(3));

c1 <= G(0) OR (P(0) AND Cin);

c2 <= G(1) OR (P(1) AND G(0)) OR (P(1) AND P(0) AND Cin);
c3 <= G(2) OR (P(2) AND G(1)) OR (P(2) AND P(1) AND G(0)) OR (P(2) AND P(1) AND P(0)
AND Cin);
Cout <= G(3) OR (P(3) AND G(2)) OR (P(3) AND P(2) AND G(1)) OR (P(3) AND P(2) AND
P(1) AND G(0)) OR (P(3) AND P(2) AND P(1) AND P(0) AND Cin);

end Behavioral;
VHDL Testbench Code for Carry Look Ahead Adder
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY Tb_Carry_Look_Ahead IS
END Tb_Carry_Look_Ahead;
ARCHITECTURE behavior OF Tb_Carry_Look_Ahead IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Carry_Look_Ahead
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
Cin : IN std_logic;
S : OUT std_logic_vector(3 downto 0);
Cout : OUT std_logic
);
END COMPONENT;

--Inputs
signal A : std_logic_vector(3 downto 0) := (others => '0');
signal B : std_logic_vector(3 downto 0) := (others => '0');
signal Cin : std_logic := '0';

--Outputs
signal S : std_logic_vector(3 downto 0);
signal Cout : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Carry_Look_Ahead PORT MAP (
A => A,
B => B,
Cin => Cin,
S => S,
Cout => Cout
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;

A <= "1111";
B <= "1111";
Cin <= '1';

wait for 10 ns;

A <= "1010";
B <= "0111";
Cin <= '0';

wait for 10 ns;

A <= "1000";
B <= "1001";
Cin <= '0';

wait;

end process;

END;

module fulladder
( input a,b,cin,
output sum,carry
);

assign sum = a ^ b ^ cin;

assign carry = (a & b) | (cin & b) | (a & cin);

endmodule
module multiplexer2
( input i0,i1,sel,
output reg bitout
);

always@(i0,i1,sel)
begin
if(sel == 0)
bitout = i0;
else
bitout = i1;
end
endmodule
RTL SCHEMATIC:

TECHNOLOGY SCHEMATIC:
PLACE AND ROUTE:
HARDWARE FUSING:

RESULT:

Thus, the Hardware fusing and testing of Carry look ahead Adder were
implemented in Spartan 3E FPGA trainer kit using Xilinx project navigator.
EXP NO: 5 Implementation of ALU with FPGA
Date:

AIM:
To design and implement ALU in FPGA Spartan 3E Trainer kit using Xilinx project
navigator.

APPARATUS REQUIRED:

S.No Nameofthe equipment/ software Quantity

1. PC with Windows 1
2. XilinxProject navigator 1

PROCEDURE:
1. Start the Xilinx ISE by using Start Program files Xilinx ISE project navigator
2. Click FileNew Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right clickclick on new source.
6. Select the Verilog Module and give the file name click next and define ports click next and
finish.
7. Writing the Verilog Code in Verilog Editor.
8. Run the Check syntax Process windowSynthesizedouble click check syntax. If
any errors found then remove the errors with proper syntax & coding.
9. Synthesis your design, from the source window select, synthesis/implementation from the
window Now double click the Synthesis -XST.
10. After Synthesis, Click on the symbol of FPGA device and Right click and select New Source,
Select Implementation Constraints File and type file name and click next.
11. Type the Net list and click save.
12. Implement the design by double clicking Implement design in the process window.
13. Then double click Generate Programming File, Double click Configure Target Device and click
OK.
14. Double click Create PROM File in the ISE iMPACT window, Select Storage Target Device as
Xilinx Flash PROM and click forward.
15. Add storage Device as xcf01s [2 M] and click forward, Type Output File Name and Location
and click OK.
16. Select the corresponding .bit file and click Open, Click No to Add Another Device and Click
OK.
17. Double click Generate File.
18. Double click Boundary Scan and Right click on the window and select Initialize Chain, Now
Select the corresponding .mcs file and click open.
19. Click OK in the Device Programming Properties window, Download the Program on to the kit
by Right clicking on the device icon and select program.
20. Verify the output in the target device.
 CODING:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.NUMERIC_STD.all;
-----------------------------------------------
---------- ALU 8-bit VHDL ---------------------
-----------------------------------------------
entity ALU is
generic (
constant N: natural := 1 -- number of shifted or rotated bits
);

Port (
A, B : in STD_LOGIC_VECTOR(7 downto 0); -- 2 inputs 8-bit
ALU_Sel : in STD_LOGIC_VECTOR(3 downto 0); -- 1 input 4-bit for selecting function
ALU_Out : out STD_LOGIC_VECTOR(7 downto 0); -- 1 output 8-bit
Carryout : out std_logic -- Carryout flag
);
end ALU;
architecture Behavioral of ALU is

signal ALU_Result : std_logic_vector (7 downto 0);

signal tmp: std_logic_vector (8 downto 0);

begin
process(A,B,ALU_Sel)
begin
case(ALU_Sel) is
when "0000" => -- Addition
ALU_Result <= A + B ;
when "0001" => -- Subtraction
ALU_Result <= A - B ;
when "0010" => -- Multiplication
ALU_Result <= std_logic_vector(to_unsigned((to_integer(unsigned(A)) * to_integer(unsigned(B))),8)) ;
when "0011" => -- Division
ALU_Result <= std_logic_vector(to_unsigned(to_integer(unsigned(A)) / to_integer(unsigned(B)),8)) ;
when "0100" => -- Logical shift left
 ALU_Result <= std_logic_vector(unsigned(A) sll N);
when "0101" => -- Logical shift right
ALU_Result <= std_logic_vector(unsigned(A) srl N);
when "0110" => -- Rotate left
ALU_Result <= std_logic_vector(unsigned(A) rol N);
when "0111" => -- Rotate right
ALU_Result <= std_logic_vector(unsigned(A) ror N);
when "1000" => -- Logical and
ALU_Result <= A and B;
when "1001" => -- Logical or
ALU_Result <= A or B;
when "1010" => -- Logical xor
ALU_Result <= A xor B;
when "1011" => -- Logical nor
ALU_Result <= A nor B;
when "1100" => -- Logical nand
ALU_Result <= A nand B;
when "1101" => -- Logical xnor
ALU_Result <= A xnor B;
when "1110" => -- Greater comparison
if(A>B) then
ALU_Result <= x"01" ;
else
ALU_Result <= x"00" ;
end if;
when "1111" => -- Equal comparison
if(A=B) then
ALU_Result <= x"01" ;
else
ALU_Result <= x"00" ;
end if;
when others => ALU_Result <= A + B ;
end case;
end process;
ALU_Out <= ALU_Result; -- ALU out
tmp <= ('0' & A) + ('0' & B);
Carryout <= tmp(8); -- Carryout flag
end Behavioral;
Testbench VHDL code for ALU:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb_ALU IS
END tb_ALU;

ARCHITECTURE behavior OF tb_ALU IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT ALU
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
ALU_Sel : IN std_logic_vector(3 downto 0);
ALU_Out : OUT std_logic_vector(7 downto 0);
Carryout : OUT std_logic
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal ALU_Sel : std_logic_vector(3 downto 0) := (others => '0');

--Outputs
signal ALU_Out : std_logic_vector(7 downto 0);
signal Carryout : std_logic;

signal i:integer;
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: ALU PORT MAP (
 A => A,
B => B,
ALU_Sel => ALU_Sel,
ALU_Out => ALU_Out,
Carryout => Carryout
);

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
A <= x"0A";
B <= x"02";
ALU_Sel <= x"0";

for i in 0 to 15 loop
ALU_Sel <= ALU_Sel + x"1";
wait for 100 ns;
end loop;
A <= x"F6";
B <= x"0A";
wait;
end process;

END;
RTL SCHEMATIC:

Simulation waveform for the ALU:

TECHNOLOGY SCHEMATIC:

PLACE AND ROUTE:

HARDWARE FUSING

RESULT:

Thus, the Hardware fusing and testing of ALU (Arithmetic and logic unit) was implemented in
Spartan 3E FPGA trainer kit using Xilinx project navigator.