ADVANCED CIRCUIT ANALYSIS

with the HP-42S

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EduCALC
27953 Cabot Rd.
Laguna Niguel, CA
ADVANCED CIRCUIT ANALYSIS

With the HP-42S

by Robert R. Boyd

Copyright 1989

Robert R. Boyd

All rights reserved

 INTRODUCTION

The purpose of this work is to present a novel method of

of circult analysis developed by the author several years
ago. The method is derived from Kirchoff’s current law
and results in a dimensionless coefficient matrix in place
of the conventional admittance matrix. Using this method,
matrix elements can be written by lnspection of the circuit,
without algebraic manipulation.

Section I presents the method of setting up the circuit

matrices. Merely by labeling the voltage nodes to be
analyzed, and the branch impedances connected to the nodes,
the node equations can be written using the principle of
superposition. It is not necessary to identify loops,
trees, chords, links, etc., of the topology. One merely
has to know how many impedances are connected to the node
and which impedance |18 connected to the driving voltage.
This information can be obtained from the ciruit diagram.
In addition, it is not necessary to convert sources to
Norton or Thevenin equivalents.

With linear circuits that contain no dependent sources,

the symmetric coefficient matrices using loop or node
analysis are very easy to set up. This mnemonic method
is presented in just about every undergraduate text on
network analysis. However, when dependent sSources are
introduced, the symmetry disappears along with the
mnemonic method. With the technique presented here,
the symmetry of the coefficient matrix is of no concern.

Other HP calculators/computers can be used with the material

in Section I. Some good choices are the HP-71B/Math Pac, the
HP-28S~, or the HP-41CV/X/Advantage module. Of course, any
computer that has complex matrix and double precision
capabilities can be used as well.

Section II is exclusively for those readers with HP-42S

calculators and familiarity with the operation of the
calculator is assumed. Most of the circuits given in
section I are analyzed with complete descriptions of the
main programs. No attempt has been made to minimize the
program code. The interested reader will probably see a
better way to do it.

= See EduCalc book "Advanced Circuit Analysis with the

HP-28S" .
A PC AT or XT with P-Spice has some advantages over writing
out the node equations and setting up the circuit matrices,
no matter how easy and systematic the information herein
makes it. There are also analog design workstations appearing
on the market that are absolutely fantastic in their capa-
bilities. However, a PC with P-Spice will run about 5,000
while the analog workstations are going for over $50,000. The
HP-425 sells for under $100. Comparing capability per dollar,
the method presented here using the HP-42S wins hands down.

NOTICE:

The author and/or EduCALC Mail Store makes no warranty of any kind
with regard to this material. The author and/or EduCALC Mail Store
shall not be llable for errors contained herein or for incidental
or consequential damages in connection with the furnishing,
performance, or use of this material.

EduCALC
27953 CABOT ROAD
LAGUNA NIGUEL, CA 92677
To my Wife LINDA: Prov 31:10-12

To my daughter JANA: Prov 31:29

 TABLE OF CONTENTS

TITLE PAGE

Section I - Setting up The Circuit Matrices

Example 1 - Solve for Vo by Superposition

(N = 3)

Example 2 Solve for Vo by Superposition

(N = 4)

Example - Ladder Network

W

b
Example - Lattice Network
s

O
Example - Twin-T Network
g

O
Example Collector Feedback
O

NV
|

Example - CE Hybrid Pi Transistor Model 11

N

Example - Inverting Op-Amp

@

Example - AdJustable Gain Differential Ampl 13

v

Example 10 - Non-Linear Circuits 15

Example 11 - Fifth Order Active Filter 16

Example 12 - Complementary Feedback Amplifier 18

Alternate Formulations 21
Section I1 - HP-42S Programs 22

Example 3 Ladder Network (DC) 26

Example 3 Ladder Network (AC) 29

Example Twin-T Network 33

Example CE Hybrid Pi Transistor Model 35

Example Inverting Op-Amp 36

Example 9 Adjustable Gain Differential Ampl 38

Example 11 - Fifth Order Active Filter 40

Example 12 - Complementary Feedback Ampl 42

Example 10 - Non-linear Circuit 44

Appendix - 1. Ladder Network Analysis 49

IT. Building Branch Impedances S3
with the HP-42S

III. Floating Voltage Sources S3

Iv. Designing with K Factors S5

References S7
SECTION I. Setting up The Circuit Matrices.

Notational convention: E => Independent voltage source

v => Dependent voltage source or node
vol tage
I => Dependent current source or node
current
2 => real or complex impedance

Two simple star networks will be analyzed to show a method

of solving for the voltage at the center node that is easy
to remember. This topology is chosen since any circuit can
be formed by combining star networks with 2 or more branches.
The method is then generalized to an N-branch star network.

Example1 Solve for Vo by superposition:

(N = 3)

Vo
El Oo———NVVYV > AVAVAY O E2

24 2,
Z
3

a. Set E= =0, Vo -> Vo’:

Page 1
 Since 22//23 = —=——=—=—===-- ,
1 1
-—— - + -— . —

2=z Za

E,
VO’ = ———mmmm oo
;o1 1
1 + 2, -——— 4+ ———)
22 2>

b. Set E: =0, Vo -> Vo":

Ez 2:.//2a Ez
VO" =e = e
22 + 2://25 2=
1 + ——————-
2+//22

E=
Voll o e - - - - - - > - - - -

1 1
1 4 22 -== 4 -—-|
\ 2, Zs |

Then by the superposition principle,

Vo
<

<
O-
N\

+
o
]

= E;K: + EzK=,

where K: and Kz are dimensionless constants determined by

2:, 22, & 25, and are always < 1.

Page 2
We try a second example to see 1f there 18 a consistent
pattern occurring.

Example2 Solve for Vo by Superposition:

(N = 4>

Vo
. O AVAVAN VWN\-—0O E_
~n
—~

By VYW& A ¢ E
4
U

E«. 22//23//24 Ez 2:1//25//2a

VO = ~-————mccmmmmr e +
21 + 22//23//24 22 + 2.//23//2a

Es 2://22//2a Ea 2://22//25
4 —mmm - +

E>

2=
1 + ————————-
21//23//2a

Ea

la
1 4+ ——--mm-
2:1//2=2//2

E=
———m 4 e .
1 1 1 1
+ —-—- 1 + 22| ——= + === 4 ——-
24 / Z! Z:B 24 l

Ea
—_—— 4 e=

1 /1 1 1
+ -—-) 1 + Za === + === 4 -——|
2a V2 2= 2a '
 Vo = Ei1K:y + EzKz + EaKs + EaKa.

Now the pattern is evident. In general:

4
Vo =
/ 1 + impedance in Sum of remaining reciprocal
i=1 gseries with E, impedances (admittances)
connected to node Vo /
N

ZE.K..
i=1
As shown in the next example, the Ei’s can be a mix of Ei
and Vi.

Now we will use this method to write node equations by

ingspection.

Example3 Ladder network.

Solve for dependent node voltages V: and Vz.

We see that the equation for V: will be the

superposition sum of E, and Vz:

(1> Vi = E:K: + VzKz, where Ki = --

Since there is only one voltage driving node Vz, the

equation for V= will have only one term:

Page 4
(2> V= = V.Ka, where Ka = -

Equations (1) and (2> can be solved for V. and Vz by

elimination or by matrix methods. By elimination:

Vi = E:1K:s + (V4 Kza)K=z, substituting (2) into (1). Then

(3

Substlituting (3) Into (2) glives V=2, or

Using matrix methods:

Rearranging (1) and (2) so that the independent terms

are on the LH side:

E: K Vi - VzK=

0 = V= - V,Ks.

From this form it is easy to construct the coefficient

matrix and independent column vector:

1 -K= Vi Ei K.

-Ka 1 V2 0

From now on, matrices will be used exclusively. As the

circuits get larger and more complicated, solving for
the unknown node voltages using algebra and the
elimination method becomes too lengthy and error prone.

Page 5
 xample 4 Lattice network.

22

Z),
AN v,
24
Now we can be methodical and consisent.

Step 1. Write dependent node equations using super-

position and assigning a unique K factor to
each term.

Vi E:K: + EzKz + VzKa

V2 = Ei1Ka + E2Ks + V;Kas (We dont care what

the K’s are until
after the matrices
are formed.)

Step 2. Put independent terms on LH side:

EiK: + EzKz =V, - VzK»

EiKa + EzKs = V2= - VK&

Step 3. Put in matrix form:

I 1 -Ka Vi E:K: + EzK=

Ks 1 V2 EiKa + EzKs

Step 4. From the circuit diagram and the equations of

step 1, write out the K factors.

Before doing this, a functional notation for the K factors

will be defined.

Let -------- = F2(A,B) ,

 ———————————————
—— = Fs(ApB'C)’

--------------------- = F4(A,B,C,D).
1 1 1
1 + A|-—-—— + === 4+ -=-
( B C D )
1
Note, for example, that F3(B,C,A) = -—-=--ccce-—-
1 1
1 + Bf--- + ——-
C A
= F3(B,A,C), l.e., after the first varliable, the order
is not important since the reciprocals can be summed in
any order.

Getting back to Example 4, we can write out the K factors

using this functional notation:

K1 = F3(21,22,24>, K2 = F3(24,21,22)

K3 = F3(22,21,24>, K4 = F3(Z25,22,23)

KS = F3(23,22,25>, K6 = F3(22,23,25)>

Remember that the first 2 in F3 is in series with the E

or V in question. For example, in V., = E;K: + ..., the
first 2 in K, is between V. and E., or Z2.. Be sure to
account for all the remaining 28 connected to node V.,
in this case 2= and Za.

One last example before going on to transistor and op-amp

circuits:

Page 7
Example5 Twin-T Network

Step 1. =

Vi = E.:K: + VzsK=

V= = Ei1Ks + VzKa

Vo = V.Ks + VzK.
Step 2.

E:K, = V, - VsKz

EiKz = V=2 - VsKa

0 = V3 - Vsz - V2K¢

Step 3.

1 0 -K= Vi E. K.

0 1 -Ka V2 = E.Ks

-K= -Ka 1 Vs 0

Step 4.

K1 = F3(21,22,23>, K2 F3(23,21,22>,

K3 = F3(24,25,26>, K4 F3(26,24,25),

KS = F3(23,26,27), K6 F3(26,23,27).

The circuit 1s now ready for solution by the HP-42S.

Page 8
At this point, we modify our basic star network by adding
current sources:

Z
E, 1 O AN P
oV 3
/’5

}®§
fié

Again, by superposition:

Vo = E.K: + Vz2K=2 + VaKas + Py 1a - les.

where K1 = F3(21,22,23), K2 = F3(22,21,23),

K3 = F3(23,21,22), and P1 = 21//22//23.

Note direction of current flow and the sign attached;

toward node => +, away from node => -,

Example 6 Col lector Feedback.

Step

V., = E;K, + VzK= -

V= = EzKs + Vi1Ka - Pz2Ib -

Va = 2Z2ale

V2 Va = Vbe ( 0.6V)

Page 9
 Step 2. (Express Ic and Ie in terms of Ib.)

E.K, =V, - V=K + P,Blb (Ic = Beta Ib = Blb>

EzKz = V> - ViKa + P21IDb

0 Va - (1 + B)Ibls [Ile = (1 + B)Ib]

Vbe = V= - Vs

Step 3.

1 -K= 0 P.B V., E:K: |

-Ka 1 0 Pz \ EzK=z

0 0 1 -(1+B)2Z2% Va - 0

0 1 -1 0 Ib Vbe

Step 4.

K1 = F2(21,24>, K2 = F2(24,21),

K3 = F2(Z22,24>, K4 = F2(24,22)

Pl = 217724, P2 = 22//24

This circuit is not easily solved by conventional methods.

Using the above matrices, the HP-42S will solve for all node
voltages and the base current Ib. Collector and emmitter
currents are easily obtained from Ic = Blb, and Ie = (1 + B)Ib.

Note that in forming the P’s associated with current sources,

they are easily remembered as the parallel combination of
all impedances connected to the node in question.

Page 10
Example 7 Common Emitter Hybrid Pi Transistor Model

co— At b2
Z Vv Z Vv
1 2

Z Z
‘J 2 LU gm\ll
| %

Note that (gwV:) is a voltage-controlled-current-source,

or VCCS.

Step 1.

Vx = ExKx + V2K2

V= = ViKs - aguViPy = Vi (Ks - guwPi)

Step 2.

E:K: = Vx - V2K2

0 = V= - Vi(Ka - gMPx)

Step 3.

1 -K= l Vi | E. K. |

(gmpx'Ka) 1 V= 0

Step 4.

K1 = F321,22,23), K2 = F3(23,21,22>

K3 = F2(23,24>, P1 = 23//24

Page 11
Example8 Inverting op-amp

A simplified model of the op-amp is obtained by the dependent

voltage source Vs = -AV:, where A |8 the open loop gain.
(Va 1s a voltage-controlled-voltage-source, or VCVS.)

The variable A can be complex to show the first order rolloff

without adding additional reactive components:

A= ———emm——— , where Aol = about 10,000 v/v,

and wi = 2pi(fl) is the frequency breakpoint , and

10 < f1 < 100 in Hz for most op-amps.

Gain A can have zeros as well as poles:

Jw
Aol (1 + ----
W=

Jw Jw
1 + ———- i + -———-
Wi Ws

For most op-amp circuits, the single pole rolloff will suffice.

Page 12
Again, steps 1 thru 4 are no different:

Step 1.

V: = ExK: + V2K2

Vz = V1Ks + VizKa = Vi Ka - AV:Ka

V:(Ks - AKA)

Step 2.

E:K: =V, - V2K2

0 = Vz - Vn(Ks - AK«)

Step 3.

1 -K= Vi E. K.

(AKa-K2) 1 V= | - | 0 |

Step 4

K1 = F2(21,22>, K2 = F2(22,21)

K3 = F3(22,23,24), K4 = F3(24,22,23)

Example9 Adjustable gain differential amplifier.

—0 v,

Page 13
Step 1.

Vi = E«K: + VzKz

V2 = ViKs + VsKa + VsKs

Va = A(Va - V)

Va = E2Ks + VsK->

V= = VaKe + VzKe

Step 2.

E:K: = V, - VzK=2

0 V= - ViKas - V3Ka -V=Ks

0 = Vo - AVa + AV,

Esz = V4 - VsK?

0 = Vs - V2K9 - VAKQ

Step 3.

1 -K= 0 0 0 Vi EiKi

-Ka 1 -Ka 0 -Ks= V2

A 0 1 -A 0 Va

0 0 0 1 -K» Va Ez=K«

0 -Ks 0 -Ke 1 Vs

Step 4.

K1 = F2(R1,R2>, K2 = F2(R2,R1)

K3 = F3(R2,R3,R4), K4 = F3(R3,R2,R4),

KS = F3(R4,R2,R3),

K6 F2(R5,R6), K7 = F2(R6,R5),

K8 F3(R6,R4,R7>, K9 = F3(R4,R6,R7)

Page 14
Example 10 Non-linear Circuits.

Some non-linear diode circuits can be solved by converting the

diodes to resistors (in series with a 0.6V source if need be).
The method is to monitor the voltages across the resistor
(diode) for polarity. If the "diode" becomes reverse biased,
then change its value to 10 Megohms. 11f it becomes forward
biased, change its value to, say, 10 ohms.

By ™ E> By
R3l D7A R5

Ezo__/\%/\.__i___ - E; o

Step 1 (For the circuit on the right)

Vi = Ei1K:s + EzaKz + VzKa

V= EzKa + ExK=s + VsKe

Va ViK> + VzKe

Page 15
 Step 2.

EiK: + EzK= Vi - VaKs

Ez2Ka + EzKs = V2> - Vi3Ks

0 = Vs - V:Ke - ViK>

Steps 3 and 4 are, as they say, "left as an excercise for the

student".

During the analysis in section II, If (V, - Vzs) < 0, set

Re = 10 ohms; if > 0 set R« = 10 Megohms. Similarly, if
(Vz - Viz) > 0, set R> = 10 ohms; if < 0 set R> = 10
Megohms.

Examples 11 and 12 following illustrate the ease of writing

node equations using the K method for relatively large and
complicated circuits.

Example 11 Fifth Order Active Filter

Page 16
 L1 abeq
A
=A PRA- T 0 0
Bx_
vA °'y- 0 1 ex-
=Y -
€A
bx_
=A
ZX_
‘A
‘e daas
’A -
SAY + TAY
FENTA SA =
OFNTA - SASA - =N'A A =
“ATA - TA=A €A =
SCA - "X'A ZA =
SXbA - ZXZA
Atd
2 dais
(=A AV
!‘X,A
= =A
O!X9A + 6X€A + BX!A
= *A
+
“A%A TA=A = ©p
+ bx!A
=A€A = =p
CXPA + !XCA +
Ad = A
"1 de8ag
 Step 4.

Ki = F4(21,22,23,24>, K2 = F4(23,21,22,24)

K3 = F4(24,21,22,23)

K4 = F3(Z23,25,26>, KOS F3(26,23,25)

K6 = F3¢Z6,27,28>, K7 F3(27,26,28)

K8 = F3(24,27,29>, K9 F3(27,24,29)>

K10 = F3(29,24,27)>, K11 = F2(210,211)

Example12 Complementary Feedback Amplifier.

B, 0— ]
“1
L4
‘ o
J Vv

Page 18
Step 1.

V. E: - lez=2.

Va2 E: K, + VaKz + IbzP,

Va V= - Icils

Va Ibi2a

Vs Ez=Ks + V<Ka + le,P2

Ve Ez=Ks + VsKe + Ic=zPas

Vbe, Va - Vs

Vbe= V2

Step 2.

E. (1 + B2)Ibz2.:

E. K, V= - VaKz - IbzP.

V= + B:Ib:Zs

Es Va + Ib:2a

EzK» Vs" VeKa - (1 + By)Ib,P=

EzK= Ve - VsKse - Bz1bzPa

Vbe, Va - Vs

Vbe= Vi - V2

Page 19
 1 0 0 0 0 0 0 (1+B=)>2. Vi

0 1 -K= 0 0 0 0 -P, V2

0 -1 1 0 0 0 Bis 0 Vs

0 0 0 1 0 0 Za 0 Va

0 0 0 0 1 -Ka -(1+4B,)P= 0 Vs

0 0 0 0 -Kas 1 0 -Bz2Ps Vo

0 0 0 1 -1 0 0 0 Ib,

1 -1 0 0 0 0 0 0 Ib=

= | E; EiK: 0 Ex EzKs EzK= Vbe, Vbe= | T

(The ™ transposes the row vector into a column vector.)

Step 4.

K1 = F2¢22,23>, K2 = F2(23,22>

K3 = F2(25,27>, K4 = F2(27,25>

KS = F2(Z26,27>, K6 = F2(27,26>

Pl = 22//23, P2 = 25//727, P3 = 26//27

In setting up the coefficient matrix, advantage should be taken

of all the zeros in the matrix (a so-called sparse matrix)> and
that the main diagaonal is nearly all 1’s. That is, one should
form an identity matrix first, and then store only the non-
zero elements.

Page 20
By now the astute reader has probably seen the similarity
of the F3 and F4 K factor functions with the parallel
impedance function. There are two alternate formulations
of these functions that may result in shorter HP-42S programs.

For example, if

K1 F4(21,22,23,24>, K2 Fa4¢z22,21,23,24,

K3 F4(23,21,22,24), K4 F4¢24,21,22,23),

a shorter way of computing Ki through K4 is

K1 F4(21,22,23,24)>, K2 = (K1%21)/22,

K3 (K1%Z21>/23, K4 = (K1ix21)/24.

Note that the denominator of Ki is 2i, I = 2, 3, 4.

Still another way of calculating K1 through K4 is

P1 21//722//723//724, then

K1 P1/21, K2 = P1/22, K3 = P1/23, and K4 = P1/24.

The form here is KiI = P1/2i

Also note that K1 + K2 + K3 + K4 = 1. Then K4 can also be

calculated by K4 = 1 - Ki - K2 - K3. Similary, for N =3

Ki = F3(21,22,23); K2 = F3(22,21,23>; K3 = F3(23,21,22);

but it is quicker to compute K3 = 1 - K1 - K2.

Page 21
SECTION II. HP-42S Programs

Due to word processor character limitations, the following sub-

stitutions will be used for the given HP-42S characters:
(Substituting J for | is due to electrical engineering preference,
and should not cause undue confusion.)

Character

> ra (right arrow)

Y da (down arrow)

R¢ Rup

R Rdn

104 X 10X
- /
1 J

We will begln from the bottom and work up. That is, the following
subprograms with global labels will be used with main programs
"SETUP", "DCAP", and "ACAP", to be described later. They should
be keyed in now.

Circuit Capacitor Inductor Resistor in Resistor in

element: gseries with gseries with
capacitor inductor

Comp 1 ex 0 - Jj/wC 0 + JwL R - js/wC R + JwL

expressjion:

Stack must
contain:
Y-reg: any any R R
X-reg: C L C L

Listing: 01 LBL "XC" 01 LBL "XL" 01 LBL "SRC" 01 LBL SRL

02 RCLx"w" 02 RCLx"w" 02 RCLx"w" 02 RCLx"w"
03 1/X 03 0 03 1/X 03 COMPLEX
04 +/- 04 XY 04 +/- 04 END
0S5 O 05 COMPLEX 05 COMPLEX
06 X<>Y 06 END 06 END
07 COMPLEX
09 END

Page 22
Circuit Resistor in Resisgstor in Operational
element: parallel with parallel with amplifier
capacitor lnductor

Complex 1/C1/R + JwC) 1/¢1/R - j/wbl) Aol/Cl + Jw/wi)

expression: Aol/Cl + Jf/f4)

Stack must
contain:
Y-reg: any
X-reg: any

Listing: 01 LBL "PRC" 01 LBL "PRL" 01 LBL "OPAMP"

02 RCLx"w" 02 RCLx"w" 02 1
03 XY 03 1/X 03 ENTER
04 1/X 04 +/- 04 RCL "F"
05 XY 0S5 XY 05 107X
06 COMPLEX 06 1/X 06 10 (fi)d
07 1/X 07 XY 07 /
08 END 08 COMPLEX 08 COMPLEX
09 1/X 09 1E4 (Aol)
10 END 10 XY
11 7/
12 STO "A"
13 END

Function: Fa2¢21,22> 21//22

Complex
expression: 1 + 21722 1721 + 1/22

Stack must
contain:
Y-reg: 21 21 or 2=z
X-reg: l=2 22 or 2.

Listing: 01 LBL "F2" 01 LBL "pzZ2"

02 1/X 02 1/X
03 x 03 XY
04 1 04 1/X
05 + 05 +
06 1/X 06 1/X
07 END 07 END

Page 23
Function: 2:.//22//23 21//22//23//24

Complex 1 1
expression: ------=-----—---—--- s-e————ee——————————--—----
1/2:, + /22 + 1/2a 1/72: + 1/22 + 1/22 + 1/2a4

Stack must
contain:
T-reg: any 21
2-reg: YA 2=
Y—reg: 2= s
X-reg: Za Za

Listing: 01 LBL "P23" 01 LBL "PZ4"

02 XEQ "pPzZ2" 02 XEQ "PZ3"
03 XEQ "pz2" 03 XEQ "Pz22"
04 END 04 END

For "PZ23" and "PZ24", the 28 can be in any order in the stack.

The following program is an initiallzing routine that must be run

before analyzing any new circuit. It need not be executed more
than once for the same circuit.

After a menu choice of AC or DC analysis, the required input is the

order n of the n x n coefficient matrix.

Page 24
 Listing Comments
01 LBL "SETUP"
02 WRAP
03 CF 01 Clear AC/DC selection flag
04 CLV "MATK" Clear old circuit matrices
05 CLV "MATE"
06 CLV "MATV"
07 " ACM
Begin menu setup
08 KEY 1 GTO 01
09 " DC"

10 KEY 4 GTO 02
11 MENU
12 STOP
13 LBL 02
14 SF 01 Set flag 01 for DC analysis
15 LBL 01
16 EXITALL
17 "Order?"
18 PROMPT
19 ENTER
20 DIM "MATK" Dimension K (coefficient) matrix
21 1
22 DIM "MATE" Dimension E (independent) column vector
23 DIM "MATV" Dimension V (node voltage) column vector
24 RECT
25 0
26 ENTER
27 COMPLEX
28 FS? 01 DC analysis?
29 GTO 01 Then do not create complex matrices
30 STOx "MATK" Create complex matrices for AC analysis
31 STOx "MATE"
32 STOx "MATV"
33 LBL 01 Begin creating MATK = I (Identity matrix)
34 INDEX "MATK"
35 Rup Place n in X-reg.
36 ENTER
37 ENTER Start in lower rh corner (element n,n)
38 LBL 00
39 STOIJ
40 1
41 STOEL Store 1 in element |, J = |
42 Rdn
43 DSE ST Y Decrement i and j pointers
44 DEG
45 DSE ST X
46 GTO 00 If 1,)J not O then repeat
47 FC? 01
48 GTO "ACAP" Go to AC Analysis Program
49 GTO "DCAP" Go to DC Analysis Program
50 END

Page 25
As an introduction, a DC analysis example will be glven first.
The ladder network on page 4 will be analyzed with resistors for
the impedances Z2: thru Za.

Generally speaking, a circuit under analysis has component

designations such as R:., Cz, La, Ra, etc. Thus we can
store R: in numbered register 01, Cz in reg. 02, etc. This
keeps alot of clutter out of the variable catalog and provides
easy assoclation of registers vs. components.

Circults analyzed here will have less than 15 components, Sso

the numbered registers can be SIZEd to 15. This will leave
room for some scratch storage 1f needed.

Example{ (DC) Ladder Network

First, the main program "DCAP" will be listed so that the program
flow can be demonstrated.

Listing Comments

01 LBL "DCAP"
02 XEQ "SKF" Store K Factors subprogram. Creates and
gstores all the required K factors. For the
DC ladder network, this will be K., K=,
and Ks (see page 4).

03 XEQ "MAT" Form the n x n K-matrix, the n x {1 E-vector,

and solve for the n x 1 V-vector containing
the node voltages.

04 LBL 01
05 INPUT "Vn" Choose which node voltage to display

06 XEQ “"GETV" This subprogram recalls and displays the

node voltage selected in line 05.

07 STOP Display node voltage

08 GTO 01 Select another node if desired
09 END

Before going any further, the following resistor values for the
ladder network should be stored in the corresponding numbered
registers:

1000 STO 01 <(R:)>

2000 STO 02 (R=2)
3000 STO 03 (Ra>
4000 STO 04 (Ra>

Also store 10 in "E1", so that the input voltage is 10 V.

Page 26
The first subprogram encountered is "SKF", which is given below:

Listing Comments

01 LBL "SKF"
02 RCL 01
03 RCL 02
04 RCL 03 Create K,
05 XEQ "pPzZ3" Get P = R://Rz2//R>
06 ENTER
07 RCL/ 01 K: = P/Rx
08 STO "K1*
09 Rdn
10 RCL/ 03 K= P/Ras
11 STO "K2"
12 RCL 03
13 RCL 04
14 XEQ "F2" Cet Ka
15 STO "K3"
16 END

Now the HP-42S has created all three K factors and we are ready
to fill the 2 x 2 K-matrix, and the 2 x 1 E-vector shown on
page 5, with the subprogram "MAT":

Listing Comments

01 LBL "MAT"
02 INDEX "MATK" Pointers at i = §j = 1.
03 J+ Skip to element 1:2, since "SETUP" already
has put 1/s on the main diagonal.
04 RCL "K2"
0S5 +/-
06 ra Put -K=- at 1:2
07 RCL "K3"
08 +/-
09 ra Put -Ks at 2:1
10 INDEX "MATE"
i1 RCL "E1" Input voltage = 10 V
12 RCLx "K1*"
13 da Put E:K, at 1:1
14 RCL "MATE"
1S5 RCL/ "MATK" Get node voltage vector
16 STO "MATV"
17 END

Page 27
Note that lines 01, 02, 10, and 14 thru 17 must be included for every
circuit to be analyzed. Thus the general format for every "MAT"
subprogram is:

01 LBL "MAT"
02 INDEX "MATK"

(fill K matrix)

INDEX "MATE"

(fill E vector)

RCL "MATE"
RCL/ "MATK"
STO "MATV"
END

The last subprogram run by the main program "DCAP" is "GETV",

which Is given below:

Listing Comments

01 LBL "GETV"
02 INDEX "MATV"
03 RCL "vVn" Vn = the selected node voltage, which is the
numbered column element of the node voltage
vector "MATV"
04 1
0S5 STOIJ Store Vn:1 pointer
06 RCLEL Get Vn
07 END

Page 28
Now the DCAP program is ready to run; but we must first execute
"SETUP" before analyzing any circuit:

XEQ "SETUP".

Choose DC (the LOG key) when the menu appears. In response to

Order?, key in the order of the K matrix, which is 2 for this
example:

2, R/S. The display should then be:

Y: [ 2x1 Matrix 1
vn? Cany)

For Vn?, key in 2 to get the voltage at node 2:

2, R/S. Vz should = 3.478 (volts) as disgsplayed in the X-reg.

Repeat for node 1: R/S, 1, R/S. V. should = 6.087 (volts).

As a check, Ki: = 0.545; Kz = 0.182; Ka = 0.571.

Example{ (<(AC) Ladder Network

AC analysis is performed by the main program "ACAP", which is listed

below:

Page 29
 Listing Comments

01 LBL "ACAP"
02 " Log Fi"
Log:io beginning frequency in Hz
03 PROMPT
04 STO " Fll

05 INPUT "PD" = points per decade of frequency

06 INPUT "ND" ND = number of decades
07 RCL+ " Fll
Add beginning frequency to get
08 STO “FL" ending or last frequency point
09 INPUT "Vn" Node to be analyzed
10 RCL "F" To convert F1 to radians/sec ("w")
11 LBL 00
12 10°X Get F from Log F
13 2
14 Pl
15 X
16 X
17 STO " w"
Store radians/sec
18 XEQ " SKF" Store K Factors subprogram (same as "DCAP")
19 XEQ "MAT" Create & solve matrices (same as "DCAP")
20 XEQ "GETV" Get node voltage selected by "Vn" input
21 -> POL Convert to polar form
22 COMPLEX complex -> real
23 XY Put magnitude in X-reg
24 LOG Convert to dBV. Lines 24 thru 26 can be deleted
25 20 if volts are desired.
26 X
27 FIX 02 Begin display setup
28 CLA
29 ARCL "F"
30 ’__ " i\
Append space
31 FIX 03 Display format for dBV
32 ARCL ST X
33 Rdn
34 FIX 00 For phase angle is deg
35 RND
36 F__ “ "

37 ARCL ST X
38 AVIEW Set flag 21 to stop
39 RCL "PD"
40 1/X
41 STO+ " Fll
Increment frequency
42 RCL "FL"
43 RCL " Fll

44 X<LY?
45 GTO 00 Repeat if not done
46 FIX 03
47 END

Page 30
As an introduction to an AC analysis, the ladder network analyzed in
the DC analysis will have the components changed as fol lows:

Reference Stored in
Element Designator New AC value Register

21 R1 10 K ohms 01
22 c2 0.01 uF 02
23 R3 10 K ohms 03
24 C4 0.01 uF 04
E1 E1l 1 "E1"

These values should now be stored in the registers shown above.

Since the matrix on page 5 has the same form whether real or
complex (DC or AC), subprogram "MAT" does not have to be modified
from the DC analysis. Only "SKF" must be modified as shown below:

Listing Comments

01 LBL "SKF"
02 RCL 02
03 XEQ *"XC" Get 22 = 0 - j/wC=
04 STO "z2"
05 RCL 04 Do the same for Ca
06 XEQ "XC"
07 STO "24"
08 RCL 01 Z: = R,
09 RCL "z2"
10 RCL 03 2 = Ra
11 XEQ "PZ23" Get P = R.//22//R>
12 ENTER
13 RCL/ 01 K: = P/R;
14 STO "Ki*
15 Rdn
16 RCL/ 03 Kz = P/Re
17 STO "K2"
18 RCL 03
19 RCL "24"
20 XEQ "F2"
21 STO "K3" The K factors are now all complex
22 END

After keying in "SKF" above, we are ready to start the AC analysis

of the ladder network, which has now become a 2-pole low-pass
passive filter. Agaln, always execute "SETUP" prior to analyzing
any new circuit:

XEQ "SETUP"; choose AC from the menu, and the order is still 2.

Page 31
We will select a frequency sweep of from 100 Hz to 100 KHz at 10
points per the 3 decades: 1In response to the "Log F1" prompt,
key in 2 (log 100 = 2).

In response to PD?, key in 10 (points per decade); and in response

to ND?, enter 3 (decades); for Vn?, we still want to look at node
2, 8o key in 2, R/S.

A sample of the outputs you should have obtained is shown below:

Log F dBV Deg

2.00 -0.118 -11

2.10 -0.186 -13
2.20 -0.292 -17

2.80 -3.273 -55 (Approximate 3 dB breakpoint)

4.00 -32.638 -154 (Approximate 3 dB breakpoint)

4.90 -67.939 -177

5.00 -71.935 -177 (End of frequency sweep)

The slope of the Bode magnitude at log F = 5 is the dB value at

log F = 4.9 minus the dB value at log F = 5 divided by the
frequency increment of 1/ND or

gslope = (-71.935 - (-67.939)>10 = -39.96 dB/decade

or approximately -40 dB/decade. This is what would be expected

for a two pole low-pass filter well beyond the second pole
frequency.

Example 4, the lattice network is omitted.

Page 32
Example5. Twin-T Network

Step 1. Store the following values in the registers indicated:

Reference Stored in
Element Designator New AC value Register

21 C1 0.01 uF 01
22 R2 133 K 02
23 C3 0.01 uF 03
24 R4 267 K 04
25 CS 0.02 uF 05
26 R6 267 K 06
27 R7 10 Meg 07
E1l El 1 "E1"

Step 2. Clear the previous "SKF" and "MAT" programs, and key in the
following new ones given without comments: (see page 8)

01 LBL "SKF" 01 LBL "MAT"

02 RCL 01 02 INDEX "MATK"
03 XEQ "XC" 03 J+
04 STO "21" 04 J+
05 RCL 03 05 RCL "K2"
06 XEQ "XC* 06 +/-
07 STO "23" 07 ra
08 RCL 05 08 J+
09 XEQ "XC" 09 J+
10 STO "25" 10 RCL "K4"
11 RCL "21" 11 +/-
12 RCL 02 12 ra
13 RCL "23" 13 RCL "K5"
14 XEQ "P23" 14 +/-
1S ENTER 15 ra
16 RCL "Ke"
16 RCL/ "21" 17 +/-
17 STO "K1" 18 ra
18 Rdn 19 INDEX "MATE"
19 RCL/ "23" 20 RCL "E1"
20 STO "K2" 21 RCLx "K1i"
21 RCL 04 22 da
22 RCL "25" 23 RCL "K3"
23 RCL 06 24 da
24 XEQ "pz3" 25 RCL "MATE"
25 ENTER 26 RCL/ MATK"
27 STO "MATV"
26 RCL/ 04 28 END
27 STO "K3"
28 Rdn
29 RCL/ 06

Page 33
30 STO "K4"
31 RCL "23"
32 RCL 06
33 RCL 07
34 XEQ "PZ23"
35 ENTER
36 RCL/ "23"
37 STO "KS5"
38 Rdn
39 RCL/ 06
40 STO "Keé"
41 END

The given component values are for a 60 Hz notch filter. Hence we want
to look at one decade between 10 and 100 Hz. Twenty points should be
enough, therefore execute the following:

XEQ "SETUP"; choose AC; Order? 3, R/S, Log F1?, 1, (log 10 = 1), R/S,
pPD?, 20, R/S, ND?, 1, Vn?, 3, R/S. Output samples are:

Log F dBV Deg

1.00 -2.046 -34

1.80 ;31.184 90 (the notch)

2.00 -11.777 76

To see what the output is at exactly 60 Hz: XEQ "ACAP", Log F17?, 60,
LOG, (see 1.778>), R/S, PD?, 1, R/S, ND?, 0, Vn?, 3, will glve Just
one output at log 60 Hz = 1.778:

1.78 -51.048 100

which verifies the notch filter design.

For the remaining circuits, just component values, listings

for "SKF" and "MAT", output sample points to verify the analysis,
and a schematic iIf necessary will be provided. Be sure to
execute "SETUP" prior to analyzing each new circuit. The
"Order?" can be obtained by inspection of the corresponding
K-matrix in section I.

Page 34
Example7. Common Emitter Hybrid Pi Transistor Model

The circult used for the analysis is shown below:

—=
u v, (Collector)
*
L |

gnv, §R7
(Emltter

Note that 21 ---> R1; 22 ---> R2//C3; 23 ---> R4//CS; and

24 ---> R6//R7. (See page 11.)

Component storage:

Reference Stored in
Element Designator Value Register

Gm GM 0.025 00
21 R1 100 01
22 R2 1 K 02
22 C3 100 pF 03
23 R4 4 Meg 04
23 CS 3 pF 0S5
24 R6 80 K 06
24 R7 10 K 07
E1l E1l 1 Not stored

Listing for "SKF" and "MAT":

01 LBL "SKF" 01 LBL "MAT"

02 RCL 02 02 INDEX "MATK"
03 RCL 03 03 J+
04 XEQ "PRC" 04 RCL "K2"
05 STO "z22" 0S5 +/-
06 RCL 04 06 ra
07 RCL 05 07 RCL "P1"
08 XEQ "PRC" 08 RCLx 00
09 STO "2Z23" 09 RCL- "K3"
10 RCL 06 10 ra

Page 35
11 RCL 07 11 INDEX "MATE"
12 XEQ "PpPzZ2" 12 RCL "Ki*
13 STO "Z24" 13 da
14 RCL 01 14 RCL "MATE"
15 RCL 22" 15 RCL/ "MATK"
16 RCL "2Z23" 16 STO "MATV"
17 XEQ "pZ3" 17 END
18 ENTER
19 RCL/ 01
20 STO "K1i*
21 Rdn
22 RCL/ "23"
23 STO "K2"
24 RCL "23"
25 RCL "Z24"
26 XEQ "Ppz2"
27 STO "p1"
28 RCL/ "23"
29 STO "K3"
30 END

Output samples for node 2:

Log F dBV Deg

3.00 46.045 180

6.20 43.336 136 (3 dB rolloff point)

8.15 -0.222 18 (Gain-bandwidth-product % 1, or f+

= 10°8.15 = 141.3 MHz.)

Example Inverting op-amp

Reference Stored in
Element Designator Value Register

21 R1 10 K RO1
22 R2 15 K RO2
23 R3 1 K RO3
23 C4 0.015 uF R0O4
24 RS 15 K ROS
E1l E1l 1 Not stored

To illustrate the affects of op-amp rolloff, change line 06 in

program "OPAMP" to: 06 10ES6.

Since we desire the output V=, the matrix gliven on page 13 |is
recreated without the substitution Vs = -AV,:

Page 36
 1 -K=z 0 V. E: K,

-Ka 1 ‘K4 Vz = 0

A 0 1 Va 0

(An alternative method i3 to solve the original matrix for V. and

modi fy "GETV" to multiply V, by -A.)

Listing for "SKF" and "MAT":

01 LBL "SKF" 01 LBL "MAT"

02 RCL 03 02 INDEX "MATK"
03 RCL 04 03 J+
04 XEQ “"SRC" 04 RCL "K2"
0S5 STO "23" 0S5 +/-
06 1 06 ra
07 RCL 01 07 J+
08 RCL 02 08 RCL "K3"
09 XEQ "F2" 09 +/-
10 STO "K1" 10 ra
11 - 11 J+
12 STO "K2" 12 RCL "K4"
13 RCL 02 13 +/-
14 RCL "23" 14 ra
15 RCL 05 1S5 RCL "A"
16 XEQ "pP23" 16 ra
17 ENTER 17 INDEX "MATE"
18 RCL/ 02 18 RCL "K1"
19 STO "K3" 19 da
20 Rdn 20 RCL "MATE"
21 RCL/ 05 21 RCL/ "MATK"
22 STO "K4" 22 STO “"MATV"
23 XEQ "OPAMP" 23 END
24 END

As can be seen from the above 3 x 3 K-matrix, the order is 3 when

executing "SETUP".

Some output points for node 3 are:

Log F dBV Deg

1.00 9.539 -180 (DC gain of 30K/10K in dBV. =180 since this
is an inverting opamp circuit.
6.00 28.094 -179 (Gain lncrease due to feedback T network.)

Now change line 06 of "OPAMP" to: 06 100

This gives an opamp pole of 100 Hz, which is more realistic. The
output at node 3 is now:

Page 37
Log F dBV Deg

1 .00 9.539 -180 (No change.)

6. 00 -4.231 91 opamp 1S not capable of high gain at

10° 6 = 1 MHz.)

Example2 Adjustable Gain Differential Amplifier

(Reference 2. >

Reference Stored in
El ement Desjgnator Val ue Register

21 R1 RO1

RRXRARRRR®
22 R2 RO2
23 R3 RO3
24 R4 RO4
25 RS ROS
26 R6 RO6
27 R7 RO7
E1 E1 " E1 "

E2 E2 " Ezn

Ll sting for "SKF" and "MAT":

01 LBL "SKF" 01 LBL " MAT "
02 1 02 INDEX "MATK"
03 RCL 01 03 J+
04 RCL 02 04 RCL n Kzu

05 XEQ "F2" 05 +/-

06 STO "K1" 06 ra
07 07 J+
08 STO "K2" 08 J+
09 RCL 02 09 J+
10 RCL 03 10 RCL " K3ll

11 RCL 04 11 +/-
12 XEQ "pP23" 12 ra
13 ENTER 13 J+
14 RCL/ 02 14 RCL NK4II

15 STO “"K3" 15 +/-

16 Rdn 16 ra
17 RCL/ 03 17 J+
18 STO "K4" 18 RCL " Ksu

19 Rup 19 +/-
20 1 Using 20 ra
21 XY K3+K4+K5=1 21 RCL " A"

22 22 ra
23 XY 23 J+
24 24 J+
25 STO "K5" 25 RCL " All

Page 38
26 1 26 +/-
27 RCL 05 27 ra
28 RCL 06 28 J+
29 XEQ "F2" 29 J+
30 STO "Ke" 30 J+
31 - 31 J+
32 STO "K7" 32 J+
33 RCL 06 33 RCL "K7"
34 RCL 04 34 +/-
35 RCL 07 35 ra
36 XEQ "PZ3" 36 J+
37 ENTER 37 RCL "K9"
38 RCL/ 06 38 +/-
39 STO "K8" 39 ra
40 Rdn 40 J+
41 RCL/ 04 41 RCL "K8"
42 STO "K9" 42 +/-
43 XEQ " OPAMP" 43 ra
44 END 44 INDEX "MATE"
45 RCL "Ei"
46 RCLx "K1i"
47 da
48 1+
49 I+
S50 RCL "E2"
51 RCLx "Ke6"
52 da
53 RCL "MATE"
54 RCL/ MATK"
S5 STO "MATV"
S6 END

Though all components are real (resistive), the opamp has an AC

rolloff component, so when executing "SETUP", choose AC. From
page 14, the order s 5.

We will examine the affects of gain setting resistor R4 at 10 Hz:

(Node 3)

Log F dBV Deg R4 value

1 21.579 -180 1 K

1 16.476 180 3 K

1 20.001 180 1.332 K

The last setting of R4 gives an output of -10 V.

Page 39
(Example 10, Non-linear circult, will be covered after example 12.)

Example11, Flfth Order Active Fllter

Reference Stored in
Element Designator Value Register

21 C1 0.03 uF RO1
22 R2 2.0 K RO2
23 R3 70 K RO3
24 C4 0.02 uF RO 4
25 CS 1.9 nF ROS
26 R6 140 K RO6
27 c7? 0.01 uF RO7
28 R8 12 K RO8
28 co 0.4 nF RO9
29 R10 2.7 K R10
210 R11 3.2 K R11
211 R12 10 K R12
E1l E1l 1 Not stored

Listing for "SKF" and "MAT":

01 LBL "SKF" 0if LBL "MAT"

02 RCL 01 02 INDEX "MATK"
03 XEQ "XC* 03 J+
04 STO "21" 04 RCL "K2"
05 RCL 04 0S +/-
06 XEQ "XC" 06 ra
07 STO "Z4" 07 J+
08 RCL 05 08 RCL "K3"
09 XEQ "XC" 09 +/-
10 STO "2Z5" 10 ra
11 RCL 07 11 J+
12 XEQ "XC" 12 J+
13 STO “27" 13 RCL "K4"
14 RCL 08 14 +/-
15 RCL 09 15 ra
16 XEQ "PRC" 16 J+
17 STO "28" 17 RCL "KS"
18 RCL "21" 18 +/-
19 RCL 02 19 ra
20 RCL 03 20 J+
21 RCL "24" 21 J+
22 XEQ "PzZ4" 22 J+
23 ENTER 23 J+
24 ENTER 24 RCL "Keé"
25 RCL/ "21" 25 +/-
26 STO "K1" 26 ra
27 Rdn 27 J+

Page 40
28 RCL/ 03 28 RCL "K7"
29 STO "K2" 29 +/-
30 Rdn 30 ra
31 RCL/ "Z24" 31 J+
32 STO "K3" 32 J+
33 RCL 03 33 RCL "Kk8"
34 RCL 06 34 +/-
35 RCL "25" 35 ra
36 XEQ "PpPZ23" 36 J+
37 ENTER 37 RCL "Ko"
38 RCL/ 03 38 +/-
39 STO "K4" 39 ra
40 Rdn 40 J+
41 RCL/ 06 41 J+
42 STO "K5" 42 RCL "K1io0"
43 RCL 06 43 +/-
44 RCL “27" 44 ra
45 RCL "2Z8" 45 S
46 XEQ "PZ3" 46 6
47 ENTER 47 STOIJ
48 RCL/ 06 48 RCL "K1i1"
49 STO "Ke" 49 +/-
S50 Rdn S0 ra
51 RCL/ "Z27" 51 J+
52 STO "K7" 52 J+
53 RCL "24" 53 RCL "A"
54 RCL "27" 54 +/-
55 RCL 10 55 ra
56 XEQ "pPzZ3" 56 J+
57 ENTER 57 RCL "A"
58 ENTER 58 ra
59 RCL/ "24" 59 INDEX "MATE"
60 STO "K8" 60 RCL "K1i*
61 Rdn 61 da
62 RCL/ "27" 62 RCL "MATE"
63 STO "K9o" 63 RCL/ "MATK"
64 Rdn 64 STO "MATV"
65 RCL/ 10 65 END
66 STO "Ki10"
67 RCL 11
68 RCL 12
69 XEQ "F2"
70 STO "Ki1"
71 XEQ "OPAMP"“
72 END

In "OPAMP", be sure that line 06 is: 06 100; and line 09 is: 09 1E4.

From page 17, the order is 6, and from page 16 we want to look at
node 6. Some outputs at node 6 are:

Page 41
Log F dBV Deg

2.00 -51.890 84

2.70 -55.156 -107

2.80 -37.701 -122

3.60 2.553 64

6.00 -2.610 -52

The area between log F = 2.0 and log F = 3.6 should show an
elliptical response with a very steep climb to the peak value
at log F = 3.6. The slope between log F = 2.7 and log F = 2.8 is:

-37.701 - (-55.156) 17.455

e = —mmeee = 174.55 dB/decade.

which indicates a very sharp high pass response.

Example12 Complementary Feedback Amplifier

Reference Stored in
Element Designator Value Register

21 R1 200 RO1
22 R2 1 K RO2
23 R3 0.1 RO3
24 R4 10 K RO4
25 RS 1.5 K ROS
26 R6 300 RO6
27 R7 5.1 K RO7
E1l E1l + 15 V "E1"
E2 E2 - 15V "E2"
E3 E3 + 5V "E3*
B1 Bi 100 “Bi"
B2 B2 100 "B2"

Page 42
Listing for "SKF" and " MAT " :

01 LBL "SKF" 01 LBL "MAT" 49 J+

02 RCL 02 02 INDEX "MATK" S0 J+
03 RCL 03 03 1 51 RCL "B2"
04 XEQ “"PZ2" 04 8 S2 RCLx "P3"
05 STO "P1" 05 STOI1J S3 +/-
06 ENTER 06 1 54 STOEL
=
07 RCL/ 02 07 RCL+ "B2" S5
08 STO "Ki* 08 RCLx 01 56 4
09 Rdn 09 STOEL 57 STOIJ
10 RCL/ 03 10 I+ S8 1
11 STO "K2" 11 RCL “Pl“ 59 STOEL
12 RCL 05 12 +/- 60 J+
13 RCL 07 13 STOEL 61 +/-
14 XEQ "pz2" 14 2 62 STOEL
15 STO "p2* 15 3 63 J+
16 ENTER 16 STOIJ 64
17 RCL/ 05 17 RCL "K2"
18 STO "K3" 18 +/- 66
19 Rdn 19 STOEL 67
20 RCL/ 07 20 I+ 68
21 STO "K4" 21 69
22 RCL 06 22 70
23 RCL 07 23 71
24 XEQ “"pz2* 24 72
25 STO "P3" 25 73 +/-
26 ENTER 26 STOIJ 74 STOEL
27 RCL/ 06 27 RCL "B1" 75 8
28 STO "KS5" 28 RCLx 03 76 1
29 Rdn 29 STOEL 77 STOI1J
30 RCL/ 07 30 1+ 78 STOEL
31 STO "Ke" 31 RCL 04 79 J+
32 END 32 STOEL 80 +/-
33 1+ 81 STOEL
34 1 82 8
35 RCL+ "B1" 83 ENTER
36 RCLx "p2* 84 STOIJ
37 +/- 85 0
38 STOEL 86 STOEL
39 J..
87 INDEX "MATE"
40 RCL " K4“ 88 RCL " E1 "

41 +/- 89 da
42 STOEL 90 RCL "E1"
43 1+ 91 RCLx “K1*
44 J_
92 da
45 RCL " Ksu 93 I+
46 +/- 94 RCL " Eall

47 STOEL 95 da
48 J+ 96 RCL " Ezn

Page 43
Listing for "MAT" Cont’:

97 RCLx "K3"
98 da
99 RCL "E2"
100 RCLx "K5"
101 da
102 0.6
103 da
104 0.6
105 da
106 RCL "MATE"
107 RCL/ "MATK"
108 STO "MATV"
109 END

Using STOIJ and STOEL function names for large, sSparse matrices
will result in a shorter listing for "MAT".

Execute "SETUP", DC, Order? = 8. The node voltages and currents are
given below in FIX 03 format:

Vi = 3.860 V6 = 3.171
vz = 3.260 Vé = 1.636
V3 = 3.258 Ibl = 1.229E-4 (7:1)
V4 = 3.771 Ib2 = 0.001 (8:1)

For an AC analysis of this circuit, It 18 suggested that the

CE hybrid pi high frequency model be substituted for the simple
linear DC model used here. A more accurate non-1inear model
can be created by using the diode equations In reference S and
the Ebers-Moll models in reference 6.

Example10 Non-linear Circult.

(See reference 3.)

Reference Stored in
Element Designator Value Register

21 R1 3 K 01
22 R2 2 K 02
23 R3 2 K 03
24 R4 3 K 04
25 RS 10 K 05
26 R6 10 Meg 06 (Initial value)
27 R7 10 Meg 07 " "
Ei El +5 "E1"
E2 E2 -5 "E2"

Listing for SKF" and “"MAT":

Page 44
01 LBL "SKF* 01 LBL "MAT"
02 RCL 01 02 INDEX "MATK"
03 RCL 02 03 J+
04 RCL 06 04 J+
05 XEQ "pPz23" 05 RCL "K3"
06 ENTER 06 +/-
07 ENTER 07 ra
08 RCL/ 01 08 J+
09 STO "Ki" 09 J+
10 Rdn 10 RCL "Ke"
11 RCL/ 02 11 +/-
12 STO "K2" 12 ra
13 Rdn 13 RCL "K7"
14 RCL/ 06 14 +/-
15 STO "K3" 15 ra
16 RCL 04 16 RCL "K8"
17 RCL 03 17 +/-
18 RCL 07 18 ra
19 XEQ "pzZ3" 19 INDEX "MATE"
20 ENTER 20 RCL "E1"
21 ENTER 21 RCLx "Ki1*"
22 RCL/ 04 22 RCL "E3"
23 STO "K4" 23 RCLx "K2"
24 Rdn 24 +
25 RCL/ 03 25 da
26 STO "KS5" 26 RCL "E2"
27 Rdn 27 RCLx "K4"
28 RCL/ 07 28 RCL "E3"
29 STO "Ké" 29 RCLx "KS"
30 RCL 06 30 +
31 RCL 07 31 da
32 RCL 05 32 RCL "MATE"
33 XEQ "pzZ3" 33 RCL/ "MATK"
34 ENTER 34 STO "MATV"
35 RCL/ 06 35 END
36 STO "K7"
37 Rdn
38 RCL/ 07
39 STO "K8"
40 END

In order to see the affect of a varying input voltage E3 and

to change the "diode" resistor values if forward or reverse
biased, a different main program is required which will be
labled "VSWP" for "voltage sweep". This main program is
similar in structure to "ACAP" and is given below with
comments:

Page 45
01 LBL "“VSwP"
02 CF 01 (Diode ON/OFF flag)
03 10E6
04 STO 06 (Initial values)
05 STO 07
06 -16 (Sweep starts from -16 V)
07 STO "EL" (Left voltage)
08 LBL 00
09 STO "E3" (Varying input voltage)
10 XEQ " SKF"
11 XEQ "MAT"
12 1
13 STO "vn"
14 XEQ "GETV" (Get V1)
15 STO 11
16 3
17 STO *“vn"
18 XEQ "GETV" (Get V3)
19 STO 13
20 CLA (Display setup)
21 FIX 00
22 ARCL "E3"
23 I_ll "
(Append space)
24 FIX 03
25 ARCL 13
26 AVIEW (E3 V3)
27 RCL 11
28 XY
29
30 X<0? (V3 - V1 < 0 => D6 is OND
31 SF 01
32 10 (ON resistance)
33 10E6 (OFF resistance)
34 FS?C 01
35 XY
36 STO 06
37 2
38 STO "vn"
39 XEQ "GETV" (Get V2)
40 RCL- 13
41 X<07? (V2 - V3) < 0 => D7 is OFF
42 SF 01
43 10E6
44 10
45 FS?C 01
XY
47 STO 07
48 1
49 STO+ "“EL" (Increment input voltage)
S0 16

Page 46
51 RCL "EL"
52 X#AY? (Stop at +15 W
S3 GTO 00 (Repeat)
54 END

In "SETUP", temporarily change line from 48 GTO "DCAP" to

48 GTO "VSWP". Execute "SETUP", choose DC, and from page 15
the order must be 3, since we are analyzing three nodes,
Vi, Vz, and Vs.

The output from -15 V to +15 V |s shown below: <(Ignore the first
out put at E3 = -16 V, since this step determines which diode
sho uld be turned on.)

E3 V3

-6.245
-5.710
-5.174
-4.639
-4.104
-3.569
-3.033
-2.498
-1.963
-1.428
-0.893
-0.357 Begin dead zone
0.178 i.e., both diodes OFF
-0.002
-0.001
0.000
0.001
0.002
0.004
0.005 End dead zone
0.893
1.428
1.963
2.498
3.033
3.569
4.104
4.639
5.174
5.710
6.245

Page 47
The "glitch" at E3 = -3 V, is due to the discrete 1 V steps in ES3.
Ideally, the program should be structured so that smaller steps
such as 0.1 V, are applied to the circuit and the output displayed
only at 1 V or 2 V intervals. The "glitch" would then disappear
since the program would more closely simulate the actual circuit
where E3 is continuous. However, this i1s not necessary Ssince
the actual circuit operation can be understood using 1 V
increments.

Page 48
 APPENDIX

I. Ladder Network Analysis

All circuits analyzed so far have used matrices for the

solution form. Ladder networks lend themselves to a more
efficient solution form which will run faster.

Given the 4 L-section ladder network shown below:

Let Be = 1/2¢

B« 1/26 + 1/C(2> + 1/Be)

Ba = 1/24 + 1/(2=s + 1/Bg)

Bz = 1/22 + 1/(2a + 1/Ba)

Then

Vi/Va =1 + 2.:B=

V2/Va = 1 + Z23Ba

Va/Va = 1 + Z2sBs

Va/Vs = 1 + 25Be

Finally V./Vs =

(1 + 2,B=2)(1 + Z3Ba)(1 + 2sB4)(1 4+ 2-Be)

Taking the inverse will give the transfer function Vs/V,.

Page 49
For output Iimpedance Zo:

20 = 2&//C2> + 2&4//C2s + 24//C22 + 2:1//22)))

Or by chained fractions:

Let Az = 1/22 + 1/2.

Aa = 1/24 + 1/(2a + 1/A2)

As = 1/24 + 1/2=s + 1/A4)

Ae 1/2e + 1/(2> + 1/A&)

20 = 1/Ae, and similarly for the input impedance Zin.

The ladder network shown below will be analyzed using the

above expressions for the output voltage. The circuit
is a model of a high frequency transformer. (Ref. 4)
The topology Is a 3 L-sectlion ladder network.

Z1 Z3
f——/;_\ A ~ /-

R R L R
Vf} VNV 2 ”VV%. - -3 a ‘JQV

\_V__/ —— ——

Page 50
Although "SKF" and "MAT" may now be lnappropriately named,
they are retained for the sake of consistency. The high
frequency transformer model can be analyzed faster with
the followlng routines than the matrix format used previously.

Store the following values in the registers indicated:

Reference Stored in
Element Designator New AC value Register

21 R1 10 01
22 Cc2 20 pF 02
23 R3 1.5 03
23 L4 1 uH 04
24 RS 20 K 05
24 L6 2 mH 06
25 R7 1.5 07
Z5 L8 1 uH 08
26 R9 1 K 09
26 C10 20 pF 10

Listing for "SKF" and "MAT":

01 LBL "SKF" 01 LBL "MAT"

02 RCL 02 02 RCL *26"
03 XEQ "XC" 03 RCL+ "25"
04 STO "22" 04 1/X
05 RCL 03 05 RCL "24"
06 RCL 04 06 1/X
07 XEQ “SRL" 07 +
08 STO "23" 08 STO "B4"
09 RCL 05 09 1/X
10 RCL 06 10 RCL+ "23"
11 XEQ "PRL" 11 1/X
12 STO "24" 12 RCL "22*
13 RCL 07 13 1/X
14 RCL 08 14 +
15 XEQ "SRL" 15 STO "B2"
16 STO "25" 16 RCL "25"
17 RCL 09 17 RCL/ "“Ze6"
18 RCL 10 18 1
19 XEQ "PRC" 19 +
20 STO "26" 20 RCL "B4"
21 END 21 RCLx "zZ3"
22 1
23 +
24 x
25 RCL "B2"
26 RCLx 01
27 1
28 +

Page 51
 29 X
30 1/X
31 END

The program "ACAP" must be modified sllghtly since we are not lookling
for an element of the "MATV" vector. Delete or flag around
l1ine 20 XEQ "GETV", and lgnore the Vn? prompt. Some outputs
of the transformer model are given below:

Log F dBV Deg

2.00 -19.296 84 (Low frequency response)

S5.00 -0.122 0 (Mid-band response)

7.40 8.849 -89 (Resonance peak)

8.00 -23.496 177 (High frequency rolloff)

Note that the resonance peak |8 followed by a sharp rolloff.

Page 52
II. Bullding Branch Impedances with the HP-42S

Branch impedances other tha the simple series and parallel

RC or RL given by the subprograms on page 22 are easy to
construct. For example, for the branch impedance Z1 shown
below R

MW
R3 Cu
4’-—’\/\/\a———* (—-———-0
p R L ( »—J@KAr——4(£§—flo

152
"

the HP-42S sequence is:

RCL 01 RCL 02 XEQ "PRC" RCL 03 RCL 04 XEQ "SRC" XEQ "pz2"

RCL 05 RCL 06 XEQ "SRL" XEQ "PZ2* RCL 07 RCL 08 XEQ "SRC"

+ STO "21"
(Insure that the stack does not fill up and an impedance lost
into the T-register.)

III. Floating Voltage Sources

Floating voltage sources are sometimes required for

diode and transistor models where the value of the
voltage source in series with a resistor iI1s about 0.6V.
Whatever the purpose, they are analyzed as shown in the
example below:

Vv
1
Ef%———figrw

Z),
Z
E3 ei 3

EO- NV &
2 Z2 V2

Page 53
Step 1.

Vi, = E:K: VzKz + (Vz - Ea)Ks or

+
V. = E:1K, Va(Kz + Ka) - EzKa

+
V= = EzKa + VK= 4+ (V. + Ez)K« or

Vz = EzKa + Vi (Ks + K&) + ExKs

Step 3.

1 -(Kz + Ka) Vi E:K:, - EakKa

-(K=s + K<) 1 Va EzKa + EzkKe

where the intermediate step 2. is skipped. Note that node

V: "sees" a voltage of V= - Ea when "looking at" node V=2
via impedance 24. Conversely, node V2 "sees" a voltage of
Vi + Ea when "looklng at" node V. via Z24. Hence the
polarity of the floating source must be observed with care
when writing the node equations.

Page 54
I1V. Designing with K Factors

The following 18 an example of how K factors can be used in

circuit design:

Given the N = 4 star network shown on page 3 where the 2’s

will be assumed all R’s, determine the required resistor
values such that:

Vo = E;K: + EzKz + EzKas + EsxKa

E«:(0.1) + E2€0.2) + Ea(0.3) + Ea0.4)

for any values of E: thru Ea. Note that

Ki + K=+ ,,, + K =1 (1)

for a star network of N branches.

One solution method would be to generate a set of four

gsimultaneous equations from Kirchoff’s Current Law or
Kirchoff’s Voltage Law, for the four unknown resistor
values. However, using K factors allows the simultaneous
equations to be avolided:

Let R, = 1K (or any convenient value), then:

Rz = Ri1K:/Kz = 1000¢0.1>/0.2 = 500 ohms.

Ra = R:Ki1/Ka = 100/0.3 = 333 ohms.

Ra = R:Ki/Ka = 100/0.4 = 250 ohms.

Page 55
For an N = 3 branch, assume the design requirements are:

Ki = 0.2, K2z = 0.25, & Ka = 0.15.

In this case, K + Kz + Ka = 0.6, and to satisfy (1)

above, we must provide a fourth branch with V4 = 0 and

Ka =1 - 0.6 =0.4.

Again letting R: be 1K:

Rz = 1000¢0.2)/.25 = 800 ohms,

R = 200/0.15 = 1333 ohms,

Ra = 200/0.4 = 500 ohms.

The star or summing network 1s useful where the output Vo

s connected to a high Impedance such as non-inverting
op amp or comparator inputs.

Page 56
References:

1. Switchina Waveforms,
Millman & Taub, 1965, p. 7.

2. OperationalAmplifiers.DesiqgnandApplications,
Graeme, Tobey, & Huelsman, 1971, p. 202.

3. IntroductiontoOperationalAmplifierTheory
and Applications, Wait, Huelsman, & Korn,
1975, p. 147.

4. ReferenceDataforRadioEnaineers, Sth Ed., ITT/Sams,

p. 12-1.

S. AlgorithmsforRPNCalculators, Ball, 1978, p. 272.

6. ModelingTheBipolarTransistor, Getreu, 1976,

Tektronix.

Page 57