Lecture 12
Placement IV
VLSI Physical Design Fundamentals
Bach Luong
Tresemi
© Tresemi 2024 VLSI Physical Design Fundamentals 1
Placement Steps
Data Import
Pre- Sanity checks
Floor placement
Planning Global placement
Global route
Detail placement
Placement
Placement
High fanout net synthesis (HFNS)
Scan chain reordering
Design Rule Violation (DRV) fixing
Post-
placement PreCTS timing optimization
CTS
Power and Area optimizations
Tie-cells insertion
Add spare cells
MBFF optimization
Routing
Congestion analysis
Guides to minimize congestion
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 2
Congestion Analysis
Data Import
What is Congestion?
• When then number of routing tracks available for routing at a given location is less than the
Floor number needed, the area is considered congested. Also known as “routing congestion”
Pre-
Planning placement
Horizontal congestion = horizontal available routing tracks - required horizontal routing track
Vertical congestion = vertical available routing tracks - vertical required horizontal routing track
Placement Placement Lower congestion number => better routability
Congestion usually happen in a higher cell density area 28
CTS Post-
placement
22
Routing
Gcell
Data Export
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Congestion Analysis
Data Import
Congestion
Floor Pre-
Planning placement
Placement Placement
Horizontal required routing tracks = 3
Available Horizontal routing tracks = 2
Horizontal Congestion overflow = available routing tracks – required routing tracks
=2-3=1
CTS Post-
placement
Impact of Congestion
Routing
• Detour routing – Lead to long delay, which could cause design timing violations
• Non-routability – Severe congestion can cause design to be non-routable.
Data Export
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Congestion Analysis
Data Import
Congestion Map
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
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Congestion Analysis
Data Import
Congestion Map
• Overflow (horizontal and vertical) score (0% => 100%)
Lower => less congestion
Floor Pre-
Planning Higher => more congestion
placement
> 1% => usually not routable
• Hotspot score (0 => ~)
Placement Placement
Lower => less congestion
Higher => more congestion
> 100 => usually not routable
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 6
Congestion Analysis
Data Import
Congestion Map
• It is critical to minimize congestion at placement stage to maximize design routability
Floor Pre-
Planning placement congestion less congestion least congestion
Placement Placement
CTS Post-
placement
Routing
Data Export
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Congestion Analysis
Data Import
Cause of Congestion
• High standard cell density in a limited region
Floor Pre-
• High standard cell pin density area
Planning placement • Standard cells near macros
• High pin density at the edge of macros
• A poor floor plan
Placement • Poor synthesis
Placement
• Poor PG strategy
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 8
Placement Steps
Data Import
Pre- Sanity checks
Floor placement
Planning Global placement
Global route
Detail placement
Placement
Placement
High fanout net synthesis (HFNS)
Scan chain reordering
Design Rule Violation (DRV) fixing
Post-
placement PreCTS timing optimization
CTS
Power and Area optimizations
Tie-cells insertion
Add spare cells
MBFF optimization
Routing
Congestion analysis
Guides to minimize congestion
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 9
Guides to Minimize Congestion
Data Import
Add placement blockage (hard, partial, soft)
• Add these blockage in congested area to reduce density
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
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Guides to Minimize Congestion
Data Import
Add halo around macro/memory
• Keep out region around macro/memory. No cells are allowed inside this region
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement Halo
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 11
Guides to Minimize Congestion
Data Import
Add cell padding
• Keep out region around a specified standard cell
Floor Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 12
Guides to Minimize Congestion
Data Import
Change placement strategy to congestion driven
• Normally default placement is timing driven. If design is congested and
has enough timing margin where congestion driven can be employed.
Floor Pre-
Planning placement
Placement Placement
Timing driven => minimized wire length
CTS Post-
placement
Routing
Congestion driven => spread out cells to minimize congestion
Data Export
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Guides to Minimize Congestion
Data Import
Update PG
- Sometime congested areas are located where there are too many PG stripes.
Floor
Reduce number of PG stripes to open up tracks for routing.
Pre-
Planning placement - PG grid still need to meet EM and IR requirements
Placement Placement
CTS Post-
placement
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 14
Guides to Minimize Congestion
Data Import
Update floorplan
- There are times when congestion are due to poor floor planning (poor memory placement.
Floor A restart/update floorplan is necessary to resolve congestion.
Pre-
Planning placement
Placement Placement
CTS Post-
placement
Routing
Data Export Congestion regions
© Tresemi 2024 VLSI Physical Design Fundamentals 15
Congestion Analysis
Data Import
Update synthesis to physical aware
• Poor synthesis can also lead to congestion
• Update to physical aware synthesis to include physical information at the start can help minimize
Floor congestion and timing related issues.
/
Planning
Pre-
placement
Floorplan/blockage data
RTL DEF
RTL
Constraints
Constraints
Placement Placement Timing Libs
Timing Libs
Floorplan/blockage/placement data
Synthesis DEF
CTS Post- Synthesis
placement
Physical Netlist Physical
Routing Netlist
Constraints Design
Constraints Design
Reports
Reports
Traditional Synthesis Flow Physical Aware Synthesis Flow
Data Export
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Outputs
Data Import
• Optimized netlist
• Optimized DEF
Floor
• Timing reports
Planning • Power reports
• Congestion maps
Placement
CTS
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 17
Review and Qualify Placement Results
Data Import
• No or minor timing violations
Floor
Planning
Placement
• DRV should be cleaned (except on clock nets)
- Max fanout
- Max cap
CTS - Max transition
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 18
Review and Qualify Placement Results
Data Import • All cells should be placed
- No overlap or unplaced cells (all cells are legalized and placed)
Floor
Planning
Placement
• A routable design (minimal congestion)
- overflow < 1%
CTS
- hotspot < 100
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 19
Review and Qualify Placement Results
Data Import
• Meet power requirements
- Total Power (dynamic, leakage, internal)
Floor
Planning
Placement
CTS
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 20
Review and Qualify Placement Results
Data Import
Summary
• No or minor timing violations
Floor
• DRV should be cleaned (except on clock nets)
Planning - Max fanout
- Max cap
- Max transition
Placement
• All cells should be legalized and placed
- No overlap or unplaced cells
• Routable design (minimal congestion)
• Meet power constraints
CTS
Routing
Data Export
© Tresemi 2024 VLSI Physical Design Fundamentals 21
© Tresemi 2024 VLSI Physical Design Fundamentals
References
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▪ Cadence RAK
© Tresemi 2024 VLSI Physical Design Fundamentals 23
