ECS Journal of Solid State Science and Technology, 3 (5) P115-P121 (2014) P115

2162-8769/2014/3(5)/P115/7/$31.00 © The Electrochemical Society

Temporary Wafer Bonding and Debonding for 3D Integration

Using an Electrochemically Active Polymer Adhesive
Hithesh K. Gatty, Stephan Schröder, Frank Niklaus, Niclas Roxhed,z and Göran Stemme
Micro and Nanosystems, KTH Royal Institute of Technology, Stockholm, Sweden

The use of thin silicon wafers is an enabling technology for 3D integration in the semiconductor industry. However, thin silicon
wafers are fragile to handle and reliable solutions are required for thin wafer handling. This paper reports a novel method of bonding
and debonding a thin wafer (<50 μm) using an electrochemically active polymer adhesive. In the presented method the carrier wafer
is first spin coated with the adhesive and then bonded to the device wafer by applying force and temperature. Debonding of the
wafer is realized at room temperature by applying a voltage between the carrier and the device wafer, which substantially reduces the
bond strength. The bonding and debonding properties of the adhesive show that temporary wafer bonding using electrochemically
active adhesives has the potential to be an attractive approach for temporary wafer bonding for thin wafer handling in 3D integration
processes.
© 2014 The Electrochemical Society. [DOI: 10.1149/2.001405jss] All rights reserved.

Manuscript submitted January 9, 2014; revised manuscript received February 19, 2014. Published March 4, 2014.

Handling of thin (<50 μm) silicon wafers is an emerging technol- using ElectRelease is illustrated in Figure 1. The adhesive is applied
ogy in the semiconductor industry to enable 3D integration, e.g. to to the cathode part, then joined to the anode part and allowed to cure
achieve small-pitch through silicon vias (TSV’s) interconnecting be- at room temperature. A typical voltage in the range of 10–50 V with a
tween 3D tiers. Thin silicon wafers are inherently fragile and difficult current density of approximately 1 mA/cm2 is used for debonding of
to handle due to their flexibility. Thus, a reliable solution is needed aluminum parts.24,25 The debonding mechanism is a result of electro-
to overcome the challenges of handling thin wafers. One possibility chemical decomposition at the anodic surface as has been discussed
to increase the handling robustness is to bond a thick carrier wafer by others.26,27 Recently, we have shown debonding on Al-coated Si
to a thin device wafer. Various methods exist for bonding a device substrates using the ElectRelease polymer.28 In another study related
wafer to a carrier wafer. One of the methods is to spin an adhesive to voltage-assisted polymer bonding with Cytop/PMMA, the influ-
layer on a carrier wafer and bond the device wafer using a wafer ence of an applied voltage during bonding on the bond strength was
bonder tool. Different polymers have been studied for use in adhesive evaluated and it was shown that very high voltages lead to reduced
wafer bonding; including epoxies, thermoplastics and photoresists.1–5 bond strength. However, the involved voltages are much higher than
For temporary bonding in wafer handling applications, both bonding the voltages used for the ElectRelease polymer and different physical
and debonding properties of the adhesive are important. The adhe- mechanisms are involved.29
sive should withstand the mechanical and thermal processes that are In the present work, the ElectRelease H23 adhesive is utilized
part of the, for example, TSV fabrication schemes.6 Moreover, the for temporary wafer bonding of ultra-thin silicon wafers and non-
whole process should be cost effective. An efficient process requires metalized silicon wafers. We present an approach for bonding and
the adhesive to be uniform and it should allow the device wafer to be debonding of a device wafer to a carrier wafer wherein debonding
released from the carrier wafer without any damage.7,8 does not require elevated temperature or solvent based release of the
Several methods have been reported for the debonding of a thin adhesive. The resulting bond strength is evaluated before and after
device wafer from the carrier wafer. In one method, an adhesively applying the voltage. In addition we have investigated the impact of
bonded wafer stack is heated to an elevated temperature at which the debonding process on the native silicon dioxide surface layer.
the adhesive softens and becomes liquid.9–13 The device wafer is
then released by sliding it off from the carrier wafer. However, one
drawback of this method is the high temperature (>200◦ C) needed Wafer Bonding Process
for debonding. Also sliding a thin device wafer from the carrier wafer
may damage the device wafer. In another method, the carrier wafer is A spin coating process was developed for controlled applica-
coated with two types of adhesives having different bond strengths, tion of the ElectRelease adhesive solution onto the carrier wafer.
as for example in the Zone bond technique.14 This technique uses one The standard mixture of the ElectRelease adhesive is too viscous
type of adhesive with low bond strength at the center of the wafer (215 Pa · s) and cannot be spin coated to appropriate thicknesses of a
and another type of adhesive with higher bond strength at the edge few microns. Hence, the electrochemically active polymer was diluted
of the wafer. The adhesive with higher bond strength is removed by a with a solvent to reduce its viscosity to enable wafer spin coating. Cy-
solvent treatment followed by debonding of the device wafer. However clopentanone (CPT) was found to be a suitable solvent for this type of
for bonding and debonding of the wafers, several time consuming electrochemically active adhesive as it did not alter the electrical and
processing steps are required. Laser ablation of a polymer sacrificial chemical properties of the adhesive. Different mixture ratios between
layer is another method in temporary wafer handling.15–18 This method ElectRelease and CPT were evaluated to find the best ratio and to
has also been used in controlled transfer of dies between two wafers obtain the target thickness for the coating.
using, e.g. polyimide or PET as an adhesive for manufacturing low– Figure 2 shows the thickness of the adhesive as a function of the
cost AFM devices.19,20 spin speed for different mixture ratios. The mixture ratio of 71.2%wt
The method presented in this paper uses an electrochemically : 11.8%wt : 17%wt (resin:hardner:CPT) was found to be a suitable
active thermosetting polymer adhesive known as ElectRelease H23 composition for spinning the adhesive on the wafer and was used for
(EIC laboratory, USA). It was developed for electrically controlled further evaluation experiments. A higher percentage of CPT in the
debonding of bonded aluminum parts. This technique is used in mixture ratio resulted in a low viscosity solution, leading to a thin
food and beverage packaging industries and for interactive packaging (<2 um) adhesive layer. However, too thin layers increased the risk
solutions.21–23 The adhesive is a two component mixture where one of short circuiting of the two wafer electrodes. The spin coated wafer
component is the base or ‘resin’ and the second the hardener or ‘activa- was soft baked at 80◦ C for 1 min on a hot plate before measuring
tor’. The basic principle of bonding and debonding of aluminum parts the thickness and uniformity of the coatings using a surface profiler
(Tencor-P10). For each spin speed the thickness of the adhesive was
measured at five points on the wafer. Bonding of the device and carrier
z
E-mail: [email protected] wafer was carried out after spin coating of the adhesive on the carrier
P116 ECS Journal of Solid State Science and Technology, 3 (5) P115-P121 (2014)

ElectreleaseTM
Aluminum H23 Aluminum
anode cathode

+ -

Bonded aluminum substrates Debonded aluminum substrates

before applying a voltage after applying a voltage
Figure 3. Illustration of the fabrication process flow for bonding a device
Figure 1. Illustration of the debonding technique using the ElectRelease H23 wafer to a carrier wafer with ElectRelease electrochemical polymer adhesive
adhesive. for the first type of stack. (a) Metal deposition on the device wafer. (b) Spin
coating on the carrier wafer with ElectRelease adhesive. (c) Illustration show-
ing the arrangement of the wafer stack after adhesive bonding of the aluminum
coated device wafer. (d) Photograph of the bonded stack showing the electrical
wafer. This was followed by thinning of the device wafer using Deep contact area of the device wafer which is exposed at the carrier wafer flat.
Reactive Ion Etching (DRIE).
To evaluate the temporary wafer bonding technique using the elec-
trochemically active adhesive as a viable solution for semiconductor coating. The carrier wafer and the fabrication process remained the
applications, two types of wafer stacks were prepared. For the first same as for the first type of stack.
type of stack, a 100 mm diameter p-doped (0.4–0.6  · cm) silicon For bonding, the prepared wafers were transferred to a Suss Mi-
wafer having a thickness of 100 μm is used as the device wafer. A crotec CB8 wafer bonder tool. A clean room tissue paper was put
250 nm thick aluminum layer was sputtered on one side of the de- on each side of the wafer stack to protect the bond chucks of the
vice wafer as shown in Figure 3a. The metallized surface is used as tool from any excessive adhesive that is squeezed out at the side of
the electrode area to be bonded to the ElectRelease layer. The carrier the wafer stack during bonding. Graphite sheets, of a thickness of
wafer was a 550 μm thick p-doped (10–20 m · cm) silicon wafer. 500 μm, were also placed on each side of the wafer/paper tissue
The diluted ElectRelease adhesive solution was spun at 2000 rpm on stack to achieve a uniform load distribution across the wafer, as illus-
the carrier wafer and soft baked at 80◦ C for 1 min on a hotplate re- trated in Figure 4. The pressure in the bond chamber was set to 10−4
sulting in a thickness of 11 μm as illustrated in Figure 3b. The total mbar and a bonding force of 1 kN was applied to the wafer stack for
thickness variation was found to be <2 μm across the wafer. The 20 min at room temperature. After this time, the temperature was
aluminum coated device wafer was then manually aligned and placed ramped up to 80◦ C with a total ramping time of 5 min. The wafer
on the carrier wafer, as shown in Figure 3c. The exposed aluminum stack was held at this temperature for 30 min while maintaining the
area on the device wafer at the carrier wafer edge flat was later used bond force. During this period the adhesive undergoes curing due to
as an electrical contact for applying a debonding voltage as shown in cross linking and hardens, which results in a bond between the device
the photograph 3d. wafer and the carrier wafer. Alternatively, curing of the adhesive can
For the second type of stack, a 300 μm thick p-doped
(0.1–0.5  · cm) silicon device wafer was used without aluminum

Top Wafer Chuck

Composition
Resin : 71.2 %
Hardner : 11.8 %
CPT : 17 % Selected composition
DEVICE WAFER Si Aluminum
and spin speed for spin
coating the adhesive ElectReleaseTM

Composition CARRIER WAFER

Resin : 60.9 % Clean
p+Si
Hardner : 10.1 % room
CPT : 29 % tissue Graphite Sheet

Bottom Wafer Chuck

Figure 2. Thickness of the adhesive versus spin speed of the diluted ElectRe-
lease adhesive after soft bake for two different mixture ratios. The thickness is
measured at five points on the wafer for each spin speed. Figure 4. Illustration of the wafer stack assembly in the wafer bond tool.
 ECS Journal of Solid State Science and Technology, 3 (5) P115-P121 (2014) P117

also be done at room temperature, which however requires a curing Direction of the
time of approximately 22–24 hr while applying the bond force. After force applied by
bonding, the wafer stack was transferred to a STS ICP DRIE etcher Ultra thin silicon
the dynamometer
where the device wafer was thinned down to approximately 40 μm. device wafer
UV release tape

Evaluation Experiments
Al
Experiments were performed to measure the bond strength before ElectRelease
and after the electrical release process. The release process occurs 50 V
when a voltage is applied to the stack. The current during the release Carrier wafer ER
of the two prepared wafer stacks was measured. For both stacks, the p+ Si
bond strength of the adhesive was measured before and after applying Metal contact
a voltage to the stack. (a)
Ultra thin silicon
Debonding of metallized silicon device wafers.— The wafer stack device wafer
was fixed to a 3 mm thick aluminum plate providing an electrical
contact to the carrier wafer. A UV release tape was attached to the
device wafer to facilitate debonding and “peel-off” evaluation ex- UV release tape Aluminum
periments. Initially, the bond strength of the adhesive was measured
without applying a voltage. A dynamometer was used to measure the
bond strength of the ElectRelease adhesive layer during peeling. It ElectRelease
was attached to a corner of the UV tape and pulled upwards, thereby Carrier wafer
exerting a pull force on the attached device wafer as illustrated in (b) p+ Si
Figure 5a.The UV tape started to peel off from the device wafer at
a force of approximately 2.25 N without releasing the wafer bond as
shown in Figure 5b.
The bond strength of the adhesive was measured again after ap-
plying a constant voltage of +50 V between the device (anode) and
the carrier (cathode) wafers as illustrated in Figure 6. The voltage was

Direction of the
force applied by
Ultra thin silicon the dynamometer
device wafer
UV release tape

Aluminum
ElectRelease
0V

Carrier wafer ER
p+ Si
(c)
Metal contact
Figure 6. (a) Illustration of the evaluation set-up for measurement of bond
(a)
strength after applying a voltage. (b) Illustration of the debonding procedure
after applying a voltage. (c) Photograph showing the debonding of the device
wafer when a force is applied to the UV tape attached to the device wafer.

switched off when the current density had dropped from a current
density corresponding to about 9 mA/cm2 to 1 mA/cm2 . The bond
strength was measured again and it was now possible to remove the
device wafer from the carrier wafer with a force of only 0.5 N, leaving
the ElectRelease adhesive on the carrier wafer (Figure 6). This result
shows that applying a voltage to the stack considerably reduces the
bond strength of the adhesive, hence enabling a quick and effortless
release of the device wafer.
To demonstrate the low force needed for debonding, the device
wafer was manually removed from the carrier wafer by applying a
gentle force on the UV tape and peeling radially inwards as shown
in Figure 7. No sign of cracking of the device wafer was observed as
(b) shown in Figure 8. However, the aluminum layer was peeled off in
a small area from the device wafer due to low adhesion between the
Figure 5. (a) Illustration of the test set-up for measurement of bond strength. aluminum and the silicon surface. The UV tape was released from the
(b) Photograph showing the force that is applied to the UV tape attached to the thin device wafer by UV light exposure for 1 min.
device wafer, measured with a dynamometer. The inset photograph shows the Using the fabrication procedure described in the wafer bonding
close-up of peeling of the UV tape from the device wafer. process section, a stack with an aluminum coated device wafer was
P118 ECS Journal of Solid State Science and Technology, 3 (5) P115-P121 (2014)

12
Maximum current density

Current density (mA/cm2)

10

+ 50 V 0V
2

0
0 20 40 60 80 100 120
Time (s)
2
Figure 9. Current density versus time when a voltage of 50 V is applied to
the wafer stack.

Table I. Different shear force and oxide thickness measurements

on three identically prepared wafer stacks.

Wafer stack samples Type of Experiments

w1w2 Shear measurement after application of a
voltage. Measurement of oxide thickness.
w3w4 Shear measurement before application of a
voltage. Measurement of oxide thickness.
w5w6 Shear measurement before and after voltage
application.

Debonding of silicon device wafers without metal coatings.— To

investigate the ability to debond silicon wafers without metal elec-
Figure 7. (a) Photograph showing the release of the thin device wafer from the trode layers, both carrier and device wafers were used that did not
carrier wafer after applying the voltage. (b) Photograph showing the released
device wafer.
contain any metal layer. For these carrier and device wafers, shear
force measurements were carried out on three identically prepared
sets of wafer stacks, as described in Table I. In addition, oxide thick-
prepared to investigate the debonding process. In particular, the current ness measurements were carried out to investigate for any changes in
density at the interface of the device wafer and the adhesive was the native oxide thickness at the device wafer-adhesive interface as a
followed over time (Figure 9). When a voltage of 50 V was applied result of the release process.
to the stack, it resulted in an initial current density of 11 mA/cm2 The wafer bond shear strength, before and after applying a volt-
that gradually dropped to about 1 mA/cm2 in approximately 50 s, age was investigated using a die shear tester, Dage PC 2400 (Nord-
thus indicating an increase in impedance over time. Once the current son Dage, UK). Figure 10 illustrates a cross-section of the shear
density had stabilized, the voltage was turned off. To estimate the test set-up with the mounted wafer stack. When bonding the two
effect of joule heating due to the current flow over the bond interface, wafers, they are aligned so that both flats are facing away from each
the temperature rise was simulated using a COMSOL model. It was other. For shear force measurements, the wafer stack was firmly fixed
found that an electrical current induced temperature increase of about on a shearing stage by placing the flat of the lower wafer at the
6–8◦ C can be expected. This temperature rise is deemed too low to stage fixation recess. The recess in combination with a vacuum fixa-
influence the debonding process. tion ensures that the lower wafer is unable to move along the shear
direction.
The shear force plots of samples w1w2 and w3w4 are shown in
Figure 11. The plots show the measured force on the shear head. The
shear head displacement represents the distance the upper wafer has
moved from its initial position relative to the lower wafer. The wafer

Shear head Wafer stack Fixation recess

Shear direction
Upper wafer flat Lower wafer flat

Vacuum fixation

Sample mounting stage

Figure 8. Debonded carrier and 40 μm thin device wafer that is still attached Figure 10. Illustration of the shear force measurement set-up for shearing of
to UV release tape. No cracking of the thin wafer was observed. the bonded and released wafer stack, respectively.
 ECS Journal of Solid State Science and Technology, 3 (5) P115-P121 (2014) P119

300
Shear Force [N]

250
w3w4 wafer stack max. shear force at 298 N Figure 11. Shear force measurement of wafer
before applying the voltage (Si chipped at the shear head) stack w1w2 and w3w4 showing a difference in
200
the forces before and after applying the volt-
wafer sheared off at 122 N age. For the w3w4 stack, the device wafer was
150 chipped at a maximum shear force of 298 N.
w1w2 wafer stack For the w1w2 wafer stack, the device wafer was
after applying the voltage sheared off at a force of 122 N.
100

50
100 101 Displacement [µm] 102

stack w1w2 (after applying a voltage) was sheared off at a force of of 163 N. Figure 12a illustrates the shear force curve for both cases,
122 N. When the same force was applied to the wafer stack w3w4 before and after the voltage is applied. The current density plot is
(before applying a voltage), it was not sheared off, indicating higher shown in Figure 12b. The current density decreases from 4.8 mA/cm2
bond strength of that stack. The maximum shear force applied to the to 1 mA/cm2 in 5 s. The decrease in current density is resulting from
w3w4 sample was 298 N before the silicon of the top wafer was an increase in the impedance at the anode-adhesive interface.26,30,31
chipped off at the shear head contact area. Thus, the shear strength One of the processes that occur during the electrical release of
of the wafer bond before applying a voltage is at least more than 2.5 aluminum substrates is the growth of aluminum oxide, which may
times higher than the shear strength of the wafer bond after applying also play a role in the release mechanism.27 To investigate the oc-
a voltage. currence of similar phenomena on silicon substrates, the device wafer
The sample w5w6 was evaluated in the same manner as samples was investigated for any changes in the silicon dioxide layer thickness.
w1w2 and w3w4, but to avoid any chipping of the top silicon wafer, Therefore, two silicon device wafers from the w1w2 and w3w4 wafer
the shearing speed and the shearing height was reduced. Figure 12 stacks were analyzed for an increase in silicon dioxide thickness on
shows the plots of the shear forces before and after the voltage is the device wafers. After the release process as described above, the
applied, along with the calculated current density over time during thickness of the silicon dioxide was measured using a Horiba UVISEL
debonding. Before applying a voltage, the bonded wafer stack could ER ellipsometer. For comparison, the native oxide thickness on a bare
withstand the maximum possible shear force of the shear tester of reference silicon wafer was measured. Figure 13 shows the distribu-
490 N. The achieved bond strength of more than 490 N demonstrates tion of the measured oxide thicknesses on different samples. Oxide
the high bond strength of the ElectRelease adhesive. After a voltage thickness measurement on the device wafer showed approximately
of 50 V was applied to the w5w6 wafer stack and a second shear test five to seven fold increase in thickness after debonding. This indicates
was performed, the top wafer was sheared off at an applied shear force that the impedance increase may be due to the formation of an oxide

500
Shear Force [N]

400 w5w6 wafer stack

before applying the voltage max. shear force at 490 N
(machine limit)
300
w5w6 wafer stack
after applying the voltage wafer sheared off at 163 N
200

100
100 101 102
(a) Displacement [µm]
5.0
Current density (mA/cm2)

4.5
Maximum current density
4.0
3.5
3.0
2.5
Time for which
2.0 the current density
1.5 reaches to 1 mA/cm2
+ 50V
1.0
0.5 5s

(b) 0
0 10 20 30 40 50 60 70
Time (s)

Figure 12. (a) Shear force measurement for sample w5w6 before and after the voltage is applied. (b) Current density as a function of time during electrical release
of the w5w6 stack when 50 V is applied.
P120 ECS Journal of Solid State Science and Technology, 3 (5) P115-P121 (2014)

(a) (b) (c)

Figure 13. Oxide thicknesses on silicon wafers measured at five locations before and after debonding. (a) Bare reference wafer showing native silicon oxide
thickness measurements before bonding (b-c) Silicon dioxide thicknesses for device wafers after debonding, showing a similar thickness increase on two device
wafers. For the w3w4 device wafer, two points show a higher thickness that could be attributed to irregularities on the wafer surface.

layer between the silicon-adhesive interface. A similar effect has been applying the voltage, the debonding was done with ease. This method
observed when bonding aluminum26 . of debonding of the silicon wafer does not require any heating of the
adhesive; neither does it require any solvent based treatment. The de-
vice wafer can easily be released and debonded by applying a voltage.
Discussion This temporary wafer bonding method has the potential to facilitate
The electrochemical debonding method is applied to two types of handling thin wafers in 3D integration processes.
device wafers. In one type, a non-conducting device wafer is coated
with an aluminum layer as the conductive material and in the other Acknowledgments
type, a highly doped silicon wafer is used without adding an alu-
minum surface coating. The advantage of using the technique with an This work has been funded by the European Research Council
aluminum coated device wafer is that the device wafer does not have (ERC) through the Advanced grant (267528): Towards Cost-Efficient
to be conductive itself i.e. glass wafers can be used. However, in this Flexible Heterogeneous Integration for Micro and Nanosystem
case a post-processing step is required to remove the aluminum coat- Fabrication.
ing from the thin device wafer. This step is not necessary when using a
highly doped silicon device wafer. Moreover, it was observed that the
release mechanism is faster when using a highly doped silicon device References
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