ELEC 401 Analog CMOS Integrated Circuit Design

Design Project: Opamp Design

Due: Friday, December 22nd, 2023, by 11:59pm

Design and simulate a two-stage fully differential operational amplifier based on the following topology in
the 45-nm CMOS process (the PDK is available through ssh-soc.ece.ubc.ca server and instruction on how
to access it can be found on our Canvas web page).

VDD VDD VDD VDD

Vbias M10 M7 M0
M8

Voutp RCM

M11 M12 Vinp M1 M2 Vinn

Voutn RCM Vref Voutp Voutn

CL CL
Vcfmb CC RC RC CC
Vcfmb

M13 M5 M3 M4 M6
M14
GND GND
GND GND GND GND

The Design specifications are summarized in the following table:

VDD 1.2 V
GND 0V
CL 2 pF
(1 pF differential
Capacitive load)
Nominal input common-mode (input DC level) VDD/2
Nominal output common-mode (output DC level) VDD/2
Overall power consumption ≤ 1 mW
Differential output peak-to-peak Swing ≥ 1.6 V
Low-frequency differential gain ≥ 40 dB
Small-signal unity gain frequency ≥ 300 MHz
Phase Margin ≥ 60
Slew rate ≥ 20 V/µs
Maximum length of transistors (Lmin=32 nm) 5×Lmin

Note that you may or may not need RC for the compensation. Please note that the output common-mode
has to be set using the simple common-mode feedback circuit that is shown in the schematic. Use
RCM=1 M, and assume that other than supply voltage, VDD = 1.2 V, you have access to two other voltage
sources, namely, Vref = 0.6 V (this is used as a reference voltage for the common-mode feedback system
circuit) and Vbias of any fixed value between 0 to VDD which is used for biasing the gate of the M0, M7, M8,
and M10. To avoid body effect at the input of the opamp, connect the body of PMOS transistors M1 and M2
to their respective source terminal. Similarly, connect the body of PMOS transistors M 11 and M12 to their
respective source terminals. The body of all the other PMOS transistors is connected to V DD and the body
of all the NMOS transistors is connected to ground (GND).

Use the designed opamp in the closed-loop inverting amplifier configuration with a gain of −1 that is shown
below. The load capacitance of the opamp is not explicitly shown in this figure, however, it is the same as
specified in the table and shown in the schematic of the opamp.
 10 M

10 M
Vin1
Vout1

Vin2 Vout2
10 M

10 M

Plot the frequency response of this structure as well as the transient response for four different differential
input steps with the common-mode of 0.6V and differential peak-to-peak value of 20 mV (Vin1 a step from
0.595 V to 0.605 V and Vin2 a step from 0.605 V to 0.595 V), −20 mV, 2 V, −2 V. Measure and report the
small-signal 10 to 90% settling time (that is, the time required for the output to reach from 10% to 90% of
its final value) and the large-signal initial rising/falling slopes of the output (i.e., slew rate).

For your project report, please prepare a document that includes a brief report on how you designed
your circuit, a table summarizing the performance results of your opamp, summary of your hand
calculations and a brief description of your design approach, required plots including the bode plot of
open-loop transfer function on which achieved phase margin and low-frequency gain are annotated,
bode plot of closed-loop system on which the 3-dB frequency of the closed-loop system is indicated,
and provide the plots of the step responses, and any comments and conclusions. Please also include the
schematic of your design with transistor sizes and component values indicated on the schematic (transistor
sizes and component values should be indicated beside each transistor/component, respectively).
Also, include any other supporting document(s) or graph(s) that you would like to hand in. Please
include these items in one file and submit it through our Canvas web page. As an additional file, please also
submit the .asc file of your LTspice schematic.

Bonus:
1) Instead for using Vbias and Vref design a supply independent biasing circuit and a simple voltage
divider that generate Vbias and Vref, respectively. Note that the power consumption of the overall
opamp including the biasing circuitry and the voltage divider should be less than 1 mW.

2) Design your opamp such that the specifications are met even if the supply voltage varies by ±10%.

Good luck!