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B022412(022) ALNat

B. Tech (Fourth Semester) Examination,

Nov.-Dec. 2023

(New Scheme)
(CSE Branch)
COMPUTER SYSTEM ARCHITECTURE

Time Allowed : Three hours

Maximum Marks : 100
Minimum Pass Marks : 35

Note : Attempt all questions. Part (a) in each unit is

compulsory. Atempt any two from (b), (c)
and (d). Part (a) is of 4 marks and part (b),
(c) and (d) are of8 marks each.

Unit-1

1. (a) What do you understand by addressing modes?

B022412(022) PTO
 2.
(d) Explainth(ce) (b) (a) (d) (c) (b)
exanple guard
bits.
Describe Define address
() Fast() Write Define of
formatsExplain bothof Write
diagramExplaininstruction
Bit
short
Progrannmed
control the
pair terms the
Booth accumulator difterences
floatingrecording notesunderflow.
overflowand representation,
22412(022)
Unit-IllMultiplication on Unit-I!
point between
unit. |2|
of based
multipliers
operations selection Draw
CPU hardwired
diagram
blockthe
algorithm and
with with
exxample. application and
proper micro
with

4. 3.
(d) (c) (b) (a) (d) (c) Explainth(eb) (a)
interrupt
diagram.th
wiExplain I/O Write the What Define decoder?
connectionprovide How Explain derive Define
and rate
down is many the
the memory of
directperipheral a virtual Cache
DMA expression
working the clearlymemory 128 associative
022412(022)
memory memory Memory.
differencescontroller
mapped devices. byte
Unit-IV
indicating ofRAM for |3|
of access 2048 in memory
daisy /O. with details. match
between
technique? bytes chips
chaining diagram. adress, logic.
organ1zation
are
I/O show
required
priority mapped Explain data
details
and and
PTO to
 |4 |
Unit-V

5. (a) Define pipclining.

(b) Draw and explain flow chart and timing diagram for
the four scgment instruction pipcline.

(c) Define parallel processing. Describe Flynn's

classification of parallel processing.
(d) Write short notes on :
() Vector processing
(i) Array processing

570| BO22412(022)