Mini Project on

Design and Implementation of FPGA-Based RSA

Encryption Decryption Module for Secure Bluetooth
Communication

SUBMITTED FOR MINIPROJECT OF FPGA LABORATORY AS PARTIAL

FULLFILMENT OF B. TECH COURSE

SUBMITTED BY:
Asmit Sou – 22ECB0A03
K. Venkata Sai Sankeerth – 22ECB0A04
SUPERVISOR:
Dr. P. Prithvi – Assistant Professor, ECE Department, National
Institute of Technology, Warangal.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

 CERTIFICATE

This is to certify that the dissertation work entitled Design and Implementation
of RSA algorithm for secure Bluetooth communication on FPGA is a bonafied
record of work carried out work by Asmit Sou(22ECB0A03) and K. Venkata
Sai Sankeerth(22ECB0A04) submitted to faculty of “Electronics and
Communication Engineering Department” , in partial fulfillment of the
requirements for the award of the degree of Bachelor of Technology in
“Electronics and Communication Engineering” at National Institute of
Technology, Warangal during academic year (2023-2024).

Dr. P. Prithvi
Assistant Professor
Department of Electronics and
Communication Engineering
National Institute of Technology
Warangal

ACKNOWLEDGEMENT

I would like to express my deepest gratitude to my faculty in-charge Dr. P.

Prithvi, Assistant Professor Department of Electronics and Communication
Engineering , National Institute of Technology, Warangal for their constant
supervision, guidance, suggestion and encouragement during this semester.
ABSTRACT:

RSA (Rivest–Shamir–Adleman) is a public-key cryptosystem that is widely used

for secure data transmission. It is also one of the oldest. The acronym "RSA"
comes from the surnames of Ron Rivest, Adi Shamir and Leonard Adleman.
The security of RSA relies on the practical difficulty of factoring the product of
two large prime numbers, the "factoring problem". Breaking RSA encryption is
known as the RSA problem. Whether it is as difficult as the factoring problem is
an open question. There are no published methods to defeat the system if a
large enough key is used.
RSA is a relatively slow algorithm. Because of this, it is not commonly used to
directly encrypt user data. More often, RSA is used to transmit shared keys for
symmetric-key cryptography, which are then used for bulk encryption–
decryption.
TABLE OF CONTENT:

• Introduction
• Need for RSA algorithm
• Operation
▪ Key generation
▪ Key distribution
▪ Encryption
▪ Decryption
▪ Bluetooth communication through UART
• Flowchart
• Codes
▪ Transmitter module
▪ Receiver module
▪ Test bench
• Simulations
▪ Schematic diagrams
▪ Simulation results
• Challenges and scope for improvement
• Conclusion
• References
 RSA CRYPTOSYSYTEM

Introduction :

RSA encryption and decryption is a widely used cryptographic technique for

securing communication in various applications such as e-commerce, online
banking, and secure email. RSA encryption involves the use of a public key and
a private key to encrypt and decrypt data.
In a public-key cryptosystem, the encryption key is public and distinct from the
decryption key, which is kept secret (private). An RSA user creates and
publishes a public key based on two large prime numbers, along with an
auxiliary value. The prime numbers are kept secret. Messages can be
encrypted by anyone, via the public key, but can only be decoded by someone
who knows the prime numbers.

Need for RSA Algorithm :

The importance of RSA encryption and decryption lies in its ability to provide
secure communication by ensuring that only authorized parties can access the
transmitted information. RSA encryption is based on the mathematical
problem of factoring large prime numbers, which makes it difficult for
unauthorized parties to decrypt the encrypted data.
Some specific benefits of RSA encryption and decryption include :
Confidentiality : RSA encryption ensures that only the intended recipient can
read the encrypted message, thus ensuring confidentiality.
Integrity : RSA encryption can detect any changes made to the encrypted
message during transmission, ensuring message integrity.
Authentication : RSA encryption allows the recipient to verify the authenticity
of the sender by using digital signatures.
Non-repudiation : RSA encryption provides non-repudiation by ensuring that
the sender cannot deny sending the message.
Overall, RSA encryption and decryption is a crucial technique for ensuring the
security and privacy of sensitive information, and its importance will continue
to grow as technology becomes more prevalent in our daily lives.

Steps to Process :
1. First select two distinct prime numbers p and q, in which they are sufficiently
large for security reasons.(They are selected by fermats test, although miller
rabins test is sought often).
2. Now find an value n = p*q, which is modulus of both the keys.
3. Now calculate the euler tution function phi(n) = (p-1)*(q-1).
4. Now chose the public key,e such that e>2 and coprime of phi(n) i.e
gcd(e,phi(n)) is 1.
5. Now try calculating private key d,which satisfies e*d mod(phi(n)) = 1.
(here e is the multiplicative inverse if ‘d*mod((n))’.)
(Infact e is the smaller value than d so encrypting the message will be easier
than decrypting.)
6. Now the cyphertext C will be the M^e*mod((n)).
7. The message text will be C^d*(mod((n))).

Explanation:
1.The euler tution function phi(n) of n with numbers which are greater than
one ,(or thus is the gcd of two numbers is 1).
2.Infact the phi(n) = (n-1) in case of fermat thereom and Plaintext and
Ciphertext will be 1 to n-1 where n is positive integer.
3.The Plaintext M and ciphertext C will be,
C=M^e(mod((n))).
M=C^d(mod((n)).
4. Each communicating entity has one public-key (e, n) or private-key (d, n)
pair, where both e and d are in fact the multiplicative inverse (modϕ(n)) of the
other. e and d are inverses of (modϕ(n)), or ed ≡ 1 (modϕ(n)) ed = 1 + kϕ(n),
for some k. M^ed(mod n) = M1 + kϕ(n)(mod n) = M1 x (M ϕ(n))k(mod ϕ(n)) =
M1 x 1k(mod n) = M. (Euler’s theorem)
5. So to decrypt a Ciphertext C = M^ed*mod(n), it is sufficient to calculate
C^d*mod(n) => M.
Flow Chart for Encryption and Decryption in RSA
algorithm :
Viability :
1. The RSA algorithm is based on the algorithm that the inverse of M
->M^e mod(n) is the function of C->C^dmod(n) in which it makes difficult to
find the phi(n) .
2.It is based on ‘factorizing theorem’ that any positive number can written as
product of prime numbers. In fact, only user may know the factorization of n ,p
and q.The fact that n is disclosed ,and p ,q are the large numbers(now it is
infeasible to factorize n to get d),gives the guarantee that no one can find the
factorization and the encrypted message.

Encryption :
Input : RSA public key(n,e), message m=>[0,n-1]
Output : Cipheryext C=m^e*mod(n).

Decryption :
Input : RSA public key(n,e),d,C.
Output:Plain text m=C^d*mod(n).
 Bluetooth Communication through UART

Bluetooth communication through UART (Universal Asynchronous Receiver-

Transmitter) is a common method for establishing wireless communication
between devices. Here's a basic overview of how it works:

1. Bluetooth Module : You'll need a Bluetooth module that supports UART

communication. Modules like HC-05 and HC-06 are commonly used for
this purpose. These modules typically have two modes of operation: AT
mode and communication mode.
2. UART Interface : Most microcontrollers and embedded systems have
UART hardware built-in, which allows serial communication. You'll
connect the TX (transmit) and RX (receive) pins of the Bluetooth module
to the corresponding pins of your microcontroller.
3. Configuration : Before using the Bluetooth module, you might need to
configure it. In AT mode, you can send AT commands to the module via
UART to set parameters such as baud rate, device name, PIN code, etc.
Once configured, you switch to communication mode.
4. Establishing Connection : In communication mode, the Bluetooth
module acts as a serial bridge between the devices it's paired with. It
transmits data received over UART wirelessly via Bluetooth, and vice
versa.
5. Data Transmission : Once the connection is established, data can be
transmitted between the devices by sending bytes over the UART
interface. Whatever data you write to the UART transmit buffer will be
transmitted wirelessly via Bluetooth to the paired device, and data
received wirelessly will be available in the UART receive buffer for
reading.
6. Handling Communication : You'll need to implement code on both the
sending and receiving devices to handle the data transmission. This
involves initializing the UART interface, configuring interrupts if
necessary, and writing code to send and receive data.
State Machine:
Components Used:
Code :
Transmitter module:
module RSA_Top(input i_Clk, // Main Clock
//Connection with Comp
input i_UART_Rx,
output o_UART_Tx,
// Bluetooth Interface
output io_PMOD_2, // RXD, Receive on RN4871 (FPGA drives this)
input io_PMOD_3, // TXD, Transmit on RN4871
output io_PMOD_8, // RST_N, Reset (active low)
input i_Comp,
//7 Segment Display
output [6:0] o_Segment,
//Displaying multiple digist using anode
output [7:0] o_Anode,
//data to be transmitted
input [7:0] i_X,
//universal Reset
input i_Rst,
input i_Tx_DV,
output o_Done);
assign io_PMOD_8=1'b1;
wire [7:0] w_Y;

//encrypting data taken as input

Ecncrption Encrypt(i_X,w_Y);
 //transmitting data using bluetooth
assign io_PMOD_2=(i_UART_Rx&&i_Comp)||(w_PMOD_2&&!i_Comp);
assign o_UART_Tx=io_PMOD_3;
wire w_PMOD_2;
UART_Tx Trans(i_Clk,i_Rst,w_Y,i_Tx_DV,w_PMOD_2,o_Tx_Active,o_Done);
wire [6:0] w_Segment;
wire [3:0] Bit;
Segment_Controller CONTROL(i_Clk,i_X,w_Y,Bit,o_Anode);
Binary_To_Hex
BCD(.i_Clk(i_Clk),.i_Binary_Num(Bit),.o_Segment(w_Segment));
Negtion_7_Segment NEG(w_Segment,o_Segment);
Endmodule

Segment Controller:
module Segment_Controller(i_Clk,i_X,i_Y,o_Bit,o_Anode);
input i_Clk;
input [9:0] i_X,i_Y;
output [7:0] o_Anode;
output [3:0] o_Bit;
//refresh rate=60hz for 7 Seg-Disp,COUNT=30Mhz/60*MHz;3 Display so
must refresh
//60hz rate
parameter
FIRST_X=3'b001,SECOND_X=3'b010,THIRD_X=3'b011,FIRST_Y=3'b100,SECOND
_Y=3'b101,THIRD_Y=3'b110,COUNT=83333;
reg [3:0] r_Bit;
reg [17:0] r_Cnt;
reg [7:0] r_Anode;
reg [2:0] s_Idx=FIRST_X;
always @(negedge i_Clk)
begin
case(s_Idx)
FIRST_X:
begin
r_Bit=i_X[3:0];
r_Anode=8'b11111110;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=SECOND_X;
r_Cnt=0;
end
else s_Idx=FIRST_X;
end
SECOND_X:
begin
r_Bit=i_X[7:4];
r_Anode=8'b11111101;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=THIRD_X;
r_Cnt=0;
end
 else s_Idx=SECOND_X;
end
THIRD_X:
begin
r_Bit={2'b00,i_X[9:8]};
r_Anode=8'b11111011;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=FIRST_Y;
r_Cnt=0;
end
else s_Idx=THIRD_X;
end
FIRST_Y:
begin
r_Bit=i_Y[3:0];
r_Anode=8'b11011111;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=SECOND_Y;
r_Cnt=0;
end
else s_Idx=FIRST_Y;
end
SECOND_Y:
begin
r_Bit=i_Y[7:4];
r_Anode=8'b10111111;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=THIRD_Y;
r_Cnt=0;
end
else s_Idx=SECOND_Y;
end
THIRD_Y:
begin
r_Bit={2'b00,i_Y[9:8]};
r_Anode=8'b01111111;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=FIRST_X;
r_Cnt=0;
end
else s_Idx=THIRD_Y;
end
default :
begin
 s_Idx=FIRST_X;
r_Cnt=0;
end
endcase
end
assign o_Anode=r_Anode;
assign o_Bit=r_Bit;
Endmodule

Binary to Hex:
module Binary_To_Hex(i_Clk,i_Binary_Num,o_Segment);
input [3:0] i_Binary_Num;
input i_Clk;
output [6:0] o_Segment;
reg [6:0] r_Hex_Encoding;
always @(posedge i_Clk)
begin
case(i_Binary_Num)
4'b0000:r_Hex_Encoding<=7'h7E;//111110
4'b0001:r_Hex_Encoding<=7'h30;
4'b0010:r_Hex_Encoding<=7'h6D;
4'b0011:r_Hex_Encoding<=7'h79;
4'b0100:r_Hex_Encoding<=7'h33;
4'b0101:r_Hex_Encoding<=7'h5B;
4'b0110:r_Hex_Encoding<=7'h5F;
4'b0111:r_Hex_Encoding<=7'h70;
4'b1000:r_Hex_Encoding<=7'h7F;
4'b1001:r_Hex_Encoding<=7'h7B;
4'b1010:r_Hex_Encoding<=7'h77;
4'b1011:r_Hex_Encoding<=7'h1F;
4'b1100:r_Hex_Encoding<=7'h4E;
4'b1101:r_Hex_Encoding<=7'h3D;
4'b1110:r_Hex_Encoding<=7'h4F;
4'b1111:r_Hex_Encoding<=7'h47;
default:r_Hex_Encoding<=7'h47;
endcase
end
assign o_Segment=r_Hex_Encoding;
Endmodule

Active low module:

module Negtion_7_Segment(i_Seg,o_Seg);
input [6:0] i_Seg;
output [6:0] o_Seg;
assign o_Seg[0]=~i_Seg[0];
assign o_Seg[1]=~i_Seg[1];
assign o_Seg[2]=~i_Seg[2];
assign o_Seg[3]=~i_Seg[3];
assign o_Seg[4]=~i_Seg[4];
assign o_Seg[5]=~i_Seg[5];
assign o_Seg[6]=~i_Seg[6];
Endmodule

Encryption:
module Multiply(i_A,i_B,o_Res);
 input [204:0] i_A,i_B;
output [204:0] o_Res;
assign o_Res=i_A*i_B;
endmodule
module Modulo(i_A,o_Res);
input [204:0] i_A;
output [7:0] o_Res;
parameter n=133;
assign o_Res=i_A%n;
endmodule
module Ecncrption(i_X,o_Y);
input [7:0] i_X;
output [7:0] o_Y;
wire [204:0] w_X={150'b0,i_X};
reg e=5'b11101;
wire [204:0] w_Inter1;
Multiply m1(w_X,w_X,w_Inter1);
wire [204:0] w_Inter2;
Multiply m2(w_Inter1,w_X,w_Inter2);
wire [204:0] w_Inter3;
Multiply m3(w_Inter2,w_Inter2,w_Inter3);
wire [204:0] w_Inter4;
Multiply m4(w_Inter3,w_X,w_Inter4);
wire [204:0] w_Inter5;
Multiply m5(w_Inter4,w_Inter4,w_Inter5);
wire [204:0] w_Inter6;
 Multiply m6(w_Inter5,w_Inter5,w_Inter6);
wire [204:0] w_Inter7;
Multiply m7(w_Inter6,w_X,w_Inter7);
wire [7:0] w_Y;
Modulo MODU(w_Inter7,w_Y);
assign o_Y=w_Y;
endmodule

Reciever Module:
RSA_Top:
module RSA_Top(input i_Clk, // Main Clock
//Connection Wtih Comp
input i_UART_Rx,
output o_UART_Tx,
// Bluetooth Interface
output io_PMOD_2, // RXD, Receive on RN4871 (FPGA drives this)
input io_PMOD_3, // TXD, Transmit on RN4871
output io_PMOD_8, // RST_N, Reset (active low)
// 7-Segment Displays, Segment1 is upper digit
output [6:0] o_Segment,
//Controlling Segment
input i_Rst,
output [7:0] o_Anode,
output o_Done);
wire w_Clk,w_Rst_Clk,w_Locked;
assign w_Rst_Clk=1'b0;
clk_wiz_0 inst
 (
// Clock out ports
.clk_out1(w_Clk),
// Status and control signals
.reset(w_Rst_Clk),
.locked(w_Locked),
// Clock in ports
.clk_in1(i_Clk)
);
assign io_PMOD_2=i_UART_Rx;
assign o_UART_Tx=io_PMOD_3;
// Drive BT chip out of reset
assign io_PMOD_8 = 1'b1;
// UART Receiver (data coming from bluetooth)
// Gets forwarded to the 7-segment displays
wire [7:0] w_Y;
UART_Rx Recieve(w_Clk,io_PMOD_3,i_Rst,w_Y);
// Binary to 7-Segment Converter
//decryption using private key
wire [7:0] w_X;
Decryption DECRYPT(w_Y,w_X);
wire [6:0] w_Segment;
wire [3:0] Bit;
Segment_Controller CONTROL(w_Clk,w_X,w_Y,Bit,o_Anode);
Binary_To_Hex
BCD(.i_Clk(w_Clk),.i_Binary_Num(Bit),.o_Segment(w_Segment));
Negtion_7_Segment NEG(w_Segment,o_Segment);
Endmodule

UART_Rx
module UART_Rx(i_Clk,i_Data,i_Rst,o_Data);
input i_Clk,i_Data,i_Rst;
//output reg o_Rst;
output reg [7:0] o_Data;
localparam IDLE=2'b00,START=2'b01,DATA=2'b10,
STOP=2'b11,Clks_Per_Bit=868,Total_Bits=8;
reg [9:0] r_Cnt;
reg [7:0] r_Byte;
reg [3:0] r_Idx;
reg [1:0] s_State;
reg r_Chk,r_Done;
always @(posedge i_Clk)
begin
case(s_State)
IDLE:
begin
r_Cnt=0;
r_Byte=0;
r_Idx=0;
r_Chk=1'b0;
if(i_Rst)begin r_Done=1'b0;s_State=IDLE;end
else if(r_Done)s_State=IDLE;
else if(i_Data==1'b0)s_State=START;
 else s_State=IDLE;
end
START:
begin
if(r_Cnt==(Clks_Per_Bit)/2&&i_Data==1'b0)
begin
s_State=DATA;
r_Cnt=0;
end
else if(r_Cnt==(Clks_Per_Bit)/2)s_State=IDLE;
else s_State=START;
r_Cnt=r_Cnt+1;
end
DATA:
begin
if(r_Cnt==Clks_Per_Bit-1)
begin
r_Byte[r_Idx]=i_Data;
r_Idx=r_Idx+1;
r_Cnt=0;
r_Chk=1'b0;
end
else if(r_Idx>0&&r_Chk!=1'b1&&(i_Data!=r_Byte[r_Idx-1]))
begin
r_Chk=1'b1;
r_Cnt=((Clks_Per_Bit-1)/2)+1;
 end
else if(r_Idx>=Total_Bits)s_State=STOP;
else
begin
r_Cnt=r_Cnt+1;
s_State=DATA;
end
end
STOP:
begin
if(r_Cnt==(Clks_Per_Bit-1)&&i_Data==1'b1)
begin
o_Data=r_Byte;
s_State=IDLE;
r_Done=1'b1;
end
else if(r_Cnt==Clks_Per_Bit-1)
begin
r_Byte=0;
s_State=IDLE;
r_Done=1'b1;
end
else
begin
r_Cnt=r_Cnt+1;
s_State=STOP;
 end
end
default: s_State=IDLE;
endcase
end
endmodule

Decryption:
`timescale 1ns / 1ps
module Multiply(i_A,i_B,o_Res);
input [289:0] i_A,i_B;
output [289:0] o_Res;
assign o_Res=i_A*i_B;
endmodule
module Modulo(i_A,o_Res);
input [289:0] i_A;
output [7:0] o_Res;
localparam n=133;
assign o_Res=i_A%n;
endmodule
module Decryption(i_Y,o_X);
input [7:0] i_Y;
output [7:0] o_X;
wire [289:0] w_Y={150'b0,i_Y};
reg [5:0]d=6'b101001;
wire [289:0] w_Inter1;
 Multiply m1(w_Y,w_Y,w_Inter1);
wire [289:0] w_Inter2;
Multiply m2(w_Inter1,w_Inter1,w_Inter2);
wire [289:0] w_Inter3;
Multiply m3(w_Inter2,w_Y,w_Inter3);
wire [289:0] w_Inter4;
Multiply m4(w_Inter3,w_Inter3,w_Inter4);
wire [289:0] w_Inter5;
Multiply m5(w_Inter4,w_Inter4,w_Inter5);
wire [289:0] w_Inter6;
Multiply m6(w_Inter5,w_Inter5,w_Inter6);
wire [289:0] w_Inter7;
Multiply m7(w_Inter6,w_Y,w_Inter7);
wire [7:0] w_X;
Modulo MODU(w_Inter7,w_X);
assign o_X=w_X;
endmodule

7 Segment controller:
`timescale 1ns / 1ps
module Segment_Controller(i_Clk,i_X,i_Y,o_Bit,o_Anode);
input i_Clk;
input [9:0] i_X,i_Y;
output [7:0] o_Anode;
output [3:0] o_Bit;
//refresh rate=60hz for 7 Seg-Disp,COUNT=30Mhz/60*MHz;3 Display so
must refresh
 //60hz rate
parameter
FIRST_X=3'b001,SECOND_X=3'b010,THIRD_X=3'b011,FIRST_Y=3'b100,SECOND
_Y=3'b101,THIRD_Y=3'b110,COUNT=83333;
reg [3:0] r_Bit;
reg [17:0] r_Cnt;
reg [7:0] r_Anode;
reg [2:0] s_Idx=FIRST_X;
always @(negedge i_Clk)
begin
case(s_Idx)
FIRST_X:
begin
r_Bit=i_X[3:0];
r_Anode=8'b11111110;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=SECOND_X;
r_Cnt=0;
end
else s_Idx=FIRST_X;
end
SECOND_X:
begin
r_Bit=i_X[7:4];
r_Anode=8'b11111101;
 r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=THIRD_X;
r_Cnt=0;
end
else s_Idx=SECOND_X;
end
THIRD_X:
begin
r_Bit={2'b00,i_X[9:8]};
r_Anode=8'b11111011;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=FIRST_Y;
r_Cnt=0;
end
else s_Idx=THIRD_X;
end
FIRST_Y:
begin
r_Bit=i_Y[3:0];
r_Anode=8'b11011111;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
 begin
s_Idx=SECOND_Y;
r_Cnt=0;
end
else s_Idx=FIRST_Y;
end
SECOND_Y:
begin
r_Bit=i_Y[7:4];
r_Anode=8'b10111111;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=THIRD_Y;
r_Cnt=0;
end
else s_Idx=SECOND_Y;
end
THIRD_Y:
begin
r_Bit={2'b00,i_Y[9:8]};
r_Anode=8'b01111111;
r_Cnt=r_Cnt+1;
if(r_Cnt>=COUNT)
begin
s_Idx=FIRST_X;
 r_Cnt=0;
end
else s_Idx=THIRD_Y;
end
default :
begin
s_Idx=FIRST_X;
r_Cnt=0;
end
endcase
end
assign o_Anode=r_Anode;
assign o_Bit=r_Bit;
endmodule
Binary to Hex converter:
module Binary_To_Hex(i_Clk,i_Binary_Num,o_Segment);
input [3:0] i_Binary_Num;
input i_Clk;
output [6:0] o_Segment;
reg [6:0] r_Hex_Encoding;
always @(posedge i_Clk)
begin
case(i_Binary_Num)
4'b0000:r_Hex_Encoding<=7'h7E;//111110
4'b0001:r_Hex_Encoding<=7'h30;
4'b0010:r_Hex_Encoding<=7'h6D;
 4'b0011:r_Hex_Encoding<=7'h79;
4'b0100:r_Hex_Encoding<=7'h33;
4'b0101:r_Hex_Encoding<=7'h5B;
4'b0110:r_Hex_Encoding<=7'h5F;
4'b0111:r_Hex_Encoding<=7'h70;
4'b1000:r_Hex_Encoding<=7'h7F;
4'b1001:r_Hex_Encoding<=7'h7B;
4'b1010:r_Hex_Encoding<=7'h77;
4'b1011:r_Hex_Encoding<=7'h1F;
4'b1100:r_Hex_Encoding<=7'h4E;
4'b1101:r_Hex_Encoding<=7'h3D;
4'b1110:r_Hex_Encoding<=7'h4F;
4'b1111:r_Hex_Encoding<=7'h47;
default:r_Hex_Encoding<=7'h47;
endcase
end
assign o_Segment=r_Hex_Encoding;
endmodule

Active Low module:

module Negtion_7_Segment(i_Seg,o_Seg);
input [6:0] i_Seg;
output [6:0] o_Seg;
assign o_Seg[0]=~i_Seg[0];
assign o_Seg[1]=~i_Seg[1];
assign o_Seg[2]=~i_Seg[2];
 assign o_Seg[3]=~i_Seg[3];
assign o_Seg[4]=~i_Seg[4];
assign o_Seg[5]=~i_Seg[5];
assign o_Seg[6]=~i_Seg[6];
endmodule

TESTBENCH:
module RSA_Test;
reg [7:0] i_X;reg i_Clk=1'b0,i_Rst,i_Tx_DV;wire [7:0] o_X;wire
o_Tx_Active,o_Done_Tx,o_Done_Rx;
Testing
DUT(i_Clk,i_Rst,i_Tx_DV,i_X,o_X,o_Tx_Active,o_Done_Tx,o_Done_Rx);
always #0.005 i_Clk=~i_Clk;
initial
begin
i_Rst=1'b1;
#0.02 i_Rst=1'b0;i_X=2;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=60;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=17;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=20;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
 #0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=132;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=89;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=103;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=3;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.02 i_Rst=1'b1;i_Tx_DV=1'b0;
#0.02 i_Rst=1'b0;i_X=1;i_Tx_DV=1'b1;
wait(o_Done_Rx&&o_Done_Tx);
#0.2 $finish;
end
endmodule
SCHEMATIC DIAGRAM:
Transmitter Synthesis:

Transmitter implementation:
Receiver Synthesis:

Receiver Implematation:
SIMULATION:
CHALLENGES AND SCOPE FOR IMPROVEMENT:
• Efficiency: One of the main challenges when implementing RSA in
Verilog code is ensuring that the algorithm is efficient and runs
quickly. This is especially important for hardware implementations,
as the goal is to minimize the number of clock cycles required for
encryption and decryption. Techniques such as pipelining can help
to improve the efficiency of RSA in Verilog code.
 • Resource Usage: Another challenge when implementing RSA in
Verilog code is managing the use of resources such as memory,
logic gates. Improving the resource usage of the Verilog code can
be achieved through various techniques such as code optimization,
minimizing the number of logic gates used.

• Security:Security plays predominant role in cryptographic

algorithm, including RSA. In Verilog code, ensuring the security of
the algorithm involves not only implementing the cryptographic
algorithm correctly, but also ensuring that the hardware
implementation is secure from physical attacks such as side-channel
attacks. Techniques such as implementing such as power analysis
resistance, and incorporating fault can help to improve the security
of RSA in Verilog code.

• RSA is a relatively slow algorithm. Because of this, it is not

commonly used to directly encrypt user data. More often, RSA is
used to transmit shared keys for symmetric-key cryptography,
which are then used for bulk encryption–decryption.

APPLICATIONS:
The RSA algorithm is widely used for secure communication and
data encryption. Here are some common applications of RSA:

• Secure communication: RSA is used for secure communication in

various applications, including email, instant messaging, and virtual
private networks (VPNs).

• Online banking and financial transactions: RSA is used to secure

online banking and financial transactions by encrypting sensitive
data such as passwords and credit card numbers.
 • Digital signatures: RSA is used to create digital signatures, which are
used to authenticate the origin and integrity of electronic
documents.

• Secure authentication: RSA is used to secure authentication

systems, such as secure logins for websites, online services, and
government systems.

• Overall, RSA plays a vital role in ensuring secure communication,

secure authentication, and secure data transfer in
various applications.

• Secure file transfer: RSA can be used to secure file transfer

protocols, such as SFTP and FTPS, which are commonly used to
transfer large files over the internet.

CONCLUSION:
In summary, when implementing RSA in Verilog code, it is important to
consider challenges such as efficiency, resource usage, security, and
scalability. Improvements can be made through techniques such as
pipelining, parallel processing, code optimization, power analysis
resistance, and modular design. By addressing these challenges and
making improvements where necessary, the implementation of RSA in
Verilog code can be made more secure, efficient, and scalable.

REFERENCE:
1. The RSA Algorithm Evgeny Milanov
https://sites.math.washington.edu/~morrow/336_09/papers/Yevgeny.p
df
2. Research and implementation of RSA algorithm for encryption and

decryption: https://ieeexplore.ieee.org/document/6021216
3. A STUDY ON MODIFIED RSA ALGORITHM IN NETWORK SECURITY:
https://www.researchgate.net/publication/360241707_A_STUDY_ON_
MODIFIED_RSA_ALGORITHM_IN_NETWORK_SECURITY