SiT3521

1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Description Features
The SiT3521 is an ultra-low jitter, user programmable ◼ Programmable frequencies (factory or via I2C/SPI)
oscillator which offers the system designer great flexibility from 1 MHz to 340 MHz
and functionality. ◼ Digital frequency pulling (DCO) via I2C/SPI
The device supports two in-system programming options ▪ Output frequency pulling with perfect pull linearity
after powering up at a default, factory programmed startup ▪ 13 programmable pull range options to ±3200 ppm
frequency:
▪ Frequency pull resolution as low as 5 ppt (0.005 ppb)
◼ Any-frequency mode where the clock output can be ◼ 0.21 ps typical integrated phase jitter (12 kHz to 20 MHz)
re-programmed to any frequency between 1 MHz and
◼ Integrated LDO for on-chip power supply noise filtering
340 MHz in 1 Hz steps
◼ 0.02 ps/mV PSNR
◼ Digitally controlled oscillator (DCO) mode where the clock
◼ -40°C to 105°C operating temperature
output can be steered or pulled by up to ±3200 ppm with
5 to 94 ppt (parts per trillion) resolution. ◼ LVPECL, LVDS, or HCSL outputs
▪ Programmable LVPECL, LVDS Swing
The device’s default start-up frequency is specified in the
ordering code. User programming of the device is achieved ▪ LVDS Common Mode Voltage Control
via I2C or SPI. Up to 16 I2C addresses can be specified by ◼ RoHS and REACH compliant, Pb-free, Halogen-free
the user either as a factory programmable option or via and Antimony-free
hardware pins, enabling the device to share the I2C with
other I2C devices. Applications
The SiT3521 utilizes SiTime’s unique DualMEMS® ◼ Ethernet: 1/10/40/100/400 Gbps
temperature sensing and TurboCompensation® technology ◼ G.fast and xDSL
to deliver exceptional dynamic performance:
◼ Optical Transport: SONET/SDH, OTN
◼ Resistant to airflow and thermal shock ◼ Clock and data recovery
◼ Resistant to shock and vibration ◼ Processor over-clocking
◼ Low jitter clock generation
◼ Superior power supply noise rejection
◼ Server, storage, datacenter
Combined with wide frequency range and user ◼ Test and measurement
programmability, this device is ideal for telecom, networking ◼ Broadcasting
and industrial applications that require a variety of
frequencies and operate in noisy environment.

Block Diagram Package Pinout (10-Lead QFN, 5.0 x 3.2 mm)

SD
A/
SC M
LK IS
O
10 9

OE / NC 1 8 VDD

OE / NC 2 7 OUT-

GND 3 6 OUT+
4 5
A1 A0
/N /N
C/ C/
M SS
O
SI

Figure 1. SiT3521 Block Diagram Figure 2. Pin Assignments (Top view)

(Refer to Table 14 for Pin Descriptions)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Ordering Information

SiT3521 AC -1C133 1 GG156.250000T

Part Family
“SiT3521” 12 mm Tape & Reel, 3 ku reel
12 mm Tape & Reel, 1 ku reel
[2]

Revision Letter
“A” is the revision of Silicon
Frequency
1.000000 to 340. 000000 MHz
Temperature Range
“C” : Extended Commercial, -20 to 70°C
DCXO Pull Range
“ I ” : Industrial, -40 to 85°C
“E” : Extended Industrial, -40 to 105°C[1] “M” : ± 25 ppm
“B” : ± 50 ppm
“C” : ± 80 ppm
Signaling Type
“E” : ±100 ppm
“1”: LVPECL
“F” : ±125 ppm
“2”: LVDS
“G” : ±150 ppm
“4”: HCSL
“H” : ±200 ppm
“X” : ±400 ppm
Package Size “L” : ± 600 ppm
“Y” : ±800 ppm
“C”: 5.0 x 3.2 mm
“S” : ±1200 ppm
“Z” : ±1600 ppm
Frequency Stability/Grade “U” : ±3200 ppm

“F”: ±10 ppm

“1”: ±20 ppm Serial IF mode
“2”: ±25 ppm
“3”: ±50 ppm “S” : SPI mode[1]
“0-G” : I2C mode (See below)
2
Voltage Supply I C Factory Programmable Addresses
2
“0-F” : I C Address factory programmed
“25”: 2.5 V ±10%
Sets Bits 3: 0 of Device I 2 C address to
“28”: 2.8 V ±10%
the Hex value of the ordering code .
“30”: 3.0 V ±10% 2
When the I C address is factory
“33”: 3.3 V ±10% programmed using these codes ,
pin A0, A1 are NC

OE Pin Control “G”: I2C address controlled by A0, A1 pins

“-”: OE under software Control. A1:A0 I2C Address
Pin 1 and 2 are both NC. 00 1100000
“1”: Pin 1 OE, Pin 2 NC 01 1100010
“2”: Pin 1 NC, Pin 2 OE 10 1101000
11 1101010 (default)

Notes:
1. -40 to 105°C option available only for I2C operation.
2. Bulk is available for sampling only.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

TABLE OF CONTENTS
Description ................................................................................................................................................................................... 1
Features....................................................................................................................................................................................... 1
Applications ................................................................................................................................................................................. 1
Block Diagram ............................................................................................................................................................................. 1
Ordering Information .................................................................................................................................................................... 2
1 Electrical Characteristics ......................................................................................................................................................... 4
2 Device Configurations and Pin-outs ........................................................................................................................................ 9
3 Waveform Diagrams ............................................................................................................................................................. 11
4 Termination Diagrams ........................................................................................................................................................... 13
LVPECL .................................................................................................................................................................... 13
LVDS ........................................................................................................................................................................ 14
HCSL ........................................................................................................................................................................ 15
5 Test Circuit Diagrams ........................................................................................................................................................... 16
6 Architecture Overview ........................................................................................................................................................... 18
7 Functional Overview ............................................................................................................................................................. 18
User Programming Interface ..................................................................................................................................... 18
Start-up output frequency and signaling types ........................................................................................................... 18
In-system programmable options.............................................................................................................................. 18
8 In-system Programmable Functional Description.................................................................................................................. 19
Any-frequency function ............................................................................................................................................. 19
DCO Functional Description ..................................................................................................................................... 23
Pull Range, Absolute Pull Range .............................................................................................................................. 25
Software OE Functional Description ......................................................................................................................... 27
9 I2C/SPI Control Registers...................................................................................................................................................... 28
Register Address: 0x00. DCO Frequency Control Least Significant Word (LSW) .................................................... 28
Register Address: 0x01. OE Control, DCO Frequency Control Most Significant Word (MSW) ................................. 29
Register Address: 0x02. DCO PULL RANGE CONTROL ........................................................................................ 29
Register Address: 0x03. Frac-N PLL Feedback Divider Integer Value and Frac-N PLL Feedback Divider Fraction
Value MSW ............................................................................................................................................................... 30
Register Address: 0x04. Frac-N PLL Feedback Divider Fraction Value LSW ........................................................... 30
Register Address: 0x05. Forward Divider, Driver Control ......................................................................................... 30
Register Address: 0x06. Driver Divider, Driver Control ............................................................................................. 31
10 I2C Operation ........................................................................................................................................................................ 32
I2C protocol ............................................................................................................................................................... 32
I2C Timing Specification ............................................................................................................................................ 35
I2C Device Address Modes ....................................................................................................................................... 36
11 SPI Operation ....................................................................................................................................................................... 37
Schematic Examples ................................................................................................................................................................. 40
Dimensions and Patterns ........................................................................................................................................................... 43
Additional Information ................................................................................................................................................................ 44
Revision History ......................................................................................................................................................................... 45

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

1 Electrical Characteristics
All Min and Max limits in the Electrical Characteristics tables are specified over temperature and rated operating voltage with
standard output terminations shown in the termination diagrams. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics – Common to LVPECL, LVDS and HCSL
Parameter Symbol Min. Typ. Max. Unit Condition
Frequency Range
Output Frequency Range f 1 – 340 MHz Factory or user programmable, accurate to 6 decimal places
Frequency Stability
Frequency Stability F_stab -10 – +10 ppm Inclusive of initial tolerance, operating temperature, rated
power supply voltage and load variations.
-20 – +20 ppm
-25 – +25 ppm
-50 – +50 ppm
First Year Aging F_1y – ±1 – ppm 1st-year aging at 25°C
Temperature Range
Operating Temperature Range T_use -20 – +70 °C Extended Commercial
-40 – +85 °C Industrial
-40 – +105 °C Extended Industrial. Available only for I2C operation, not SPI.
Supply Voltage
Supply Voltage Vdd 2.97 3.3 3.63 V
2.7 3.0 3.3 V
2.52 2.8 3.08 V
2.25 2.5 2.75 V
Input Characteristics – OE Pin
Input Voltage High VIH 70% – – Vdd OE pin
Input Voltage Low VIL – – 30% Vdd OE pin
Input Pull-up Impedance Z_in – 100 – kΩ OE pin, logic high or logic low
Output Characteristics
Duty Cycle DC 45 – 55 %
Startup and Output Enable/Disable Timing
Start-up Time T_start – – 3.0 ms Measured from the time Vdd reaches its rated minimum value
Output Enable/Disable Time – T_oe_hw – – 3.8 µs Measured from the time OE pin reaches rated VIH and VIL to
Hardware control via OE pin the time clock pins reach 90% of swing and high-Z.
See Figure 9 and Figure 10
Output Enable/Disable Time – T_oe_sw – – 6.5 µs Measured from the time the last byte of command is
Software control via I2C/SPI transmitted via I2C/SPI (reg1) to the time clock pins reach 90%
of swing and high-Z. See Figure 30 and Figure 31

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Table 2. Electrical Characteristics – LVPECL Specific

Parameter Symbol Min. Typ. Max. Unit Condition
Current Consumption
Current Consumption Idd – – 89 mA Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V
OE Disable Supply Current I_OE – – 58 mA OE = Low
Output Disable Leakage Current I_leak – 0.15 – A OE = Low
Maximum Output Current I_driver – – 32 mA Maximum average current drawn from OUT+ or OUT-
Output Characteristics
Output High Voltage VOH Vdd - 1.1V – Vdd - 0.7V V See Figure 5
Output Low Voltage VOL Vdd - 1.9V – Vdd - 1.5V V See Figure 5
Output Differential Voltage Swing V_Swing 1.2 1.6 2.0 V See Figure 6
Rise/Fall Time Tr, Tf – 225 290 ps 20% to 80%, see Figure 6
Jitter
RMS Phase Jitter (random) – T_phj – 0.225 0.340 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
DCO Mode Only all Vdd levels
– 0.1 0.14 ps f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
RMS Phase Jitter (random) – T_phj – 0.225 0.340 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
Any-frequency Mode Only all Vdd levels
– 0.11 0.15 ps f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
RMS Period Jitter[3] T_jitt – 1 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V

Note:
3. Measured according to JESD65B.

Table 3. Electrical Characteristics – LVDS Specific

Parameter Symbol Min. Typ. Max. Unit Condition
Current Consumption
Current Consumption Idd – – 80 mA Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V
OE Disable Supply Current I_OE – – 61 mA OE = Low
Output Disable Leakage Current I_leak – 0.15 – A OE = Low

Output Characteristics
Differential Output Voltage VOD 250 – 455 mV f = 156.25MHz See Figure 7
Delta VOD ΔVOD – – 50 mV See Figure 7
Offset Voltage VOS 1.125 – 1.375 V See Figure 7
Delta VOS ΔVOS – – 50 mV See Figure 7
Rise/Fall Time Tr, Tf – 400 470 ps Measured with 2 pF capacitive loading to GND, 20% to 80%,
see Figure 8
Jitter
RMS Phase Jitter (random) – T_phj – 0.21 0.275 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
DCO Mode Only all Vdd levels
– 0.1 0.12 ps f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
RMS Phase Jitter (random) – T_phj – 0.21 0.367 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
Any-frequency Mode Only all Vdd levels
– 0.1 0.12 ps f = 156.25, IEEE802.3-2005 10 GbE jitter mask integration
bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
RMS Period Jitter[4] T_jitt – 1 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V

Note:
4. Measured according to JESD65B.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Table 4. Electrical Characteristics – HCSL

Parameter Symbol Min. Typ. Max. Unit Condition
Current Consumption
Current Consumption Idd – – 93 mA Excluding Load Termination Current, Vdd = 3.3 V or 2.5 V
OE Disable Supply Current I_OE – – 60 mA OE = Low
Output Disable Leakage Current I_leak – 0.15 – µA OE = Low
Output Characteristics
Output High Voltage VOH 0.60 – 0.90 V See Figure 5
Output Low Voltage VOL -0.05 – 0.08 V See Figure 5
Output Differential Voltage Swing V_Swing 1.2 1.4 1.8 V See Figure 6
Rise/Fall Time Tr, Tf – 360 465 ps Measured with 2 pF capacitive loading to GND, 20% to 80%,
see Figure 6
Jitter
RMS Phase Jitter (random) – T_phj – 0.215 0.280 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz
DCO mode only all Vdd levels
– 0.09 0.12 ps f = 156.25 MHz, IEEE802.3-2005 10 GbE jitter mask
integration bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
RMS Phase Jitter (random) – T_phj – 0.220 0.320 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz,
Any-frequency mode only all Vdd levels
– 0.1 0.12 ps f = 156.25 MHz, IEEE802.3-2005 10 GbE jitter mask
integration bandwidth = 1.875 MHz to 20 MHz, all Vdd levels
RMS Period Jitter[5] T_jitt – 1.0 1.6 ps f = 100, 156.25 or 212.5 MHz, Vdd = 3.3 V or 2.5 V

Note:
5. Measured according to JESD65B.

Table 5. I2C Electrical Characteristics – SCLK, SDA, 1 MHz SCLK, 255 Ohm, 550 pF (Max I2C Bus Load)
Parameter Symbol Min. Typ. Max. Unit Condition
Input Voltage Low VIL – – 30% Vdd
Input Voltage High VIH 70% – – Vdd
Output Voltage Low VOL – – 0.4 V
Input Leakage current[6] IL 0.5 – 24 µA 0.1 Vdd < VOUT < 0.9 Vdd
Input Capacitance CIN – – 5 pF

Note:
6. Including leakage current from 160 kOhm pull resister at typical condition to Vdd.

Table 6. SPI Electrical Characteristics – SCLK, MOSI, SS

¯¯ , MISO
Parameter Symbol Min. Typ. Max. Unit Condition
Input Pins – SCKL, MOSI, SS
¯¯
Input Voltage Low VIL – – 10% Vdd
Input Voltage High VIH 90% – – Vdd
Input Capacitance CIN – – 5 pF
Output Pin – MISO
Output Voltage High VOH 90% – – Vdd IOH = 2.2 mA (Vdd = 2.5 V)
Output Voltage Low VOL – – 10% Vdd IOL = 2.7 mA (Vdd = 2.5 V)
Leakage in high impedance mode IL 0.5 – 24 µA 0.1 Vdd< VOUT < 0.9 Vdd

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Table 7. Typical Phase Noise: Default start-up or reprogrammed frequency in DCO mode – LVDS output clock
Output Frequency Phase Noise (dBc/Hz)
Frequency Offsets
156.25 MHz 322.265625 MHz
100 Hz -97.8 -91.5
1 kHz -122.9 -116.5
10 kHz -131.1 -124.6
100 kHz -132.9 -126.3
1 MHz -148.2 -132.0
10 MHz -156.9 -153.0
20 MHz -157.7 -154.2

Table 8. Typical Phase Noise: Reprogrammed frequency in any-frequency Mode – LVDS output clock
Output Frequency Phase Noise (dBc/Hz)
Frequency Offsets
156.25 MHz 322.265625 MHz
100 Hz -98.5 -92.7
1 kHz -123.0 -116.6
10 kHz -131.9 -125.3
100 kHz -134.8 -127.9
1 MHz -146.9 -131.2
10 MHz -156.7 -152.7
20 MHz -157.7 -154.1

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Table 9. Absolute Maximum

Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part.
Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter Min. Max. Unit
Continuous Power Supply Voltage Range (Vdd) -0.5 4.0 V
Input Voltage, Maximum (any input pin) – Vdd + 0.3 V V
Input Voltage, Minimum (any input pin) -0.3 – V
Storage Temperature -65 150 ºC
Maximum Junction Temperature – 135 ºC
Soldering Temperature[7] (follow standard Pb-free soldering guidelines) – 260 ºC

Note:
7. Exceeding this temperature for an extended period of time may damage the device.

Table 10. Thermal Consideration[8]

Package JA, 4 Layer Board (°C/W) JC, Bottom (°C/W)
5032, 10-pin 55[9] 20

Note:
8. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above Table 10.
9. Value for JA assumes the center pad is soldered down.

Table 11. Maximum Operating Junction Temperature[10]

Max Operating Temperature(ambient) Maximum Operating Junction Temperature
70°C 95°C
85°C 110°C
105°C 130°C

Note:
10. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.

Table 12. Environmental Compliance

Parameter Test Conditions Value Unit
Mechanical Shock Resistance MIL-STD-883F, Method 2002 10,000 g
Mechanical Vibration Resistance MIL-STD-883F, Method 2007 70 g
Soldering Temperature (follow standard Pb free soldering guidelines) MIL-STD-883F, Method 2003 260 °C
Moisture Sensitivity Level MSL1 @ 260°C – –
Electrostatic Discharge (HBM) HBM, JESD22-A114 2,000 V
Charge-Device Model ESD Protection JESD220C101 750 V
Latch-up Tolerance JESD78 Compliant

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

2 Device Configurations and Pin-outs

Table 13. Device Configurations
Programming Interface Addressing Mode Pin 4 Pin 5 Pin 9 Pin 10
Pin controlled A1 A0 SDA SCLK
I2C
Software NC NC SDA SCLK
SPI – ¯¯
SS MOSI MISO SCLK

Pin-out Top Views (10-Lead QFN, 5.0 mm x 3.2 mm)

SCLK
SCLK

MISO
SDA

10 9 10 9

OE / NC 1 8 VDD OE / NC 1 8 VDD

OE / NC 2 7 OUT- OE / NC 2 7 OUT-

GND 3 6 OUT+ GND 3 6 OUT+

4 5 4 5
MOSI

SS
A1 / NC

A0 / NC

Figure 3. I2C Mode Figure 4. SPI Mode

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Table 14. Pin Description

Internal Pull-up/
Pin Symbol I/O Function
Pull Down Resistor
Pin 1 and Pin 2 functions are set by the ordering code in Ordering Information Table.
If Software OE mode is selected in Ordering Table, both pin 1 and pin 2 are NC.
100 kΩ Pull-Up H[11]: Specified frequency output
OE Input
1 L: Output Driver is disabled:
OUT- = High-Z
OUT+ = High-Z
NC No Connect No Connect
Pin 1 and Pin 2 functions are set by the ordering code in Ordering Information Table.
If Software OE mode is selected in Ordering Table, both pin 1 and pin 2 are NC.
100 kΩ Pull-Up H[11]: Specified frequency output
OE Input
2 L: Output Driver is disabled:
OUT- = High-Z
OUT+ = High-Z
NC No Connect No Connect
3 GND Ground Connect to ground
I2C Address Select, Most Significant Bit (MSB)
A1 A0 I2C Address
100 kΩ Pull-Up 0 0 1100000
A1 Input
0 1 1100010
4 1 0 1101000
1 1 1101010 (Default)
No Connect. I2C Address is factory set to one of the 16 available addresses shown in
NC No Connect
Table 27 and also on the Ordering Information Table.
̅̅̅
SS Input 100 kΩ Pull-Up SPI Chip select, active low
I2C Address Select, Least Significant Bit (LSB)
A1 A0 I2C Address
100 kΩ Pull-Up 0 0 1100000
A0 Input
0 1 1100010
5 1 0 1101000
1 1 1101010 (Default)
No Connect. I2C Address is factory set to one of the 16 available addresses shown in
NC No Connect
Table 27 and also on the Ordering Information Table.
MOSI Input 100 kΩ Pull-Up SPI serial data input
6 OUT+ Output Oscillator output
7 OUT- Output Complementary oscillator output
8 VDD Power Connect to Vdd[12]
SDA Input 200 kΩ Pull-Up I2C serial data input
9
MISO Output 200 kΩ Pull-Up SPI serial data output
10 SCLK Input 200 kΩ Pull-Up I2C/SPI serial clock input

Notes:
11. In OE mode for noisy environments, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If OE pin needs to be left floating,
use the NC option.
12. 0.1 μF capacitor in parallel with a 10 μF capacitor are required between VDD and GND.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

3 Waveform Diagrams
OUT-

VOH

OUT+

VOL

GND

Figure 5. LVPECL, HCSL Voltage Levels per Differential Pin (i.e. OUT+, or OUT-)

80% 80%

V_ Swing
0V
t
20% 20%

Tr Tf

Figure 6. LVPECL, HCSL Voltage Levels Across Differential Pair (i.e. OUT+ minus OUT-)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Waveform Diagrams (continued)

OUT-

VOD

OUT+
VOS

GND

Figure 7. LVDS Voltage Levels per Differential Pin (i.e. OUT+, or OUT-)

80% 80%

0V
t
20% 20%

Tr Tf

Figure 8. LVDS Differential Waveform (i.e. OUT+ minus OUT-)

Vdd Vdd
OE Voltage
VIH

VIL
T_oe_hw
OE Voltage
T_oe_hw
OUT- 90% OUT-

HZ HZ

OUT+ OUT+
GND GND

Figure 9. Hardware OE Enable Timing Figure 10. Hardware OE Disable Timing

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

4 Termination Diagrams
LVPECL

Shunt Bias Termination

LVPECL network 0.1μF
OUT+ Zo = 50Ω D+

OUT- Zo = 50Ω D-
0.1μF

RB RB VDD RB
50 Ω 50 Ω

3.3 V 100 Ω
VT
2.5 V 48.7 Ω

Figure 11. LVPECL with AC-coupled Termination

VDD
Thevenin-equivalent
Termination network
R1 R1
LVPECL
OUT+ Zo = 50Ω D+

OUT- Zo = 50Ω D-

VDD R1 R2 R2 R2

3.3 V 127 Ω 82.5 Ω

2.5 V 250 Ω 62.5 Ω

Figure 12. LVPECL DC-coupled Load Termination with Thevenin Equivalent Network

Y-Bias Termination
network
LVPECL
OUT+ Zo = 50Ω D+

OUT- Zo = 50Ω D-

R1 R2
VDD R1 R2 R3

3.3 V 50 Ω 50 Ω 50 Ω C1 R3
0.1μF
2.5 V 50 Ω 50 Ω 18 Ω

Figure 13. LVPECL with Y-Bias Termination

Shunt Bias
LVPECL Termination network
OUT+ Zo = 50Ω D+

OUT- Zo = 50Ω D-

50 Ω 50 Ω

VT=VDD-2V

Figure 14. LVPECL with DC-coupled Parallel Shunt Load Termination

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Termination Diagrams (continued)

LVDS

LVDS
OUT+ Zo = 50Ω OUT+
100 Ω
OUT- Zo = 50Ω OUT-

Figure 15. LVDS single DC Termination at the Load

LVDS 0.1μF
OUT+ Zo = 50Ω OUT+
100 Ω 100 Ω 0.1μF
OUT- Zo = 50Ω OUT-

Figure 16. LVDS Double AC Termination with Capacitor Close to the Load

LVDS
OUT+ Zo = 50Ω OUT+
100 Ω 100 Ω
OUT- Zo = 50Ω OUT-

Figure 17. LVDS Double DC Termination

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Termination Diagrams (continued)

HCSL

R1
OUT+ Zo = 50Ω D+

OUT- Zo = 50Ω D-
R2
50Ω 50Ω

R1 = R2 = 33 Ω

Figure 18. HCSL Interface Termination

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

5 Test Circuit Diagrams

Test Point
Vout Termination
VDD

SDA
9 8 7 6

Power SCL A0/NC

10 uF 0.1 uF 10 5
Supply

A1/NC
1 2 3 4

VDD

OE 1 kΩ NC

Figure 19. Test Circuit (I2C mode and OE Function for Pin 1)

Test Point
Vout Termination
VDD

SDA
9 8 7 6

Power SCL A0/NC

10 uF 0.1 uF 10 5
Supply

A1/NC
1 2 3 4

VDD
NC

1 kΩ
OE

Figure 20. Test Circuit (I2C mode and OE Function for Pin 2)

Test Point
Vout Termination
VDD

SDA
9 8 7 6

Power SCL A1/NC

10 uF 0.1 uF 10 5
Supply

A0/NC
1 2 3 4

NC NC

Figure 21. Test Circuit (I2C mode and NC Function for both Pin1 and Pin2)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Test Circuit Diagrams (continued)

Test Point
Vout Termination
VDD

MISO 8 7
9 6

Power SCL MOSI

10 uF 0.1 uF 10 5
Supply

1 4 SS
2 3

VDD

OE 1 kΩ NC

Figure 22. Test Circuit (SPI mode and OE Function for Pin 1)

Test Point
Vout Termination
VDD

MISO 8 7
9 6

Power SCL MOSI

10 uF 0.1 uF 10 5
Supply

2 4 SS
2 3

VDD NC

1 kΩ
OE

Figure 23. Test Circuit (SPI mode and OE Function for Pin 2)

Test Point
Vout Termination
VDD

MISO
9 8 7 6

Power 0.1 uF
SCL SS
10 uF 10 5
Supply

MOSI
1 2 3 4

NC NC

Figure 24. Test Circuit (SPI mode and NC Function for both Pin1 and Pin2)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

6 Architecture Overview 7 Functional Overview

Based on SiTime’s innovative Elite Platform ®, the SiT3521 The SiT3521 is designed for maximum frequency flexibility
delivers exceptional dynamic performance, i.e. resilience to with an array of factory programmable options, enabling
environmental stressors such as shock, vibration and fast system designers to configure this precision device for
temperature transients. Underpinning the Elite platform are optimal performance in a given application.
SiTime’s unique DualMEMS temperature sensing
architecture and TurboCompensation technology, illustrated User Programming Interface
in Figure 1. The SiT3521 supports either I2C or SPI interface (slave
only) as a factory programmable option via the ordering
DualMEMS is a noiseless temperature sensing scheme. It codes. For I2C, the user has the option of using one of the
consists of two MEMS resonators fabricated on the same four default addresses selectable with two address pins
die substrate. The TempFlat resonator is designed with a (A0, A1) or specifying one of the sixteen factory
flat frequency characteristic over temperature whereas the programmed addresses. Refer to I2C/SPI Device Address
temperature sensing resonator is by design sensitive to Modes section for details.
temperature changes. The ratio of frequencies between
these two resonators provides an accurate reading of the Table 15. Programming Interface Ordering Codes
resonator temperature with 30 µK resolution.
Programming Addressing Ordering
Interface Mode Code
By placing the two MEMS resonators on the same die, this
temperature sensing scheme eliminates the thermal lag I2C 2 address pins – A0, A1 “G”
and gradients between the resonator and the temperature Factory programmed “0-F”
sensor, an inherent weakness of the legacy quartz TCXOs. SPI Chip select pin “S”
The DualMEMS temperature sensor is then combined with
a state-of-the-art temperature compensation circuit in the Start-up output frequency and signaling types
CMOS IC. The TurboCompensation design, with >100 Hz The SiT3521 is shipped with a default start-up frequency
compensation bandwidth, achieves dynamic frequency between 1 MHz to 340 MHz in steps of 1 Hz that a user
stability that is far superior to any quartz devices. The 7th specifies in the ordering code.
order compensation algorithm enables additional
optimization of frequency stability and frequency slope A user can also specify one of the three differential
over temperature within any specific temperature range of signaling types in the ordering code.
choice for a given system design. Table 16. Output Format Ordering Codes
The Elite platform also incorporates a high resolution, low Output Format Ordering Code
noise frequency synthesizer along with the industry
LVPECL “1“
standard I2C and/or SPI bus. This unique combination
enables system designers to digitally control the output LVDS “2”
frequency in steps as low as 5 ppt (parts per trillion) and HCSL “4”
over a wide frequency range from 1 MHz to 340 MHz.
In-system programmable options
For more information regarding the Elite platform and its
benefits please visit: The SiT3521 enables software control of the following
features via I2C/SPI:
◼ SiTime's breakthroughs section
◼ Any-frequency feature: Output frequency that can be
◼ TechPaper: DualMEMS Temperature Sensing Technology re-programmed to any value between 1 MHz and
◼ TechPaper: DualMEMS Resonator TDC 340 MHz in 1 Hz steps
◼ DCO feature: Output frequency that can be steered
(pulled) by up to ±3200 ppm with 5 to 94 ppt resolution
◼ Software OE feature: Enabling or disabling of the
output driver

Refer to Chapter 9 for programming details.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

8 In-system Programmable Functional Description

Figure 25 shows hi-level block diagram of In-system programmable oscillator showing user accessible and non-user-
accessible circuit blocks.

Software
OE

Frac-N OUT+
Forward
MEMS PLL
Divider
94 MHz (feedback
(M)
divider N) OUT-

Driver
DCO Control

User Non User

Accessible Block Accessible Block

Figure 25. In-system Programmable Oscillator Block Diagram

Any-frequency function Table 18. Any-frequency user-accessible blocks

The any-frequency feature allows users to re-program Block Available Register Register
Name values Name Address
the device output to a new frequency between 1 MHz to
340 MHz and optimize output driver according to the 13.08511 to N_reg 0x03[15:0] = N_reg[31:16]
N
given new frequency after power-up through the I2C or 15.96875 [31:0] 0x04[15:0] = N_reg[15:0]
SPI interface. Device output frequency is defined by a
M_reg
combination of Frac-N PLL feedback divider (N) and M 2 to 8191
[12:0]
0x05[15:3] = M_reg[12:0]
forward divider (M).
0x05[2:0] =
Equation 1: Output frequency, Driver Driver Control Driver Control Reg [5:3]
0 to 63
Control Reg [5:0] 0x06[2:0] =
94 MHz*N Driver Control Reg [2:0]
Fout =
M
Step 1: N and M dividers values calculation
Table 17 is showing unsupported any-frequency
Frequencies. Find the lowest allowed M divider value which gives N
value (see Equation 2) within allowed Frac-N PLL
Table 17. List of Unsupported Frequencies feedback divider range (see Table 18):
Unsupported Frequency Range (MHz)
Equation 2:
Min. Max.
Fout*M
300.2125 307.5001 N=
94 MHz

To re-program device to the desired output frequency, Table 19 below shows implementation of this step for the
user should calculate the most appropriate Frac-N PLL 75 MHz output frequency example. The combination
feedback and forward divider combination. For a given satisfying above conditions is highlighted in blue.
output frequency, the choice of dividers combination Table 19. Frac-N PLL Feedback Divider and Forward
must fall within the allowable ranges (See the Table 18). Divider Combination Calculation for Output Frequency
Calculation of the appropriate N and M values and = 75 MHz
selection of proper Driver Control values consist of the M N
following steps. Throughout these steps, and example Within 2 to 8191 Within 13.08511 to 15.96875
using LVPECL 75 MHz output frequency will be used. 16 12.76596
17 13.56383
18 14.36170
19 15.15957
20 15.95745

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Step 2: Calculate N and M Dividers Binary Values Step 3: Select appropriate Drive Control values

The selected combination of Frac-N PLL feedback Select appropriate Drive Control values based on Table 20.
divider and forward divider values should be converted Table 20. Driver Control settings
to binary words and then written to the device’s control
registers. Number conversion, conditioning and write Drive Control
Output Frequency
Output Driver Reg
procedure are as follows. The values calculated in the (MHz)
[5:0]
previous steps for 75 MHz output frequency will be used
1 to 250 110110b
for example purposes. LVPECL
250.000001 to 340 101110b
Step 2.1: Convert N value to binary word (N_reg)
1 to 250 001000b
32 bits are intended for N divider value: MSB 5 bits for LVDS or HCSL
250.000001 to 340 000000b
integer and LSB 27 for fractional parts
In the example, Driver Control Reg[5:0]: = 110110b
1) Take the integer part of the N divider value and
convert to binary.
Step 4: Write N and M binary values to the device
In our example, integer part is dec: 13 and
bin: 01101 Step 4.1: Read back the contents of 0x06[15:0]
2) Execute bitwise XOR operation on the integer Reg6 read back is needed to capture the value of this
part (01101b) and 01110b mask. register so the same values can be written along with
The reason for the 01110b mask is to set the the Driver Control Reg[2:0] value
default value when the device is in an un- Step 4.2: Write registers to the device in the
programmed state and all bit values are 0. following sequence

N_reg[31:27] = 01101b (given integer part) XOR 1) Address 0x03

01110b (mask) = 00011b (final value) 0x03[15:11] = N_reg[31:27] (integer part)
0x03[10:0] = M_reg[26:16] (fractional part, MSW)
3) Fractional part of the N divider value should be
multiplied by 2 27 and then rounded towards 2) Address 0x04
nearest integer. Then it should be converted to 0x04[15:0] = N_reg[15:0] (fractional part, LSW)
binary value resulting in a 27-bit binary word.
3) Address 0x06
Because the fractional part of N is always
0x06[15:3] = Values red out at step 3.1
positive, no sign bit should be used. In our
example, 0x06[2:0] = Driver Control Reg[2:0]
227 * 0.56383 = 75,675,981.57824. Rounding to 4) Address 0x05
the nearest integer gives 75,675,982 and 0x05[15:3] = N_reg[12:0]
converting 0x05[2:0] = Driver Control Reg[5:3]
to binary:
After the forward divider value 0x05 is written, the
N_reg[26:0] = outputs will be disabled until the PLL locks to the new
100100000101011100101001110b (final value) frequency and is stable. When the PLL is stable, the
clock output will be re-enabled. Figure 26 and Figure 27
Step 2.2: Convert M divider value to binary word show the write sequence, output disable and
programming time for I2C and SPI interfaces.
1) M divider value should be converted to 13-bit
binary word. As forward divider is always
positive no sign bit should be used.
In this example, the M value is dec: 17,
bin: 0000000010001b
2) Execute bitwise XOR operation on the M value
and 0000000011011b mask.
M_reg[12:0] = 0000000010001b (given M) XOR
0000000011011b = 0000000001010b (final value)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Frac-N PLL[31:27] Frac-N PLL[26:16]

St D_Address[6:0] W A R_Address[7:0]=03 A [15:11] [10:8] A [7:0] A

0x03[15:8] 0x03[7:0]

Frac-N PLL[15:0]

[15:8] A [7:0] A ReSt D_Address[6:0] W A R_Address[7:0]=06 A

0x04[15:8] 0x04[7:0]

Driver Cotrol[2:0]

[15:8] A [7:3] [2:0] A ReSt D_Address[6:0] W A R_Address[7:0]=05 A

0x06[15:8] 0x06[7:0]

PostDiv[12:0] Driver Control[5:3]

[15:8] A [7:3] [2:0] A Sp

0x05[15:8] 0x05[7:0]

Rest of
write
Slave Drives Bit(s) on Bus
transaction
Tprogramming
Master Drives Bit(s) on Bus Output Frequency f0 Output Frequency f1
OUT+
St Start OUT-
Sp Stop
Tdisable
W Write Output Disabled
R Read OUT+ = High-Z
A Acknowledge OUT- = High-Z
ReSt Repeated Start

Figure 26. Changing the Default Start-up Output Frequency Using Auto Address Incrementing (I2C)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Frac-N PLL[31-27] Frac-N PLL[26:16]

0x57 R_Address[7:0]=03 [15:11] [10:8] [7:0]

0x03[15:8] 0x03[7:0]

Frac-N PLL[15:0]

[15:8] [7:0] Tdelay 0x57 R_Address[7:0]=06

0x04[15:8] 0x04[7:0]

Driver Control[2:0]

[15:8] [7:3] [2:0] Tdelay 0x57 R_Address[7:0]=05

0x06[15:8] 0x06[7:0]

PostDiv[12:0] Driver Control[5:3]

[15:8] [7:3] [2:0]

0x05[15:8] 0x05[7:0]

Rest of
write
transaction
Tprogramming
Output Frequency f0 Output Frequency f1
OUT+
OUT-

Tdisable
Output Disabled
OUT+ = High-Z
OUT- = High-Z

Figure 27. Changing the Default Start-up Output Frequency Using Auto Address Incrementing (SPI)

Table 21. Output Disable and Enable Times when Changing the Output Frequency
Parameter Symbol Min. Typ. Max. Unit Condition

Delay between transactions Tdelay 125 – – µs SPI only

Output Disable Time Tdisable – – 2.3 µs At 85°C ambient

Settling Time for Frequency Change Tre-programming – – 421 µs At 85°C ambient

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

DCO Functional Description The pull range is specified by the value loaded in the
The DCO feature allows users to steer (pull) output digital pull range control register. The 16 pull range
frequency by up to ±3200 ppm with 5 to 94 ppt resolution choices are specified in the control register and range
through the I2C or SPI digital interface. from ±6.25 ppm to ±3200 ppm.

There are several advantages of DCO relative to analog Table 22 below shows the frequency resolution vs. pull
voltage control (VCXO) range programmed value.

a. Frequency Control Resolution as low as 5 ppt. Table 22. Frequency Resolution vs. Pull Range
This high resolution minimizes accumulated time Programmed Pull Range Frequency Precision
error in synchronization applications. ±25 ppm 5x10-12
b. Lower system cost – A VCXO may need a Digital ±50 ppm 5x10-12
to Analog Converter (DAC) to drive the control ±80 ppm 5x10-12
voltage input. In a DCO, the frequency control is ±100 ppm 5x10-12
achieved digitally by register writes to the control ±125 ppm 5x10-12
registers via I2C, thereby eliminating the need for a ±150 ppm 5x10-12
DAC. ±200 ppm 5x10-12
c. Better Noise Immunity – The analog signal used to ±400 ppm 1x10-11
drive the voltage control pin of a VCXO can be
±600 ppm 1.4x10-11
sensitive to noise and the trace over which the
±800 ppm 2.1x10-11
signal is routed can be susceptible to noise
±1200 ppm 3.2x10-11
coupling from the system. The DCO does not
±1600 ppm 4.7x10-11
suffer from analog noise coupling since the
±3200 ppm 9.4x10-11
frequency control is performed digitally through
I2C.
d. No Frequency Pull non-linearity. The frequency The ppm frequency offset is specified by the 26-bit DCO
pulling is achieved via fractional feedback divider Frequency control register in two’s complement format as
of the PLL, eliminating any pull non-linearity described in the I2C/SPI Register Descriptions. The power
concern which is typical of quartz based VCXOs. up default value is 00000000000000000000000000b
This improves dynamic performance in closed which sets the output frequency at its nominal value
loop operations. (0 ppm). To change the output frequency, a frequency
control word is written to 0x00[15:0] (Least Significant
e. Programmable Wide Pull Range – The DCO
Word) and 0x01[9:0] (Most Significant Word). The LSW
pulling mechanism is via the fractional feedback
value should be written first followed by the MSW value;
divider and is therefore not constrained by
the frequency change is initiated after the MSW value is
resonator pullability as in quartz based solutions.
written.
The SiT3521 offers 16 frequency pull range
options from ±6.25 ppm to ±3200 ppm, thereby
giving system designers great flexibility.

In the DCO mode, the device powers up at the nominal

operating frequency and pull range specified by the
ordering code. After power-up both the pull range and
output frequency can be controlled via I2C/SPI writes to
the respective control registers. The maximum output
frequency change is constrained by the pull range limits.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Figure 28. Pull range and Frequency Control Word

Figure 28 shows how the two’s complement signed value of Two examples follow, assuming the ±200 ppm pull range.
the frequency control word sets the output frequency within
the ppm pull range set by 0x02[3:0]. This example shows Example 1:
use of ±200 ppm pull range. Therefore, to set the desired Default start-up output frequency = 156.25 MHz
output frequency, one just needs to calculate the fraction of Desired output frequency = 156.2640625 MHz (+90 ppm)
full scale value ppm, covert to two’s complement binary and
225-1 corresponds to +200 ppm, and the fractional value
then write the values to the frequency control registers.
required for +90 ppm can be calculated as follows.
90 ppm/200 ppm * (225-1) = 15,099,493.95
The following formula generates the control word value:
Rounding to the nearest whole number yields 15,099,494
Control word Value = and converting to two complement gives a binary value of
= RND((225-1) * ppm shift from nominal/pull range) 111001100110011001100110 and E66666 in hex.
where RND is the rounding function which rounds the Example 2:
number to the nearest whole number.
Default start-up output frequency = 122.88 MHz
Desired output frequency = 122.873856 MHz (-50 ppm)
Following formula shown above,
(-50 ppm/200 ppm) * (225-1) = -8,388,607.75
Rounding to the nearest whole number results in
-8,388,608.
Converting to two’s complement binary results in
11100000000000000000000000 and 3800000 in hex.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

To Summarize, the procedure for calculating the It is important to note that the maximum DCO Frequency
frequency control word associated with a given ppm Control update rate is 38 kHz regardless of I2C/SPI bus speed.
offset is as follows:
Pull Range, Absolute Pull Range
1) Calculate the fraction of the half pull range
needed. For example, if the total pull range is set Pull range (PR) is the amount of frequency deviation that will
for ±100 ppm and a +20 ppm shift from the result from changing the control voltage over its maximum
range under nominal conditions.
nominal frequency is needed, this fraction is
20 ppm/100 ppm = 0.2 Absolute pull range (APR) is the guaranteed controllable
frequency range over all environmental and aging conditions.
2) Multiply this fraction by the full half scale word Effectively, it is the amount of pull range remaining after
value, 225-1 = 33,554,431, round to the nearest taking into account frequency stability tolerances over
whole number and convert the result to two’s variables such as temperature, power supply voltage, and
complement binary. Following the +20 ppm aging, i.e.:
example, this value is 0.2 * 33,554,431 =
6,710,886.2 and rounded to 6,710,886. APR = PR − Fstability − Faging
3) Write the two’s complement binary value starting
with the Least Significant Word (LSW) where Fstability is the device frequency stability due to initial
0x00[16:0], followed by the Most Significant
tolerance and variations on temperature, power supply, and load.
Word (MSW), 0x01[9:0]. If the user desires that
the output remains enabled while changing the Table 23 below shows the pull range and corresponding APR
frequency, a 1 must also be written to the OE values for each of the frequency vs. temperature ordering
control bit 0x01[10] if the device has software options.
OE Control Enabled.

Table 23. DCO Pull Range, APR Options

Pull Range Ordering Programmed Pull APR ppm APR ppm APR ppm APR ppm
Code Range ppm ±10 ppm option ±20 ppm option ±25 ppm option ±50 ppm option

M ±25 ±10 – – –

B ±50 ±35 ±25 ±20 –

C ±80 ±65 ±55 ±50 ±25

E ±100 ±85 ±75 ±70 ±45

G ±125 ±110 ±100 ±95 ±70

H ±200 ±185 ±175 ±170 ±145

X ±400 ±385 ±385 ±380 ±345

Y ±800 ±785 ±785 ±780 ±745

Z ±1600 ±1585 ±1585 ±1580 ±1545

U ±3200 ±3185 ±3185 ±3180 ±3145

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Figure 29 below shows the I2C sequence for writing the

4-byte control word using auto address incrementing. It is
important to note that if the I2C function is under software
control, the software OE control bit 0x01[10] should be
“1” during the write sequence to avoid disabling the
output.

Digital Frequency Control – Least Significant Word (LSW) [15:0]

St D_Address[6:0] W A R_Address[7:0]=00 A LSW[15:8] A LSW[7:0] A

0x00[15:8] 0x00[7:0]

Digital Frequency Control – Most Significant Word (MSW) [9:0]

X X X X X OE 9 8 A MSW[7:0] A Sp
0x01[15:8] 0x01[7:0]

STOP
condition f0 + f1 ±0.5%

Output f0 Tsettle
Frequency
Tfdelay
Slave Drives Bit(s) on Bus

Master Drives Bit(s) on Bus

St Start
Sp Stop

W Write

R Read

A Acknowledge

OE Output Enable

X “Don’t Care” Register Bit not used.

Figure 29. Writing the Frequency Control Word

Table 24. DCO Delay and Settling Time

Parameter Symbol Min. Typ. Max. Unit Condition
Time from end of 0x01 reg MSW to start of frequency pull, as shown in
Frequency Change Delay Tfdelay – 103 140 µs
Figure 29
Frequency Settling Time Tsettle – 16.5 20 µs Time to settle to ±0.5% of frequency offset, as shown in Figure 29

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Software OE Functional Description

Output driver can be enabled or disabled through control Important note: By default (at startup) output is disabled
registers 0x01[10] (corresponding part number option in this mode and should be enabled by corresponding
should be selected to enable this function, please refer write operation after start-up.
to the OE Pin Control option in Ordering Information
section). To enable the output driver, this register should
be set to 1, to disable – to 0.

OE
NOT USED[15:11]
Control[10] DCO Frequency Control[9:0]

St D_Address[6:0] W A R_Address[7:0]=01 A [15:11] [10] [9:8] A [7:0] A Sp

0x01[15:8] 0x01[7:0]

T_oe_sw
OUT+
OUT-
Output Disabled
OUT+
Output Disabled
OUT-

Figure 30. Enable/Disable software OE (I2C)

OE
NOT USED[15:11]
Control[10] DCO Frequency Control[9:0]

0x57 R_Address[7:0]=01 [15:11] [10] [9:8] [7:0]

0x01[15:8] 0x01[7:0]

T_oe_sw
OUT+
OUT-
Output Disabled
OUT+
Output Disabled
OUT-

Figure 31. Enable/Disable software OE (I2C)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

9 I2C/SPI Control Registers

The any-frequency, DCO software OE and drive strength control features enable control of frequency pull range, frequency
pull value, Output Enable and Drive strength setting via I2C/SPI writes to the control registers.
Table 25 below shows the register map summary and the detailed register descriptions follow.
Table 25. Register Map Summary
Address Bits Access Description
0x00 [15:0] RW DCO FREQUENCY CONTROL LEAST SIGNIFICANT WORD (LSW)
0x01 [15:11] R NOT USED
[10] RW OE CONTROL. This bit is only active if the output enable function is under software control. If the device is
configured for hardware control using an OE pin, writing to this bit has no effect. Selection of Pin or Software OE
Control is an ordering option shown in Ordering Information Table.
[9:0] RW DCO FREQUENCY CONTROL MOST SIGNIFICANT WORD (MSW)
0x02 [15:4] R NOT USED
[3:0] RW DCO PULL RANGE CONTROL
0x03 [15:11] RW FRAC-N PLL FEEBDACK DIVIDER INTEGER VALUE
[10:0] RW FRAC-N PLL FEEBDACK DIVIDER FRACTIONAL VALUE, MOST SIGNIFICANT WORD (MSW)
0x04 [15:0] RW FRAC-N PLL FEEBDACK DIVIDER FRACTIONAL VALUE, LEAST SIGNIFICANT WORD (LSW)
0x05 [15:3] RW FORWARD DIVIDER
[2:0] RW DRIVER CONTROL
0x06 [15:2] R NOT USED
3 RW DRIVER DIVIDER VALUE
[2:0] RW DRIVER CONTROL

Register Descriptions
Register Address: 0x00. DCO Frequency Control Least Significant Word (LSW)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name DCO FREQUENCY CONTROL LEAST SIGNIFICANT WORD (LSW)[15:0]

Bits Name Access Description

15:0 DCO FREQUENCY CONTROL RW Bits [15:0] are the lower 16 bits of the 26 bit FrequencyControlWord and are the Least
LEAST SIGNIFICANT WORD Significant Word (LSW). The upper 10 bits are in regsiter 0x01[9:0] and are the most
significant Frequency Control Word (MSW). The lower 16 bits together with upper 10
bits specify a 26-bit frequency control word.

This power up default values of all 26 bits are 0 which sets the output frequency at
its nominal value. After powerup, the system can write to these two registers to pull
the frequency across the pull range. The register values are 2’s complement to
support positive and negative control values. The LSW value should be written
before the MSW value because the frequency change is initiated when the new
values are loaded into the MSW. More details and examples are discussed in the
next section.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Register Address: 0x01. OE Control, DCO Frequency Control Most Significant Word (MSW)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R R R R RW RW RW RW RW RW RW RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name NOT USED OE DCO FREQUENCY CONTROL[9:0] MSW

Bits Name Access Description

15:11 NOT USED R Bits [15:10] are read only and return all 0’s when read. Writing to these bits have no
effect.
10 OE Control RW Output Enable Software Control. Allows the user to enable and disable the output
driver via I2C.
0 = Output Disabled (Default)
1 = Output Enabled

This bit is only active if the output enable function is under software control. If the
device is configured for hardware control using an OE pin, writing to this bit has no
effect.
9:0 DCO FREQUENCY CONTROL RW Bits [9:0] are the upper 10 bits of the 26 bit Frequency Control Word and are the Most
MOST SIGNIFICANT WORD (MSW) Significant Word (MSW). The lower 16 bits are in register 0x00[15:0] and are the least
significant Frequency Control Word (MSW). Theses lower 16 bits together with upper
10 bits specify a 26-bit frequency control word.

This power up default values of all 26 bits are 0 which sets the output frequency at its
nominal value. After powerup, the system can write to these two registers to pull the
frequency across the pull range. The register values are 2’s complement to support
positive and negative control values. The LSW value should be written before the
MSW value because the frequency change is initiated when the new values are
loaded into the MSW. More details and examples are discussed in the next section.

Register Address: 0x02. DCO PULL RANGE CONTROL

Bit 15 14 13 12 11 10 9 6 5 6 5 4 3 2 1 0
Access R R R R R R R R R R R R RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 X[13] X[13] X[13] X[13]
Name NONE DCO PULL RANGE CONTROL

Note:
13. Default values are factory set but can be over-written after power-up.

Bits Name Access Description

15:4 NONE R Bits [15:4] are read only and return all 0’s when read. Writing to these bits have no
effect.

3:0 DCOs PULL RANGE CONTROL RW Sets the digital pull range of the DCO. The table below shows the available pull range
values and associated bit settings. The default value is factory programmed.

Bit
3210
0000: Not used
0001: Not used
0010: Not Used
0011: ±25 ppm
0100: ±50 ppm
0101: ±80 ppm
0110: ±100 ppm
0111: ±125 ppm
1100: ±150 ppm
1001: ±200 ppm
1010: ±400 ppm
1011: ±600 ppm
1100: ±800 ppm
1101: ±1200 ppm
1110: ±1600 ppm
1111: ±3200 ppm

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Register Address: 0x03. Frac-N PLL Feedback Divider Integer Value and Frac-N PLL Feedback
Divider Fraction Value MSW
Bit 15 14 13 12 11 10 9 6 5 6 5 4 3 2 1 0
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default x x x x x x x x x x x x x x x x
Frac-N PLL Feedback Divider Integer
Name Frac-N PLL Feedback Divider Fraction Value, MSW
Value

Bits Name Access Description

15:11 Frac-N PLL Feedback Divider RW Sets the integer value of the Frac-N PLL feedback divider. The default value is factory
Integer Value programmed to correspond to the desired output frequency (hence the x notation in the
default value field) and can be changed by the user after powerup.

10:0 Frac-N PLL Feedback Divider RW Most Significant Word (MSW) of Frac-N PLL feedback divider fraction value. The MSW
Fraction Value, MSW comprises the upper 11 bits of the 27-bit control word. The default value is factory
programmed to correspond to the desired output frequency (hence the x notation in the
default value field) and can be changed by the user after powerup.

Register Address: 0x04. Frac-N PLL Feedback Divider Fraction Value LSW
Bit 15 14 13 12 11 10 9 6 5 6 5 4 3 2 1 0
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default x x x x x x x x x x x x x x x x
Name Frac-N PLL Feedback Divider Fraction Value, LSW

Bits Name Access Description

15:0 Frac-N PLL Feedback Divider RW Sets the Least Significant Word of the Frac-N PLL feedback divider fraction. The
Fraction Value, LSW default value is factory programmed to correspond to the desired output frequency
(hence the x notation in the default value field) and can be changed by the user after
powerup.

Register Address: 0x05. Forward Divider, Driver Control

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Default x x x x x x x x x x x x x 0 0 0
Name Forward Divider Driver Control

Bits Name Access Description

15:3 Forward Divider RW Forward Divider Value. The default value is factory programmed to correspond to
the desired output frequency (hence the x notation in the default value field) and
can be changed by the user after powerup. The Forward Divider Value Range is
[2:8191].
2:0 Driver Control RW LVDS or HCSL driver
Bit Value Frequnecy range
001 1 to 250 MHz
000 250.000001 to 340 MHz
LVPECL driver
Bit Value Frequnecy range
110 1 to 250 MHz
101 250.000001 to 340 MHz

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Register Address: 0x06. Driver Divider, Driver Control

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Access R R R R R R R R R R R R RW RW RW RW
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Driver
Name NOT USED Driver Control
Divider

Bits Name Access Description

15:4 NOT USED R Bits [15:4] are read only and return all 0’s when read. Writing to these bits have no
effect.
3 Driver Divider RW Driver divider value. DO NOT change this bit. Default value is 2 for SiT3521.
Bit Value Driver Divider
0 2 (default, DO NOT change)
1 1 (bypass)
2:0 Driver Control RW LVDS or HCSL driver
Bit Value Frequency range
000 1 to 340 MHz
LVPECL driver
110 1 to 340 MHz

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

10 I2C Operation
I2C protocol
Data valid START and STOP conditions
The SDA line must be stable during the high period of the The idle I2C bus state occurs when both SCLK and SDA
SCLK. SDA transitions are allowed only during SCLK low are not being driven by any master and are therefore in a
level for data communication. Only one transition is logic HI state due to the pull up resistors. Every
allowed during low SCLK pulse to communicate one bit of transaction begins with a START (S) signal and ends with
data. Figure 32 shows the detailed timing diagram. a STOP (P) signal. A START condition is defined by a
high to low transition on the SDA while SCLK is high. A
STOP condition is defined by a low to high transition on
the SDA while SCLK is high. START and STOP conditions
are always generated by master. This slave module also
supports repeated START (Sr) condition which is same as
START condition instead of STOP condition (Blue color
line shows repeated START in Figure 33).

SDA

SCLK

data line stable: change of data setup time

data valid allowed

Figure 32. Data and clock timing relation in I2C bus

SDA
hold time hold time setup time
SCLK
S P
START Condition STOP Condition

Figure 33. START and STOP (or repeated START) condition

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Data Transfer Format Write/Read sequence

Every data byte is eight bits long. The number of bytes This I2C slave module supports 7-bit device addressing
that can be transmitted per transfer is unrestricted. Data is format. The 8th bit is a read/write bit and “1” indicates a
transferred with the MSB (Most Significant Bit) first. The read transaction and a “0” indicates a write transaction.
detailed data transfer format is shown in Figure 34 below. The register addresses are 8-bits long with an address
range of 0 to 255 (00h to FFh). Auto address incrementing
The acknowledge bit must occur after every byte transfer is supported which allows data to be transferred to
and it allows the receiver to signal the transmitter that the contiguous addresses without the need to write each
byte was successfully received and another byte may be address beyond the first address. Since the maximum
sent. The acknowledge signal is defined as follows: the register address value is 255, the address will roll from
transmitter releases the SDA line during the acknowledge 255 to back to 0 when auto address incrementing is used.
clock pulse so the receiver can pull the SDA line low and it Obviously, auto address incrementing should only be used
remains stable low during the high period of this clock for writing to contiguous addresses. The data format is 16-
pulse. Setup and hold times must also be taken into bit (two bytes) with the most significant byte being
account. When SDA remains high during this ninth clock transferred first. For a read operation, the starting register
pulse, this is defined as the Not-Acknowledge signal address must be written first. If that is omitted, reading will
(NACK). The master can then generate either a STOP start from the last address in the auto-increment counter
condition to abort the transfer, or a repeated START of the device, which has a startup default of 0x00.
condition to start a new transfer. The only condition that
leads to the generation of NACK from the SiT3521 is
when the transmitted address does not match the slave
address. When the master is reading data from SiT3521,
the SiT3521 expects the ACK from the master at the end
of received data, so that the slave releases the SDA line
and the master can generate the STOP or repeated
START. If there is NACK signal at the end of data, then
the SiT3521 tries to send the next data. If the first bit of
next data is “0”, then the SiT3521 holds the SDA line to
“0”, thereby blocking the master from generating a
STOP/(re)START signal.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

SDA
MSB acknowledge acknowledge
from slave from slave

SCLK S or 1 2 7 8 9 1 2 3 to 8 9 P or
Sr ACK ACK Sr

START Condition STOP Condition

Figure 34. Data Transfer Format

SDA

1 to 7 8 9 1 to 8 9 1 to 8 9 1 to 8 9
SCL S P
START slave W ACK register ACK data-MSB ACK data-LSB ACK STOP
condition address address condition

Figure 35. Write Sequence

SDA

1 to 7 8 9 1 to 8 9 1 to 8 9
SCL S P
START slave R ACK data-MSB ACK data-LSB ACK STOP
condition address condition

Figure 36. Read Sequence

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

I2C Timing Specification

The below timing diagram and table illustrate the timing relationships for both master and slave.

tf tr tSU;DAT

VIH
SDA
VIL

tf tr tHD;DAT tVD;DAT tHIGH

VIH
SCLK 1 2 8 9
VIL
tHD;STA
1/fSCLK tLOW
S
START Condition
tBUF

SDA

tSU;STA tHD;STA tVD;ACK tSU;STO

SCLK 8 9
P S
Sr
STOP Condition START Condition
Repeated START Condition

Figure 37. I2C Timing Diagram

Table 26. I2C Timing Requirements

All Min and Max limits are specified over temperature and rated operating voltage with 255 Ohm resistor and 550 pF output
load unless otherwise stated. Typical values are at 25°C and nominal supply voltage.
Standard mode Fast mode Fast mode plus [14]
Parameter Symbol Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
SCLK clock frequency fSCLK – – 100 – – 400 – – 1000 kHz
Low period of SCLK clock tLOW 470 – – 1300 – – 500 – – ns
High period of SCLK clock tHIGH 400 – – 600 – – 260 – – ns
Rise time of both SCLK and SDA tr – – 120 – – 120 – – 120 ns
Fall time of both SCLK and SDA tf 30 – 300 30 – 300 30 – 120 ns
Hold time for Start condition tHD;STA 4000 – – 600 – – 260 – – ns
Setup time for Start condition tSU;STA 470 – – 600 – – 260 – – ns
Data setup time tSU;DAT 250 – – 100 – – 50 – – ns
Data hold time tHD;DAT 0 – – 0 – – 0 – – ns
Data valid time tVD;DAT – – 3450 – – 900 – – 450 ns
Data valid acknowledge time tVD;ACK – – 3450 – – 900 – – 450 ns
Setup time for stop condition tSU:STO 400 – – 600 – – 260 – – ns
I2C bus free time between
tBUF 470 – – 1300 – – 500 – – ns
stop and start

Notes:
14. Fast mode plus is not supported in Extended Industrial temperature range.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

I2C Device Address Modes

There are two I2C Address modes: Table 28 is only valid for the ordering option which does
not use the I2C address pins A0, A1.
1) Factory Programmed Mode. The lower 4 bits of the
7-bit device address are set by ordering code as shown Table 28. Pin Selectable I2C Address Control
in Table 27 below. There are 16 factory programmed A1 A0
I2C Address
addresses available. In this mode, pins 4 and 5 are NC Pin 4 Pin 5

and pin control of the I2C address is not available. 0 0 1100000

2) A0, A1 Pin Control. This mode allows the user to 0 1 1100010

select between four I2C Device addresses as shown 1 0 1101000

in Table 28. 1 1 1101010

Table 27. Factory Programmed I2C Address Control Ordering Information Table is only valid for the ISP-DCXO
I2C Address Ordering Code Device I2C Address device option which uses pin control (A0, A1) of the I2C
0 1100000 address. This mode corresponds to ordering code “G” in
the I2C address section of the ordering code table.
1 1100001
2 1100010
3 1100011
4 1100100
5 1100101
6 1100110
7 1100111
8 1101000
9 1101001
A 1101010
B 1101011
C 1101100
D 1101101
E 1101110
F 1101111

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

11 SPI Operation
SPI (Serial Peripheral Interface) is a 4-pin synchronous The following Figure 38 illustrates the logical connection
serial protocol that allows a master device to initiate half- between one SPI master and 3 SPI slaves. Note that this
duplex communication with one or more slave devices. diagram is shows only an example logical connection and
The pin functions are as follows: is not a detailed schematic intended to show pull-up
resistors and other components which may also be
SCLK: Serial Clock which supports up to 5 MHz operating required.
frequency.
There are two allowed states for idle SCLK state, HI and
MOSI: Master Output Slave Input. This is the data input LOW and these states are called clock phase. There are
pin to the SiT3521 and is used by the master to write data also two modes for clock sampling edge, rising edge and
to the SiT3521 control registers. falling edge and these modes are called clock polarity.
MISO: Master Input Slave Output. This is the data output Since there are two allowed clock phases and two allowed
pin of the SiT3521 and is used by the master to read data clock polarities, this means there are four total modes of
from the SiT3521 control registers. SPI operation as illustrated below in Figure 39.

¯¯ : Active Low SPI Chip Select. This pin is used by the

SS
master to select the SiT3521 as the active slave device on
the SPI bus. When the master drives the SiT3521 pin low,
the SiT3521 is selected as the target of a read or write
transaction.

Slave 0 Slave 1 Slave 2

SCLK

SCLK

SCLK
MOSI
MISO

MOSI
MISO

MOSI
MISO
SS

SS

SS
SPI
Master

MOSI
MISO
SCLK

SS0
SS1
SS2

Figure 38. Multi-slave SPI bus connections

SCLK Polarity SCLK Phase

Mode
SCLK_POL SCLK_PHA
Low
At Start Rising
Mode 0
Edge

Low
At Start Falling
Mode 1 Edge

Falling
Mode 2 Edge
High
At Start

Rising
Mode 3 Edge
High
At Start

Figure 39. SPI operation modes

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

The SiT3521 can support all four operating modes. By The detail register descriptions are covered in the I2C/SPI
default, modes 0 and 3 are supported, but modes 1 and 2 Control Registers.
can be supported in the future.
A description of DCO control is in DCO Functional
The serial byte interface format is shown below: 8-bit Description and a description of changing the output center
command (read or write), 8-bit SPI address and 16-bit data. frequency is in any-frequency Functional Description.
The serial order is most significant bit (MSB) first. The SPI The below Figure 41 shows the timing diagram for modes
protocol also supports auto address incrementing which 0 and 3.
means the address will automatically increment after the
first transaction. Auto address incrementing will result in
higher data throughput when writing to registers with
contiguous addresses. If it is required to write to non-
contiguous addresses, a write command and register
address must be used for each transaction after the
delay (125 us min). Without such delay, the device will
consider command and address bytes as a data for the
consequent register.

Command[7:0] Address[7:0] Data[15:0]

WRITE: 57h
READ: A5h 00: DCXO Frequency Control
01: DCXO Frequency Control, OE
02: DCXO Pull Range Control
03: PFM Control
04: PFM Control
05: PLL Post Divider Control
Differential Drive Strength
06: Differential Driver Control

Figure 40. SPI control word format

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

VIH
SS
VIL
tSCLK
tsSU tHIGH tsH

SCLK

tdSU tdH tLOW

MOSI

tV

VOH
MISO
VOL

Figure 41. SPI Timing Diagram (Mode 0/3)

Table 29. SPI Timing Requirements[15]

Parameter Symbol Min. Typ. Max. Unit
Setup time for MOSI to SCLK Rising Edge tdSU 28 – – ns
Hold time for MOSI to SCLK Rising edge tdH 1 – – ns
Time from active edge of SCLK clock to valid MISO data available at pin tv – – 30 ns
Period of SCLK tSCLK – – 200 ns
High Width of SCLK tHIGH – tSCLK/2 – ns
Low Width of SCLK tLOW – tSCLK/2 – ns
Setup time for SSB falling edge to SCLK rising edge tsSU 1.5*tSCLK – – ns
Hold time from SSB rising edge to SCLK rising edge tsH 1.5*tSCLK – – ns

Notes:
15. SPI is not supported in Extended Industrial temperature range.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Schematic Examples

Figure 42. Schematic Example (LVPECL, I2C mode)

Figure 43. Schematic Example (HCSL, I2C mode)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Schematic Examples (continued)

Figure 44. Schematic Example (LVDS, I2C mode)

Figure 45. Schematic Example (LVPECL, SPI mode)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Schematic Examples (continued)

Figure 46. Schematic Example (HCSL, SPI mode)

Figure 47. Schematic Example (LVDS, SPI mode)

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Dimensions and Patterns

Package Size – Dimensions (Unit: mm)[16] Recommended Land Pattern (Unit: mm)[17]

5.0 x 3.2 x 0.85 mm

Notes:
16. Top Marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the assembly location of the
device.
17. The center pad has no electrical function. Soldering down the center pad to the GND is recommended for best thermal dissipation, but is optional.

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Additional Information
Table 30. Additional Information
Document Description Download Link
ECCN #: EAR99 Five character designation used on the —
commerce Control List (CCL) to identify dual
use items for export control purposes.
HTS Classification Code: A Harmonized Tariff Schedule (HTS) code —
8542.39.0000 developed by the World Customs Organization
to classify/define internationally traded goods.
Part number Generator Tool used to create the part number based on https://www.sitime.com/part-number-generator
desired features.
Manufacturing Notes Tape & Reel dimension, reflow profile and https://www.sitime.com/support/resource-library/manufacturing-notes-sitime-
other manufacturing related info products
Qualification Reports RoHS report, reliability reports, http://www.sitime.com/support/quality-and-reliability
composition reports
Performance Reports Additional performance data such as phase http://www.sitime.com/support/performance-measurement-report
noise, current consumption, and jitter for
selected frequencies
Termination Techniques AN10029 Termination design http://www.sitime.com/support/application-notes
recommendations
Layout Techniques AN10006 Layout recommendations http://www.sitime.com/support/application-notes
Time Master Web Based Tool to establish proper programming https://www.sitime.com/time-master-web-based-configurator
Configurator

Evaluation Boards SiT6712EB Evaluation Board User Manual https://www.sitime.com/support/user-guides

Demo Boards SiT6701DM, SiT6702DM Demo Board User https://www.sitime.com/support/user-guides
Manual

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SiT3521 1 to 340 MHz Elite Platform I2C/SPI Programmable Oscillator

Revision History
Table 31. Revision History
Revisions Release Date Change Summary
0.1 3-Mar-2017 Initial draft
0.2 10-Mar-2017 Added I2C Timing diagram for ISP Function
Modified Block Diagram to include approximate MEMS frequency (47 MHz)
Updated ISP function procedure
Updated Package Drawing
0.21 10-Mar-2017 Added Table 5, I 2C Electrical Characteristics
0.22 11-Oct-2017 Fixed I2C Timing diagram on page 12 to show output disabled when first PFM value is written.
Added Output Drive Strength Control to Block Diagram on page 9
Changed PFM Range from 12.59 - 16.34 to 13.83 – 15.43.
Changed 156.25 MHz programming example so that it corresponds to the new PFM range.
Updated logo and company address, other page layout changes
0.90 2-Apr-2018 Preliminary release
0.99 22-Aug-2018 Updated thermal numbers, fixed minor errors
0.991 25-Apr-2020 ±10 ppm option
Updated POD (Dimensions Drawings)
Added Evaluation and Demo Boards reference in Additional Information
Other page layout changes
Added HTS classification code
Added 105°C support for I2C operation
Increased max operating junction temperature for 70°C and 85°C ambient
Updated Frac-N PLL numbers in Table 19
Updated I2C Timing Requirements for “Fall time of both SCLK and SDA”
1.0 4-Nov-2020 Updated I2C Write/Read Sequence section
Updated schematics
Updated frequency re-programming section
Updated register description section
Removed HCSL maximum output current specification
Changed rev table date format
Final release
1.01 30-Apr-2021 Updated Table 17
Updated hyperlink to Manufacturing Notes; Changed date format

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© SiTime Corporation 2017-2021. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liabili ty for any loss, damage
or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect
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