KARPAGAM INSTITUTE OF TECHNOLOGY DPCO LAB MANUAL

EXPERIMENTS

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DESIGN
1.Absorption Law
A+AB = A

2. Involution (or) Double complement Law

A=A

3. Idempotent Law
A+A=A

A.A = A

4.Demorgan’s Law
A+B = A.B

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EXP NO: 1
VERIFICATION OF BOOLEAN THEOREMS USING LOGIC
GATES

AIM:
To verify the Boolean theorems using logic gates.
APPARATUS REQUIRED:

COMPONENT SPECIFICATION QUANTITY

SL.NO

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. IC TRAINER KIT - 1

CONNECTING
6. - AS REQUIRED
WIRES

PROCEDURE:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc.
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
THEORY:
BASIC BOOLEAN LAWS
1. Commutative Law
The binary operator OR, AND is said to be commutative if,
A+B = B+A
A.B=B.A
2. Associative Law
The binary operator OR, AND is said to be associative if,
A+(B+C) = (A+B)+C
A.(B.C) = (A.B).C
3.Distributive Law
The binary operator OR, AND is said to be distributive if,
A+(B.C) = (A+B).(A+C)
A.(B+C) = (A.B)+(A.C)

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5. Distributive Law
A+(B.C) = (A+B).(A+C)

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4.Absorption Law
A+AB = A
A+AB = A+B
5.Involution (or) Double complement Law
A=A
6.Idempotent Law
A+A = A
A.A = A
7.Complementary Law
A+A' = 1
A.A' = 0
8.De Morgan’s Theorem
The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
The complement of the product is equal to the sum of the individual complements.
A.B = A + B
9. Consensus Theorem
Consensus theorem is used to simplify the Boolean expression by eliminating the
redundant terms.
AB+A'C+BC = AB+A'C

Proof: AB+A'C+BC = AB+A'C+BC (A+A')

= AB+A'C+ABC+A'BC
= AB(1+C)+A'C(1+B)
= AB+A'C. (using OR law, 1+C=1 and 1+B=1)

RESULT:
Thus the above stated Boolean laws are verified successfully.

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LOGIC DIAGRAM:
HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

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EXP.NO: 2
DESIGN AND IMPLEMENTATION OF COMBINATIONAL
CIRCUITS USING GATES FOR ARBITRARY FUNCTIONS

AIM:
To design and construct combinational circuits half adder, full adder, half subtractor
and full subtractor circuits and also to verify the truth table using logic gates.
APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY.

1. AND GATE IC 7408 1

2. X-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

4. OR GATE IC 7432 1

5. IC TRAINER KIT - 1
CONNECTING
6. - AS REQUIRED
WIRES
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one from the
sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as
a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry
out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a
half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output
will be taken from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be
applied using X-OR Gate, borrow output can be implemented using an AND Gate and an
inverter.
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half subtractor
put together gives a full subtractor .The first half subtractor will be C and A B. The output
will be difference output of full subtractor. The expression AB assembles the borrow output
of the half subtractor and the second term is the inverted difference output of first X-OR.

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LOGIC DIAGRAM:
FULL ADDER
FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC

K-Map for CARRY:

CARRY = AB + BC + AC

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PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

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LOGIC DIAGRAM:
HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:

BORROW = A’B

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LOGIC DIAGRAM:
FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

A B C BORROW DIFFERENCE

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

K-Map for Difference: K-Map for Borrow:

Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C

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RESULT:
Thus the adder and subtractor using combinational circuits were designed and the
truth tables were verified successfully.

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PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER

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EXPT NO: 3
IMPLEMENTATION OF 4-BIT BINARY ADDER/SUBTRACTOR
CIRCUITS

AIM:
To design and implement 4-bit adder and subtractor circuits using IC7483.
APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. IC IC 7483 1

2. EX-OR GATE IC 7486 1

3. NOT GATE IC 7404 1

4. IC TRAINER KIT - 1

5. CONNECTING WIRES - AS REQUIRED

THEORY:
4 BIT BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends bits
of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to left, with
subscript 0 denoting the least significant bits. The carries are connected in chain through the
full adder. The input carry to the adder is C 0 and it ripples through the full adder to the output
carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C 0 must be
equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot
be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits
must be represented in BCD and should appear in the form listed in the columns.

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LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:
4-BIT BINARY ADDER/SUBTRACTOR

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PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

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TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

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RESULT:
Thus the designs of 4-bit adder and subtractor have been verified using logic gates
and truth table is successfully.

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LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

K-Map for G3: K-Map for G1:

G3 = B3

K-Map for G2:

K-Map for G0:

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EXPT NO: 4
IMPLEMENTATION OF CODE CONVERTERS

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
APPARATUS REQUIRED:
SL.NO COMPONENT SPECIFICATION QUANTITY
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
CONNECTING
6. - AS REQUIRED
WIRES
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same information.
Thus, code converter is a circuit that makes the two systems compatible even though each
uses different binary code.
The bit combination assigned to binary code to gray code. Since each code uses four
bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-
weighted code.
The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.
A code converter is a circuit that makes the two systems compatible even though each
uses a different binary code. To convert from binary code to Excess-3 code, the input lines
must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.
A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that implements
this circuit. Now the OR gate whose output is C+D has been used to implement partially each
of three outputs

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TRUTH TABLE:

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

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PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

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LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

K-Map for B3: K-Map for B1:

B3 = G3
K-Map for B2: K-Map for B0:

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TRUTH TABLE:
Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

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LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR

K-Map for E3: K-Map for E1:

E3 = B3 + B2 (B0 + B1)
K-Map for E2:

K-Map for E0:

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TRUTH TABLE:
BCD input Excess – 3 outputs

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x
1 1 1 0 x x x x
1 1 1 1 x x x x

LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR

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K-Map for A: K-Map for C:

A = X1 X2 + X3 X4 X1

K-Map for B:
K-Map for D:

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TRUTH TABLE:
Excess – 3 Input BCD Output

X1 X2 X3 X4 A B C D

0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

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RESULT:
Thus the code convertors were designed and the truth tables were verified successfully.

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LOGIC DIAGRAM:
BCD ADDER

K MAP

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EXPT NO: 5
IMPLEMENTATION OF BCD ADDER, ENCODER AND
DECODER CIRCUITS

AIM:
To implement BCD adder, encoder and decoder circuits using logic gates.
APPARATUS REQUIRED:
S. No Name of the Apparatus Range Quantity
1. Digital IC trainer - 1
2. NOT Gate IC 7404 1
3. OR Gate IC 7432 1
4. AND Gate IC7408 1
5. Bread Board - 1
6. NOT Gate IC7404 1
7. Connecting wires and probes - As required
THEORY:
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an input
carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot
be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits
must be represented in BCD and should appear in the form listed in the columns.
A BCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal
digits, together with the input carry, are first added in the top 4 bit adder to produce the binary
sum.
ENCODER:
An encoder has 2n input lines and n output lines. In encoder the output lines generates
the binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary code.
In encoder it is assumed that only one input has a value of one at any given time otherwise
the circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are
zero. The zero outputs can also be generated when D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has
fewer bits than the output code. Each input code word produces a different output code word
i.e there is one to one mapping can be expressed in truth table. In the block diagram of
decoder circuit the encoded information is present as n input producing 2 n possible outputs. 2n
output values are from 0 through out 2n – 1.

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TRUTH TABLE:

BCD SUM CARRY

S4 S3 S2 S1 C
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

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PROCEDURE:
1. The connections are made as per the circuit diagram.
2. The different IC’s are placed in the breadboard and inputs are given to the IC’s
and the corresponding circuits are noted.
3. The truth tables for the corresponding circuits are verified.

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BCD TO DECODER:
PIN DIAGRAM FOR IC 74147:

LOGIC DIAGRAM FOR ENCODER:

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TRUTH TABLE:

INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

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TRUTH TABLE:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0
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RESULT:
The BCD adder, encoder and decoder circuits were designed and the input and output were
verified successfully.
 DPCO LAB MANUAL|46

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR MULTIPLEXER:

TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
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EXPT NO: 6
IMPLEMENTATION OF FUNCTIONS USING MULTIPLEXERS

AIM:
To design and implement multiplexer using logic gates.
APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY

1. 3 I/P AND GATE IC 7411 2

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. IC TRAINER KIT - 1

5. CONNECTING WIRES - AS REQUIRED

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller number
of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
n
particular input line is controlled by a set of selection lines. Normally there are 2 input line and
n selection lines whose bit combination determine which input is selected.
PROCEDURE:
1. Connections are given as per circuit diagram.
2. Logical inputs are given as per circuit diagram.
3. Observe the output and verify the truth table.

RESULT:
 DPCO LAB MANUAL|48

Thus the multiplexer using logic gates was designed and implemented successfully.
PIN DIAGRAM:

LOGIC DIAGRAM:

LOGIC DIAGRAM:
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EXP. NO: 7
IMPLEMENTATION OF THE SYNCHRONOUS COUNTERS

AIM:
To design and construct the synchronous up and down counter using JK flip-flops.
APPARATUS REQUIRED:
SL.No. COMPONENT SPECIFICATION QUANTITY
NO.
1 IC TRAINER KIT - 1

7476 2
2 IC
7408 1

3 CONNECTING WIRES - AS REQUIRED

THEORY:
SYNCHRONOUS UP COUNTER:
When counter is clocked such that each flip flop in the counter is triggered at the same time,
the counter is called as synchronous counter. Here, clock signal is connected in parallel to clock
input of both the flip flops. But the QA output of first stage is used to drive the J and K input of the
second stage.
SYNCHRONOUS DOWN COUNTER:
Ripple counter could be made to count down by using the inverted output of each flip flop to
drive the next flip flop in the counter can be constructed in a similar manner that is used by the
interval flip flop output to drive the following JK flip flop input.
PROCEDURE:
1. The connections are made as per the circuit diagram.
2. The different IC’s are placed in the breadboard and inputs are given to the IC’s and the
corresponding circuits are noted.
3. The truth tables for the corresponding circuits are verified.
 DPCO LAB MANUAL|50

TRUTH TABLE:
 DPCO LAB MANUAL|51

RESULT:
 DPCO LAB MANUAL|52

Thus the synchronous up and down counter were designed and verified successfully.
PIN DIAGRAM:

LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1
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EXPT NO: 8
IMPLEMENTATION OF A UNIVERSAL SHIFT REGISTER

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out
APPARATUS REQUIRED:

SL.NO COMPONENT SPECIFICATION QUANTITY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. CONNECTING WIRES - AS REQUIRED

THEORY:
A register is capable of shifting its binary information in one or both directions is known as
shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output
of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses
which causes the shift in the output of the flip flop.
The simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of
register one bit position to right.
PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
 DPCO LAB MANUAL|54

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:

TRUTH TABLE:

OUTPUT
CLK DATA
QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1
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LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1
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LOGIC DIAGRAM:
PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK
DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0
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RESULT:
 DPCO LAB MANUAL|60

Thus the design and implementation of Universal shift register is verified successfully.
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EXP. NO: 9
SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

AIM:
To study computer architecture simulator SMPCache.
THEORY:
SMPCache Overview:
SMPCache is a trace-driven simulator for the analysis of cache memory systems on
symmetric multiprocessors. The simulation is based on a model built according to the architectural
basic principles of these systems. The simulator has a full graphic and user-friendly interface, and it
operates on PC systems with Windows. It can be used for experimenting the different theoretical
aspects about cache memories and multiprocessors in the regular courses of Computer Architecture.
Some of the parameters that they can study with the simulator are: Program locality; influence of the
number of processors, cache coherence protocols, schemes for bus arbitration, mapping, replacement
policies, cache size (blocks in cache), number of cache sets (for set associative caches), number of
words by block (memory block size), word wide. Furthermore, students can use SMPCache as
reference for checking their own simulators. The construction of the simulator forces to know in
depth the theoretical considerations about cache memory systems, and particularly on multiprocessor
environments (cache coherence, cache coherence protocols). In this way, we have observed that we
can acquire a better and larger knowledge about these aspects.
The simulator has proved its utility on program analysis and design strategies of memory
systems on multiprocessors. The previous features enable the simulator to be used in order to
understand the design of organizations that run optimally a determinate type of parallel programs or
to improve the operating mode of a concrete parallel architecture.
Features of SMPCache:

Processors in SMP 1, 2, 3, 4, 5, 6, 7 or 8

Cache coherence protocols MSI, MESI (Illinois) or Dragon

Schemes for bus arbitration Random, LRU or LFU

Word wide (bits) 8, 16, 32 or 64

Words by block 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 or 1024

Blocks in main memory 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
4096, 8192, 16384, 32768, 65536, 131072,
262144, 524288, 1048576, 2097152 or 4194304

Blocks in cache 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 or 2048
 DPCO LAB MANUAL|62

SMPCACHE SIMULATOR ENVIRNOMENT:

(Graphic interface of the simulator SIMCache)

 DPCO LAB MANUAL|63

(State transition diagram for a particular cache block.)

Mapping Direct, Set-Associative or Fully-

Associative

Cache sets (for set associative caches) 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024
or 2048

Replacement policies Random, LRU, FIFO or LFU

Writing strategies Write-Back (for cache coherence protocols

used)

Cache levels in the memory hierarchy 1

References To memory words

Maximum block size 8 KB

Maximum main memory size 32 GB

Maximum cache size (excluded labels, block state 16 MB

bits, counts, etc.)

SMPCache Simulation types:

 DPCO LAB MANUAL|64

There are three kinds of simulation and it is possible to change from one to other without
waiting the simulation end:
 Step by step: The simulation is stopped after every memory access.
 With breakpoint: The simulation is stopped when a specific number of memory accesses
is reached.
 Complete execution: The simulation is stopped when all the memory traces are finished.
Parameter measurements of SMPCache:
SMPCache simulator is used to measure parameters like:
 Number of bus transactions (it depends on cache coherence protocol).
 Number of block transfers on the bus.
 Bus traffic taking into account the previous measurements.
 Number of state transitions (each block in a cache has a state associated with it).
 Number of state transitions from a particular state to other.
 Global number of memory accesses, and for types: instruction captures, data readings and
data writings.
 Number of cache hits and misses, as well as hit and miss rate.
Realization of simulation:
 Observing the complete multiprocessor and all the memory blocks.
 DPCO LAB MANUAL|65

 Observing a specific cache and all the memory blocks.

 Observing the complete multiprocessor, but focusing on a particular block.
 Observing a specific cache and a particular memory block.
 DPCO LAB MANUAL|66

RESULT:
Thus the computer architecture simulator SMPCache is studied successfully.

EXPERIMENTS BEYOND
SYLLABUS
 DPCO LAB MANUAL|67

EXP. NO: 10
Design entry simulation and implementation of 4 bit Ripple Carry Adder

AIM:
To design simulate and implement 4- bit Ripple Carry Adder in Spartan-3E FPGA
APPARATUS REQUIRED:
Xilinx ISE software, Spartan-3E FPGA, Personal computer
PROCEDURE:
1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box will appear
and give the name of the file and select Next.
2) A Project Setting dialog box will appear, choose the Simulator as ISIM (VHDL / Verilog) & click
Next. A project Summary dialog box will appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog module and
give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A programming
window will appear and write the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than we have to select
Check Syntax for checking the Syntax.
 DPCO LAB MANUAL|68

6) Then Select the Simulation Tool bar and select the file name of the program written. Click Isim
Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output window will open the assigned input and output ports. Give the inputs to the ports
by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User Constraint and
then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning – port Synthesis, new window will open, in that Select Scalar posts.
Now click Site and assign the input and output pin numbers that is present in the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize → View RTL → port. Click → Logic gates and then View technology scheme
→ pic (LUT).
14) Now Select Summation ∑ and select Analysis → synthesis report.
15) Then Select Implement design that is present on the left side of the window. Under Implement
design click translate → map → place and route.
16) Select generate programming file and Switch ON FPGA kit.

Output:
 DPCO LAB MANUAL|69

17) In this Window click Configure target device → manage configure → Survey → No.
18) Click No. It shows the dialog box as Welcome to Impart, click OK and Select Yes Configure.
Now give the filename and Open → SPI or BPT Prom give number.
19) A Window will Open, click Device 1 → OK. Click Identify Succeed → IC. Right Click IC and
Select program.
20) The program is successfully dumped into the kit and it displays as Program succeeded. The
Inputs are given using the switch in the kit and the corresponding output can be seen.
PROGRAM:
4- BIT RIPPLE CARRY ADDER
module fulladder(X, Y, Ci, S, Co);
input X, Y, Ci;
output S, Co;
wire w1,w2,w3;
//Structural code for one bit full adder
xor G1(w1, X, Y);
xor G2(S, w1, Ci);
and G3(w2, w1, Ci);
and G4(w3, X, Y);
or G5(Co, w2, w3);
 DPCO LAB MANUAL|70

endmodule
module rippe_adder(X, Y, S, Co);
input [3:0] X, Y;// Two 4-bit inputs
output [3:0] S;
output Co;
wire w1, w2, w3;
// instantiating 4 1-bit full adders in Verilog
fulladder u1(X[0], Y[0], 1'b0, S[0], w1);
fulladder u2(X[1], Y[1], w1, S[1], w2);
fulladder u3(X[2], Y[2], w2, S[2], w3);
fulladder u4(X[3], Y[3], w3, S[3], Co);
endmodule

RESULT:
Thus the 4- bit Ripple Carry Adder was successfully designed using verilog HDL and
implemented in Spartan FPGA.
 DPCO LAB MANUAL|71

EXP. NO: 11 DESIGN ENTRY SIMULATION AND IMPLEMENTATION OF 32 TO 1

MULTIPLEXER USING 2 TO 1 MULTIPLEXER

AIM:
To design simulate and implement 32-to-1 multiplexer using 2-to-1 multiplexer in Spartan-
3E FPGA.
APPARATUS REQUIRED:
Xilinx ISE software, Spartan-3E FPGA, Personal computer.
PROCEDURE:
1) Open the file and ISE Design Suit. Click FILE and Select New Project. A dialog box will appear
and give the name of the file and select Next.
2) A Project Setting dialog box will appear, choose the Simulator as ISIM (VHDL / Verilog) & click
Next. A project Summary dialog box will appear in that Select Finish.
3) In the project toolbar, select New VHDL Source. Then Select the file type as Verilog module and
give name to the file.
4) A dialog boxy appears and assign the input and Output ports and click Ok. A programming
window will appear and write the required program and save it.
5) On the left side choose Synthesize XST. If the Synthesize is successful than we have to select
Check Syntax for checking the Syntax.
 DPCO LAB MANUAL|72

6) Then Select the Simulation Tool bar and select the file name of the program written. Click Isim
Simulator. It displays Behavioral Syntax and Simulate Behavioral.
7) Now Select the behavioral Syntax first and then the Simulate behavioral.
8) Now the output window will open the assigned input and output ports. Give the inputs to the ports
by selecting force Constant and click Run all to View the outputs.
9) After Simulation is over, select Implementation. Under Implementation select User Constraint and
then select input pin planning (Plan Ahead) - port - Synthesis.
10) Now connect the kit to the System.
11) After input pin planning – port Synthesis, new window will open, in that Select Scalar posts.
Now click Site and assign the input and output pin numbers that is present in the kit.
12) Select the check box for all the inputs and outputs and Save it.
13) Select Synthesize → View RTL → port. Click → Logic gates and then View technology scheme
→ pic (LUT).
14) Now Select Summation ∑ and select Analysis → synthesis report.
15) Then Select Implement design that is present on the left side of the window. Under Implement
design click translate → map → place and route.
16) Select generate programming file and Switch ON FPGA kit.
17) In this Window click Configure target device → manage configure → Survey → No.
 DPCO LAB MANUAL|73

18) Click No. It shows the dialog box as Welcome to Impart, click OK and Select Yes Configure.
Now give the filename and Open → SPI or BPT Prom give number.
19) A Window will Open, click Device 1 → OK. Click Identify Succeed → IC. Right Click IC and
Select program.
20) The program is successfully dumped into the kit and it displays as Program succeeded. The
Inputs are given using the switch in the kit and the corresponding output can be seen.
PROGRAM:
32-TO-1 MULTIPLEXER USING 2-TO-1 MULTIPLEXER
module mux2x32to32( DataOut,Data0, Data1, Select);
output [31:0] DataOut; // Data Out
input [31:0] Data0, Data1; // Data In 1 and 2
input Select;
// if Select = 0, DataOut = Data0
// otherwise, DataOut = Data1
mux2_1 mux0(DataOut[0],Data0[0],Data1[0],Select);
mux2_1 mux1(DataOut[1],Data0[1],Data1[1],Select);
mux2_1 mux2(DataOut[2],Data0[2],Data1[2],Select);
mux2_1 mux3(DataOut[3],Data0[3],Data1[3],Select);
mux2_1 mux4(DataOut[4],Data0[4],Data1[4],Select);
mux2_1 mux5(DataOut[5],Data0[5],Data1[5],Select);
mux2_1 mux6(DataOut[6],Data0[6],Data1[6],Select);
 DPCO LAB MANUAL|74

mux2_1 mux7(DataOut[7],Data0[7],Data1[7],Select);
mux2_1 mux8(DataOut[8],Data0[8],Data1[8],Select);
mux2_1 mux9(DataOut[9],Data0[9],Data1[9],Select);
mux2_1 mux10(DataOut[10],Data0[10],Data1[10],Select);
mux2_1 mux11(DataOut[11],Data0[11],Data1[11],Select);
mux2_1 mux12(DataOut[12],Data0[12],Data1[12],Select);
mux2_1 mux13(DataOut[13],Data0[13],Data1[13],Select);
mux2_1 mux14(DataOut[14],Data0[14],Data1[14],Select);
mux2_1 mux15(DataOut[15],Data0[15],Data1[15],Select);
mux2_1 mux16(DataOut[16],Data0[16],Data1[16],Select);
mux2_1 mux17(DataOut[17],Data0[17],Data1[17],Select);
mux2_1 mux18(DataOut[18],Data0[18],Data1[18],Select);
mux2_1 mux19(DataOut[19],Data0[19],Data1[19],Select);
mux2_1 mux20(DataOut[20],Data0[20],Data1[20],Select);
mux2_1 mux21(DataOut[21],Data0[21],Data1[21],Select);
mux2_1 mux22(DataOut[22],Data0[22],Data1[22],Select);
mux2_1 mux23(DataOut[23],Data0[23],Data1[23],Select);
mux2_1 mux24(DataOut[24],Data0[24],Data1[24],Select);
mux2_1 mux25(DataOut[25],Data0[25],Data1[25],Select);
mux2_1 mux26(DataOut[26],Data0[26],Data1[26],Select);

Output:
 DPCO LAB MANUAL|75

mux2_1 mux27(DataOut[27],Data0[27],Data1[27],Select);
mux2_1 mux28(DataOut[28],Data0[28],Data1[28],Select);
mux2_1 mux29(DataOut[29],Data0[29],Data1[29],Select);
mux2_1 mux30(DataOut[30],Data0[30],Data1[30],Select);
mux2_1 mux31(DataOut[31],Data0[31],Data1[31],Select);
endmodule
// fpga4student.com: FPGA projects, Verilog projects, VHDL projects
// Verilog project: Verilog code for Multiplexer
// Verilog code for 2x5-to-5 Multiplexer
module mux2x5to5( AddrOut,Addr0, Addr1, Select);
output [4:0] AddrOut; // Address Out
input [4:0] Addr0, Addr1; // Address In 1 and 2
input Select;
mux2_1 mux0(AddrOut[0],Addr0[0],Addr1[0],Select);
mux2_1 mux1(AddrOut[1],Addr0[1],Addr1[1],Select);
mux2_1 mux2(AddrOut[2],Addr0[2],Addr1[2],Select);
mux2_1 mux3(AddrOut[3],Addr0[3],Addr1[3],Select);
mux2_1 mux4(AddrOut[4],Addr0[4],Addr1[4],Select);
endmodule
// fpga4student.com: FPGA projects, Verilog projects, VHDL projects
 DPCO LAB MANUAL|76

// Verilog project: Verilog code for Multiplexer

// Verilog code for 2-to-1 Multiplexer
module mux2_1(O,A,B,sel);
// if sel = 0, O = A
// if sel = 1, O =B
output O;
input A,B,sel;
not #(50) not1(nsel,sel);
and #(50) and1(O1,A,nsel);
and #(50) and2(O2,B,sel);
or #(50) or2(O,O1,O2);
endmodule

Result:
Thus the 4- bit Ripple Carry Adder was successfully designed using verilog HDL and
implemented in Spartan FPGA.