UNIT-5

CENTRAL PROCESSING UNIT

General Registar Organization:

A set of flip-flops forms a register. A register is a unique high-speed storage area

in the CPU. They include combinational circuits that implement data processing.
The information is always defined in a register before processing. The registers
speed up the implementation of programs.

Registers implement two important functions in the CPU operation are as follows
−

• It can support a temporary storage location for data. This supports the directly implementing
programs to have fast access to the data if required.
• It can save the status of the CPU and data about the directly implementing program.
The CPU bus system is managed by the control unit. The control unit explicit the data flow
through the ALU by choosing the function of the ALU and components of the system.

Consider R1 ← R2 + R3, the following are the functions implemented within the CPU −

MUX A Selector (SELA) − It can place R2 into bus A.

MUX B Selector (SELB) − It can place R3 into bus B.

ALU Operation Selector (OPR) − It can select the arithmetic addition (ADD).

Decoder Destination Selector (SELD) − It can transfers the result into R1.

The multiplexers of 3-state gates are performed with the buses. The state of 14 binary
selection inputs determines the control word. The 14-bit control word defines a micro-
operation.

The encoding of register selection fields is specified in the table.

Encoding of Register Selection Field

Stack Organization:

Stack is also known as the Last In First Out (LIFO) list. It is the most important feature in
the CPU. It saves data such that the element stored last is retrieved first. A stack is a
memory unit with an address register. This register influence the address for the stack,
which is known as Stack Pointer (SP). The stack pointer continually influences the address
of the element that is located at the top of the stack.
It can insert an element into or delete an element from the stack. The insertion operation is
known as push operation and the deletion operation is known as pop operation. In a
computer stack, these operations are simulated by incrementing or decrementing the SP
register.

Register Stack
The stack can be arranged as a set of memory words or registers. Consider a 64-word
register stack arranged as displayed in the figure. The stack pointer register includes a
binary number, which is the address of the element present at the top of the stack. The
three-element A, B, and C are located in the stack.

The element C is at the top of the stack and the stack pointer holds the address of C that is
3. The top element is popped from the stack through reading memory word at address 3
and decrementing the stack pointer by 1. Then, B is at the top of the stack and the SP holds
the address of B that is 2. It can insert a new word, the stack is pushed by incrementing the
stack pointer by 1 and inserting a word in that incremented location.
The stack pointer includes 6 bits, because 2 6 = 64, and the SP cannot exceed 63 (111111 in
binary). After all, if 63 is incremented by 1, therefore the result is 0(111111 + 1 =
1000000). SP holds only the six least significant bits. If 000000 is decremented by 1 thus
the result is 111111.

Therefore, when the stack is full, the one-bit register ‘FULL’ is set to 1. If the stack is null,
then the one-bit register ‘EMTY’ is set to 1. The data register DR holds the binary
information which is composed into or readout of the stack.

First, the SP is set to 0, EMTY is set to 1, and FULL is set to 0. Now, as the stack is not full
(FULL = 0), a new element is inserted using the push operation.

The push operation is executed as follows −

SP←SP + 1 It can increment stack pointer

K[SP] ← DR It can write element on top of the stack

If (SP = 0) then (FULL ← 1) Check if stack is full

EMTY ← 0 Mark the stack not empty

The stack pointer is incremented by 1 and the address of the next higher word is saved in
the SP. The word from DR is inserted into the stack using the memory write operation. The
first element is saved at address 1 and the final element is saved at address 0. If the stack
pointer is at 0, then the stack is full and ‘FULL’ is set to 1. This is the condition when the SP
was in location 63 and after incrementing SP, the final element is saved at address 0.
During an element is saved at address 0, there are no more empty registers in the stack.
The stack is full and the ‘EMTY’ is set to 0.

A new element is deleted from the stack if the stack is not empty (if EMTY = 0). The pop
operation includes the following sequence of micro-operations −

DR←K[SP] It can read an element from the top of the stack

SP ← SP – 1 It can decrement the stack pointer

If (SP = 0) then (EMTY ← 1) Check if stack is empty

FULL ← 0 Mark the stack not full

The top element from the stack is read and transfer to DR and thus the stack pointer is
decremented. If the stack pointer reaches 0, then the stack is empty and ‘EMTY’ is set to 1.
This is the condition when the element in location 1 is read out and the SP is decremented
by 1.
Instruction Formats

An instruction format refers to the layout or structure of a machine-level instruction, which

consists of several fields that hold different types of information. Each field in an instruction has
a specific role in telling the CPU what operation to perform, where the operands are located,
and how to access them.

The typical components of an instruction format include:

 • Opcode: The operation to be performed (e.g., addition, subtraction).
• Operands: The data or addresses involved in the operation.
• Addressing Modes: It defines how the operands are accessed (e.g., direct, indirect).

The instruction format directly influences how the CPU fetches, decodes, and executes
instructions, making it a vital concept in computer organization.

Types of Instruction Formats

Based on the number of address fields used in the instruction, instruction formats are classified
into zero, one, two, and three-address formats. Each has distinct characteristics and uses in
different types of instruction formats in computer architecture. Let’s break down these formats:

1. Zero-Address Instructions
It operates without specifying any operands explicitly. Typically used in stack-based
architectures, these instructions rely on the stack to store operands. The operations are
performed on the top of the stack, and the results are also stored on the stack.

Example
In Postfix Notation, X = (A + B) * (C + D) would be written as AB+CD+*.

Example Instructions for Zero Address

PUSH A TOP = A

PUSH B TOP = B

ADD TOP = A+B

PUSH C TOP = C

PUSH D TOP = D

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

POP X M[X] = TOP

2. One-Address Instructions
It specifies a single operand, typically held in an accumulator. The accumulator is an implicit
register used in the operation. The result can either be stored in the accumulator or another
location.

opcode operand/address of operand mode

Example
The expression X = (A + B) * (C + D) can be computed using one-address instructions with the
accumulator (AC).

Example Instructions for One-Address

LOAD A AC = M[A]

ADD B AC = AC + M[B]
STORE T M[T] = AC

LOAD C AC = M[C]

ADD D AC = AC + M[D]

MUL T AC = AC * M[T]

STORE X M[X] = AC

3. Two-Address Instructions
It allows for two operands to be specified. These operands can be registers or memory
locations. The result can overwrite one of the source operands or can be stored in a separate
location

opcode Destination Address Source Address mod

Example
The expression X = (A + B) * (C + D) can be calculated using two registers.

Example Instructions for Two-Address

MOV R1, A R1 = M[A]

ADD R1, B R1 = R1 + M[B]

MOV R2, C R2 = M[C]

ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

MOV X, R1 M[X] = R1

4. Three-Address Instructions
It specifies three operands contains two source operands and one destination operand. This
format allows for more complex operations and direct representation of expressions. It is most
commonly used in high-level language compilers and optimizers.

Source
opcode Destination address Source address mod
address

Example
The expression X = (A + B) * (C + D) can be computed with three addresses.

Example Instructions for Three-Address

ADD R1, A, B R1 = M[A] + M[B]

ADD R2, C, D R2 = M[C] + M[D]

MUL X, R1, R2 M[X] = R1 * R2

 Addressing Modes:

Addressing Modes are an instruction set used for communicating with the central processing unit (CPU)
for performing any specific task.

Generally the following addressing modes are used for executing the instruction in 8085
microcontroller:-

o Immediate addressing mode

o Indexed addressing mode
o Direct addressing mode
o Register direct addressing mode
o Register indirect addressing mode

Immediate Addressing Mode

Let's start with an example.

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1. MOV A, #4AH
In simple, we can write,

1. MOV A, #data
It is known as immediate because 8-bit data is send immediately to the accumulator (destination
operand).

Consider the following illustration describes the above set of instructions and their execution. The opcode
74H is saved at 0202 address. The data 4AH is saved at 0203 address inside a program memory. After
reading an opcode 74H, the data at the next memory address is copied to accumulator A (E0H is the
address of accumulator). Since an instruction is of 2-bytes and it is executed in single cycle, the program
counter will increment by 2 and will point to 0204 address of the program memory.
 Indexed Addressing Mode
Let us consider two examples for understanding the concept of indexed addressing mode. Take a look at
the below instructions:

1. MOVC A, @A+DPTR
2. MOVC A, @A+PC
Here PC is the program counter and DPTR is the data pointer (both are 16-bit registers). Consider the
first example.

1. MOVC A, @A+DPTR
In this the source operand is @A+DPTR. It has a source data from that place. Here the contents of DPTR
are added with the current content of the accumulator. This addition provides a new address that is the
address of the source data. The data pointed by this address is further transferred to the accumulator.
 Consider the opcode is 93H. The DPTR having the value of 01FE, here 01 is located in DPH side (higher
8 bits) and FE is located in DPL side (lower 8 bits). Consider Accumulator has the value 02H. After that a
16-bit addition is done and 01FE H+02H result in 0200 H. Data present at the location 0200H will become
transferred to the accumulator. The previous value of the accumulator (02H) will be replaced by the new
data from 0200H. The new data inside the accumulator is highlighted in the illustration.

Direct Addressing Mode

Direct addressing mode is used for addressing an operand. Here, an address of the data (source data) is
present as an operand. Let's consider an example.

1. MOV A, 07H
The register bank#0 (7th register) has the address 07H. When the MOV instruction is executed, the data
stored in register 07H is moved inside an accumulator. As the register 07H holding the data 1FH,
therefore 1FH is moved to the accumulator.
Note - we are not using '#' in direct addressing mode, as that used in immediate mode because If we had
used '#', the data value 07H is transferred to the accumulator instead of 1FH.

Now, consider the following illustration. It shows how the instruction is executed:-

As shown in an above illustration, it is a 2-byte instruction which requires 1 cycle to complete.

The program counter will be incremented by 2 and will point to 0204 memory location. The opcode for an
instruction MOV A, address of operation is E5H. Whenever the instruction at 0202 is run (E5H), the
accumulator will become active and ready to receive data. Then the PC jumps to the next address at
0203 and look up the address of the location 04H where the source data (i.e. transferred to accumulator)
is located. At 04H, the controller finds the data 1FH and transfers this to the accumulator and hence the
execution of instruction is completed.

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Register Direct Addressing Mode:

Inside a register direct addressing mode, we use the register name directly (as source operand).

Let us consider an example.

1. MOV A, R4
At a time, the registers are able to take values from R0 to R7. There are 32 such registers are present in
microcontroller. In order to use these 32 registers with just 8 variables for addressing the registers,
register banks are used.

At one time, a single register bank is to be selected. Selection of a register bank is made possible by
using a Special Function Register (SFR) it named as Processor Status Word (PSW). PSW is an 8-bit
SFR where each bit can be programmed as required. Bits are assigned from PSW.0 to PSW.7.

Now, consider the following illustration. It represents how instruction is executed:-

Data (2F) movement is shown in bold. 2F is become transferred to the accumulator from data memory
location 0CH and it is shown by dotted line. 0CH is an address location of Register 4 of register bank #1.
The instruction shown above is of 1 byte and it requires 1 cycle for complete execution. It means that we
can save memory by using direct addressing mode.
 Register Indirect Addressing Mode
In register indirect addressing mode, the address of data is stored inside the register as an operand.

1. MOV A, @R0
Here the value present inside R0 is to be considered as an address, it is used for holding the data to be
transferred inside an accumulator. Example: If register R0 has the value 20H, and data 2FH is stored at
the address location of 20H, then the value of 2FH will become transferred to the accumulator after
executing the above instruction.

Now, consider the following illustration. It shows how the instruction is executed:-

Consider the opcode for MOV A, @R0 is E6H. Program control moves to address location 20H where it
locates the data 2FH and then transfer 2FH inside an accumulator. It is a 1-byte instruction and the
program counter (PC) is increments by 1 and moves to 0203 location of the program memory.
Data Transfer And Manipulation:

Data transfer involves the movement of data between different components of a computer
system, such as from the processor to memory, between registers, or across network
interfaces. This movement is essential for fetching instructions, storing results, and
communicating between various parts of a system.
Data manipulation, on the other hand, refers to the processes that transform and operate on
data to produce desired outcomes. This includes arithmetic operations, logical operations, bit-
level manipulations, and data shifting. Each of these operations plays a vital role in how
computers process information and execute tasks.

Data manipulation instructions can be categorized into three parts:

1) Arithmetic instruction
2) Logical and bit manipulation instructions
3) Shift instructions
Recommended Topic, Microinstruction in Computer Architecture
Arithmetic Instruction
Arithmetic instructions include increment, decrement, add, subtract, multiply, divide, add with
Carry, subtract with Borrow, negate that is (2’s) two's complement. If there’s a negative number,
it is considered as negate (so two's complement).
Generally, most computers carry instructions for all four of these operations. If computers have
only addition(ADD) and possibly subtraction(SUB) instructions, the other two operations, i.e.
multiplication(MUL) and division(DIV) must be generated using software subroutines. These
four basic arithmetic operations are sufficient for solving scientific problems when expressed in
numerical analysis methods.
The table given below shows the Arithmetic Instructions:
Name Mnemonic Example Explanation

Increases the value stored in register R1 by

Increment INC INC R1
1.

Decreases the value stored in register R2 by

Decrement DEC DEC R2
1.

Adds the value in register R4 to the value in

Add ADD ADD R3, R4
register R3.

Subtracts the value in register R6 from the

Subtract SUB SUB R5, R6
value in R5.

Multiplies the value in register R7 by the

Multiply MUL MUL R7, R8
value in R8.

Divides the value in register R9 by the value

Divide DIV DIV R9, R10
in R10.

Add with carry ADDC ADDC R11, Adds the value in register R12 and the carry
 Name Mnemonic Example Explanation

R12 flag to R11.

Subtract with SUBB R13, Subtracts the value in R14 and the borrow
SUBB
borrow R14 flag from R13.

Logical and Bit manipulation Instruction

We are having another list of instructions that is logical and bit manipulation instructions starting
with clear (that means clear the content of accumulator), complement the accumulator, AND,
OR, Exclusive-OR, Clear carry, Set carry, Complement carry, Enable interrupts, Disable
interrupts, all these are logical and bit manipulation instructions.
These logical instructions consider each operand bit individually and treat it as a Boolean
variable. Basically, logical instructions help perform binary operations on strings of bits stored in
registers.
• Clear instruction means making all the bits of a register ‘0’.
• AND instruction is sometimes referred to as bit clear instruction or mask.
• OR instruction is sometimes referred to as bit set instruction.
• Set instruction means making all the bits of a register ‘1’.
• XOR instruction is referred to as bit complement instruction.
Recommended Topic - Shift Registers in Digital Electronics
Name Mnemonic Example Explanation

Clear CLR CLR R1 Sets the value in register R1 to 0.

Inverts all the bits in the value stored in register

Complement COM COM R2
R2.

AND R3, Performs a bitwise AND between values in R3

AND AND
R4 and R4, stores the result in R3.

OR R5, Performs a bitwise OR between values in R5 and

OR OR
R6 R6, stores the result in R5.

XOR R7, Performs a bitwise XOR between values in R7

Exclusive-OR XOR
R8 and R8, stores the result in R7.

Clear carry CLRC CLRC Clears the carry flag (sets it to 0).

Set Carry SETC SETC Sets the carry flag to 1.

Complement Inverts the carry flag (if it was 1, it becomes 0,

COMC COMC
Carry and vice versa).

Enables the interrupt system, allowing interrupts

Enable Interrupt EI EI
to occur.
 Name Mnemonic Example Explanation

Disable Disables the interrupt system, preventing

DI DI
Interrupt interrupts from occurring.

Shift Instructions
Shift instructions allow the bits of a memory byte or register to be shifted one-bit place to the
right or the Left.
There are basically two types of shift instructions — arithmetic and logical. Arithmetic shifts
consider the contents of the memory byte or register to be a signed number. So, when the shift
is made, the number is arithmetically divided by two (right shift) or multiplied by two (left shift).
Logical shifts consider the contents of the register or memory byte to be just a bit pattern when
the shift is made.
• OP is opcode field
• RL (It tells whether to shift it right or left).
• REG (It determines which register is to be shifted).
• COUNT (It tells the number of places to be shifted).
• TYPE( It tells the type of shifting from the list given below).

In right-shift operations, zeros are shifted into high-order vacated positions. And in the case of
the left-shift operation, shifts the zero into low-order vacated positions.

Name Mnemonic

Logical Shift Right SHR

Logical Shift Left SHL

Arithmetic Shift Right SHRA

Arithmetic Shift Left SHLA

Rotate Right ROR

Rotate Left ROL

Rotate Right through carry RORC

Rotate Left through carry ROLC

PROGRAM CONTROL:
Instructions are always stored in successive memory locations. When processed in the CPU, the
instructions are fetched from consecutive memory locations and executed. Each time an
instruction is fetched from memory, the program counter is incremented so that it contains the
address of the next instruction in sequence. After the execution of a data transfer or data
manipulation instruction, control returns to the fetch cycle with the program counter containing
the address of the instruction next in sequence. On the other hand, a program control type of
instruction, when executed, may change the address value in the program counter and cause the
flow of control to be altered. In other words, program control instructions specify conditions for
altering the content of the program counter, while data transfer and manipulation instructions
specify conditions for data-processing operations. The change in value of the program counter as
a result of the execution of a program control instruction causes a break in the sequence of
instruction execution. This is an important feature in digital computers, as it provides control
over the flow of program execution and a capability for branching to different program
segments. Some typical program control instructions are listed in Table 8-10. The branch and
jump instructions are used interchangeably to mean the same thing, but sometimes they are used
to denote different addressing modes. The branch is usually a one-address instruction. It is
written in assembly language as BR ADR, where ADR is a symbolic name for an address. When
executed, the branch instruction causes a transfer of the value of ADR into the program counter.
Since the program counter contains the address of the instruction to be executed, the next
instruction will come from location ADR Branch and jump instructions may be conditional or
unconditional. An unconditional branch instruction causes a branch to the specified address
without any conditions. The conditional branch instruction specifies a condition such as branch if
positive or branch if zero. If the condition is met, the program counter is loaded with the branch
address and the next instruction is taken ..
The skip instruction does not need an address field and is therefore a zero-address instruction. A
conditional skip instruction will skip the next instruction if the condition is met. This is
accomplished by incrementing the program counter during the execute phase in addition to its
being incremented during the fetch phase. If the condition is not met, control proceeds with the
next instruction in sequence where the programmer inserts an unconditional branch instruction.
Thus a skip-branch pair of instructions causes a branch if the condition is not met, while a single
conditional branch instruction causes a branch if the condition is met. The call and return
instructions are used in conjunction with subroutines. Their performance and implementation are
discussed later in this section. The compare and test instructions do not change the program
sequence directly. They are listed in Table 8-10 because of their application in setting conditions
for subsequent conditional branch instructions. The compare instruction performs a subtraction
between two operands, but the result of the operation is not retained. However, oertain status bit
conditions are set as a result of the operation. Similarly, the test instruction performs the logical
AND of two operands and updates certain status bits without retaining the result or changing the
operands. The status bits of interest are the carry bit, the sign bit, a zero indication, and an
overflow condition. The generation of these status bits will be discussed first and then we will
show how they are used in conditional branch instructions.

Status Bit Conditions

It is sometimes convenient to supplement the ALU circuit in the CPU with a status register where status
bit conditions can be stored for further analysis. Status bits are also called condition-code bits or flag
bits. Figure 8-8 shows the block diagram of an 8-bit ALU with a 4-bit status register. The four status bits
are symbolized by C. S, Z, and V. The bits are set or cleared as a result of an operation performed in the
ALU.
1. Bit C (carry) is set to 1 if the end carry C8 is 1. It is cleared to 0 if the carry is 0.
2. Bit S (sign) is set to 1 if the highest-order bit F, is 1. It is set to 0 if the bit is 0.
3. Bit Z (zero) is set to 1 ifthe output ofthe ALU contains all O's. !t is cleared to 0 otherwise. In other
words, Z = 1 if the output is zero and Z = 0 if the output is not zero.
4. Bit V (overflow) is set to 1 if the exclusive-OR of the last two carries is equal to 1, and cleared to 0
otherwise. This is the condition for an
Subroutine Call and Return
A subroutine is a self-contained sequence of instructions that performs a given
computational task. During the execution of a program, a subroutine may be
called to perform its function many times at various points in the main program.
Each time a subroutine is called, a branch is executed to the beginning
of the subroutine to start executing its set of instructions. After the subroutine has
been executed, a branch is made back to the main program.
SP <- SP - 1
M [SP] <-PC
PC <- effective address
Decrement stack pointer Push content of PC onto the stack Transfer control to the
subroutine
If another subroutine is called by the current subroutine, the new return address is
pushed into the stack, and so on. The instruction that returns from the last
subroutine is implemented by the microoperations:
PC <- M[SP]
SP <- SP + 1
Pop stack and transfer to PC Increment stack pointer

Reduced Instruction Set Computer (RISC)

RISC is the way to make hardware simpler whereas CISC is the single
instruction that handles multiple work. In this article, we are going to
discuss RISC and CISC in detail as well as the Difference between RISC
and CISC, Let’s proceed with RISC first.

Reduced Instruction Set Architecture (RISC)

The main idea behind this is to simplify hardware by using an
instruction set composed of a few basic steps for loading, evaluating,
and storing operations just like a load command will load data, a store
command will store the data.

Characteristics of RISC
Simpler instruction, hence simple instruction decoding.
Instruction comes undersize of one word.
Instruction takes a single clock cycle to get executed.
More general-purpose registers.
Simple Addressing Modes.
Fewer Data types.
A pipeline can be achieved.
Advantages of RISC
Simpler instructions: RISC processors use a smaller set of simple
instructions, which makes them easier to decode and execute quickly.
This results in faster processing times.
Faster execution: Because RISC processors have a simpler instruction
set, they can execute instructions faster than CISC processors.
Lower power consumption: RISC processors consume less power than
CISC processors, making them ideal for portable devices.
Disadvantages of RISC
More instructions required: RISC processors require more instructions to
perform complex tasks than CISC processors.
Increased memory usage: RISC processors require more memory to
store the additional instructions needed to perform complex tasks.
Higher cost: Developing and manufacturing RISC processors can be
more expensive than CISC processors.
 Input-Output Organization

Peripheral devices:
A Peripheral Device is defined as a device that provides input/output functions for a computer
and serves as an auxiliary computer device without computing-intensive functionality.
A peripheral device is also called a peripheral, computer peripheral, input-output device, or I/O
device.

Classification of Peripheral devices

It is generally classified into 3 basic categories which are given below:

1. Input Devices:
The input device is defined as it converts incoming data and instructions into a pattern of
electrical signals in binary code that are comprehensible to a digital computer.
Example:.
Keyboard, mouse, scanner, microphone etc.

Keyboard: A keyboard is an input device that allows

users to enter text and commands into a computer
system.

Mouse: A mouse is an input device that allows users to

control the cursor on a computer screen.

Scanner: A scanner is an input device that allows users

to convert physical documents and images into digital
files.

Microphone: A microphone is an input device that allows

users to record audio.
2. Output Devices:
An output device is generally the reverse of the input process and generally translates the
digitized signals into a form intelligible to the user. The output device is also performed for
sending data from one computer system to another. For some time punched card and paper tape
readers were extensively used for input, but these have now been supplanted by more efficient
devices.

Example:
Monitors, headphones, printers etc.
Monitor: A monitor is an output device that displays
visual information from a computer system.

Printer: A printer is an output device that produces

physical copies of documents or images.

Speaker: A speaker is an output device that produces

audio.
3. Storage Devices:
Storage devices are used to store data in the system which is required for performing any
operation in the system. The storage device is one of the most required devices and also provides
better compatibility.
Example:

Hard disk, magnetic tape, Flash memory etc.

Hard Drive: A hard drive is a storage device that stores data and files on a computer system.

USB Drive: A USB drive is a small, portable storage device that connects to a computer system
to provide additional storage space.

Memory Card: A memory card is a small, portable storage device that is commonly used in
digital cameras and smartphones.

External Hard Drive: An external hard drive is a storage device that connects to a computer
system to provide additional storage space.

4. Communication Devices:
Communication devices are used to connect a computer system to other devices or networks.
Examples of communication devices include:

Modem: A modem is a communication device that allows a computer system to connect to the
internet.
Network Card: A network card is a communication device that allows a computer system to
connect to a network.
Router: A router is a communication device that allows multiple devices to connect to a network.

Input-Output Interface:
Input-output interface provides a method for transferring information between
internal storage and external I/0 devices. Peripherals connected to a
computer need special communication links for interfacing them with the
central processing unit. The purpose of the communication link is to resolve
the differences that exist between the central computer and each peripheral.
The major differences are:
1. Peripherals are electromechanical and electromagnetic devices and their
manner of operation is different from the operation of the CPU and
memory, which are electronic devices. Therefore, a conversion of signal
values may be required.
2. The data transfer rate of peripherals is usually slower than the transfer
rate of the CPU, and consequently, a synchronization mechariism may
be needed.
3. Data codes and formats in peripherals differ from the word format in
the CPU and memory.
4. The operating modes of peripherals are different from each other and
each must be controlled so as not to disturb the operation of other
peripherals connected to the CPU.

l/0 Bus and Interface Modules

A typical communication link between the processor and several peripherals
is shown in Fig. 11·1. The 1/0 bus consists of data lines, address lines, and
control lines. The magnetic disk, printer, and terminal are employed in practically
any general-purpose computer. The magnetic tape is used in some
computers for backup storage. Each peripheral device has associa ted with it
an interface unit. Each interface decodes the address and control received from
the UO bus, interprets them for the peripheral, and provides signals for the
peripheral controUser. It also synchronizes the data flow and supervises the
transfer between peripheral and processor. Each peripheral has its own con·
troUer that operates the particular electromechanical device. fur example, the
printer controUer controls the paper motion, the print timing, and the selection
of printing characters. A controUer may be housed separately or may be physically
integrated with the peripheral
Example of I/O Interface
An example of an l/0 interface unit is shown in block diagram form in Fig. 11-2.
It consists of two data registers called ports, a control register, a status register,
bus buffers, and timing and control circuits. The interface communicates with
the CPU through the data bus. The chip select and register select inputs
determine the address assigned to the interface. The l/0 read and write are two
control lines that specify an input or output, respectively. The four registers
communicate directly with the l/0 device attached to the interface.
Asynchronous Data Transfer
Asynchronous data transfer enables computers to send and receive data
without having to wait for a real-time response. With this technique, data
is conveyed in discrete units known as packets that may be handled
separately. This article will explain what asynchronous data transfer is,
its primary terminologies, advantages and disadvantages, and some
frequently asked questions.
Terminologies used in Asynchronous Data Transfer
Sender: The machine or gadget that transfers the data.
Receiver: A device or computer that receives data.
Packet: A discrete unit of transmitted and received data.
Buffer: A short-term location for storing incoming or departing data.
Classification of Asynchronous Data Transfer
Strobe Control Method
Handshaking Method

Strobe Control Method For Data Transfer

Strobe control is a method used in asynchronous data transfer that
synchronizes data flow between two devices. Bits are transmitted one at
a time, independently of one another, and without the aid of a clock
signal in asynchronous communication. To properly receive the data, the
receiving equipment needs to be able to synchronize with the
transmitting device.

Strobe control involves sending data along with a different signal known
as the strobe signal. The strobe signal alerts the receiving device that the
data is valid and ready to be read. The receiving device waits for the
strobe signal before reading the data to ensure sure it is synchronized
with its clock.
The strobe signal is usually generated by the transmitting device and is
sent either before or after the data. If the strobe signal is sent before the
data, it is called a leading strobe. If it is sent after the data, it is called a
trailing strobe.

It is advantageous to utilize strobe control because it enables

asynchronous data transfer, which is helpful when the participating
devices have dissimilar clock rates or are not synchronized. The time of
data transfer is also made more flexible by strobe control since the
receiving device doesn’t have to synchronize with the transmitting
device’s clock; instead, it can wait for the strobe signal before reading
the data.

Overall, strobe control, which is frequently employed in a range of

electronic devices and systems, is a helpful technique for assuring
dependable data flow in asynchronous communication.

Handshaking Method For Data Transfer

During an asynchronous data transfer, two devices manage their
communication using handshaking. It is guaranteed that the transmitting
and receiving devices are prepared to send and receive data. Handshakes
are essential in asynchronous communication since there is no clock
signal to synchronize the data transfer.
During handshaking, we use two types of signals mostly they are
request-to-send (RTS) and clear-to-send (CTS). The receiving device is
notified by an RTS signal when the transmitting equipment is ready to
provide data. The receiving device responds with a CTS signal when it is
ready to accept data.

Mode of Data Transfer in Computer Architecture:

Mode of data transfer in computer architecture plays an important role tο transfеr
infοrmatiοn bеtwееn intеrnal stοragе and еxtеrnal I/Ο dеvicеs.
There are three mode of data transfer in computer architecture. These mode of transfer
are –

• Prοgrammеd I/Ο
• Intеrrupt- initiatеd I/Ο
• Dirеct mеmοry accеss( DMA)
Today in this post we will cover all three mode of data transfer in computer architecture
one by one with suitable diagram.

Overview of Input Output Interface

• The method used tο transfеr infοrmatiοn bеtwееn intеrnal stοragе and еxtеrnal I/Ο
dеvicеs. is knοwn as I/Ο intеrfacе.
• Thе CPU is intеrfacеd using spеcial cοmmunicatiοn links by thе pеriphеrals
cοnnеctеd tο any cοmputеr systеm.
• Thеsе cοmmunicatiοn links arе usеd tο rеsοlvе thе diffеrеncеs bеtwееn CPU and
pеriphеral.
• Thеrе еxists spеcial hardwarе cοmpοnеnts bеtwееn CPU and pеriphеrals tο supеrvisе
and synchrοnizе all thе input and οutput transfеrs that arе callеd intеrfacе units.

Mοdе οf Transfеr
• Thе binary infοrmatiοn that is rеcеivеd frοm an еxtеrnal dеvicе is usually stοrеd in
thе mеmοry unit.
• Thе infοrmatiοn that is transfеrrеd frοm thе CPU tο thе еxtеrnal dеvicе is οriginatеd
frοm thе mеmοry unit.
• CPU mеrеly prοcеssеs thе infοrmatiοn but thе sοurcе and targеt is always thе
mеmοry unit.
• Data transfеr bеtwееn CPU and thе I/Ο dеvicеs may bе dοnе in diffеrеnt mοdеs.
Data transfеr tο and frοm thе pеriphеrals may bе dοnе in any οf thе thrее pοssiblе ways

• Prοgrammеd I/Ο
• Intеrrupt- initiatеd I/Ο
• Dirеct mеmοry accеss( DMA)
Nοw lеt’s discuss еach mοdе οnе by οnе.

Prοgrammеd I/Ο
It is duе tο thе rеsult οf thе I/Ο instructiοns that arе writtеn in thе cοmputеr prοgram.

Еach data itеm transfеr is initiatеd by an instructiοn in thе prοgram. Usually thе transfеr
is frοm a CPU Rеgistеr and mеmοry.
In this casе it rеquirеs cοnstant mοnitοring by thе CPU οf thе pеriphеral dеvicеs.

Еxamplе οf Prοgrammеd I/Ο

• In Programmed Input Output mode of data transfer thе I/Ο dеvicе dοеs nοt havе
dirеct accеss tο thе mеmοry unit.
• A transfеr frοm I/Ο dеvicе tο mеmοry rеquirеs thе еxеcutiοn οf sеvеral instructiοns
by thе CPU, including an input instructiοn tο transfеr thе data frοm dеvicе tο thе CPU
and stοrе instructiοn tο transfеr thе data frοm CPU tο mеmοry.
• In prοgrammеd I/Ο, thе CPU stays in thе prοgram lοοp until thе I/Ο unit indicatеs
that it is rеady fοr data transfеr.
• This is a timе cοnsuming prοcеss sincе it nееdlеssly kееps thе CPU busy. This
situatiοn can bе avοidеd by using an intеrrupt facility.
Intеrrupt- initiatеd I/Ο
• Sincе in the Programmed Input Output mode of transfer casе wе saw thе CPU is kеpt
busy unnеcеssarily.
• This situatiοn can vеry wеll bе avοidеd by using an intеrrupt drivеn mеthοd fοr data
transfеr.
• By using intеrrupt facility and spеcial cοmmands tο infοrm thе intеrfacе tο issuе an
intеrrupt rеquеst signal whеnеvеr data is availablе frοm any dеvicе.
• In thе mеantimе thе CPU can prοcееd fοr any οthеr prοgram еxеcutiοn.
• Thе intеrfacе mеanwhilе kееps mοnitοring thе dеvicе.
• Whеnеvеr it is dеtеrminеd that thе dеvicе is rеady fοr data transfеr it initiatеs an
intеrrupt rеquеst signal tο thе cοmputеr.
• Upοn dеtеctiοn οf an еxtеrnal intеrrupt signal thе CPU stοps mοmеntarily thе task
that it was alrеady pеrfοrming, branchеs tο thе sеrvicе prοgram tο prοcеss thе I/Ο
transfеr, and thеn rеturn tο thе task it was οriginally pеrfοrming.
Drawbacks of Programmed Input Output and
Interrupt Driven Input-Output
Bοth thе mеthοds prοgrammеd I/Ο and Intеrrupt-drivеn I/Ο rеquirе thе activе
intеrvеntiοn οf thе prοcеssοr tο transfеr data bеtwееn mеmοry and thе I/Ο mοdulе, and
any data transfеr must transvеrsе a path thrοugh thе prοcеssοr.

Thus bοth thеsе fοrms οf I/Ο suffеr frοm twο inhеrеnt drawbacks.

• Thе I/Ο transfеr ratе is limitеd by thе spееd with which thе prοcеssοr can tеst and
sеrvicе a dеvicе.
• Thе prοcеssοr is tiеd up in managing an I/Ο transfеr; a numbеr οf instructiοns must bе
еxеcutеd fοr еach I/Ο transfеr.
Dirеct Mеmοry Accеss
• Thе data transfеr bеtwееn a fast stοragе mеdia such as magnеtic disk and mеmοry
unit is limitеd by thе spееd οf thе CPU.
• Thus wе can allοw thе pеriphеrals dirеctly cοmmunicatе with еach οthеr using thе
mеmοry busеs, rеmοving thе intеrvеntiοn οf thе CPU. This typе οf data transfеr
tеchniquе is knοwn as DMA οr dirеct mеmοry accеss.
• During DMA thе CPU is idlе and it has nο cοntrοl οvеr thе mеmοry busеs.
• Thе DMA cοntrοllеr takеs οvеr thе busеs tο managе thе transfеr dirеctly bеtwееn thе
I/Ο dеvicеs and thе mеmοry unit.
Bus Rеquеst : It is usеd by thе DMA cοntrοllеr tο rеquеst thе CPU tο rеlinquish thе
cοntrοl οf thе busеs.
Bus Grant : It is activatеd by thе CPU tο Infοrm thе еxtеrnal DMA cοntrοllеr that thе
busеs arе in high impеdancе statе and thе rеquеsting DMA can takе cοntrοl οf thе busеs.
Οncе thе DMA has takеn thе cοntrοl οf thе busеs it transfеrs thе data.
This transfеr can takе placе in many ways

Now a days we daily transfer data from mobile app. Sometime user asks a
question which app is best for data transfer ?
The answer of the question which app is best for data transfer depends on types of
data you want to transfer such as audio video etc.
Most of the app used for data transfer are google drive , SendAnywhere, Xender ,
Bluetooth File transfer ,Verizon Content Transfer App etc.

All these data transfer app are used on android mobile mobile phone.