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INDEX
Ex.
No.
Experiment Name Page

01 Design and simulate a CMOS 'Inverter' and verify its functionality. 01 - 04

02 Design and simulate a CMOS 'OR Gate' and verify its functionality. 05 - 08

03 Design and simulate a CMOS 'NOR Gate' and verify its functionality. 09 - 12

04 Design and simulate a CMOS 'AND Gate' and verify its functionality. 13 - 16

05 Design and simulate a CMOS 'NAND Gate' and verify its functionality. 17 - 20

06 Design and simulate a CMOS 'XOR Gate' and verify its functionality. 21 - 24

07 Design and simulate a CMOS 'XNOR Gate' and verify its functionality. 25 - 27
 Experiment No: 01
Experiment Name: Design and simulate a CMOS 'Inverter' and verify its
functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS inverter circuit.
 Simulate the inverter's switching functionality.
 Verify the inverter's output logic behavior through simulation.

Apparatus:
1. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
2. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 29, 2024

Theory:
A CMOS inverter consists of two transistors: an n-channel MOSFET (nMOS) and a p-
channel MOSFET (pMOS). The NMOS transistor is placed between the output node and
ground, while the PMOS transistor is connected between the power supply (V DD) and the
output node.
The operation of the CMOS inverter is based on the complementary action of the
transistors. When the input voltage (Vin) is low, the PMOS is in the ON state, and the
NMOS is OFF. As a result, the output (Vout) is connected to VDD, providing a high output
voltage. Conversely, when Vin is high, the NMOS transistor turns ON, and the PMOS turns
OFF, connecting the output to the ground and producing a low output voltage.
The transition region, where both transistors are partially conducting, is responsible for

1
switching between logic states. During this transition, the inverter consumes power due to
the simultaneous conduction of both NMOS and PMOS transistors. This transient period is
minimized to achieve efficient switching with minimal power loss.

In an ideal CMOS inverter, the input and output voltages exhibit complementary behavior:
a high input results in a low output and vice versa. CMOS technology is preferred for
inverter designs due to its low power dissipation during steady-state operation. It only
consumes power during switching events when capacitive loads are charged and
discharged.
The CMOS inverter also forms the basis for understanding more complex CMOS gates.
Understanding its functionality provides insight into the behavior of digital circuits, noise
margins, and switching characteristics.

Truth Table:

Input (A) Output (Y)

0 1

1 0

2
LTspice Circuit Design:

3
Input/Output Plot Window

Discussion: The CMOS inverter effectively showcased the anticipated output behavior by
producing a distinct logic inversion of the input. The design made effective use of both NMOS
and PMOS transistors, highlighting their complementary functions. This experiment validated
the inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.

4
 Experiment No: 02
Experiment Name: Design and simulate a CMOS 'OR' gate and verify its functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS OR circuit.
 Simulate the circuit's switching functionality.
 Verify the circuit's output logic behavior through simulation.

Apparatus:
3. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
4. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 24, 2024

Theory:
A CMOS inverter consists of two transistors: an n-channel MOSFET (nMOS) and a p- channel
MOSFET (pMOS). The NMOS transistor is placed between the output node and ground, while
the PMOS transistor is connected between the power supply (VDD) and the output node. An OR
gate is a NOT-NOT-OR or NOT-NOR. Then, it is a NOR gate followed by an inverter.

The output of a OR gate is logic 0 with logic 0 in both inputs. The outcomes for other input
combinations are logic 1.

5
 Figure. A CMOS two-input OR gate.

Figure shows a CMOS two-input OR gate. P-channel transistors Q1 and Q2 are connected in
series between +V and the output terminal. N-channel transistors Q3 and Q4 are connected in
parallel between the output and ground.

When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are “off,” and the
output is logic 1. When the output voltage is HIGH, Q6 is in the ON state, and the Q5 is OFF.
As a result, the output (Vout) is connected to ground, providing a LOW output voltage. This
confirms the first row of the truth table above.

With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a logic 0
output. When the output voltage is LOW, Q5 is in the ON state, and the Q6 is OFF. As a result,
the output (Vout) is connected to VDD, providing a HIGH output voltage. This confirms the first
row of the truth table above. that confirms the last row of the truth table.

For the two remaining input combinations, either Q1 is “off” and Q3 is “on” or Q2 is “off” and
is Q4 “on”. In these cases, the output is logic 0. When the output voltage is LOW, Q5 is in the
ON state, and the Q6 is OFF. As a result, the output (Vout) is connected to VDD, providing a
HIGH output voltage. Which is consistent with the above truth table.

The transition region, where both transistors are partially conducting, is responsible for switching
between logic states. During this transition, the inverter consumes power due to the simultaneous
conduction of both NMOS and PMOS transistors. This transient period isminimized to achieve
efficient switching with minimal power loss.

6
Truth Table:
Input(A) Input(B) Output(Y=A+B)

0 0 0

0 1 1

1 0 1

1 1 1

LTspice Circuit Design:

7
Input/Output Plot Window

Discussion: The CMOS ‘OR’ effectively showcased the anticipated output behavior by
producing a distinct logic output of the input. The design made effective use of both NMOS and
PMOS transistors, highlighting their complementary functions. This experiment validated the
inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.

8
 Experiment No: 03
Experiment Name: Design and simulate a CMOS 'NOR' gate and verify its functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS OR circuit.
 Simulate the circuit's switching functionality.
 Verify the circuit's output logic behavior through simulation.

Apparatus:
5. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
6. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 24, 2024

Theory:
A CMOS inverter consists of two transistors: an n-channel MOSFET (nMOS) and a p- channel
MOSFET (pMOS). The NMOS transistor is placed between the output node and ground, while
the PMOS transistor is connected between the power supply (VDD) and the output node

The output of a NOR gate is logic 0 with logic 1 in both inputs. The outcomes for other input
combinations are logic 0.

9
 Figure. A CMOS two-input NOR gate.

Figure shows a CMOS two-input OR gate. P-channel transistors Q1 and Q2 are connected in
series between +V and the output terminal. N-channel transistors Q3 and Q4 are connected in
parallel between the output and ground.

When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are “off,” and the
output is logic 1. This confirms the first row of the truth table above.

With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a logic 0
output. This confirms the last row of the truth table.

For the two remaining input combinations, either Q1 is “off” and Q3 is “on” or Q2 is “off” and
is Q4 “on”. In these cases, the output is logic 0. Which is consistent with the above truth table.

The transition region, where both transistors are partially conducting, is responsible for switching
between logic states. During this transition, the inverter consumes power due tothe simultaneous
conduction of both NMOS and PMOS transistors. This transient period isminimized to achieve
efficient switching with minimal power loss.

10
Truth Table:
Input(A) Input(B) Output(Y=(A+B)’)

0 0 1

0 1 0

1 0 0

1 1 0

LTspice Circuit Design:

11
Input/Output Plot Window

Discussion: The CMOS ‘OR’ effectively showcased the anticipated output behavior by
producing a distinct logic output of the input. The design made effective use of both NMOS and
PMOS transistors, highlighting their complementary functions. This experiment validated the
inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.

12
 Experiment No: 04
Experiment Name: Design and simulate a CMOS 'AND' gate and verify its functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS AND circuit.
 Simulate the circuit's switching functionality.
 Verify the circuit's output logic behavior through simulation.

Apparatus:
7. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
8. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 24, 2024

Theory:
A CMOS inverter consists of two transistors: an n-channel MOSFET (nMOS) and a p- channel
MOSFET (pMOS). The NMOS transistor is placed between the output node and ground, while
the PMOS transistor is connected between the power supply (VDD) and the output node. An AND
gate is a NOT-NOT-AND or NOT-NAND. Then, it is a NAND gate followed by an inverter.

The output of a AND gate is logic 1 with logic 1 in both inputs. The outcomes for other input
combinations are logic 0.

13
 Figure. A CMOS two-input AND gate.

Figure shows a CMOS two-input AND gate. P-channel transistors Q1 and Q2 are connected in
series between +V and the output terminal. N-channel transistors Q3 and Q4 are connected in
parallel between the output and ground.

When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are “off,” and the
output is logic 1. When the output voltage is HIGH, Q6 is in the ON state, and the Q5 is OFF.
As a result, the output (Vout) is connected to ground, providing a LOW output voltage. This
confirms the first row of the truth table above.

With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a logic 0
output. When the output voltage is LOW, Q5 is in the ON state, and the Q6 is OFF. As a result,
the output (Vout) is connected to VDD, providing a HIGH output voltage. This confirms the first
row of the truth table above. that confirms the last row of the truth table.

For the two remaining input combinations, when one of the inputs is a logic “1” and the other
one is a logic “0”, either Q3 is “off” and Q2 is “on” or Q4 is “off” and Q1 is “on.” The output in
both cases is a logic “1”. When the output voltage is HIGH, Q6 is in the ON state, and the Q5 is
OFF. As a result, the output (Vout) is connected to VDD, providing a LOW output voltage. Which
is consistent with the above truth table.

The transition region, where both transistors are partially conducting, is responsible for switching
between logic states. During this transition, the inverter consumes power due to the simultaneous
conduction of both NMOS and PMOS transistors. This transient period isminimized to achieve
efficient switching with minimal power loss.

14
Truth Table:
Input(A) Input(B) Output(Y=A.B)

0 0 0

0 1 0

1 0 0

1 1 1

LTspice Circuit Design:

15
Input/Output Plot Window

Discussion: The CMOS ‘AND’ effectively showcased the anticipated output behavior by
producing a distinct logic output of the input. The design made effective use of both NMOS and
PMOS transistors, highlighting their complementary functions. This experiment validated the
inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.

16
 Experiment No: 05
Experiment Name: Design and simulate a CMOS 'NAND' gate and verify its functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS NAND circuit.
 Simulate the circuit's switching functionality.
 Verify the circuit's output logic behavior through simulation.

Apparatus:
9. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
10. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 24, 2024

Theory:
A CMOS inverter consists of two transistors: an n-channel MOSFET (nMOS) and a p- channel
MOSFET (pMOS). The NMOS transistor is placed between the output node and ground, while
the PMOS transistor is connected between the power supply (VDD) and the output node

The output of a NAND gate is logic 0 with logic 1 in both inputs. The outcomes for other input
combinations are logic 1.

17
 Figure. A CMOS two-input NAND gate.

Figure shows a CMOS two-input NAND gate. P-channel transistors Q1 and Q2 are connected in
series between +V and the output terminal. N-channel transistors Q3 and Q4 are connected in
parallel between the output and ground.

When both inputs, A and B, are logic 0, Q1 and Q2 are “on,” and Q3 and Q4 are “off,” and the
output is logic 1. This confirms the first row of the truth table above.

With both inputs logic 1, Q3 and Q4 are “on,” and Q1 and Q2 are “off,” producing a logic 0
output. That confirms the last row of the truth table.

For the two remaining input combinations, when one of the inputs is a logic “1” and the

other one is a logic “0”, either Q3 is “off” and Q2 is “on” or Q4 is “off” and Q1 is “on.” The
output in both cases is a logic “1”. Which is consistent with the above truth table.
The transition region, where both transistors are partially conducting, is responsible for switching
between logic states. During this transition, the inverter consumes power due to the simultaneous
conduction of both NMOS and PMOS transistors. This transient period isminimized to achieve
efficient switching with minimal power loss.

18
Truth Table:
Input(A) Input(B) Output (Y= (A.B)’)

0 0 1

0 1 1

1 0 1

1 1 0

LTspice Circuit Design:

19
Input/Output Plot Window

Discussion: The CMOS ‘NAND’ effectively showcased the anticipated output behavior by
producing a distinct logic output of the input. The design made effective use of both NMOS and
PMOS transistors, highlighting their complementary functions. This experiment validated the
inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.

20
 Experiment No: 06
Experiment Name: Design and simulate a CMOS 'XOR' gate and verify its functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS XOR circuit.
 Simulate the circuit's switching functionality.
 Verify the circuit's output logic behavior through simulation.

Apparatus:
11. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
12. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 24, 2024

Theory:
The logic gate performs this modulos sum operation without including carry is known as XOR
gate. An XOR gate is normally two inputs logic gate where the output is only logical 1 when
only one input is logical 1. When both inputs are equal, either are 1 or both are 0, the output will
be logical 0.

The XOR gate is also known as an anti-coincidence gate or inequality detector because it outputs
1 only when the inputs are exclusively different. This exclusive behavior defines

the ‘exclusive OR gate’ operation.

21
The transition region, where both transistors are partially conducting, is responsible for switching
between logic states. During this transition, the inverter consumes power due to the simultaneous
conduction of both NMOS and PMOS transistors. This transient period isminimized to achieve
efficient switching with minimal power loss.

Truth Table:
Input(A) Input(B) Output(Y=A’B+AB’)

0 0 0

0 1 1

1 0 1

1 1 0

22
LTspice Circuit Design:

23
Input/Output Window:

Discussion: The CMOS ‘XOR’ effectively showcased the anticipated output behavior by
producing a distinct logic output of the input. The design made effective use of both NMOS and
PMOS transistors, highlighting their complementary functions. This experiment validated the
inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.
24
 Experiment No: 07
Experiment Name: Design and simulate a CMOS 'X-NOR' gate and verify its functionality.

Objectives:
The aim of this experiment is to -
 Design a CMOS X-NOR circuit.
 Simulate the circuit's switching functionality.
 Verify the circuit's output logic behavior through simulation.

Apparatus:
13. Hardware (MSI Laptop)
 Device name: MSI GF63 Thin 12UC
 Processor: 12th Gen Intel(R) Core(TM) i7-12650H 2.30 GHz
 Installed RAM: 32.00 GB (31.7 GB usable)
 Installed SSD: SAMSUNG MZLV41T0HBLB-00BTW (1TB)
 System type: 64-bit operating system, x64-based processor
14. Software (LTspice)
 Version: 24.0.12
 Platform type: 64-bit (win64)
 Update Date: September 24, 2024

Theory:
An XNOR gate, also known as an equivalence gate or an EX-NOR gate, is a digital logic gate
that outputs true (1) when an even number of true inputs are present. It produces a true output if
both of its inputs are the same (either both true or both false). It is also known as the material
biconditional. This logic gate is denoted by this sign “⊙”.

In Boolean notation,Y=AB+A’B’An XNOR gate is a specially designed logic gate having only
two inputs and one output. The output of the XNOR gate is logic 1 when both the inputs are logic
1 or logic 0. In other words, the output of the XNOR gate is logic 1 when both the inputs are the
same. For different inputs, the output of the XNOR gate is logic 0. Hence, the XNOR gate is
used to implement similarity checker circuits.

25
Truth Table:
Input(A) Input(B) Output(Y=AB+A’B’)

0 0 1

0 1 0

1 0 0

1 1 1

LTSpice Circuit diagram:

26
Input/Output Plot Window

Discussion: The CMOS ‘X-NOR’ effectively showcased the anticipated output behavior by
producing a distinct logic output of the input. The design made effective use of both NMOS and
PMOS transistors, highlighting their complementary functions. This experiment validated the
inverter's position as a key component in digital circuits, underscoring the significance of
grasping basic logic gates in VLSI design.

27