RT9756A

8A Single Cell Smart Cap Divider and Direct Charge Charger

with 8-Channel ADC, USB BC 1.2 Detection
General Description Features
The RT9756A is a high efficiency and high charge  Integrates Cap Divider Mode (DIV2 Mode) and
current charger. The efficiency is up to 98.2% when Direct Charging Mode (Bypass Mode)
VBAT = 4V, IBAT = 2A and the maximum charge current  Supports BC1.2
is up to 8A in DIV2 mode. The efficiency is up to 99.1%  External OVPMOS Control and Regulation
when VBAT = 4V, IBAT = 1A and the maximum charger  High Absolute Maximum Rating of 37V
current is up to 5A in bypass mode. The device  Fast Reaction Time 100ns and Fast Turn Off
integrates smart cap divider topology, direct charging Time 100ns
mode, external overvoltage protection control, an input  VBAT Voltage Regulation (VBAT REG)
reverse blocking NFET and 2-way regulation, a dual-  IBAT Current Regulation (IBAT REG)
phase charge pump core, 14-way protection, 9-way  Dual-Phase Charge Pump Core
system alarm, 8-Channel high speed analog-to-digital  8A Output Current Capability
converter and USB BC 1.2 detection. The high speed  Efficiency Up to 98.2% when VBAT = 4V,
analog-to-digital converter provides input and output IBAT = 2A (DIV2 Mode)
voltage, current and temperature information for the  Efficiency Up to 99.1% when VBAT = 4V,
host. The host can monitor the information by I2C serial IBAT = 1A (Bypass Mode)
interface.  100kHz to 1000kHz Variable Switching
Frequency Stay Out of Audio Band
The recommended junction temperature range is 40C
 Spread Spectrum Technology for EMI
to 125C, and the ambient temperature range is 40C
Reduction
to 85C.

Applications
 Smart Phones
 Tablet

Simplified Application Circuit

CBST1 CFLY1

VAC BST1 CFH1 CFL1

OVPGATE
PMID
CPMID
RT9756A
VBUS
CVAC
CVBUS
USB

VOUT
D+
DP_SYNCOUT COUT
D-
DM_TS
BATP
2 100Ω
I C Battery
Host INT BATN/SRP_SYNCIN
RSEN

REGN SRN_ADDR

GND
AGND BST2 CFH2 CFL2

CBST2 CFLY2

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RT9756A
 8-Channel 12-bit ADC Ordering Information
 High Speed Data Rate for 128 Times Average RT9756A -
Per Channel
Packing
 VBUS, IBUS, VOUT, VBAT, IBAT, TDIE, DP, DM A: Standard
8-Channel for Voltage/Current/Temperature B: Pin 1 Orientation
Measurement (Quadrant 2, Follow EIA-481)
 Input Reverse Blocking NFET
Package Type
 Block the Reverse Current P: WL-CSP-36B 2.8x2.8 (BSC)
 3-Error Charge Pump Switch Protection
Note:
 VBUS Voltage Too High Error Protection
Richtek products are Richtek Green Policy compliant
before Switch (VBUS_HIGH_ERR)
and compatible with the current requirements of
 VBUS Voltage Too Low Error Protection before
IPC/JEDEC J-STD-020.
Switch (VBUS_LOW_ERR)
 CFLY Short Error Protection Before Switch Marking Information
(CFLY_DIAG)
31: Product Code
 11-Way System Protection XXYY: Wafer ID with Check Sum
31XXYY
 VAC Overvoltage Protection (VAC_OVP) CCC-RRR: IC Coordinate (X, Y)
CCC-RRR
YMDNN: Date Code
 VBUS Overvoltage Protection (VBUS_OVP) YMDNN
 IBUS Overcurrent Protection (IBUS_OCP)
 Higher IBUS Overcurrent Protection
(IBUS_OCP_H) Pin Configuration
 IBUS Undercurrent Protection (IBUS_UCP) (TOP VIEW)
 VOUT Overvoltage Protection (VOUT_OVP)
 VBAT Overvoltage Protection (VBAT_OVP)
A1 A2 A3 A4 A5 A6
 IBAT Overcurrent Protection (IBAT_OCP) VAC VBUS VBUS VBUS VBUS OVPGATE
 Dropout Overvoltage Protection (VDR_OVP) B1 B2 B3 B4 B5 B6
 TS Over-Temperature Protection (TS_OTP) BST1 PMID DP_ DM_TS PMID BST2
SYNCOUT
 Junction Over-Temperature Protection C1 C2 C3 C4 C5 C6
(TDIE_OTP) CFH1 CFH1 SDA SCL CFH2 CFH2

 9-Way System Alarm D1 D2 D3 D4 D5 D6

 VBUS Overvoltage Alarm (VBUS_OVP_ALM) VOUT VOUT BATN/SRP_ SRN_ VOUT VOUT
SYNCIN ADDR
 IBUS Overcurrent Alarm (IBUS_OCP_ALM) E1 E2 E3 E4 E5 E6
 IBUS Undercurrent Alarm (IBUS_UCP-ALM) CFL1 CFL1 BATP INT CFL2 CFL2

 VBAT Overvoltage Alarm (VBAT_OVP_ALM) F1 F2 F3 F4 F5 F6

 IBAT Overcurrent Alarm (IBAT_OCP_ALM) GND GND AGND REGN GND GND

 IBAT Undercurrent Alarm (IBAT_UCP-ALM)

 TDIE Over-Temperature Alarm
WL-CSP-36B 2.8x2.8 (BSC)
(TDIE_OTP_ALM)
 DP Overvoltage Alarm (DP_OV_ALM)
 DM Overvoltage Alarm (DM_OV_ALM)

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 RT9756A
Functional Pin Description
Pin No. Pin Name I/O Pin Function
Input voltage sense pin. Connect to VBUS if the external N-FET is
A1 VAC AI
not used.
These pins are the input power supply and must be connected
A2, A3, A4, A5 VBUS P together on the PCB. One 2.2F capacitor must be connected from
VBUS to GND and placed close to these pins.
External N-FET control pin, connect to the gate of the external N-
A6 OVPGATE AO
FET.
The high-side MOSFET driver positive supply. One 0.1F capacitor
B1 BST1 P must be connected from BST1 to CFH1 and placed as close as
possible to the device.
Connected to the drain of the reverse blocking NFET. One 10F
B2, B5 PMID P capacitor must be connected from PMID to GND and placed as close
as possible to the device.
Positive line of the USB data line pair. DP/DM based USB
DP_
B3 AIO host/charging port detection. In the parallel configuration, connect
SYNCOUT
this pin to BATN/SRP_SYNCIN pin of the slave.
Negative line of the USB data line pair. DP/DM based USB
host/charging port detection. This pin has another function as a
B4 DM_TS AIO
temperature sensing input. Requires external NTC thermistor,
resistor divider and voltage reference.
The high-side MOSFET driver positive supply. One 0.1F capacitor
B6 BST2 P must be connected from BST2 to CFH2 and placed as close as
possible to the device.
Flying capacitor positive node. Three 22F capacitors must be
C1, C2 CFH1 P connected from CFL1 to CFH1 and placed as close as possible to
the device. These pins must be connected together on the PCB.
I2C serial data line. Connect to pull-up voltage via 10k pull-up
C3 SDA DIO
resistor.
I2C serial clock line. Connect to pull-up voltage via 10k pull-up
C4 SCL DI
resistor.
Flying capacitor positive node. Three 22F capacitors must be
C5, C6 CFH2 P connected from CFL2 to CFH2 and placed as close as possible to
the device. These pins must be connected together on the PCB.
Power supply. Connect to positive terminal of the battery pack.
These pins must be connected together on the PCB. Two 10F
D1, D2, D5, D6 VOUT P
capacitors must be connected from VOUT to GND and placed as
close as possible to the device.
Negative input for battery voltage sensing and positive input for
battery current sensing. Place a 5m or 2m resistor between
BATN/SRP_ BATN/SRP_SYNCIN and SRN_ADDR. Connect a 100resistor in
D3 AI
SYNCIN series with negative terminal of battery pack if battery current sensing
is not used. In parallel configuration, connect this pin to
DP_SYNCOUT pin of master.

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RT9756A
Pin No. Pin Name I/O Pin Function
Negative input for battery current sensing. Place 5m or 2m
resistor between SRN_ADDR and BATN/SRP_SYNCIN. Connect
SRN_ADDR to GND to set slave address = 0x6F, or float
D4 SRN_ADDR AI
SRN_ADDR to set slave address = 0x6E. To set slave address =
0x6E, the parasitic capacitance of the SRN_ADDR pin must be less
than 100pF.
Flying capacitor negative node. Three 22F capacitors must be
E1, E2 CFL1 P connected from CFL1 to CFH1 and placed as close as possible to
the device. These pins must be connected together on the PCB.
Positive input for battery voltage sensing. Connect a 100 resistor in
E3 BATP AI
series with positive terminal of battery pack.
Open drain interrupt output. Connect to pull-up voltage via 10k pull-
E4 ̅̅̅̅̅
INT DO ̅̅̅̅̅ pin sends a
up resistor. Normally high, when event happen, INT
256s low pulse to the system.
Flying capacitor negative node. Three 22F capacitors must be
E5, E6 CFL2 P connected from CFL2 to CFH2 and placed as close as possible to
the device. These pins must be connected together on the PCB.
F1, F2, F5, F6 GND P Power ground.
F3 AGND AI Analog ground.
Internal LDO output. This pin is the internal power supply VDDA. One
4.7F capacitor must be connected from REGN to AGND and placed
F4 REGN AO
as close as possible to the device. Do not use this pin for other
function.

Functional Block Diagram

PMID BST1 CFH1 CFL1

Q0 Q11 Q14
VBUS GND

OVPGATE External
OVP VBUS
VAC Control Driving Driving Driving
Q12 Q13 VOUT
Control Control Control
TDIE
Power
REGN Select Current Sensing DP_SYNCOUT

DM_TS
VOUT ADC + VBUS
- PMID
DP_SYNCOUT BC12 & Other
Proprietary Protection + BATP
DM_TS Protocols -
Driving Driving
Q22 Q23 BATN/SRP_SYNCIN
Control Control
+
SDA 2 Digital - SRN_ADDR
I C Interface
SCL Control
AGND
Q21 Q24

INT BST2 CFH2 CFL2

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 RT9756A
Absolute Maximum Ratings (Note 1)
 Supply Pin Voltage, VAC ----------------------------------------------------------------------------------------------- 0.3V to 37V
 Supply Pin Voltage, VBUS --------------------------------------------------------------------------------------------- 0.3V to 22V
 Supply Pin Voltage, VOUT --------------------------------------------------------------------------------------------- 0.3V to 6V
 Control Pin Voltage, OVPGATE (Note 2) ----------------------------------------------------------------------- 0.3V to 37V
 Terminal Pin Voltage, OVPGATE to VBUS ------------------------------------------------------------------------ 22V to 14V
 Terminal Pin Voltage, PMID ------------------------------------------------------------------------------------------- 0.3V to 14V
 Terminal Pin Voltage, DP_SYNCOUT, DM_TS------------------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, BST1, BST2 ---------------------------------------------------------------------------------- 0.3V to 18V
 Terminal Pin Voltage, BST1 to CFH1, BST2 to CFH2 ---------------------------------------------------------- 0.3V to 14V
 Terminal Pin Voltage, CFH1, CFH2 --------------------------------------------------------------------------------- 0.3V to 12V
 Terminal Pin Voltage, CFL1, CFL2 ---------------------------------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, PMID to CFH1, PMID to CFH2 ---------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, CFH1 to VOUT, CFH2 to VOUT --------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, CFH1 to CFL1, CFH2 to CFL2 ----------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, VOUT to CFL1, VOUT to CFL2 ---------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, ̅̅̅̅̅
INT, SDA, SCL, REGN -------------------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, BATP, BATN/SRP_SYNCIN ------------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, SRN_ADDR ---------------------------------------------------------------------------------- 0.3V to 6V
 Terminal Pin Voltage, BATN/SRP_SYNCIN to SRN_ADDR --------------------------------------------------- 0.5V to 0.5V
 Terminal Pin Voltage, GND to AGND -------------------------------------------------------------------------------- 0.5V to 0.5V
 ̅̅̅̅̅ --------------------------------------------------------------------------------------------- 0mA to 6mA
Terminal Pin Current, INT
 Power Dissipation, PD @ TA = 25C
WL-CSP-36B 2.8x2.8 (BSC) ----------------------------------------------------------------------------------------- 3.42W
 Package Thermal Resistance (Note 3)
WL-CSP-36B 2.8x2.8 (BSC), JA------------------------------------------------------------------------------------ 29.26C/W
 Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------------- 260C
 Junction Temperature --------------------------------------------------------------------------------------------------40C to 150C
 Storage Temperature Range ----------------------------------------------------------------------------------------- 65C to 150C
 ESD Susceptibility (Note 4)
HBM (Human Body Model), per ANSI/ESDA/JEDEC JS-001 ------------------------------------------------ ±2kV
CDM (Charged Device Model), per JEDEC Specification JESD22-C101 ---------------------------------±500V
Latch-Up ------------------------------------------------------------------------------------------------------------------- ±100mA

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RT9756A
Recommended Operating Conditions (Note 5)
 Supply Pin Voltage Range, VAC ---------------------------------------------------------------------------------- 3V to 17V
 Supply Pin Voltage Range (Device in Operating Mode), VAC --------------------------------------------- 3V to 12V
 Supply Input Voltage Range (Device in DIV2 Mode), VBUS, ---------------------------------------------- 6V to 11V
 Supply Input Voltage Range (Device in Bypass Mode), VBUS -------------------------------------------- 3V to 5V
 Output Voltage Range, VOUT-------------------------------------------------------------------------------------- 3V to 5V
 Positive Flying Capacitor Voltage Range, CFH1, CFH2 ---------------------------------------------------- 0V to 11V
 Negative Flying Capacitor Voltage Range, CFL1, CFL2 --------------------------------------------------- 0V to 5V
 Voltage Range Across Q11 and Q21, PMID to CFH1, PMID to CFH2 ---------------------------------- 0V to 5V
 Voltage Range Across Q12 and Q22, CFH1 to VOUT, CFH2 to VOUT -------------------------------- 0V to 5V
 Voltage Range Across Q13 and Q23, VOUT to CFL1, VOUT to CFL2 --------------------------------- 0V to 5V
 Analog Sense Voltage Range, BATP --------------------------------------------------------------------------- 0V to 5V
 Analog Sense Voltage Range, BATN/SRP_SYNCIN, SRN_ADDR ------------------------------------- 0V to 0.04V
 Battery Positive and Negative Voltage Sense Range, BATP to BATN/SRP_SYNCIN -------------- 0V to 5V
 I/O Control Voltage Range, SDA, SCL, ̅̅̅̅̅
INT ------------------------------------------------------------------- 0V to 5V
 I/O Control Voltage Range, DP_SYNCOUT, DM_TS ------------------------------------------------------- 0V to 3.3V
 Input Current Range (Device in DIV2 Mode), IBUS---------------------------------------------------------- 0A to 4A
 Input Current Range (Device in Bypass Mode), IBUS ------------------------------------------------------ 0A to 5A
 Ambient Temperature Range ------------------------------------------------------------------------------------- 40C to 85C
 Junction Temperature Range ------------------------------------------------------------------------------------- 40C to 125C

Electrical Characteristics
(TA = 25C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
External OVP Control
Operation voltage VOVPGATE
– VBUS. VAC = 3V to 3.5V or
7 10 11
VBUS = 3V to 3.5V. Set by
Register 0x0004[0] = 1.
Operation voltage VOVPGATE
– VBUS. VAC = 3.5V to 9V or
OVPGATE Voltage VOVPGATE 9 10 11 V
VBUS = 3.5V to 9V. Set by
Register 0x0004[0] = 1.
Operation voltage VOVPGATE
– VBUS. VAC = 3V to 9V or
4.5 4.8 5.1
VBUS = 3V to 9V. Set by
Register 0x0004[0] = 0.
VAC rising threshold to turn
VAC Insert Threshold VAC_INSERT_TH 2.6 2.8 3 V
on external MOS
Deglitch between VAC over
VAC Insert Threshold
tVAC_INSERT_RIS_DEG VAC_INSERT_TH and sent an -- 1 -- ms
Rising Deglitch Time ̅̅̅̅̅.
INT

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 RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
VAC falling hysteresis to turn
VAC Insert Hysteresis VAC_INSERT_HY 250 500 750 mV
off external MOS
VBUS rising threshold to turn
VBUS Insert Threshold VBUS_INSERT_TH 2.65 2.8 2.95 V
on external MOS
VBUS Insert Threshold
tBUS_INSERT_RIS_DEG -- 17 -- s
Rising Deglitch Time
VBUS falling hysteresis to
VBUS Insert Hysteresis VBUS_INSERT_HY 50 150 250 mV
turn off external MOS
VOUT < VOUT_INSERT_TH.
Deglitch time between VAC
higher than VAC_INSERT_TH 22 25 28
and start to turn on external
MOS. (Note 6)
VAC Insert Deglitch Time tVAC_INSERT_DEG ms
VOUT > VOUT_INSERT_TH.
Deglitch time between VAC
higher than VAC_INSERT_TH 20 22 24
and start to turn on external
MOS. (Note 6)
I2C programmable, 3-bit
VAC OVP Range VAC_OVP_RAN DAC, 6.5V, 11V to 17V 6.5 -- 17 V
(Note 7)
VAC OVP Accuracy VAC_OVP_ACC VAC_OVP threshold accuracy 2 -- 2 %
VAC falling to turn on
VAC OVP Hysteresis VAC_OVP_HY external MOS after VAC 250 500 750 mV
OVP happen.
Duration between VAC over
VAC_OVP threshold and
OVPGATE start to turn off
OVPGATE Reaction Time tVAC_OVP_RE external MOS. VAC_OVP set -- 100 -- ns
17V, VAC slew rate =
12V/s, VAC rises from 5V to
22V. (Note 6)
Duration between
OVPGATE start to turn off
OVPGATE Turn-Off Time tVAC_OVP_OFF external MOS and the -- 100 -- ns
external MOS be fully turn
off, CGS = 4nF. (Note 6)
If device in regulation and no
Regulation Time Out tREG_TIMEOUT VDR_OVP for this time, the 585 650 715 ms
device will stop charge.
Power Select and Source
ADC disable, charge
disable, OVPGATE disable,
VBUS and VAC are open,
VBUS Quiescent Current IBUS_IQ VOUT no present, no -- 250 300 A
VBUS_OVP happen.
Measure quiescent current
on VBUS. VBUS = 3V to 12V.

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RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
ADC disable, charge
disable, OVPGATE disable,
VOUT no present. Measure -- 250 300 A
quiescent current on VAC.
VAC = 12V, VBUS = 0V.
ADC disable, charge
disable, OVPGATE enable,
VOUT no present, no
VAC Quiescent Current IAC_IQ -- 650 -- A
VAC_OVP happen. Measure
quiescent current on VAC.
VAC = 0V to 12V.
ADC enable, charge disable,
OVPGATE enable, VOUT
no present. Measure -- 3 4 mA
quiescent current on VAC.
VAC = 3V to 12V.
ADC disable, charge
disable. VAC no present.
EN_I2C_
LEVEL_DETECTION = 0, -- 5 10 A
VOUT falling from 4.5V to 0V.
VOUT Quiescent Current IOUT_IQ Measure quiescent current
on VOUT.
ADC enable, charge disable.
VAC no present. Measure
-- 2 3 mA
quiescent current on VOUT.
VOUT = 0V to 4.5V.
VDDA UVLO Threshold VDDA_UVLO_TH VDDA rising 2.45 2.6 2.75 V
VDDA falling to turn off
VDDA UVLO Hysteresis VDDA_UVLO_HY REGN and stop ADC 100 250 400 mV
function.
VDDA UVLO Falling VDDA falling to stop I2C
VDDA_UVLO_F -- 2 -- V
Threshold work.
Duration time between VDDA
Device Wake Up Time tWAKE_UP > VDDA_UVLO_TH and device -- -- 2.5 ms
can start I2C communicate.
Duration time between
Soft-Start Time tSOFT_START CHG_EN = 1 and the device -- -- 92 ms
start switching
VOUT Insert Threshold VOUT_INSERT_TH VOUT rising 2.65 2.8 2.95 V
VOUT Insert Threshold
tVOUT_INSERT_RIS_DEG -- 17 -- s
Rising Deglitch Time
VOUT Insert Hysteresis VOUT_INSERT_HY VOUT falling 50 150 250 mV

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 RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
Cap Divider Charger
DIV2 mode, charge enable.
Q0 RON RQ0 -- 7.1 11 m
VBUS = 9V, VOUT = 4.5V.
DIV2 mode, charge enable.
Q11, Q21 RON RQ11, RQ21 -- 12 19 m
VBUS = 9V, VOUT = 4.5V.
DIV2 mode, charge enable.
Q12, Q22 RON RQ12, RQ22 -- 9.5 13 m
VBUS = 9V, VOUT = 4.5V.
DIV2 mode, charge enable.
Q13, Q23 RON RQ13, RQ23 -- 12.5 19.5 m
VBUS = 9V, VOUT = 4.5V.
DIV2 mode, charge enable.
Q14, Q24 RON RQ14, RQ24 -- 11 17 m
VBUS = 9V, VOUT = 4.5V.
Bypass Mode RON Bypass mode, charge
RBYPASS_MODE -- 17.85 27 m
(VBUS to VOUT) enable. VOUT = 4.5V.
Charge Switch Frequency
fSW 100 -- 1000 kHz
Range
Charge Switch Frequency
fSW _SIZE -- 100 -- kHz
Step Size
Charge Switch Frequency
fSW _ACC fSW = 200kHz to 1000kHz 10 -- 10 %
Accuracy
Protection
VBAT OVP Range VBAT_OVP_RAN Rising 4.2 -- 4.975 V
VBAT OVP Step Size VBAT_OVP_SIZE -- 25 -- mV
VBAT_OVP = 4.4V to 4.55V 1 -- 1
VBAT OVP Accuracy VBAT_OVP_ACC %
VBAT_OVP = 4.2V to 4.65V 1.5 -- 1.5
VBAT OVP Deglitch Time tVBAT_OVP_DEG -- 3 -- s
BATP Leakage Current ILKG_BATP -- -- 1.2 A
BATN Leakage Current ILKG_BATN -- -- 1 A
IBAT_OCP Range IBAT_OCP_RAN Rising 2 -- 8.3 A
IBAT_OCP Step Size IBAT_OCP_SIZE -- 100 -- mA
IBAT_OCP = 3A to 8A,
IBAT_OCP Accuracy IBAT_OCP_ACC 200 -- 200 mA
RSEN = 0.002
IBAT OCP Deglitch Time tIBAT_OCP_DEG -- 50 -- s
DIV2 mode. VBUS rising. 6 -- 12.3
VBUS OVP Range VBUS_OVP_RAN V
Bypass mode. VBUS rising. 3 -- 6.15
DIV2 mode -- 100 --
VBUS OVP Step Size VBUS_OVP_SIZE mV
Bypass mode 50
DIV2 mode, VBUS_OVP =
1 -- 1
8.9V to 11.5V
VBUS OVP Accuracy VBUS_OVP_ACC %
Bypass mode, VBUS_OVP =
1 -- 1
4.2V to 5V
DIV2 mode. VBUS falling. -- 500 --
VBUS OVP Hysteresis VBUS_OVP_HY mV
Bypass mode. VBUS falling. -- 200 --

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RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
VBUS rising slope with
10V/s. ADC enable. During
between VBUS over
VBUS OVP Rising VBUS_OVP threshold and
tVBUS_OVP_RISE_RE -- 0.1 -- s
Reaction Time device start to turn off
charger and reverse the
body diode of Q0.
(Note 6)
VBUS rising slope with
10V/s. ADC enable.
During between VBUS under
VBUS OVP Falling
tVBUS_OVP_FALL_RE VBUS_OVP_HY threshold and -- 0.1 -- s
Reaction Time
the body diode of Q0 start to
be turned forward.
(Note 6)
IBUS_OCP Range IBUS_OCP_RAN Rising 1 -- 5.5 A
IBUS_OCP Step Size IBUS_OCP_SIZE -- 250 -- mA
IBUS_OCP Accuracy IBUS_OCP_ACC 100 -- 100 mA
IBUS_OCP Deglitch tIBUS_OCP_DEG -- 50 -- s
IBUS_OCP_H Threshold IBUS_OCP_H Rising (Note 6) -- 6.8 -- A
During between IBUS over
IBUS_OCP_H Reaction IBUS_OVP_H threshold and
tIBUS_OCP_H_RE -- 2 -- s
Time device start to turn off
charger. (Note 6)
Rising, IBUS_UCP_RISE =
300mA, set by Register 160 300 420
IBUS_UCP_RISE 0x0007[6] = 0
IBUS_UCP_RISE_ACC mA
Accuracy Rising, IBUS_UCP_RISE =
500mA, set by Register 400 500 600
0x0007[6] = 1
IBUS_UCP_RISE
tIBUS_UCP_RISE_DEG -- 22 -- s
Deglitch Time
Falling, IBUS_UCP_FALL =
150mA, set by Register 40 150 320
IBUS_UCP_FALL 0x0007[6] = 0
IBUS_UCP_FALL_ACC mA
Accuracy Falling, IBUS_UCP_FALL =
250mA, set by Register 140 250 420
0x0007[6] = 1
tIBUS_UCP_FALL_DEG = 22s,
set by Register 0x005D[3] = -- 22 -- s
IBUS_UCP_FALL 0
tIBUS_UCP_FALL_DEG
Deglitch Time tIBUS_UCP_FALL_DEG = 5ms,
set by Register 0x005D[3] = -- 5 -- ms
1

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 RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
tBUS_UCP_TIMEOUT = 12.5ms,
set by Register 0x005D[7:5] 11.25 12.5 13.75
= 001
tBUS_UCP_TIMEOUT = 25ms,
set by Register 0x005D [7:5] 22.5 25 27.5
= 010
tBUS_UCP_TIMEOUT = 50ms,
set by Register 0x005D [7:5] 45 50 55 ms
= 011
tBUS_UCP_TIMEOUT = 100ms,
IBUS UCP Time Out tIBUS_UCP_TIMEOUT set by Register 0x005D [7:5] 90 100 110
= 100
tBUS_UCP_TIMEOUT = 400ms,
set by Register 0x005D [7:5] 360 400 440
= 101
tBUS_UCP_TIMEOUT = 1.5s,
set by Register 0x005D [7:5] 1.35 1.5 1.65
= 110
sec
tBUS_UCP_TIMEOUT = 100s,
set by Register 0x005D [7:5] 90 100 110
= 111
VDR OVP Accuracy VDR_OVP_ACC Rising, VDR_OVP = 300mV 200 300 400 mV
tVDR_OVP_DEG = 8s, set by
-- 8 -- s
Register 0x0005[4] = 0
VDR OVP Deglitch Time tVDR_OVP_DEG
tVDR_OVP_DEG = 5ms, set by
-- 5 -- ms
Register 0x0005[4] = 1
VOUT OVP Accuracy VOUT_OVP_ACC Rising, VOUT_OVP = 4.9V 4.8 4.9 5 V
VOUT OVP Deglitch Time tVOUT_OVP_DEG -- 3 -- s
Thermal Shutdown
TDIE_OTP_TH Rising 130 140 150 °C
Threshold
Thermal Shutdown
TDIE_OTP_HY Falling -- 20 -- °C
Hysteresis
Thermal Shut Down
tTDIE_DEG -- 3 -- s
Deglitch Time
DIV2 mode. VBUS rising.
VBUS_HIGH_ERR = 2.328 2.4 2.472
VBUS_HIGH_ERR VBUS/VOUT
VBUS_HIGH_ERR_ACC V/V
Accuracy Bypass mode. VBUS rising.
VBUS_HIGH_ERR = 1.14 1.2 1.26
VBUS/VOUT
DIV2 mode. VBUS falling.
2 2.04 2.08
VBUS_LOW_ERR VBUS_LOW_ERR = VBUS/VOUT
VBUS_LOW_ERR_ACC V/V
Accuracy Bypass mode. VBUS falling.
0.905 0.952 1
VBUS_LOW_ERR = VBUS/VOUT

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11
RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
In VBAT = 4V, if device
detect the short resistance
of flying capacitor smaller
CFLY Short Detect Level RCFLY_DIAG -- -- 16 
than this level while soft-
start duration, the device will
stop charging.
Alarm
VBAT_OVP_ALM Range VBAT_OVP_ALM_RAN Rising 4.2 -- 4.975 V
VBAT_OVP_ALM Step
VBAT_OVP_ALM_SIZE -- 25 -- mV
Size
VBAT_OVP_ALM
VBAT_OVP_ALM_HY Falling -- 50 -- mV
Hysteresis
VBAT_OVP_ALM VBAT_OVP_ALM = 4.2V to
VBAT_OVP_ALM_ACC 0.5 -- 0.5 %
Accuracy 4.5V
IBAT_OCP_ALM Range IBAT_OCP_ALM_RAN Rising 2 -- 8.3 A
IBAT_OCP_ALM Step
IBAT_OCP_ALM_SIZE -- 100 -- mA
Size
IBAT_OCP_ALM
IBAT_OCP_ALM_HY Falling -- 100 -- mA
Hysteresis
IBAT_OCP_ALM IBAT_OCP_ALM = 3A to 6A,
IBAT_OCP_ALM_ACC 200 -- 200 mA
Accuracy RSEN = 0.002
IBAT_UCP_ALM Range IBAT_UCP_ALM_RAN Falling 0 -- 3.15 A
IBAT_UCP_ALM Step
IBAT_UCP_ALM_SIZE -- 50 -- mA
Size
IBAT_UCP_ALM
IBAT_UCP_ALM_HY Rising -- 50 -- mA
Hysteresis
IBAT_UCP_ALM IBAT_UCP_ALM = 3A,
IBAT_UCP_ALM_ACC 200 -- 200 mA
Accuracy RSEN = 0.002
DIV2 mode. VBUS rising. 6 -- 12.3
VBUS_OVP_ALM Range VBUS_OVP_ALM_RAN V
Bypass mode. VBUS rising. 3 -- 6.15

VBUS_OVP_ALM Step DIV2 mode -- 100 --

VBUS_OVP_ALM_SIZE mV
Size Bypass mode -- 50 --

VBUS_OVP_ALM DIV2 mode. VBUS falling. -- 100 --

VBUS_OVP_ALM_HY mV
Hysteresis Bypass mode. VBUS falling. -- 50 --
VBUS_OVP_ALM Falling, VBUS_OVP_ALM = 6V
VBUS_OVP_ALM_ACC 35 -- 35 mV
Accuracy to 9V.
IBUS_OCP_ALM Range IBUS_OCP_ALM_RAN Rising 0 -- 6 A
IBUS_OCP_ALM Step
IBUS_OCP_ALM_SIZE -- 100 -- mA
Size
IBUS_OCP_ALM
IBUS_OCP_ALM_HY Falling -- 100 -- mA
Hysteresis
IBUS_OCP_ALM
IBUS_OCP_ALM_ACC IBUS_OCP_ALM = 1A to 4A 150 -- 150 mA
Accuracy
IBUS_UCP_ALM Range IBUS_UCP_ALM_RAN Rising 0 -- 3.175 A

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 RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
IBUS_UCP_ALM Step
IBUS_UCP_ALM_SIZE -- 25 -- mA
Size
IBUS_UCP_ALM
IBUS_UCP_ALM_HY Falling -- 50 -- mA
Hysteresis
IBUS_UCP_ALM
IBUS_UCP_ALM_ACC IBUS_UCP_ALM = 0.3A to 0.5A 150 -- 150 mA
Accuracy
TDIE_OTP_ALM Range TDIE_OTP_ALM_RAN Rising 25 -- 152.5 °C
TDIE_OTP_ALM Step
TDIE_OTP_ALM_SIZE -- 1 -- °C
Size
TDIE_OTP_ALM
TDIE_OTP_ALM_HY Falling -- 10 -- °C
Hysteresis
TDIE_OTP_ALM
TDIE_OTP_ALM_ACC 4 -- 4 °C
Accuracy
DP_OV_ALM Rising
VDP_OV_ALM_TH Rising -- 4.5 -- V
Threshold
DP_OV_ALM Hysteresis VDP_OV_ALM_HY Falling -- 100 -- mV
DP_OV_ALM Accuracy VDP_OV_ALM_ACC 50 -- 50 mV
DM_OV_ALM Rising
VDM_OV_ALM_TH Rising -- 4.5 -- V
Threshold
DM_OV_ALM Hysteresis VDM_OV_ALM_HY Falling -- 100 -- mV
DM_OV_ALM Accuracy VDM_OV_ALM_ACC 50 -- 50 mV
ADC Specification
ADC Sample Rate fSAMPLE_RATE 1800 2000 2200 kHz
12bit, 128 averages
ADC Data Rate tDATA_ADC Report data for each -- 1.2 -- ms
channel
VBUS ADC Range VBUS_ADC_RAN 0 -- 14 V
VBUS = 6V to 9V 35 -- 35 mV
VBUS ADC Accuracy VBUS_ADC_ACC
VBUS = 3.3V to 11.5V 2 -- 2 %
IBUS ADC Range IBUS_ADC_RAN 0 -- 6 A
IBUS = 2A 5 -- 5 %
IBUS ADC Accuracy IBUS_ADC_ACC
IBUS = 0A to 4A 150 -- 150 mA
VOUT ADC Range VOUT_ADC_RAN 0 -- 5 V
VOUT ADC Accuracy VOUT_ADC_ACC VOUT = 3V to 4.5V 20 -- 20 mV
VBAT ADC Range VBAT_ADC_RAN 0 -- 5 V
VBAT = 3V to 4.5V 0.5 -- 0.5 %
VBAT ADC Accuracy VBAT_ADC_ACC
VBAT = 4.45V 10 -- 10 mV
IBAT ADC Range IBAT_ADC_RAN 0 -- 10 A

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RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
IBAT = 3A to 8A,
200 -- 200 mA
RSEN = 0.002
IBAT = 2A,
IBAT ADC Accuracy IBAT_ADC_ACC 5 -- 5
RSEN = 0.002
%
IBAT = 7A,
2 -- 2
RSEN = 0.002
TDIE ADC Range TDIE_ADC_RAN 40 -- 152.5 °C
TDIE ADC Accuracy TDIE_ADC_ACC TJ = 25C 4 -- 4 °C
DP_ADC Range DP_ADC_RAN 0 -- 5 V
DP_ADC Accuracy DP_ADC_ACC 50 -- 50 mV
DM_ADC Range DM_ADC_RAN 0 -- 5 V
DM_ADC Accuracy DM_ADC_ACC 50 -- 50 mV
REGN
ADC enabled, VBUS  5.5V 4.9 5 5.1
ADC enabled, VBUS < 5.5V,
VBUS VBUS
REGN LDO Output Without VAC and VOUT, VBUS
VREGN - 0.7 + 0.1 V
Voltage VBUS > VDDA_UVLO_TH
Without VAC and VOUT, VOUT - VOUT
VOUT
VOUT > VDDA_UVLO_TH 0.1 + 0.1
Pull-Down
VAC < 5V -- 270 -- 
VAC Pull-Down Resistor RVAC_PD
VAC > 5V -- 22 -- mA
VAC Pull-Down Time Out tVAC_PD 360 400 440 ms
VBUS Pull-Down Resistor RVBUS_PD VBUS = 3V to 14V 0.6 1 1.4 k

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 RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
Watchdog Time Out
No I2C communication for
0.5s, set by Register
0.45 0.5 0.55
0x0000[2:0] = 000
(Note 6)
No I2C communication for
1s, set by Register
0.9 1 1.1
0x0000[2:0] = 001
(Note 6)
No I2C communication for
5s, set by Register
4.5 5 5.5
0x0000[2:0] = 010
(Note 6)
No I2C communication for
30s, set by Register
27 30 33
0x0000[2:0] = 011
(Note 6)
Watchdog Time Out WDT sec
No I2C communication for
40s, set by Register
36 40 44
0x0000[2:0] = 100
(Note 6)
No I2C communication for
80s, set by Register
72 80 88
0x0000[2:0] = 101
(Note 6)
No I2C communication for
128s, set by Register
115.2 128 140.8
0x0000[2:0] = 110
(Note 6)
No I2C communication for
255s, set by Register
229.5 255 280.5
0x0000[2:0] = 111
(Note 6)
̅̅̅̅̅)
Logic Output Pin (INT
̅̅̅̅̅
INT Output Low Sink current = 100A -- -- 0.1
VOL_INT V
Threshold Sink current = 2mA -- -- 0.3
̅̅̅̅̅
INT High Level Leakage
ILKG_INT Pull-up rail 1.8V -- -- 1 A
Current
̅̅̅̅̅
INT Pin Pull-Low Time tINT_PULL_LOW -- 256 -- s
Synchronize Function
DP_SYNCOUT Output VREGN
VOH_DP_SYNCOUT Register 0x005F[7] = 1 -- -- V
High Threshold - 0.4
DP_SYNCOUT Output
VOL_DP_SYNCOUT Register 0x005F[7] = 1 -- -- 0.2 V
Low Threshold
BATN/SRP_SYNCIN VREGN
VIH_BATN/SRP_SYNCIN Register 0x005F[5] = 1 -- -- V
Input High Threshold x 0.75
BATN/SRP_SYNCIN VREGN
VIL_BATN/SRP_SYNCIN Register 0x005F[5] = 1 -- -- V
Input Low Threshold x 0.25

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RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
VDD of I2C Detection
VDD level of I2C = 1.2V
when SDA voltage <
VTH_I2C_level.
VDD level of I2C = 1.8V
VDD Level of I2C when SDA voltage >
VTH_I2C_level 1.3 1.5 1.65 V
Detection Threshold VTH_I2C_level.
(VDD level of I2C can only
change to 1.8V from 1.2V. It
cannot change to 1.2V from
1.8V.)
VSDA Rising Deglitch
tI2C_level -- 17.5 -- s
Time
DP/DM Detection
DP Source Voltage VDP_SRC 0.5 0.6 0.7 V
DM Source Voltage VDM_SRC 0.5 0.6 0.7 V
Data Detect Voltage VDAT_REF 0.25 0.325 0.4 V
Logic Threshold Voltage VLGC_CHG 0.8 -- 2 V
DP Sink Current IDP_SINK 25 45 65 A
DM Sink Current IDM_SINK 25 45 65 A
Data Contact Detect
IDP_SRC 7 10 13 A
Current Source
DP Pull-Down Resistance RDP_DWN 14.25 20 24.8 k
DM Pull-Down Resistance RDM_DWN 14.25 20 24.8 k
DP Source On-Time tDP_SRC_ON 40 64 80 ms
DM Source On-Time tDM_SRC_ON 40 64 80 ms
DCD Timeout tDCD_TIMEOUT Register 0x0044[6:5] = 01 300 -- 900 ms

I2C Characteristics
(Note 6)
Parameter Symbol Test Conditions Min Typ Max Unit

SCL, SDA High-Level Input I2C_level = 1.8V 1.17 -- --

VIH_I2C V
Threshold Voltage I2C_level = 1.2V 0.78 -- --

SCL, SDA Low-Level Input I2C_level = 1.8V -- -- 0.63

VIL_I2C V
Threshold Voltage I2C_level = 1.2V 0.42
Sink current = 3mA, pull-up rail
-- -- 0.36
SDA Low-Level Output 1.8V
VOL_I2C V
Threshold Voltage Sink current = 3mA, pull-up rail
-- -- 0.24
1.2V

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 RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
Standard-mode -- -- 100
Fast-mode -- -- 400 kHz
SCL Clock Frequency fCLK Fast-mode plus -- -- 1000
High-speed mode Cb = 400pF -- -- 1.7
MHz
High-speed mode Cb = 100pF -- -- 3.4
Standard-mode 4.7 -- --
Bus Free Time between Stop
tBUF Fast-mode 1.3 -- -- s
and Start Condition
Fast-mode Plus 0.5 -- --
Standard-mode 4 -- --
Fast-mode 0.6 -- -- s
(Repeated) Start Hold Time tHD;STA Fast-mode plus 0.26 -- --
High-speed mode Cb = 400pF 160 -- --
ns
High-speed mode Cb = 100pF 160 -- --
Standard-mode 4.7 -- --
Fast-mode 0.6 -- -- s
(Repeated) Start Setup Time tSU;STA Fast-mode plus 0.26 -- --
High-speed mode Cb = 400 pF 160 -- --
ns
High-speed mode Cb = 100 pF 160 -- --
Standard-mode 4 -- --
Fast-mode 0.6 -- -- s
STOP Condition Setup Time tSU;STO Fast-mode plus 0.26 -- --
High-speed mode Cb = 400pF 160 -- --
ns
High-speed mode Cb = 100pF 160 -- --
Standard-mode 0.1 -- --
Fast-mode 0.1 -- --
SDA Data Hold Time tHD;DAT Fast-mode plus 0.1 -- -- ns
High-speed mode Cb = 400pF 0.1 -- 150
High-speed mode Cb = 100pF 0.1 -- 70
Standard-mode -- -- 3.45
SDA Valid Acknowledge
tVD;ACK Fast-mode -- -- 0.9 s
Time
Fast-mode plus -- -- 0.45
Standard-mode 250 -- --
Fast-mode 100 -- --
SDA Setup Time tSU;DAT Fast-mode plus 50 -- -- ns
High-speed mode Cb = 400pF 10 -- --
High-speed mode Cb = 100pF 10 -- --

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RT9756A
Parameter Symbol Test Conditions Min Typ Max Unit
Standard-mode 4.7 -- --
Fast-mode 1.3 -- -- s
SCL Clock Low Time tLOW Fast-mode Plus 0.5 -- --
High-speed mode Cb = 400pF 320 -- --
ns
High-speed mode Cb = 100pF 160 -- --
Standard-mode 4 -- --
Fast-mode 0.6 -- -- s
SCL Clock High Time tHIGH Fast-mode Plus 0.26 -- --
High-speed mode Cb = 400pF 120 -- --
ns
High-speed mode Cb = 100pF 60 -- --
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. For testing absolute maximum rating of OVPGATE pin, VBUS pin should be power-on with 20V initially. After VBUS has
kept 20V for 25.6ms, the OVPGATE can be biased.
Note 3. JA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-thermal-
conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard.
Note 4. Devices are ESD sensitive. Handling precautions are recommended.
Note 5. The device is not guaranteed to function outside its operating conditions.
Note 6. Specification is guaranteed by design and/or correlation with statistical process control.
Note 7. When set Bypass mode, VAC OVP must be 6.5V for surge condition.

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 RT9756A
Typical Application Circuit
CFLY1
22μF

CFLY2
22μF

CBST1 CFLY3
0.1μF 22μF

A6 A1 B1 C1, C2 E1, E2
OVPGATE VAC BST1 CFH1 CFL1
Q5 Q6
A2, A3,
VBUS A4, A5 B2, B5
VBUS PMID

CVAC CVBUS CPMID

USB Type-C Port

1μF 2.2μF 10μF

RT9756A

D+ B3
DP_SYNCOUT

D- B4 D1, D2, D5, D6

DM_TS VOUT
COUT1 COUT2
10μF 10μF

Pull-Up
Battery
Pack
E3
BATP
R3 R2 R1 R4 +
10kΩ 10kΩ 10kΩ 100Ω
C3
SDA D3
BATN/SRP_SYNCIN
C4
Host SCL RSEN
0.002Ω
E4
INT D4
SRN_ADDR

F4
REGN
CREGN
4.7μF
GND AGND BST2 CFH2 CFL2
F1, F2, F3 B6 C5, C6 E5, E6
F5, F6

CBST2 CFLY4
0.1μF 22μF

CFLY5
22μF

CFLY6
22μF

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19
RT9756A
Below are recommended components information

Table 1. BOM List

Name Part Number Description Package Manufacturer
CVAC GRM155R61H105KE05 CAP, CERM, 1F, 50V, 10%, X5R 0402 MuRata
CVBUS GRM155R61E225KE11 CAP, CERM, 2.2F, 25V, 10%, X5R 0402 MuRata
N-Channel 30V, 2.4m logic level
Q5, Q6 PSMN2R4-30MLD MOSFET in LFPAK33, using LFPAK33 Nexperia
NextPowerS3 Technology
CFLY1,
CFLY2,
CFLY3,
GRM187R61A226ME15 CAP, CERM, 22F, 10V, 20%, X5R 0603 MuRata
CFLY4,
CFLY5,
CFLY6
COUT1,
GRM185R60J106ME15 CAP, CERM, 10F, 6.3V, 20%, X5R 0603 MuRata
COUT2
CPMID GRM188R61E106MA73 CAP, CERM, 10F, 25V, 20%, X5R 0603 MuRata
CBST1,
GRM033R61C104KE14 CAP, CERM, 0.1F, 16V, 10%, X5R 0201 MuRata
CBST2
CREGN GRM155R61A475MEAAD CAP, CERM, 4.7F, 10V, 20%, X5R 0402 MuRata
R1, R2, R3 WR04X1002FTL RES, 10k, 1%, 0.0625W 0402 Walsin
R4 CR0402F100RQ10Z RES, 100, 1%, 0.063W 0402 EVER OHMS
Stackpole
RSEN CSNL1206FT2L00 RES, 0.002, 1%, 1W 1206
Electronics Inc

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 RT9756A
Typical Operating Characteristics
Charge Efficiency vs. Charge Current Charge Efficiency vs. Charge Current
(DIV2 Mode) (DIV2 Mode)
99.0 99.0

98.5 98.5

98.0 98.0

Charge Efficiency (%)

Charge Efficiency (%)

97.5 97.5

97.0 97.0 fSW = 200kHz

fSW = 500kHz
96.5 96.5 fSW = 800kHz
VOUT = 3.5
fSW = 1000kHz
96.0 VOUT = 4V 96.0
VOUT = 4.5V
95.5 95.5

95.0 95.0
fSW = 500kHz, 3 x 22F CFLY per Phase VOUT = 4V, 3 x 22F CFLY per Phase
94.5 94.5
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
Charge Current (A) Charge Current (A)

Charge Efficiency vs. Charge Current Charge Efficiency vs. Charge Current
(DIV2 Mode) (Bypass Mode)
99.0 99.5
3 x 22F CFLY per Phase
98.5
98.0 4 x 22F CFLY per Phase 99.0
Charge Efficiency (%)

Charge Efficiency (%)

97.5
97.0
98.5 VOUT = 3.5
96.5 VOUT = 4V
1 x 22F CFLY per Phase
96.0 VOUT = 4.5V
2 x 22F CFLY per Phase 98.0
95.5 3 x 22F CFLY per Phase
4 x 22F CFLY per Phase
95.0
94.5 97.5

94.0 VOUT = 4V, fSW = 500kHz

93.5 97.0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5
Charge Current (A) Charge Current (A)

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RT9756A
Register Description
Register Map
Threshold/
Function Name STAT FLAG MASK Enable Deglitch
Setting
REG_RST -- -- -- -- 0x0000[7] --
CHG_EN -- -- -- -- 0x0000[6] --
OPERATION_MODE -- -- -- 0x0000[5] -- --
WDT -- 0x000F[5] 0x0010[5] 0x0000[2:0] 0x0000[3] --
FSW -- -- -- 0x0001[7:4] -- --
FSW_SHIFT -- -- -- 0x0001[3:2] -- --
PHASE_DELAY -- -- -- 0x0001[1:0] -- --
PHASE_ANGLE -- -- -- 0x0002[3:0] -- --
OVPGATE -- -- -- 0x0004[0] 0x0004[6] --
CON_SWITCHING 0x005C[7] -- 0x005C[6] -- -- --
IC_STAT 0x005C[5:4] -- -- -- -- --
IBAT_RSEN -- -- -- 0x005E[1:0] -- --
Pin Configuration -- -- -- 0x005F[7:5] -- --
VAC_PD -- 0x000B[6] 0x000C[6] -- 0x0005[7] --
VBUS_PD -- 0x000B[5] 0x000C[5] -- 0x0005[6] --
CFLY_DIAG -- 0x000F[0] 0x0010[0] -- 0x0002[7] --
TDIE_OTP 0x004C[3] 0x000D[3] 0x000E[3] -- 0x0002[6] --
VBUS_LOW_ERR 0x004C[2] 0x000D[2] 0x000E[2] -- 0x0002[5] --
VBUS_HIGH_ERR 0x004C[1] 0x000D[1] 0x000E[1] -- 0x0002[4] --
VAC_OVP 0x004B[7] 0x000B[7] 0x000C[7] 0x0004[3:1] 0x0004[4] --
VDR_OVP 0x004B[4] 0x000B[4] 0x000C[4] -- 0x0005[5] 0x0005[4]
VBUS_OVP 0x004B[3] 0x000B[3] 0x000C[3] 0x0006[5:0] 0x0006[7] --
IBUS_UCP_RISE -- 0x000B[1] 0x000C[1] 0x0007[6] 0x0007[7] --
IBUS_UCP_FALL -- 0x000B[0] 0x000C[0] 0x0007[6] 0x0007[7] 0x005D[3]
IBUS_OCP 0x004B[2] 0x000B[2] 0x000C[2] 0x0007[4:0] 0x0007[5] --
IBUS_OCP_H -- 0x0061[0] 0x0061[1] -- -- --
VBAT_OVP 0x004C[7] 0x000D[7] 0x000E[7] 0x0008[4:0] 0x0008[7] --
IBAT_OCP 0x004C[6] 0x000D[6] 0x000E[6] 0x0009[5:0] 0x0009[7] --
VOUT_OVP 0x004E[0] 0x0049[0] 0x004A[0] -- 0x005E[3] --
IBAT_REG 0x004C[4] 0x000D[4] 0x000E[4] 0x000A[4:3] 0x000A[5] --
VBAT_REG 0x004C[5] 0x000D[5] 0x000E[5] 0x000A[1:0] 0x000A[2] --
VAC_INSERT 0x004C[0] 0x000D[0] 0x000E[0] -- -- --
VBUS_INSERT 0x004D[7] 0x000F[7] 0x0010[7] -- -- --
VOUT_INSERT 0x004D[6] 0x000F[6] 0x0010[6] -- -- --
VAC_UVLO 0x004D[4] 0x000F[4] 0x0010[4] -- -- --

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22
 RT9756A
Threshold/
Function Name STAT FLAG MASK Enable Deglitch
Setting
VBUS_UVLO 0x004D[3] 0x000F[3] 0x0010[3] -- -- --
VDDA_UVLO -- 0x0063[1] 0x0063[0] -- -- --
IBUS_UCP_TIMEOUT 0x004D[2] 0x000F[2] 0x0010[2] 0x005D[7:5] -- --
TS_OTP 0x005F[1] 0x005F[3] 0x005F[2] 0x0060[7:0] 0x005F[0]
ADC 0x004D[1] 0x000F[1] 0x0010[1] 0x0011[6] 0x0011[7] --
0x0012[5:0]
VBUS_ADC -- -- -- 0x0011[5] --
0x0013[7:0]
0x0014[5:0]
IBUS_ADC -- -- -- 0x0011[4] --
0x0015[7:0]
0x0016[5:0]
VBAT_ADC -- -- -- 0x0011[3] --
0x0017[7:0]
0x0018[5:0]
IBAT_ADC -- -- -- 0x0011[2] --
0x0019[7:0]
TDIE_ADC 0x001A[7:0] -- -- -- 0x0011[1] --
0x0056[5:0]
VOUT_ADC -- -- -- 0x0056[7]
0x0057[7:0]
0x0058[5:0]
DP_ADC -- -- -- 0x0058[7]
0x0059[7:0]
0x005A[5:0]
DM_ADC -- -- -- 0x005A[7]
0x005B[7:0]
VBAT_OVP_ALM 0x004E[7] 0x0049[7] 0x004A[7] 0x004F[4:0] 0x004F[7] --
IBAT_OCP_ALM 0x004E[6] 0x0049[6] 0x004A[6] 0x0050[5:0] 0x0050[7] --
VBUS_OVP_ALM 0x004E[5] 0x0049[5] 0x004A[5] 0x0051[5:0] 0x0051[7] --
IBUS_OCP_ALM 0x004E[4] 0x0049[4] 0x004A[4] 0x0052[5:0] 0x0052[7] --
IBAT_UCP_ALM 0x004E[3] 0x0049[3] 0x004A[3] 0x0053[5:0] 0x0053[7] --
IBUS_UCP_ALM 0x004E[2] 0x0049[2] 0x004A[2] 0x0054[6:0] 0x0054[7] --
TDIE_OTP_ALM 0x004E[1] 0x0049[1] 0x004A[1] 0x0055[6:0] 0x0055[7] --
DP_OV_ALM 0x0061[5] 0x0061[7] 0x0061[3] -- -- --
DM_OV_ALM 0x0061[4] 0x0061[6] 0x0061[2] -- -- --
0x0046[7:3]
BC1.2 0x0045[4:0] 0x0047[4:0] -- 0x0044[7:2] --
0x0046[1:0]
0x0048
0x0066
DPDM Manual -- -- -- -- --
0x006D
0x006E

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23
RT9756A
Register Description
I2C Slave Address: 1101111 (6FH) when SRN_ADDR pin is connected to GND
I2C Slave Address: 1101110 (6EH) when SRN_ADDR pin is floating
R: Read only
RC: Read and clear
RW: Read and write
RWC: Read and write, also automatically clear by particular condition
RWSC: Read and write, also automatically set/clear by particular condition

Register Address: 0x0000, Register Name: CHG_CTL1

WDT REG
Bit Bit Name Default Type Description
RST RST
Register reset
7 REG_RST 0 N Y RW 0: No register reset (default)
1: Reset registers
Charger control bit
6 CHG_EN 0 Y Y RW 0: Disable charge (default)
1: Enable charge
This bit selects converter operation mode.
OPERATION_
5 1 N N RW 0: Bypass mode
MODE
1: DIV2 mode (default)
4 Reserved 0 NA NA NA Reserved
Disable Watchdog
3 WDT_DIS 0 N Y RW 0: Enable watchdog (default)
1: Disable watchdog
Set the watchdog timer.
000: 0.5s (default)
001: 1s
010: 5s
2:0 WDT_TIMER 000 N Y RW 011: 30s
100: 40s
101: 80s
110: 128s
111: 255s

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 RT9756A
Register Address: 0x0001, Register Name: CHG_CTL2
WDT REG
Bit Bit Name Default Type Description
RST RST
Set the switching frequency.
0000 to 1001: 100kHz to 1000kHz in
7:4 FSW_SET 0100 N Y RW 100kHz steps
1010 to 1111: Reserved
0100: 500kHz (default)
Adjust switching frequency for EMI.
00: Nominal frequency (default)
3:2 FREQ_SHIFT 00 N Y RW 01: Nominal frequency + 10%
10: Nominal frequency - 10%
11: Spread spectrum
Adjust delay time between two phases.
It is strongly prohibited during operation.
Should be determined before CHG_EN set
PHASE_ 1.
1:0 00 N Y RW
DELAY 00: 0ns (default)
01: 15ns
10: 30ns
11: 45ns

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RT9756A
Register Address: 0x0002, Register Name: CHG_CTL3
WDT REG
Bit Bit Name Default Type Description
RST RST
Enable CFLY short protection before charge
CFLY_DIAG_ mode is enabled.
7 1 N Y RW
EN 0: Disable
1: Enable (default)
Enable TDIE over-temperature protection.
6 TDIE_OTP_EN 1 N Y RW 0: Disable
1: Enable (default)
Enable VBUS voltage too high error
VBUS_LOW_ protection before charge mode is enabled.
5 1 N Y RW
ERR_EN 0: Disable
1: Enable (default)
Enable VBUS voltage too low error
VBUS_HIGH_ protection before charge mode is enabled.
4 1 N Y RW
ERR_EN 0: Disable
1: Enable (default)
Select phase A angle in DIV2 mode.
It is strongly prohibited during operation.
Should be determined before CHG_EN set
1.
00: 0 degree (default)
01: 90 degree
10: 180 degree
PHASE_A_
3:2 00 N Y RW 11: 270 degree
ANGLE
(If the RT9756A operate in single
application, the bits are recommended to set
00.
If the RT9756A operates in parallel
application and enables synchronous
function, the bits are recommended to set
00 in Master mode and 01 in Slave mode.)
Select phase B angle in DIV2 mode.
It is strongly prohibited during operation.
Should be determined before CHG_EN set
1.
00: 0 degree
01: 90 degree
10: 180 degree (default)
PHASE_B_
1:0 10 N Y RW 11: 270 degree
ANGLE
(If the RT9756A operates in single
application, the bits are recommended to set
10.
If the RT9756A operates in parallel
application and enables synchronous
function, the bits are recommended to set
10 in Master mode and 11 in Slave mode.)

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26
 RT9756A
Register Address: 0x0003, Register Name: DEVICE_INFO
WDT REG
Bit Bit Name Default Type Description
RST RST
Device
7:4 0000 Y Y R Device revision
Revision
Device ID
3:0 Device ID 0111 Y Y R
0111: RICHTEK product

Register Address: 0x0004, Register Name: VAC_PROTECTION

WDT REG
Bit Bit Name Default Type Description
RST RST
7 Reserved 0 NA NA NA Reserved
Disable OVPGATE.
6 OVPMOS_DIS 0 Y Y RW 0: Enable OVPGATE (default)
1: Disable OVPGATE
5 Reserved 0 NA NA NA Reserved
Enable VAC overvoltage protection.
4 VAC_OVP_EN 1 Y Y RW 0: Disable
1: Enable (default)
VAC overvoltage threshold
000-110 is determined by VAC_OVP = 11V +
VAC_OVP[2:0] x 1V.
3:1 VAC_OVP 001 N Y RW
Writing all 1 to these bits set the VAC_OVP to
6.5V.
Default = 12V
Select OVPMOS VGS voltage.
It is strongly prohibited when OVPMOS is
turned on. Should be determined before
0 OVPGATE 0 N N RW
OVPMOS is turned on.
0: 4.8V (default)
1: 10V

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RT9756A
Register Address: 0x0005, Register Name: PD_VDR_OVP
WDT REG
Bit Bit Name Default Type Description
RST RST
Enable VAC pull-down resistor.
0: Disable (default)
7 VAC_PD_EN 0 N N RW 1: Enable
(VAC pull-down resistor is only enable for
400ms, and then this bit is reset to default.)
Enable VBUS pull-down resistor.
6 VBUS_PD_EN 0 N Y RW 0: Disable (default)
1: Enable
Enable Dropout overvoltage protection.
5 VDR_OVP_EN 1 N Y RW 0: Disable
1: Enable (default)
This is deglitch time after the device reaches
VDR_OVP_ the VDR_OVP threshold before the part
4 DEGLITCH_ 0 N Y RW stops switching.
SET 0: 8s (default)
1: 5ms
3:0 Reserved 0000 NA NA NA Reserved

Register Address: 0x0006, Register Name: VBUS_OVP

WDT REG
Bit Bit Name Default Type Description
RST RST
Enable VBUS overvoltage protection.
VBUS_OVP_
7 1 Y Y RW 0: Disable
EN
1: Enable (default)
6 Reserved 0 NA NA NA Reserved
VBUS overvoltage threshold.
The setting is determined by difference
modes.
Device in DIV2 mode:
5:0 VBUS_OVP 011101 N Y RW VBUS_OVP = 6V + VBUS_OVP[5:0] Х
100mV, Default: 8.9V (b011101)
Device in BYPASS mode:
VBUS_OVP = 3V + VBUS_OVP[5:0] Х 50mV,
Default: 4.45V (b011101)

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28
 RT9756A
Register Address: 0x0007, Register Name: IBUS_OCP_UCP
WDT REG
Bit Bit Name Default Type Description
RST RST
Enable IBUS undercurrent protection.
IBUS_UCP_
7 1 N Y RW 0: Disable
EN
1: Enable (default)
This bit is set the IBUS_UCP threshold and
it can only be changed prior to enabling
switching. The system should control the
IBUS_UCP_
6 0 N Y RW IBUS current rise to IBUS_UCP_RISE
THRESHOLD
within the IBUS_UCP_TIMEOUT.
0: 300mA rising, 150mA falling (default)
1: 500mA rising, 250mA falling
Enable IBUS overcurrent protection.
IBUS_OCP_
5 1 N Y RW 0: Disable
EN
1: Enable (default)
IBUS overcurrent threshold.
IBUS_OCP = 1A + IBUS_OCP[4:0] x 250mA.
4:0 IBUS_OCP 01000 N Y RW
10010 to 11111: IBUS_OCP = 5.5A.
Default: 3A (b01000)

Register Address: 0x0008, Register Name: VBAT_OVP

WDT REG
Bit Bit Name Default Type Description
RST RST
Enable VBAT overvoltage protection.
VBAT_OVP_
7 1 N Y RW 0: Disable
EN
1: Enable (default)
6:5 Reserved 00 NA NA NA Reserved
VBAT overvoltage threshold.
4:0 VBAT_OVP 00110 N Y RW VBAT_OVP = 4.2V + VBAT_OVP[4:0] x 25mV
Default: 4.35V (b00110)

Register Address: 0x0009, Register Name: IBAT_OCP

WDT REG
Bit Bit Name Default Type Description
RST RST
Enable IBAT overcurrent protection.
7 IBAT_OCP_EN 1 N Y RW 0: Disable
1: Enable (default)
6 Reserved 0 NA NA NA Reserved
IBAT overcurrent threshold
5:0 IBAT_OCP 110100 N Y RW IBAT_OCP = 2A + IBAT_OCP[5:0] x 100mA
Default: 7.2A (b110100)

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RT9756A
Register Address: 0x000A, Register Name: REG_CTRL
WDT REG
Bit Bit Name Default Type Description
RST RST
7:6 Reserved 00 NA NA NA Reserved
Enable IBAT current regulation.
5 IBAT_REG_EN 0 N Y RW 0: Disable (default)
1: Enable
These two bits set the threshold below
IBAT_OCP where the part starts regulation.
00: 200mA below IBAT_OCP setting (default)
4:3 IBAT_REG 00 N Y RW 01: 300mA below IBAT_OCP setting
10: 400mA below IBAT_OCP setting
11: 500mA below IBAT_OCP setting
(2A is the minimum level of IBAT_REG.)
Enable VBAT voltage regulation.
VBAT_REG_
2 0 N Y RW 0: Disable (default)
EN
1: Enable
These two bits set the threshold below
VBAT_OVP where the part starts regulation.
00: 50mV below VBAT_OVP setting (default)
1:0 VBAT_REG 00 N Y RW 01: 100mV below VBAT_OVP setting
10: 150mV below VBAT_OVP setting
11: 200mV below VBAT_OVP setting
(4.2V is the minimum level of IBAT_REG.)

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30
 RT9756A
Register Address: 0x000B, Register Name: INT_FLAG1
WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅ when a VAC_OVP
Set 1 and send an INT
event occurs.
VAC_OVP_
7 0 N N RC 0: No VAC_OVP Fault
FLAG
1: VAC_OVP Fault has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when a VAC pull-
down event occurs.
VAC_PD_
6 0 N N RC 0: No VAC pull down
FLAG
1: VAC pull down has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when a VBUS pull-
down event occurs.
VBUS_PD_
5 0 N N RC 0: No VBUS pull down
FLAG
1: VBUS pull down has occurred
(Clear upon read.)
̅̅̅̅̅ when a VDR_OVP
Set 1 and send an INT
has occurred.
VDR_OVP_
4 0 N N RC 0: No VDR_OVP Fault
FLAG
1: VDR_OVP Fault has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when VBUS is over
than VBUS_OVP threshold.
VBUS_OVP_
3 0 N N RC 0: No VBUS_OVP Fault.
FLAG
1: VBUS_OVP Fault has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when IBUS is over
than IBUS_OCP threshold.
IBUS_OCP_
2 0 N N RC 0: No IBUS_OCP Fault.
FLAG
1: IBUS_OCP Fault has occurred.
(Clear upon read.)
̅̅̅̅̅ when IBUS current is
Set 1 and send an INT
over than IBUS_UCP_RISE threshold.
IBUS_UCP_
1 0 N N RC 0: No IBUS_UCP rising.
RISE_FLAG
1: IBUS_UCP rising has occurred.
(Clear upon read.)
̅̅̅̅̅ when IBUS current is
Set 1 and send an INT
lower than IBUS_UCP_FALL threshold.
IBUS_UCP_
0 0 N N RC 0: No IBUS_UCP falling.
FALL_FLAG
1: IBUS_UCP falling has occurred.
(Clear upon read.)

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31
RT9756A
Register Address: 0x000C, Register Name: INT_MASK1
WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅.
Masks a VAC_OVP event to send an INT
VAC_OVP_
7 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a VAC_PD event to send an INT
VAC_PD_
6 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a VBUS_PD event to send an INT
VBUS_PD_
5 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a VDR_OVP event to send an INT
VDR_OVP_
4 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a VBUS_OVP event to send an INT̅̅̅̅̅.
VBUS_OVP_
3 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a IBUS_OCP event to send an ̅̅̅̅̅
INT.
IBUS_OCP_
2 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a IBUS_UCP rising event to send an
IBUS_UCP_ ̅̅̅̅̅.
INT
1 0 N Y RW
RISE_MASK 0: Unmask (default)
1: Mask
Masks a IBUS_UCP falling event to send an
IBUS_UCP_ ̅̅̅̅̅.
INT
0 0 N Y RW
FALL_MASK 0: Unmask (default)
1: Mask

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32
 RT9756A
Register Address: 0x000D, Register Name: INT_FLAG2
WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅ when VBAT is over
Set 1 and send an INT
than VBAT_OVP threshold.
VBAT_OVP_
7 0 N N RC 0: No VBAT_OVP Fault.
FLAG
1: VBAT_OVP Fault has occurred.
(Clear upon read.)
̅̅̅̅̅ when IBAT is over
Set 1 and send an INT
than IBAT_OCP threshold.
IBAT_OCP_
6 0 N N RC 0: No IBAT_OCP Fault.
FLAG
1: IBAT_OCP Fault has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when VBAT_REG
has been active.
VBAT_REG_
5 0 N N RC 0: No VBAT_REG.
FLAG
1: VBAT_REG has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when IBAT_REG
has been active.
IBAT_REG_
4 0 N N RC 0: No IBAT_REG.
FLAG
1: IBAT_REG has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when die
temperature is over than TDIE threshold.
TDIE_OTP_
3 0 N N RC 0: No TDIE_OTP Fault.
FLAG
1: TDIE_OTP Fault has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when VBUS voltage
is lower than VBUS_LOW_ERR threshold.
VBUS_LOW_
2 0 N N RC 0: No VBUS_LOW_ERR Fault.
ERR_FLAG
1: VBUS_LOW_ERR Fault has occurred.
(Clear upon read.)
̅̅̅̅̅ when VBUS voltage
Set 1 and send an INT
is over than VBUS_HIGH_ERR threshold.
VBUS_HIGH_
1 0 N N RC 0: No VBUS_HIGH_ERR Fault.
ERR_FLAG
1: VBUS_HIGH_ERR Fault has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when VAC is over
than VAC_INSERT threshold.
VAC_INSERT_
0 0 N N RC 0: No VAC_INSERT.
FLAG
1: VAC_INSERT has occurred.
(Clear upon read.)

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RT9756A
Register Address: 0x000E, Register Name: INT_MASK2
WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅.
Masks a VBAT_OVP event to send an INT
VBAT_OVP_
7 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a IBAT_OCP event to send an INT
IBAT_OCP_
6 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a VBAT_REG event to send an INT
VBAT_REG_
5 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a IBAT_REG event to send an INT
IBAT_REG_
4 0 N Y RW 0: Unmask (default)
MASK
1: Mask
̅̅̅̅̅.
Masks a TDIE_OTP event to send an INT
TDIE_OTP_
3 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a VBUS_LOW_ERR event to send
VBUS_LOW_ ̅̅̅̅̅.
an INT
2 0 N Y RW
ERR_MASK 0: Unmask (default)
1: Mask
Masks a VBUS_HIGH_ERR event to send
VBUS_HIGH_ an INT̅̅̅̅̅.
1 0 N Y RW
ERR_MASK 0: Unmask (default)
1: Mask
Masks a VAC_INSERT event to send an
VAC_INSERT_ ̅̅̅̅̅
INT.
0 0 N Y RW
MASK 0: Unmask (default)
1: Mask

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 RT9756A
Register Address: 0x000F, Register Name: INT_FLAG3
WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅ when VBUS is over
Set 1 and send an INT
than VBUS_INSERT threshold.
VBUS_
7 0 N N RC 0: No VBUS_INSERT.
INSERT_FLAG
1: VBUS_INSERT has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when VOUT is over
than VOUT_INSERT threshold.
VOUT_
6 0 N N RC 0: No VOUT_INSERT.
INSERT_FLAG
1: VOUT_INSERT has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when a watchdog
time out event occurs.
5 WDT_FLAG 0 N N RC 0: No watchdog time out.
1: Watchdog time out has occurred.
(Clear upon read.)
̅̅̅̅̅ when VAC is lower
Set 1 and send an INT
than VAC_INSERT threshold.
VAC_UVLO_
4 0 N N RC 0: No VAC_UVLO.
FLAG
1: VAC_UVLO has occurred.
(Clear upon read.)
̅̅̅̅̅ when VBUS is lower
Set 1 and send an INT
than VBUS_INSERT threshold.
VBUS_UVLO_
3 0 N N RC 0: No VBUS_UVLO.
FLAG
1: VBUS_UVLO has occurred.
(Clear upon read.)
If IBUS is not ramped to the IBUS_UCP_RISE
threshold in IBUS_UCP_TIMEOUT time
after CHG_EN = 1, the converter will stop
IBUS_UCP_
switching. Set 1 and send an ̅̅̅̅̅
INT when this
2 TIMEOUT_ 0 N N RC
event happens.
FLAG
0: No IBUS_UCP_TIMEOUT.
1: IBUS_UCP_TIMEOUT has occurred.
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when ADC
conversion is completed in 1-shot mode.
ADC_DONE_
1 0 N N RC 0: No ADC conversion.
FLAG
1: ADC conversion is completed.
(Clear upon read.)
̅̅̅̅̅ when CFLY short
Set 1 and send an INT
during converter soft-start.
CFLY_DIAG_
0 0 N N RC 0: No CFLY short.
FLAG
1: CFLY short has occurred.
(Clear upon read.)

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RT9756A
Register Address: 0x0010, Register Name: INT_MASK3
WDT REG
Bit Bit Name Default Type Description
RST RST
Masks a VBUS_INSERT event to send an
VBUS_ ̅̅̅̅̅.
INT
7 INSERT_ 0 N Y RW
0: Unmask (default)
MASK
1: Mask
Masks a VOUT_INSERT event to send an
VOUT_ ̅̅̅̅̅
INT.
6 INSERT_ 0 N Y RW
0: Unmask (default)
MASK
1: Mask
Masks a watchdog time out event to send
an ̅̅̅̅̅
INT.
5 WDT_MASK 0 N Y RW
0: Unmask (default)
1: Mask
Masks a VAC_UVLO event to send an ̅̅̅̅̅
INT.
VAC_UVLO_
4 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a VBUS_UVLO event to send an
VBUS_UVLO_ ̅̅̅̅̅
INT.
3 0 N Y RW
MASK 0: Unmask (default)
1: Mask
Masks a IBUS_UCP_TIMEOUT event to
IBUS_UCP_
send an ̅̅̅̅̅
INT.
2 TIMEOUT_ 0 N Y RW
0: Unmask (default)
MASK
1: Mask
Masks a ADC conversion event to send an
ADC_DONE_ ̅̅̅̅̅
INT.
1 0 N Y RW
MASK 0: Unmask (default)
1: Mask
Masks a CFLY short event to send an ̅̅̅̅̅
INT.
CFLY_DIAG_
0 0 N Y RW 0: Unmask (default)
MASK
1: Mask

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36
 RT9756A
Register Address: 0x0011, Register Name: ADC_CTRL
WDT REG
Bit Bit Name Default Type Description
RST RST
Enable ADC conversion.
7 ADC_EN 0 Y Y RW 0: Disable (default)
1: Enable
ADC conversion rate
0: Continuous mode (default)
6 ADC_RATE 0 N Y RW 1: 1-shot mode
(In 1-shot mode, ADC_EN will be reset to 0
after ADC conversion is completed.)
Disable VBUS_ADC.
VBUS_ADC_
5 0 N Y RW 0: Enable Conversion (default)
DIS
1: Disable Conversion
Disable IBUS_ADC.
IBUS_ADC_
4 0 N Y RW 0: Enable Conversion (default)
DIS
1: Disable Conversion
Disable VBAT_ADC.
VBAT_ADC_
3 0 N Y RW 0: Enable Conversion (default)
DIS
1: Disable Conversion
Disable IBAT_ADC.
IBAT_ADC_
2 0 N Y RW 0: Enable Conversion (default)
DIS
1: Disable Conversion
Disable TDIE_ADC.
TDIE_ADC_
1 0 N Y RW 0: Enable Conversion (default)
DIS
1: Disable Conversion
0 Reserved 0 NA NA NA Reserved

Register Address: 0x0012, Register Name: VBUS_ADC1

WDT REG
Bit Bit Name Default Type Description
RST RST
7:6 Reserved 00 NA NA NA Reserved
VBUS ADC high byte
5:0 VBUS_ADC1 000000 N N R HSB<5:0>: 8192mV, 4096mV, 2048mV,
1024mV, 512mV, 256mV

Register Address: 0x0013, Register Name: VBUS_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
VBUS ADC low byte
7:0 VBUS_ADC0 00000000 N N R LSB<7:0>: 128mV, 64mV, 32mV, 16mV,
8mV, 4mV, 2mV, 1mV

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37
RT9756A
Register Address: 0x0014, Register Name: IBUS_ADC1
WDT REG
Bit Bit Name Default Type Description
RST RST
7:6 Reserved 00 NA NA NA Reserved
IBUS ADC high byte
5:0 IBUS_ADC1 000000 N N R HSB<5:0>: 8192mA, 4096mA, 2048mA,
1024mA, 512mA, 256mA

Register Address: 0x0015, Register Name: IBUS_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
IBUS ADC low byte
7:0 IBUS_ADC0 00000000 N N R LSB<7:0>: 128mA, 64mA, 32mA, 16mA,
8mA, 4mA, 2mA, 1mA

Register Address: 0x0016, Register Name: VBAT_ADC1

WDT REG
Bit Bit Name Default Type Description
RST RST
7:6 Reserved 00 NA NA NA Reserved
VBAT ADC high byte
5:0 VBAT_ADC1 000000 N N R HSB<5:0>: 8192mV, 4096mV, 2048mV,
1024mV, 512mV, 256mV

Register Address: 0x0017, Register Name: VBAT_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
VBAT ADC low byte
7:0 VBAT_ADC0 00000000 N N R LSB<7:0>: 128mV, 64mV, 32mV, 16mV,
8mV, 4mV, 2mV, 1mV

Register Address: 0x0018, Register Name: IBAT_ADC1

WDT REG
Bit Bit Name Default Type Description
RST RST
7:6 Reserved 00 NA NA NA Reserved
IBAT ADC high byte
5:0 IBAT_ADC1 000000 N N R HSB<5:0>: 8192mA,4096mA, 2048mA,
1024mA, 512mA, 256mA

Register Address: 0x0019, Register Name: IBAT_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
IBAT ADC low byte
7:0 IBAT_ADC0 00000000 N N R LSB<7:0>: 128mA, 64mA, 32mA, 16mA,
8mA, 4mA, 2mA, 1mA

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38
 RT9756A
Register Address: 0x001A, Register Name: TDIE_ADC0
WDT REG
Bit Bit Name Default Type Description
RST RST
TDIE ADC LSB<7:0>: 128°C, 64°C, 32°C,
7:0 TDIE_ADC 00000000 N N R 16°C, 8°C, 4°C, 2°C, 1°C
TDIE = 40°C + TDIE_ADC<7:0> x 1°C

Register Address: 0x0044, Register Name: BC12_CTL

WDT REG
Bit Bit Name Default Type Description
RST RST
Enable BC1.2 detection.
0: Disable BC1.2 detection (default)
1: Enable BC1.2 detection
7 BC12_EN 0 Y Y RW
(BC1.2 detection cannot be enable if
DP_SYNCOUT_CFG = 1, DM_TS_CFG =
1)
BC1.2 data contact timer.
00: Disable DCD timeout function
DCD_
01: Enable 600ms DCD timeout function
6:5 TIMEOUT_ 01 Y Y RW
(default)
SET
10: Enable 900ms DCD timeout function
11: Wait data contact
Enable primary detection high reference
voltage option.
4 VLGC_OPT 0 Y Y RW
0: Disable (default)
1: Enable
Host mode setting in OTG.
00: DPDM floating (default)
3:2 HOST_MODE 00 Y Y RW 01: SDP
10: CDP
11: DCP
1:0 Reserved 00 NA NA NA Reserved

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39
RT9756A
Register Address: 0x0045, Register Name: BC12_FLAG1
WDT REG
Bit Bit Name Default Type Description
RST RST
7:4 Reserved 0000 NA NA NA Reserved
Set 1 and send an ̅̅̅̅̅
INT when BC1.2
detection done.
BC12_DONE_
3 0 N N RC 0: BC1.2 detection not ready
FLAG
1: BC12_DONE_STAT rising detection done
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when data contact
detection fail in DCD_TIMEOUT time.
0: DCD Timeout event of BC1.2 detection
2 DCDT_FLAG 0 N N RC not occurs
1: DCD Timeout event of BC1.2 detection
occurs
(Clear upon read.)
Set 1 and send an INT̅̅̅̅̅ when CDP flow
done.
0: No CDP flow
CDP_DONE_
1 0 N N RC 1: CDP flow done
FLAG
(This bit will be updated when HOST mode
is changed.)
(Clear upon read.)
Set 1 and send an INT̅̅̅̅̅ when CDP primary
detection start.
0: CDP primary detection does not start
CDP_PD_
0 0 N N RC 1: CDP primary detection starts
FLAG
(This bit will be updated when HOST mode
is changed.)
(Clear upon read.)

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40
 RT9756A
Register Address: 0x0046, Register Name: BC12_STAT1
WDT REG
Bit Bit Name Default Type Description
RST RST
000: No VBUS
001: VBUS flow is under going
010: SDP
011: NSTD
7:5 USB_STATUS 000 N Y R
100: DCP
101: CDP
110: Reserved
111: Reserved
4 Reserved 0 NA NA NA Reserved
BC12 status bit
BC12_DONE_
3 0 N N R 0: BC12 NOT complete
STAT
1: BC12 complete
2 Reserved 0 NA NA NA Reserved
CDP flow done
0: No CDP flow
CDP_DONE_
1 0 N N R 1: CDP flow done.
STAT
(This bit will be updated when HOST mode
is changed.)
CDP primary detection start.
0: CDP primary detection does not start
CDP_PD_
0 0 N N R 1: CDP primary detection started
STAT
(This bit will be updated when HOST mode
is changed.)

Register Address: 0x0047, Register Name: BC12_MASK1

WDT REG
Bit Bit Name Default Type Description
RST RST
7:4 Reserved 0000 NA NA NA Reserved
Masks a BC12_DONE event to send an ̅̅̅̅̅
INT.
BC12_DONE_
3 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a DCDT event to send an ̅̅̅̅̅
INT.
2 DCDT_MASK 0 N Y RW 0: Unmask (default)
1: Mask
Masks a CDP_DONE event to send an ̅̅̅̅̅
INT.
CDP_DONE_
1 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Masks a CDP_PD event to send an ̅̅̅̅̅
INT.
CDP_PD_
0 0 N Y RW 0: Unmask (default)
MASK
1: Mask

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41
RT9756A
Register Address: 0x0048, Register Name: DPDM_CTL
WDT REG
Bit Bit Name Default Type Description
RST RST
Enable DP, DM voltage setting function.
SET_DPDM_
7 0 N Y RW 0: Disable DP, DM set function (default)
EN
1: Enable DP, DM set function
DP output voltage selection.
000: Set DP to HZ (default)
001: Set DP to 0 V
010: Set DP to 0.6V
6:4 SET_DP 000 N Y RW
011: Set DP to 1.8V
100: Set DP to 2.8V
101: Set DP to 3.3V
110 to 111: Reserved
DM output voltage selection.
000: Set DM to HZ (default)
001: Set DM to 0 V
010: Set DM to 0.6V
3:1 SET_DM 000 N Y RW
011: Set DM to 1.8V
100: Set DM to 2.8V
101: Set DM to 3.3V
110 to 111: Reserved
0: DPDM protocol can be enable with
VAC_INSERT_
VAC_INSERT_STATUS = 1 (default)
0 PROTOCOL_ 0 N Y RW
1: DPDM protocol can be enable with
DIS
VAC_INSERT_STATUS = 1 or 0

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42
 RT9756A
Register Address: 0x0049, Register Name: INT_FLAG4
WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅ when VBAT is over
Set 1 and send an INT
than VBAT_OVP_ALM threshold.
VBAT_OVP_
7 0 N N RC 0: No VBAT_OVP_ALM Fault
ALM_FLAG
1: VBAT_OVP_ALM Fault has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when IBAT is over
than IBAT_OCP_ALM threshold.
IBAT_OCP_
6 0 N N RC 0: No IBAT_OCP_ALM Fault
ALM_FLAG
1: IBAT_OCP_ALM Fault has occurred
(Clear upon read.)
̅̅̅̅̅ when VBUS is over
Set 1 and send an INT
than VBUS_OVP_ALM threshold.
VBUS_OVP_
5 0 N N RC 0: No VBUS_OVP_ALM Fault
ALM_FLAG
1: VBUS_OVP_ALM Fault has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when IBUS is over
than IBUS_OCP_ALM threshold.
IBUS_OCP_
4 0 N N RC 0: No IBUS_OCP_ALM Fault
ALM_FLAG
1: IBUS_OCP_ALM Fault has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when IBAT current is
lower than IBAT_UCP_ALM threshold.
IBAT_UCP_
3 0 N N RC 0: No IBAT_UCP_ALM rising
ALM_FLAG
1: IBAT_UCP_ALM rising has occurred
(Clear upon read.)
Set 1 and send an ̅̅̅̅̅
INT when IBUS current is
lower than IBUS_UCP_ALM threshold.
IBUS_UCP_
2 0 N N RC 0: No IBUS_UCP_ALM rising
ALM_FLAG
1: IBUS_UCP_ALM rising has occurred
(Clear upon read.)
̅̅̅̅̅ when die
Set 1 and send an INT
temperature is over than TDIE_ALM
TDIE_OTP_ threshold.
1 0 N N RC
ALM_FLAG 0: No TDIE_OTP_ALM Fault
1: TDIE_OTP_ALM Fault has occurred
(Clear upon read.)
̅̅̅̅̅ when VOUT is over
Set 1 and send an INT
than VOUT_OVP threshold.
VOUT_OVP_
0 0 N N RC 0: No VOUT_OVP Fault
FLAG
1: VOUT_OVP Fault has occurred
(Clear upon read.)

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RT9756A
Register Address: 0x004A, Register Name: INT_MASK4
WDT REG
Bit Bit Name Default Type Description
RST RST
Masks a VBAT_OVP_ALM event to send an
VBAT_OVP_ ̅̅̅̅̅.
INT
7 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
Masks a IBAT_OCP_ALM event to send an
IBAT_OCP_ ̅̅̅̅̅
INT.
6 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
Masks a VBUS_OVP_ALM event to send an
VBUS_OVP_ ̅̅̅̅̅
INT.
5 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
Masks a IBUS_OCP_ALM event to send an
IBUS_OCP_ ̅̅̅̅̅
INT.
4 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
Masks a IBAT_UCP_ALM event to send an
IBAT_UCP_ ̅̅̅̅̅
INT.
3 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
Masks a IBUS_UCP_ALM event to send an
IBUS_UCP_ ̅̅̅̅̅
INT.
2 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
Masks a TDIE_OTP_ALM event to send an
TDIE_OTP_ ̅̅̅̅̅.
INT
1 0 N Y RW
ALM_MASK 0: Unmask (default)
1: Mask
̅̅̅̅̅.
Masks a VOUT_OVP event to send an INT
VOUT_OVP_
0 0 N N RW 0: Unmask (default)
MASK
1: Mask

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 RT9756A
Register Address: 0x004B, Register Name: INT_STAT1
WDT REG
Bit Bit Name Default Type Description
RST RST
Set 1 when a VAC_OVP event occurs.
VAC_OVP_ Persists until condition is no longer valid.
7 0 N N R
STAT 0: No VAC_OVP Fault
1: VAC_OVP Fault has occurred.
6:5 Reserved 00 NA NA NA Reserved
Set 1 when a VDR_OVP has occurred.
VDR_OVP_ Persists until condition is no longer valid.
4 0 N N R
STAT 0: No VDR_OVP Fault
1: VDR_OVP Fault has occurred.
Set 1 when VBUS is over than VBUS_OVP
threshold. Persists until condition is no
VBUS_OVP_
3 0 N N R longer valid.
STAT
0: No VBUS_OVP Fault
1: VBUS_OVP Fault has occurred.
Set 1 when IBUS is over than IBUS_OCP
threshold. Persists until condition is no
IBUS_OCP_
2 0 N N R longer valid.
STAT
0: No IBUS_OCP Fault
1: IBUS_OCP Fault has occurred.
1:0 Reserved 00 NA NA NA Reserved

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RT9756A
Register Address: 0x004C, Register Name: INT_STAT2
WDT REG
Bit Bit Name Default Type Description
RST RST
Set 1 when VBAT is over than VBAT_OVP
threshold. Persists until condition is no
VBAT_OVP_
7 0 N N R longer valid.
STAT
0: No VBAT_OVP Fault.
1: VBAT_OVP Fault has occurred.
Set 1 when IBAT is over than IBAT_OCP
threshold. Persists until condition is no
IBAT_OCP_
6 0 N N R longer valid.
STAT
0: No IBAT_OCP Fault.
1: IBAT_OCP Fault has occurred.
Set 1 when VBAT_REG has been active.
VBAT_REG_ Persists until condition is no longer valid.
5 0 N N R
STAT 0: No VBAT_REG.
1: VBAT_REG has occurred.
Set 1 when IBAT_REG has been active.
IBAT_REG_ Persists until condition is no longer valid.
4 0 N N R
STAT 0: No IBAT_REG.
1: IBAT_REG has occurred.
Set 1 when die temperature is over than
TDIE threshold. Persists until condition is no
TDIE_OTP_
3 0 N N R longer valid.
STAT
0: No TDIE_OTP Fault.
1: TDIE_OTP Fault has occurred.
Set 1 when VBUS voltage is lower
VBUS_LOW_ERR threshold. Persists until
VBUS_LOW_
2 0 N N R condition is no longer valid.
ERR_STAT
0: No VBUS_LOW_ERR Fault
1: VBUS_LOW_ERR Fault has occurred.
Set 1 when VBUS voltage is over
VBUS_HIGH_ERR threshold. Persists until
VBUS_HIGH_
1 0 N N R condition is no longer valid.
ERR_STAT
0: No VBUS_HIGH_ERR Fault.
1: VBUS_HIGH_ERR Fault has occurred.
Set 1 when VAC is over than VAC_INSERT
threshold. Persists until condition is no
VAC_INSERT_
0 0 N N R longer valid.
STAT
0: No VAC_INSERT.
1: VAC_INSERT has occurred.

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46
 RT9756A
Register Address: 0x004D, Register Name: INT_STAT3
WDT REG
Bit Bit Name Default Type Description
RST RST
Set 1 when VBUS is over than VBUS_INSERT
threshold. Persists until condition is no
VBUS_
7 0 N N R longer valid.
INSERT_STAT
0: No VBUS_INSERT.
1: VBUS_INSERT has occurred.
Set 1 when VOUT is over than VOUT_INSERT
threshold. Persists until condition is no
VOUT_
6 0 N N R longer valid.
INSERT_STAT
0: No VOUT_INSERT
1: VOUT_INSERT has occurred.
5 Reserved 0 NA NA NA Reserved
Set 1 when VAC is lower than VAC_INSERT
threshold. Persists until condition is no
VAC_UVLO_
4 0 N N R longer valid.
STAT
0: No VAC_UVLO.
1: VAC_UVLO has occurred.
Set 1 when VBUS is lower than VBUS_INSERT
threshold. Persists until condition is no
VBUS_UVLO_
3 0 N N R longer valid.
STAT
0: No VBUS_UVLO.
1: VBUS_UVLO has occurred.
Set 1 when IBUS_UCP_TIMEOUT is
IBUS_UCP_ occurring. Persists until condition is no
2 TIMEOUT_ 0 N N R longer valid.
STAT 0: No IBUS_UCP_TIMEOUT.
1: IBUS_UCP_TIMEOUT is occurring.
Set 1 when the ADC conversion is
completed in 1-shot mode. This bit will
change to '0' when an ADC conversion is
requested in 1-shot mode, and it will change
ADC_DONE_
1 0 N N R back to '1' when the conversion is complete.
STAT
During continuous conversion mode, this bit
will be '0'
0: Conversion not complete.
1: Conversion complete.
0 Reserved 0 NA NA NA Reserved

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RT9756A
Register Address: 0x004E, Register Name: INT_STAT4
WDT REG
Bit Bit Name Default Type Description
RST RST
Set 1 when VBAT is over than VBAT_OVP_ALM
threshold. Persists until condition is no
VBAT_OVP_
7 0 N N R longer valid.
ALM_STAT
0: No VBAT_OVP_ALM Fault
1: VBAT_OVP_ALM Fault has occurred.
Set 1 when IBAT is over than IBAT_OCP_ALM
threshold. Persists until condition is no
IBAT_OCP_
6 0 N N R longer valid.
ALM_STAT
0: No IBAT_OCP_ALM Fault
1: IBAT_OCP_ALM Fault has occurred.
Set 1 when VBUS is over than
VBUS_OVP_ALM threshold. Persists until
VBUS_OVP_
5 0 N N R condition is no longer valid.
ALM_STAT
0: No VBUS_OVP_ALM Fault
1: VBUS_OVP_ALM Fault has occurred.
Set 1 when IBUS is over than IBUS_OCP_ALM
threshold. Persists until condition is no
IBUS_OCP_
4 0 N N R longer valid.
ALM_STAT
0: No IBUS_OCP_ALM Fault
1: IBUS_OCP_ALM Fault has occurred.
Set 1 when IBAT current is lower than
IBAT_UCP_ALM threshold. Persists until
IBAT_UCP_
3 0 N N R condition is no longer valid.
ALM_STAT
0: No IBAT_UCP_ALM rising
1: IBAT_UCP_ALM rising has occurred.
Set 1 when IBUS current is lower than
IBUS_UCP_ALM threshold. Persists until
IBUS_UCP_
2 0 N N R condition is no longer valid.
ALM_STAT
0: No IBUS_UCP_ALM rising
1: IBUS_UCP_ALM rising has occurred.
Set 1 when die temperature is over than
TDIE_OTP_ALM threshold. Persists until
TDIE_OTP_
1 0 N N R condition is no longer valid.
ALM_STAT
0: No TDIE_OTP_ALM Fault
1: TDIE_OTP_ALM Fault has occurred.
Set 1 when VOUT is over than VOUT_OVP
threshold. Persists until condition is no
VOUT_OVP_
0 0 N N R longer valid.
STAT
0: No VOUT_OVP Fault
1: VOUT_OVP Fault has occurred.

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48
 RT9756A
Register Address: 0x004F, Register Name: VBAT_OVP_ALM
WDT REG
Bit Bit Name Default Type Description
RST RST
Disable VBAT_OVP_ALM.
VBAT_OVP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
6:5 Reserved 00 NA NA NA Reserved
Battery overvoltage alarm threshold.
VBAT_OVP_ VBAT_OVP_ALM
4:0 00000 N Y RW
ALM = 4.2V + VBAT_OVP_ALM[4:0] x 25mV
Default: 4.2V (b00000)

Register Address: 0x0050, Register Name: IBAT_OCP_ALM

WDT REG
Bit Bit Name Default Type Description
RST RST
Disable IBAT_OCP_ALM.
IBAT_OCP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
6 Reserved 0 NA NA NA Reserved
Battery overcurrent alarm threshold.
IBAT_OCP_ IBAT_OCP_ALM
5:0 110010 N Y RW
ALM = 2A + IBAT_OCP_ALM[5:0] Х 100mA
Default: 7A (b110010)

Register Address: 0x0051, Register Name: VBUS_OVP_ALM

WDT REG
Bit Bit Name Default Type Description
RST RST
Disable VBUS_OVP_ALM.
VBUS_OVP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
6 Reserved 0 NA NA NA Reserved
VBUS overvoltage alarm threshold.
The setting is determined by difference
modes.
Device in DIV2 mode: VBUS_OVP = 6V +
VBUS_OVP_
5:0 011100 N Y RW VBUS_OVP[5:0] x 100mV, Default: 8.8V
ALM
(b011100)
Device in BYPASS mode: VBUS_OVP = 3V +
VBUS_OVP[5:0] x 50mV, Default: 4.4V
(b011100)

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49
RT9756A
Register Address: 0x0052, Register Name: IBUS_OCP_ALM
WDT REG
Bit Bit Name Default Type Description
RST RST
Disable IBUS_OCP_ALM.
IBUS_OCP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
6 Reserved 0 NA NA NA Reserved
IBUS overcurrent alarm threshold.
IBUS_OCP_ The setting is determined by IBUS_OCP_ALM
5:0 011100 N Y RW
ALM = IBUS_OCP_ALM[5:0] x 100mA.
Default: 2.8A (b011100)

Register Address: 0x0053, Register Name: IBAT_UCP_ALM

WDT REG
Bit Bit Name Default Type Description
RST RST
Disable IBAT_UCP_ALM.
IBAT_UCP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
6 Reserved 0 NA NA NA Reserved
IBAT undercurrent alarm threshold.
IBAT_UCP_ IBAT_UCP_ALM = IBAT_UCP_ALM [5:0] x
5:0 101000 N Y RW
ALM 50mA
Default: 2A (b101000)

Register Address: 0x0054, Register Name: IBUS_UCP_ALM

WDT REG
Bit Bit Name Default Type Description
RST RST
Disable IBUS_UCP_ALM.
IBUS_UCP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
IBUS undercurrent alarm threshold.
IBUS_UCP_ IBUS_UCP_ALM = IBUS_UCP_ALM [6:0] x
6:0 0101000 N Y RW
ALM 25mA
Default: 1A (b0101000)

Register Address: 0x0055, Register Name: TDIE_OTP_ALM

WDT REG
Bit Bit Name Default Type Description
RST RST
Disable TDIE_OTP_ALM.
TDIE_OTP_
7 0 N Y RW 0: Enable (default)
ALM_DIS
1: Disable
TDIE alarm threshold.
TDIE_OTP_
6:0 1100100 N Y RW TDIE_ALM = 25°C + TDIE_ALM[6:0] x 1°C
ALM
Default: 125°C (b1100100)

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50
 RT9756A
Register Address: 0x0056, Register Name: VOUT_ADC1
WDT REG
Bit Bit Name Default Type Description
RST RST
Disable VOUT_ADC.
VOUT_ADC_
7 0 N Y RW 0: Enable conversion (default)
DIS
1: Disable conversion
6 Reserved 0 NA NA NA Reserved
VOUT ADC high byte
5:0 VOUT_ADC1 000000 N N R HSB<5:0>: 8192mV, 4096mV, 2048mV,
1024mV, 512mV, 256mV

Register Address: 0x0057, Register Name: VOUT_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
VOUT ADC low byte
7:0 VOUT_ADC0 00000000 N N R LSB<7:0>: 128mV, 64mV, 32mV, 16mV,
8mV, 4mV, 2mV, 1mV

Register Address: 0x0058, Register Name: DP_ADC1

WDT REG
Bit Bit Name Default Type Description
RST RST
Disable DP ADC.
7 DP_ADC_DIS 1 N Y RW 0: Enable
1: Disable (default)
6 Reserved 0 NA NA NA Reserved
DP ADC high byte
5:0 DP_ADC1 000000 N Y R HSB<5:0>: 8192mV, 4096mV, 2048mV,
1024mV, 512mV, 256mV

Register Address: 0x0059, Register Name: DP_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
DP ADC
7:0 DP_ADC0 00000000 N Y R LSB<7:0>: 128mV, 64mV, 32mV, 16mV,
8mV, 4mV, 2mV, 1mV

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51
RT9756A
Register Address: 0x005A, Register Name: DM_ADC1
WDT REG
Bit Bit Name Default Type Description
RST RST
Disable DM ADC.
7 DM_ADC_DIS 1 N Y RW 0: Enable
1: Disable (default)
6 Reserved 0 NA NA NA Reserved
DM ADC high byte
5:0 DM_ADC1 000000 N Y R HSB<5:0>: 8192mV, 4096mV, 2048mV,
1024mV, 512mV, 256mV

Register Address: 0x005B, Register Name: DM_ADC0

WDT REG
Bit Bit Name Default Type Description
RST RST
DM ADC low byte
7:0 DM_ADC0 00000000 N Y R LSB<7:0>: 128mV, 64mV, 32mV, 16mV,
8mV, 4mV, 2mV, 1mV

Register Address: 0x005C, Register Name: CON_STAT

WDT REG
Bit Bit Name Default Type Description
RST RST
Set 1 and send an ̅̅̅̅̅
INT when the converter
start switching and IBUS_UCP_TIMEOUT
CON_ timer start. Only one ̅̅̅̅̅
INT is sent when
7 SWITCHING_ 0 N N R switching starts. Persists until condition is
STAT no longer valid.
0: No CON_SWITCHING
1: SWITCHING is occurring.
Masks a CON_SWITCHING event to send
CON_
an ̅̅̅̅̅
INT.
6 SWITCHING_ 0 N N RW
0: Unmask (default)
MASK
1: Mask
Indicate converter operation status.
00: Standby mode
5:4 IC_STAT 00 N N R 01: Bypass mode
10: Forward DIV2 mode
11: Reserved
3:0 Reserved 0000 NA NA NA Reserved

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52
 RT9756A
Register Address: 0x005D, Register Name: IBUS_UCP_TIMEOUT
WDT REG
Bit Bit Name Default Type Description
RST RST
Adjustable timeout for IBUS to rise to
IBUS_UCP_RISE threshold.
000: Timeout disabled
001: 12.5ms
IBUS_UCP_ 010: 25ms
7:5 111 N Y RW
TIMEOUT 011: 50ms
100: 100ms
101: 400ms
110: 1.5s
111: 100s (default)
4 Reserved 0 NA NA NA Reserved
IBUS_UCP_ This bit sets the deglitch time for
FALL_ VBUS_UCP_FALL.
3 0 N Y RW
DEGLITCH_ 0: 22s (default)
SET 1: 5ms
2:0 Reserved 000 NA NA NA Reserved

Register Address: 0x005E, Register Name: other1

WDT REG
Bit Bit Name Default Type Description
RST RST
EN_I2C_
0: Disable
7 LEVEL_ 1 NA NA RW
1: Enable (default)
DETECTION
0: 1.8V
6 I2C_level 1 NA NA RW
1: 1.2V (default)
5:4 Reserved 00 NA NA NA Reserved
Enable VOUT overvoltage protection.
VOUT_OVP_
3 1 N Y RW 0: Disable
EN
1: Enable (default)
2 Reserved 1 NA NA NA Reserved
This bit selects the external battery current
sense resistor value.
00: 1m
1:0 IBAT_RSEN 01 N N RW
01: 2m(default)
10: 5m
11: 10m

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53
RT9756A
Register Address: 0x005F, Register Name: other2
WDT REG
Bit Bit Name Default Type Description
RST RST
DP_SYNCOUT pin configuration.
0: DP_SYNCOUT pin is configured as DP
pin. (default)
DP_SYNCOUT
7 0 N N RW 1: DP_SYNCOUT pin is configured as
_CFG
SYNCOUT pin.
(All DP pin functions are invalid when
DP_SYNCOUT = 1.)
DM_TS pin configuration.
0: DM_TS pin is configured as DM pin.
(default)
6 DM_TS_CFG 0 N N RW 1: DM_TS pin is configured as TS pin.
(All TS functions are invalid when DM_TS =
0. All DM pin functions are invalid when
DM_TS = 1.)
BATN/SRP_SYNCIN pin configuration
0: BATN/SRP_SYNCIN pin is configured as
BATN/SRP pin. (default)
BATN_SRP_ 1: BATN/SRP_SYNCIN pin is configured as
5 0 N N RW
SYNCIN_CFG SYNCIN pin.
(All sensing and protection of VBAT and
IBAT are invalid when BATN/SRP_SYNCIN
= 1.)
4 Reserved 0 NA NA NA Reserved
Set 1 and send an ̅̅̅̅̅
INT when TS ADC is
lower than TS_OTP threshold.
TS_OTP_
3 0 N N RC 0: No TS_OTP
FLAG
1: TS_OTP has occurred.
(Clear upon read.)
Masks a TS_OTP event to send an ̅̅̅̅̅
INT
TS_OTP_
2 0 N Y RW 0: Unmask (default)
MASK
1: Mask
Set 1 when TS ADC is lower than TS_OTP
threshold. Persists until condition is no
TS_OTP_
1 0 N N R longer valid.
STAT
0: No TS_OTP
1: TS_OTP has occurred.
Enable TS_OTP.
0 TS_OTP_EN 0 N Y RW 0: Disable (default)
1: Enable

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54
 RT9756A
Register Address: 0x0060, Register Name: TS_OTP
WDT REG
Bit Bit Name Default Type Description
RST RST
TS_OTP Threshold
7:0 TS_OTP 00000000 N Y RW TS_OTP = TS_OTP[7:0] x 7mV
Default: 0V (b00000000)

Register Address: 0x0061, Register Name: DPDM_OV_ALM

WDT REG
Bit Bit Name Default Type Description
RST RST
̅̅̅̅̅ when DP_ADC is
Set 1 and send an INT
over than 4.5V.
DP_OV_ALM_
7 0 N N RC 0: No DP_OV_ALM Fault
FLAG
1: DP_OV_ALM Fault has occurred.
(Clear upon read.)
̅̅̅̅̅ when DM_ADC is
Set 1 and send an INT
over than 4.5V.
DM_OV_ALM_
6 0 N N RC 0: No DM_OV_ALM Fault
FLAG
1: DM_OV_ALM Fault has occurred.
(Clear upon read.)
DP_OV_ALM status when DP_ADC is over
than 4.5V. Persists until condition is no
DP_OV_ALM_
5 0 N N R longer valid.
STAT
0: No DP_OV_ALM fault
1: DP_OV_ALM fault has occurred.
DM_OV_ALM status when DM_ADC is over
than 4.5V. Persists until condition is no
DM_OV_ALM_
4 0 N N R longer valid.
STAT
0: No DM_OV_ALM fault
1: DM_OV_ALM fault has occurred.
Masks a DP_OV_ALM event to send an
DP_OV_ALM_ ̅̅̅̅̅
INT.
3 0 N Y RW
MASK 0: Unmask (default)
1: Mask
Masks a DM_OV_ALM event to send an
DM_OV_ALM_ ̅̅̅̅̅.
INT
2 0 N Y RW
MASK 0: Unmask (default)
1: Mask
̅̅̅̅̅.
Masks a IBUS_OCP_H to send an INT
IBUS_OCP_H
1 0 N Y RW 0: Unmask (default)
_MASK
1: Mask
̅̅̅̅̅, when
Set 1 and send an INT
IBUS_OCP_H trigger.
IBUS_OCP_H
0 0 N N RC 0: No IBUS_OCP_H fault.
_FLAG
1: IBUS_OCP_H Fault has occurred.
(Clear upon read)

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RT9756A
Register Address: 0x0062, Register Name: REVISION
WDT REG
Bit Bit Name Default Type Description
RST RST
7:2 Reserved 000000 NA NA NA Reserved
1:0 PRODUCT_ID 01 N N RO 01: RT9756A

Register Address: 0x0063, Register Name: other3

WDT REG
Bit Bit Name Default Type Description
RST RST
7:3 Reserved 00000 NA NA NA Reserved
Set 1 and send an INT when power-on
ready.
CHIP_RESET_
2 0 N N RC 0: No power-on ready fault.
FLAG
1: Power-on ready has occurred.
(Clear upon read.)
Set 1 and send an INT when trigger
VDDA_UVLO.
VDDA_UVLO_
1 0 N N RC 0: No VDDA_UVLO fault.
FLAG
1: VDDA_UVLO fault has occurred.
(Clear upon read.)
Masks a VDDA_UVLO to send an INT.
VDDA_UVLO_
0 0 N Y RW 0: Unmask (default)
MASK
1: Mask

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 RT9756A
Register Address: 0x0066, Register Name: DPDM_SEL1
WDT REG
Bit Bit Name Default Type Description
RST RST
DP discharge level selection when
SET_DPDM_EN = 1.
DP_DISCHG_ 00: Bypass
7:6 11 N Y RW
SEL 01: 20k
10: 45A
11: 60A (default)
DM discharge level selection when
SET_DPDM_EN = 1.
DM_DISCHG_ 00: Bypass
5:4 11 N Y RW
SEL 01: 20k
10: 45A
11: 60A (default)
DP pull-up resistor level selection when
SET_DPDM_EN = 1.
DP_PULL_ 00: 1.2k
3:2 11 N Y RW
SEL 01: 2.7k
10: 15k
11: Bypass (default)
DM pull-up resistor level selection when
SET_DPDM_EN = 1.
DM_PULL_ 00: 1.2k
1:0 11 N Y RW
SEL 01: 2.7k
10: 15k
11: Bypass (default)

Register Address: 0x006D, Register Name: DPDM_CON5

WDT REG
Bit Bit Name Default Type Description
RST RST
DP discharge current or resistor enable
DP_DISCHG_ control when SET_DPDM_EN = 1.
7 0 N Y RW
EN 0: Disable (default)
1: Enable
6:4 Reserved 110 NA NA NA Reserved
DM discharge current or resistor enable
DM_DISCHG_ control when SET_DPDM_EN = 1.
3 0 N Y RW
EN 0: Disable (default)
1: Enable
2:0 Reserved 110 NA NA NA Reserved

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RT9756A
Register Address: 0x006E, Register Name: DPDM_CON6
WDT REG
Bit Bit Name Default Type Description
RST RST
DP pull-up current source enable control
when SET_DPDM_EN = 1.
7 DP_PULL_IEN 0 N Y RW
0: Disable (default)
1: Enable (10A)
DP pull-up resistor enable control when
DP_PULL_RE SET_DPDM_EN = 1.
6 0 N Y RW
N 0: Disable (default)
1: Enable
5:4 Reserved 11 NA NA NA Reserved
DM pull-up current source enable control
when SET_DPDM_EN = 1.
3 DM_PULL_IEN 0 N Y RW
0: Disable (default)
1: Enable (10A)
DM pull-up resistor enable control when
DM_PULL_RE SET_DPDM_EN = 1.
2 0 N Y RW
N 0: Disable (default)
1: Enable
1:0 Reserved 110 NA NA NA Reserved

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58
 RT9756A
Application Information

Richtek’s component specification does not include the following information in the Application Information section.
Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their
own designs and reserve suitable design margin to ensure the functional suitability of their components and systems.

Operation Principle If the power dissipation of topology is ignored, the

output power can be expressed as equation 4:
The cap divider topology relies on a smart wall adapter
to control the voltage and current of input in order to VBAT x IBAT = VBUS x IBUS --- (4)

charge. Based on the cap divider topology, the 4 If the equation 3 is substituted into equation 4, the IBAT
MOSFETs (Q1 to Q4) are used to charge and discharge can be expressed as equation 5:
flying capacitor (CFLY) alternately. The simplified circuit IBAT = 2 x IBUS --- (5)
of cap divider is shown in Figure 1(A). According to the equations above, the battery voltage is
In period 1: When Q1 and Q3 are turned on and Q2 and half of the input voltage and the current flow into the
Q4 are turned off, the CFLY and BAT are in series with battery is twice the input current in cap divider topology.
VBUS. The BUS current is supplied to COUT and BAT For the efficiency and output ripple improvement in
directly. During this period, the voltage of CFLY can be application, the dual phase cap divider topology with
expressed as equation 1: phase shift 180-degree between phases are built in the
VCFLY = VBUS - VBAT ---- (1) RT9756A.

In period 2: When Q1 and Q3 are turned off and Q2 and The RT9756A also has Bypass mode for direct charging.
Q4 are turned on, the CFLY and BAT are in parallel. The To use Bypass mode, set OPERATION_MODE
current of BAT is only supplied by CFLY. During this (0x0000[5]) = 0 before start charging. In the Bypass
period, the voltage of CFLY can be expressed as mode, Q1, Q2 and Q4 turn on continuously as shown in
equation 2: Figure 1(B).

VCFLY = VBAT ---- (2)

If the equation 2 is substituted into equation 1, the
equation 1 can be expressed as equation 3:
VBAT = VBUS / 2 ---- (3)

IBUS CFLY IBAT

VBUS
Q1 + -
VBUS VCFLY VBAT

Q2
Period 1
CFLY
Q3 COUT VBAT
IBUS IBAT

+
Q4 VBUS CFLY V VBAT
- CFLY

Period 2
A. DIV2 mode

IBUS IBAT

+
VBUS CFLY V VBAT
- CFLY

B. Bypass mode

Figure 1. Simplified Circuit of Cap Divider

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59
RT9756A
Charge System Introduction charger and smart cap divider charger to achieve high
current charging period. These devices can
The RT9756A is a smart cap divider charger used in
communicate with each other through I2C serial
slave charger application. The RT9756A generates high
interface.
output current with cap divider topology. Before
The charge profile of high capacity battery using
enabling the RT9756A, the host sets up all of protection
switching charger and cap divider charger is shown in
and alarm functions and disables main charger in power
Figure 3. In order to achieve the charge profile, the
solution. The host must monitor the alarms that set up
switching charger is required to dominate pre-charge,
in RT9756A during high current charging period and
fast charge when battery voltage is lower than system
communicate with the smart wall adapter to control the
startup voltage, constant voltage and termination
charging current flow into the battery.
periods, respectively. The cap divider charger is used to
Figure 2 is the simplified charge system block. In this
achieve fast charge period. To shorten the constant
charge system, RT9756A is used to detect USB BC1.2
voltage period, the cap divider charger is controlled to
of adapter and the PD controller is used to communicate
reduce the charge current by ramp step when battery
with adapter by PD protocol. Once the smart wall
voltage triggers the VBAT_OVP_ALM.
adapter is detected, the AP will control the switching

Wireless TX/RX

CFH1 CFL1
OVPGATE VAC

Phase 1 VOUT
VBUS

OVP IC D+
RT9756A
D- GND

2
I C
Phase 2

CFH2 CFL2

VBUS
LX System

SYS

Switching Charger
2 e.g., RT9471 BAT
Smart Wall Adapter Type C I C
Connector
GND
VBUS
Type C VBUS
Connector
D+ D+

D- Battery
D-
CC1
CC1 PD Controller
CC2 e.g., RT1715
CC2
CC1

CC2
2
I C BUS

AP

Figure 2. Simplified Charge System

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60
 RT9756A

IBAT (A) VBAT (V)

5
VBAT_OVP_ALM

3
System Startup Level
IBAT_UCP_ALM
2

Pre-Charge Level
1

Pre-charge current
End of charge current
Time
Fast Charge by Constant Voltage by
Fast Charge by Cap divider charger Constant Voltage by switching charger
Switching charger Cap divider charger
Pre-charge by
Switching charger

Figure 3. Charge Profile using Switching Charger and Cap Divider Charger

While the RT9756A is charging, the host needs to communicate with smart wall adapter to control the charging
current provided by the RT9756A. The communication flow between smart wall adapter and charge system is shown
in Figure 4. In order to prevent abnormal events when charging, the RT9756A is established with many adjustable
protections and alarm functions. All alarms and protections are activated in specific operation condition that are
shown in Table 2 and Table 4, respectively.

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RT9756A
Smart Wall PD
Adapter System with PD, Switching charger and RT9756A
Controller

No Switching Charger
Adapter Plug-in Run BC1.2 Battery > 2V operate in trickle
charge mode

Yes

No Switching Charger
Battery > 3V operate in Pre-
charge mode

Yes

No Switching Charger
Battery > 3.45V operate in Fast-
charge mode

Yes

No
System wake up Wake up system

Yes

Set charger initial setting

Run PD
and enable RT9756A ADC
protocol
to monitor Battery

Smart Yes Disable

Adapter Switching Charger

No

Adjustable Yes Start HV switching

DCP charge process

No

Start 5V switching
charge process

Set V BUS limit to 2.04 x VBAT

Set I BUS limit to desired
value by ramp step

Trigger RT9756A No
Enable RT9756A to charge
abnormal event

Yes

calculate the voltage drop

of charging path

Readjust charge condition

depend on abnormal event Monitor VBAT & IBAT

Increase BUS voltage or

BUS current to charging

VBAT > No IBAT < No

VBAT_OVP_ALM IBAT_UCP_ALM

Yes Yes
Decrease BUS voltage or
BUS current to control
charge current

Disable RT9756A and than

enable switching charger to
continues CV charging

Figure 4. System Control Flow Chart

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62
 RT9756A
Device Power-Up function are still active before sensing circuits are turned
off. When the device disables sensing circuit, all of
The device is powered by VDDA and the VDDA voltage
protections and INSERT function are disabled except
can be measured through the REGN pin. When VDDA
VAC_INSERT, VAC_OVP and VBUS_OVP.
voltage is higher than VDDA_UVLO threshold, the device
will start working. The VDDA voltage can be powered 8-Channel Analog to Digital Converter
by VAC or VBUS or VOUT and that is dominated by the
The RT9756A integrates 8-Cannel ADC conversion for
higher voltage level.
users to monitor input and output status of the device.
Once the RT9756A is powered, the device will activate
The ADC function is allowed to operate if VDDA >
the address detection mechanism to assign the slave
VDDA_UVLO_TH. Once VDDA exceeds VDDA_UVLO_TH
address of device. The slave address of device is
rising threshold, the RT9756A will reset ADC_EN to
determined by the state of the SRN_ADDR pin after
disable if VDDA < VDDA_UVLO_TH. The ADC function can
power-on. Depending on whether the SRN_ADDR pin
operate in continuous mode or 1-shot mode. Users can
is short to ground or floating, the slave address is 0x6F
enable ADC function and select conversion mode via
or 0x6E. After address detection is finished, the host
I2C serial interface control (0x0011). In continuous
can communicate with the RT9756A by I2C serial
mode, the ADC function will convert all ADC channel
interface. Furthermore, the reaction time during VDDA >
and report ADC data to related registers continuously.
VDDA_UVLO to I2C release (tVDDA_START) is around
In 1-shot mode, ADC function will reset ADC_EN bit to
400sec.
0 after converting each ADC channel. Each ADC
The RT9756A includes a watchdog timer that is enabled channel can be enabled or disabled. The device uses
by default. If the device is not read or written before ADC conversion data to detect all alarm function,
watchdog timer timeout, the ADC_EN and CHG_EN will TS_OTP, VBUS_LOW_ERR and VBUS_HIGH_ERR.
be set to default value. The register table shows which Due to this feature, the ADC function will be forced to
registers are reset by watchdog. Moreover, the convert each ADC channel with continuous mode and
watchdog timeout flag and ̅̅̅̅̅
INT pulse will be triggered ADC cannot be controlled via register after charging.
to inform the host. Figure 6 is ADC function operation flow chart; Users can
If the VOUT is not higher than VOUT_INSERT rising follow the flow chart to control ADC function. While
threshold, the charge cannot be enabled. Once VOUT reading the data of registers, high byte has to be read
exceeds VOUT_INSERT rising threshold, the minimum firstly, and then the following is low byte. Moreover, high
allowable VOUT for enable charge is VOUT_INSERT falling byte and low byte have to be read with I2C multi-byte
threshold. Before charge enable, the RT9756A can reading method in one transmission, which is
report ADC information while the ADC is enabled. After terminated with one STOP condition.
charge enable, the RT9756A reports ADC information
no matter whether the ADC is enabled or not.
In order to reduce quiescent current, most of sensing
circuit inside the RT9756A will be turned off after
address detection is finished and ADC_EN and
CHG_EN are disabled for 500ms. In other words, part
of protections and insert function are still activated
before disabling device sensing circuit. Figure 5 shows
the device power on flow with protections and insert
function activation list in each state. The VAC_OVP,
VBAT_OVP, VOUT_OVP, VBUS_OVP, TDIE_OTP,
TS_OTP, VBUS_HIGH_ERR, VBUS_ LOW_ERR,
VOUT_INSERT, VBUS_INSERT and VAC_INSERT

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RT9756A
Function Activation List :
VAC_OVP VBUS_HIGH_ERR
VBAT_OVP VBUS_LOW_ERR
VOUT_OVP VOUT_INSERT
VBUS_OVP VBUS_INSERT
TDIE_OTP VAC_INSERT
TS_OTP

No

Device address detection Yes Deglitch ADC_EN &

ADC_EN = 0 &
2 CHG_EN = 0
and I C release CHG_EN = 0
for 500msec

No Yes

VDDA > VDDA_UVLO Function Activation List :

Disable Most of Sensing Circuit
VAC_INSERT
for Power Save
VAC_OVP
VBUS_OVP

ADC_EN = 0 & Yes

CHG_EN = 0

No
Function Activation List :
Enable Sensing Circuit Refer to Table 2.
for Protections Active VOUT_INSERT
VBUS_INSERT
VAC_INSERT

Normal Operation

Yes ADC_EN = 0 & No

CHG_EN = 0

Figure 5. Device Power-On Flow with Protections and Insert Function Activation List

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 RT9756A

RT9756A
CHG_EN = 0 &
ADC_EN = 0

N
ADC_EN = 1
or
CHG_EN = 1?

Y
VDDA < VDDA_UVLO? Reset CHG_EN = 0
(Hysteresis = 250mV) & ADC_EN = 0

reset
ADC_DONE_STATUS = 0

VBUS_ADC_DIS = 0 Y
converting & reporting
or
VBUS_ADC
CHG_EN = 1?

Converting other channel

TDIE_ADC_DIS = 0 Y
converting & reporting
or TDIE_ADC
CHG_EN = 1?

N
Y

ADC_EN = 1 Y ADC_RATE = 0 N
Enable Enable Disable
or or Reset ADC_EN = 0
ADC_DONE_STATUS = 1 ADC_DONE_FLAG = 1 ADC_EN = 0
CHG_EN = 1? CHG_EN = 1?

Figure 6. ADC Function Operation Flow Chart

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RT9756A
Protection Feature

The RT9756A integrates 14 protections to protect device charging in unexpected condition. All protection activations
are based on CHG_EN and ADC_EN bit except VAC_OVP and VBUS_OVP. Users need to set CHG_EN or ADC_EN
bit to 1 to enable related protection. Each protection functions can be disabled by enable bits. Table 2 shows the
enable condition and protect method for each protection.

Table 2. Protection Trigger Condition and Behavior

Threshold
Protection Refer to Reset
Enable Condition Deglitch Time Protection Method
Function Electrical Method
Spec.
VAC lower
Turn off OVPGATE
VAC > VAC_INSERT & VAC  12V than
VAC_OVP NA and
OVPMOS_DIS = 0 (Programmable) hysteresis
Reset CHG_EN = 0
500mV
VBUS  8.9V in
DIV2 mode
VBUS < OVP
VBUS_OVP VDDA > VDDA_UVLO VBUS  4.5V in NA Reset CHG_EN = 0
level
DIV2 mode
(Programmable)
CHG_EN = 1 or VBAT  4.35V VBAT < OVP
VBAT_OVP 3s Reset CHG_EN = 0
ADC_EN = 1 (Programmable) level
CHG_EN = 1 or VOUT < OVP
VOUT_OVP VOUT  4.9V 3s Reset CHG_EN = 0
ADC_EN =1 level
IBUS  3A
IBUS_OCP CHG_EN = 1 50s Reset CHG_EN = 0 NA
(Programmable)
IBUS_OCP_H CHG_EN = 1 IBUS  6.8A NA Reset CHG_EN = 0 NA
IBUS  150mA 22s
IBUS_UCP CHG_EN = 1 Reset CHG_EN = 0 NA
(Programmable) (Programmable)
IBAT  7.2A
IBAT_OCP CHG_EN = 1 50s Reset CHG_EN = 0 NA
(Programmable)
CHG_EN = 1 or TDIE < OTP
TDIE_OTP TDIE  150°C 3s Reset CHG_EN = 0
ADC_EN = 1 level
(VAC - VBUS) 8s
VDR_OVP CHG_EN = 1 Reset CHG_EN = 0 NA
 300mV (Programmable)
CFLY_DIAG CHG_EN = 1 RCFLY  16 NA Reset CHG_EN = 0 NA
(CHG_EN = 1 or
TS pin >
ADC_EN =1) TS pin  0V
TS_OTP NA Reset CHG_EN = 0 TS_OTP
& DM_ADC_DIS = 0 (Programmable)
level
& DM_TS_CFG = 1
CHG_EN = 1
(before switching) or
ADC_EN = 1 VBUS / VOUT  VBUS / VOUT
VBUS_LOW_ERR NA Reset CHG_EN = 0
(VBUS_ADC and 2.04 > 2.04
VOUT_ADC must
be enabled)

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 RT9756A
Threshold
Protection Refer to Reset
Enable Condition Deglitch Time Protection Method
Function Electrical Method
Spec.
CHG_EN = 1
(before switching) or
ADC_EN = 1 VBUS / VOUT  VBUS / VOUT
VBUS_HIGH_ERR NA Reset CHG_EN = 0
(VBUS_ADC and 2.4 < 2.4
VOUT_ADC must
be enabled)

 VAC Pin Overvoltage Protection (VAC_OVP)  VBUS Charge Voltage Protection

The RT9756A integrates VAC_OVP function to (VBUS_HIGH_ERR and VBUS_LOW_ERR)
monitor adaptor voltage by VAC pin and control The device integrates VBUS_HIGH_ERR and
external MOSFET by OVPGATE pin. The VAC_OVP VBUS_LOW_ERR to prevent users from adjusting
function is powered by VAC pin, it will be enabled if wrong VBUS for charge. In no charge condition, if
VAC voltage is higher than VAC_INSERT and VBUS is higher than VBUS_HIGH_ERR threshold or
OVPMOS_DIS is set to 0. The device will provide a VBUS lower than VBUS_LOW_ERR threshold, the device
VOVPGATE voltage to turn on external MOSFET if VAC will force CHG_EN bit to disable. Both of
is higher than VAC_INSERT for a tVAC_INSERT_DEG time. VBUS_HIGH_ERR and VBUS_LOW_ERR will be
If the VAC voltage is higher than VAC_OVP threshold, disabled after the device successfully starts to charge.
the device will start to turn off external MOSFET after The device diagnoses VBUS_HIGH_ERR and
a tVAC_OVP_RE time and it will turn off the external VBUS_LOW_ERR from VBUS ADC and VOUT ADC
MOSFET within tVAC_OVP_OFF time. Figure 7 shows values. For using these two functions, enabling VBUS
the timing of VAC_OVP function. Users should make ADC and VOUT ADC conversion is necessary.
sure the adaptor voltage will not be higher than
 Input and Output Overvoltage Protection
absolute maximum rating of VAC pin and external
(VBUS_OVP, VOUT_OVP, VBAT_OVP)
MOSFET (prevented by external TVS, etc.).
The device has VBUS_OVP, VBAT_OVP and
V
VOUT_OVP functions to detect input and output
charge voltage condition. If input and output charge
voltage is higher than protection threshold, the device
will turn off charger and reset CHG_EN to disable.
OVPGATE
The VBUS_OVP function monitors VBUS voltage by
VAC_OVP_rising
VAC_OVP_falling
VBUS pin. The VOUT_OVP function monitors VOUT
VAC voltage by VOUT pin. In high charging current
application, the system might have large voltage drop
VAC_INSERT_rising
VAC_INSERT_falling between the device and battery pack. For the
t application, the device integrates VBAT_OVP to
tVAC_OVP_RE tVAC_INSERT_DEG
tVAC_INSERT_DEG tVAC_OVP_OFF monitor differential voltage between BATP and
BATN/SRP_SYNCIN. Users should connect a 100
Figure 7. OVPGATE Operation Timing resistorwith BATP to battery pack to achieve remote
sense for the device. Users can adjust the protection
level of VBUS_OVP and VBAT_OVP.

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RT9756A
 Input and Output Overcurrent Protection  Input Undercurrent Protection (IBUS_UCP)
(IBUS_OCP, IBUS_OCP_H, IBAT_OCP) The device integrates IBUS_UCP function to prevent
The IBUS_OCP and IBUS_OCP_H functions monitor reverse current from battery to VBUS. The
input current via Q0. If CHG_EN bit is enabled, the IBUS_UCP detects input current by Q0. Figure 8
Q0 will turn on and IBUS_OCP will start detecting shows the flow chart of IBUS_UCP, the device
input current. If the IBUS is larger than IBUS_OCP enables IBUS_UCP_RISE threshold and counting
threshold, the device stops charging and resets timer after start charging. Once IBUS is larger than
CHG_EN bit to disable. If the IBUS rises over IBUS_UCP_RISE threshold, the device will stop
IBUS_OCP_H level fast, the device stops charging counting timer and enable IBUS_UCP_FALL
immediately after IBUS_OCP_H reaction Time and threshold. If the IBUS is smaller than IBUS_UCP_RISE
reset CHG_EN bit to disable. The IBAT_OCP and the timer is already longer than
function detects battery current via IBUS_UCP_TIMEOUT, the device will enable
BATN/SRP_SYNCIN and SRN_ADDR pin. Users IBUS_UCP_FALL threshold. After the device
should connect a 2m resistor in series with battery enables IBUS_UCP_FALL threshold, if the IBUS is
pack. The SRN_ADDR and BATN/SRP_SYNCIN smaller than IBUS_UCP_FALL threshold, the device will
should connect on the resistor in parallel. The internal stop charging and reset CHG_EN to disable. Figure
protector will convert the differential voltage of 9 shows IBUS_UCP behavior in different application.
BATN/SRP_SYNCIN and SRN_ADDR to current
value. The ratio between the differential voltage and
current value can be determined by register setting.
If the current value is larger than IBAT_OCP threshold,
the device will stop charging and reset CHG_EN to
disable. Users can adjust the IBUS_OCP and
IBAT_OCP threshold via register setting.

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 RT9756A

Ready to Charge

enable
N
IBUS_UCP_FALL_FLAG = 1 N
deglitch IBUS_UCP_FALL =
Is CHG_EN = 1?
1 to 22μs or 5ms? (depend on
0x005D bit3)

Y
Y
Y

Stop charging and reset

CHG_EN = 0
N
N Is CHG_EN = 1 ?

IBUS < I BUS_UCP_FALL ?

Y
N N
is IBUS_UCP_TIMEOUT
is I BUS > I BUS_UCP_RISE?
Enable?
N

is CHG_EN=1

Y Y

enable
IBUS_UCP_RISE_FLAG = 1
N
is IBUS_UCP_TIMEOUT
triggered ?

enable
IBUS_UCP_TIMEOUT_FLAG
=1

Figure 8. Flow Chart of IBUS_UCP Function

1 2 3 4 1 3
1 2 3 4 5

CHG_EN CHG_EN
CHG_EN

IBUS_UCP_RISE IBUS_UCP_RISE
IBUS_UCP_RISE
IBUS IBUS
IBUS_UCP_FALL IBUS_UCP_FALL IBUS
IBUS_UCP_FALL

IBUS_UCP_ IBUS_UCP_ IBUS_UCP_

Rising_IRQ Rising_IRQ Rising_IRQ

IBUS_UCP_ IBUS_UCP_ IBUS_UCP_

Falling_IRQ Falling_IRQ Falling_IRQ

Time out IRQ Time out IRQ Time out IRQ

Time Out Time Out Time Out

Figure 9. IBUS_UCP Behavior in Different Application

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RT9756A
 Device Thermal Shutdown (TDIE_OTP) Pull-Up
The device integrates TDIE_OTP to prevent system
charging in over-temperature condition. The
DM_TS
TDIE_OTP function monitors the die temperature of
the device. If the die temperature is higher than NTC
TDIE_OTP threshold, the device will stop charging and
reset CHG_EN bit to disable.
Figure 10. TS Function Connection
 Flying Capacitor Diagnose (CFLY_DIAG)
The device integrates CFLY_DIAG function to Regulation Feature
diagnose the health of flying capacitors. After The device has VBAT_REG and IBAT_REG regulation
CHG_EN is enabled, the device starts soft-start functions to regulate instant current change and voltage
process in tSOFT_START. In the soft-start process, the change for the battery. Users can set the regulation
CFLY_DIAG function will diagnose the resistance threshold by register setting.
between CFL and CFH for each phase. If the
The VBAT_REG function monitors differential voltage
resistance is smaller than RCFLY_DIAG, the device will
between BATP and BATN/SRP_SYNCIN pin. If the
stop soft-start process and reset CHG_EN to disable.
differential voltage is higher than VBAT_REG threshold,
If the device succeeds to start charging after soft-start
the device will control OVPGATE voltage to regulate
process, the CFLY_DIAG function will stop activating.
charge current. IBAT_REG function converts the
If the CFLY is short after soft-start, the device can be
differential voltage between SRN_ADDR and
protected by other protections (e.g., IBUS_OCP,
BATN/SRP_SYNCIN to current value. If the current
VBAT_OVP, VOUT_OVP, CON_OCP, etc.).
value is higher than IBAT_REG threshold, the device will
 Dropout Voltage Protection (VDR_OVP) control OVPGATE voltage to regulate charge current. If
the regulation functions are triggered and persist for
The large voltage drop on external MOSFET might
tREG_TIMEOUT, the device will stop charging and reset
cause high power loss and a lot of heat in the system.
CHG_EN to disable. When regulation functions are
In order to prevent the situation, the device integrates
triggered, system should adjust charging condition to
VDR_OVP function to monitor the voltage drop
prevent the device from triggering the tREG_TIMEOUT and
between VAC and VBUS pin. If the voltage drop is
VDR_OVP.
higher than VDR_OVP threshold, the device will stop
charging and reset CHG_EN to disable.

 TS Over-Temperature Protection (TS_OTP)

The device integrates temperature sense (TS)
function to diagnose the external temperature with
NTC thermistor. The voltage on NTC thermistor
varies with different temperature. Figure 10 shows
the DM_TS pin connection for the TS function. The
device diagnoses TS_OTP from the DM_TS pin ADC
value if DM_TS_CFG(0x005F[6]) is set to 1. If the
external sensing voltage is lower than TS_OTP
threshold, the device will stop charging and reset
CHG_EN bit to disable. The temperature information
is derived from the DM_TS pin ADC value. For using
this function, enabling DM ADC conversion is
necessary.
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 RT9756A
Alarm Feature

The device integrates 9 alarm functions for system to monitor the charge condition. The alarm functions use the ADC
conversion data to monitor the charge condition. Table 3 shows the relationship between alarm functions and ADC
channels, users should make sure the ADC channel is enabled when using related alarm functions. If the alarm
function is triggered, the device will send an interrupt to alarm system but charger will not stop charging. Table 4
shows the enable condition for each alarm.

Table 3. Alarm Function with Related ADC Channel

Alarm Function Related ADC Channel Need Enabled Sense Node
BATP and
VBAT_OVP_ALM VBAT_ADC
BATN/SRP_SYNCIN pin
BATN/SRP_SYNCIN and
IBAT_OCP_ALM IBAT_ADC
SRN_ADDR pin
BATN/SRP_SYNCIN and
IBAT_UCP_ALM IBAT_ADC
SRN_ADDR pin
VBUS_OVP_ALM VBUS_ADC VBUS pin
IBUS_OCP_ALM IBUS_ADC Q0
IBUS_UCP_ALM IBUS_ADC Q0
TDIE_OTP_ALM TDIE_ADC DIE temperature
DP_OV_ALM DP_ADC DP pin
DM_OV_ALM DM_ADC DM pin

Table 4. Alarm Function Activation List

Alarm Function Enable Condition
VBUS_OVP_ALM CHG_EN = 1 or ADC_EN =1
VBAT_OVP_ALM CHG_EN = 1 or ADC_EN =1
IBUS_OCP_ALM CHG_EN = 1
IBUS_UCP_ALM CHG_EN = 1
IBAT_OCP_ALM CHG_EN = 1
IBAT_UCP_ALM CHG_EN = 1
TDIE_OTP_ALM CHG_EN = 1 or ADC_EN =1
DP_OV_ALM ADC_EN =1 & DP_ADC_DIS=0
DM_OV_ALM ADC_EN =1 & DM_ADC_DIS=0

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RT9756A
External MOSFET Control by OVPGATE

The RT9756A has one OVPGATE pin to control the external MOSFET. The external MOSFET control can support
both the single or the back-to-back external N-channel MOSFET. The external MOSFET can be controlled on or off
by setting register OVPMOS_DIS. If OVPMOS_DIS is set to 0, the OVPGATE pin will drive external MOSFET to turn
on when the VAC voltage is higher than VAC_INSERT threshold or the VBUS voltage is higher than VBUS_INSERT
threshold for a tVAC_INSERT_DEG time. The OVPGATE pin will drive external MOSFET to turn off if the VAC voltage is
lower than VAC_INSERT threshold and the VBUS voltage is lower than VBUS_INSERT threshold. If the VAC OVP event
is present, the external MOSFET will be also turned off. The information is detailed in VAC_OVP function description
section. If OVPMOS_DIS is set to 1, the OVPGATE pin will force external MOSFET to turn off.
The voltage between OVPGATE to VBUS can be set to 10V or 4.8V by OVPGATE(0x0004[0]). If the OVPGATE
voltage level has to be changed, OVGATE and charger must be disable(0x0004[6] = 1 and 0x0000[6] = 0) first, and
then set the OVPGATE voltage level. After over 2ms, the OVPGATE can be enabled again. Figure 11 shows the
flow of changing OVPGATE setting. OVPGATE register control bit cannot be set if OVPMOS_DIS = 0 or CHG_EN =
1.

Is OVPGATE level set N

change ?

Is OVPMOS_DIS = 1 & N Set OVPGATE to previous

CHG_EN = 0 ? setting

Delay 2ms

OVPGATE level setting

Change done

Figure 11. Flow Chart of Changing OVPGATE Setting

BC1.2 General Description

The BC1.2 detection is through USB2.0 D+ and D- lines upon connection. There are three charging ports defined in
the BC1.2 spec: Dedicated Charging Port (DCP), Charging Downstream Port (CDP) and Standard Downstream Port
(SDP). The detection results are reported in USB_STATUS (0x0046[7:5]). When the adapter is plugged in, the device
can start BC1.2 detection if BC12_EN = 1 (0x0044[7] = 1). Data Contact Detect timeout can be set by
DCD_TIMEOUT_SET (0x0044[6:5]). The RT9756A supports both portable device role (sink role) and downstream
port or charging downstream port (source role). When the device is source role, set HOST_MODE (0x0044[3:2]) to
choose the charging port type. BC12_EN (0x0044[7]), HOST_MODE (0x0044[3:2]) and other protocol function
cannot be enabled in the same time. To change the charging port type, HOST_MODE (0x0044[3:2]) must be set to
00 first.

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 RT9756A
DP/DM Output Control Mode Spread Spectrum

DP/DM output control mode is enabled by The device integrates spread spectrum function for
SET_DPDM_EN(0x0048[7]). The output is controlled users to optimize the EMI influence on system design.
by programmed SET_DP (0x0048[6:4]) and SET_DM The device switching frequency is decided by register
(0x0048[3:1]). The device will ignore BC1.2 detection 0x0001[7:4]. The spectral density will concentrate on
when SET_DPDM_EN = 1. the switching frequency. Users can enable the spread
spectrum function by set 0x0001[3:2] register. After the
I2C Level Selection spread spectrum function is enabled, the device will
The RT9756A can support VDD = 1.2V or 1.8V of I2C. modulate the switching frequency for 10% to reduce
When EN_I2C_LEVEL_DETECTION (0x005E[7]) is the spectral density.
enable, I2C level can change from 1.2V to 1.8V if pull-
Parallel Application
up voltage of SDA pin is higher than VTH_I2C_level, and
I2C_level (0x005E[6]) will be 0. Because I2C level For high capacity battery charging application, it is
detection function is not automatically disabled, users available to use two RT9756A in parallel architecture.
should disable this function after the RT9756A wakes The advantages of using parallel architecture are
up and VDD of I2C is ready. If users want to set reducing cable losses, improve efficiency of charge
I2C_level (0x005E[6]), EN_I2C_LEVEL_DETECTION system and cut down charging period. The high power
(0x005E[7]) must be disable first. I2C level detection solution that uses two RT9756A are shown in Figure 12.
function would not change I2C level from 1.8V to 1.2V In order to avoid unstable ripple issue while charging
even if SDA voltage is lower than VTH_I2C_level. If users with parallel architecture, the RT9756A is established
want to charge I2C level from 1.8V to 1.2V, disabled with synchronization function at the DP_SYNCOUT pin
EN_I2C_LEVEL_DETECTION (0x005E[7]) first, then and BATN/SRP_SYNCIN pin. The DP_SYNCOUT pin
set I2C_level (0x005E[6]) = 1. and BATN/SRP_SYNCIN pin are multi-function pins
that depends on different configuration. The slave
Interrupt (INT), STAT, FLAG AND MASK
address is configured by SRN_ADDR pin while device
The INT pin is an open drain structure; users should powers up, and the configuration mode is set by
connect a supply voltage via a current source or pull-up DP_SYNCOUT_CFG (0x005F[7]) or
resistors on the pin. When the device triggers an event, BATN_SRP_SYNCIN_CFG (0x005F[5]). Table 5
the INT pin will pull-low for tINT_PULL_LOW to notify host. shows the configuration mode setting. When RT9756A
The register map shows all state, flag and control bit of is configured to master mode (RT9756A_M), the
the device. DP_SYNCOUT pin provides synchronization pulses
When the device triggers the event with FLAG, it will with frequency equal to twice switching frequency and
send an INT signal to host and set the FLAG bit to 1. 50% duty cycle, so the DP and DM pin cannot
The FLAG bit can be cleared after read. The device will implement any protocol function. When RT9756A is
not send another INT signal until the FLAG is cleared configured to slave mode (RT9756A_S), the
and a new event occurs again. The MASK bit can BATN/SRP_SYNCIN pin is used to receive pulses for
disable INT pin to send a signal to host. The STAT and synchronization, so the VBAT and IBAT sense functions
FLAG bit are still updated even though the MASK bit is are disabled. For using the synchronization function, the
set to 1. DP_SYNCOUT pin of master device and
BATN/SRP_SYNCIN pin of slave device should be
The STAT bits show current statue of the device and
connected to each other. BATN_SRP_SYNCIN_CFG
are updated as the status change. All of STAT bits will
cannot set to 1 when slave address is 0x6F, and
not send INT signal to system when the STAT bit is
DP_SYNCOUT_CFG cannot set to 1 when slave
triggered except SWITCHING_STAT.
address is 0x6E.

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RT9756A
In DIV2 mode, all of phase angle in the device need to function, VAC_INSERT_PROTOCOL_DIS should be
be defined correctly for optimize output ripple and set to 1 because all protocol function is restricted by
charging efficiency, especially parallel application. The VAC_INSERT_STAT = 1.
A phase between master and slave device should be If parallel architecture is used, the start-up sequence
shifted 90 degrees, the A and B phase in the same should be compiled with the rules below. The
device should be shifted 180 degrees. It is strongly RT9756A_S should be enabled before host enables the
prohibited to change PHASE_A_ANGLE (0x0002[3:2]) RT9756A_M in order to achieve parallel application.
and PHASE_B_ANGLE (0x0002[1:0]) during charging. The RT9756A_S will not switch until the
In parallel application, only master device’s OVP BATN/SRP_SYNCIN pin receives synchronization
MOSFET is used. Furthermore, the OVPGATE function pulses provided by the RT9756A_M. The
should be turned off in slave device and the OVPGATE communication flow between smart wall adapter and
pin should be left floating. Moreover, only slave device’s parallel charge system is shown in Figure 13.
DP and DM pin can be used. To enable DPDM protocol

Table 5. Configuration Mode Setting Description

Slave Address Register Configuration
0x6F DP_SYNCOUT_CFG = 0 Standalone
0x6F DP_SYNCOUT_CFG = 1 Master
0x6E BATN_SRP_SYNCIN_CFG = 0 Standalone
0x6E BATN_SRP_SYNCIN_CFG = 1 Slave

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 RT9756A
CFLY1 CFLY7

CFLY2 CFLY8

CBST1 CFLY3 CFLY9 CBST3

A6 A1 B1 C1, C2 E1, E2 E1, E2 C1, C2 B1 A1 A6

OVPGATE VAC BST1 CFH1 CFL1 CFL1 CFH1 BST1 VAC OVPGATE

Q5 Q6
USB Type-C Port

A2, A3, A2, A3,

B2, B5 B2, B5
VBUS A4, A5 A4, A5
VBUS PMID PMID VBUS

CVBUS1 CPMID1 CPMID2 CVBUS2

CVAC RT9756A RT9756A
(Master) (Slave)
Pull Up

USB Type-C Port

D1, D2, D5, D6 D1, D2, D5, D6 D-
VOUT VOUT DM_TS
B4
R1 R2 R3
CVOUT1 CVOUT2 CVOUT3 CVOUT4
10kΩ 10kΩ 10kΩ C3 D+
SDA DP_SYNCOUT
B3
C4
Host SCL
Battery
E4 Pack
/INT E3
BATP BATP F4
F4 E3
REGN R4 + REGN
CREGN1 D3 D3 CREGN2
BATN/SRP_SYNCIN BATN/SRP_SYNCIN
Pull Up
RSEN
R4 C3
D4 D4 SDA
B4 SRN_ADDR SRN_ADDR
DM_TS
C4
SCL
RT
B3 E4
DP_SYNCOUT /INT

GND AGND BST2 CFH2 CFL2 CFL2 CFH2 BST2 AGND GND
F1, F2, F3 B6 C5, C6 E5, E6 E5, E6 C5, C6 B6 F3 F1, F2,
F5, F6 F5, F6

CBST2 CFLY4 CFLY10 CBST4

CFLY5 CFLY11

CFLY6 CFLY12

Figure 12. Parallel Application Circuit

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RT9756A
Smart Wall
PD Controller System with PD, Switching charger and two RT9756A
Adapter

No Switching Charger
Adapter Plug-in Run BC1.2 Battery > 2V operate in trickle
charge mode

Yes

No Switching Charger
Battery > 3V operate in Pre-
charge mode

Yes

No Switching Charger
Battery > 3.45V operate in Fast-
charge mode

Yes

No
System wake up Wake up system

Set charger initial setting

Run PD
and enable RT9756A
protocol
ADC to monitor Battery

Smart Yes Disable

Adapter Switching Charger

No

Adjustable Yes Start HV switching

DCP charge process

No
Start 5V switching
charge process

Set VBUS limit to 2.04 x VBAT

Set I BUS limit to desired value
by ramp step

Trigger RT9756A No
Enable RT9756A_M
abnormal event

Yes
calculate the voltage drop
of charging path, and then
disable RT9756A_M

Enable RT9756A_S to wait for

synchronization pulses.
Readjust charge Enable RT9756A_M to produce
condition depend on synchronization pulses and start charging.
abnormal event

Increase BUS voltage or

BUS current to charging Monitor VBAT & IBAT

No IBAT < No
VBAT > VBAT_ALM
IBAT_U CP_ALM

Yes Yes
Decrease BUS voltage or
BUS current to control
charge current
Disable RT9756A and
than enable switching
charger to continues CV
charging

Figure 13. System Control Flow Chart with Parallel Charge System

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76
 RT9756A
I2C Serial Interface
The RT9756A integrates I2C interface for host to program charging parameter and monitor device status. The
interface requires a serial clock line (SCL) and a serial data line (SDA). The host should initiate a data transfer on
the bus and generates the clock signals to permit that transfer. The device operates with address 0x6F or 0x6E to
receive control input from the host. The SCL and SDA pin are open drain structures. Users should connect a supply
voltage via a current source or pull-up resistors on SCL and SDA. Figure 14 shows the I2C waveform information,
the data line must be stable during the high period of SCL line. The high or low state of SDA can only change when
SCL line is low.

SDA

tLOW tBUF
tF tR tSU;DAT tF tHD;STA tSP tR

SCL

tHD;STA tSU;STA tSU;STO

S tHD;DAT tHIGH Sr P S

Figure 14. I2C Waveform Information

The RT9756A operates as an I2C slave device with address 0x6F or 0x6E (depends on SRN_ADDR pin). Every byte
on SDA line must be 8-bit long. The register address size is two byte. Send the high byte of the register address first
and then the low byte of the register address. Figure 15 shows the byte format. All of transactions begin with a START
pattern and can be terminated with a STOP pattern. After START, the master should send a slave address. The
slave address is 7-bit long followed by the eighth bit as a data direction bit (R/W). The direction bit setting to 0
indicates a transmission and 1 indicates a request for data. The master should take an acknowledge bit after every
byte. The master should release SDA line during the acknowledge clock pulse so the slave device can pull low the
SDA line to signal the master that the byte was successfully received. The RT9756A supports multi read/write and
SCL line can be up to 3.4MHz.

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RT9756A
Read single byte of data from Register
Slave Address Register Address High Byte Register Address Low Byte Slave Address

S 0 A A A Sr 1 A

R/W
Assume Address = m

MSB Data LSB

A P
Data for Address = m

Read N bytes of data from Registers

Slave Address Register Address High Byte Register Address Low Byte Slave Address

S 0 A A A Sr 1 A

R/W
Assume Address = m

MSB Data 1 LSB MSB Data 2 LSB MSB Data N LSB

A A A P
Data for Address = m Data for Address = m + 1 Data for Address = m + N - 1

Write single byte of data to Register

Slave Address Register Address High Byte Register Address Low Byte MSB Data LSB

S 0 A A A A P

R/W Data for Address = m

Assume Address = m

Write N bytes of data to Registers

Slave Address Register Address High Byte Register Address Low Byte MSB Data 1 LSB

S 0 A A A A

R/W Data for Address = m

Assume Address = m

MSB Data 2 LSB MSB Data N LSB

A A P
Data for Address = m + 1 Data for Address = m + N - 1

Driven by Master, Driven by Slave, P Stop, S Start, Sr Repeat Start

Figure 15. Read and Write Function

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 RT9756A
Thermal Considerations 5.0

Maximum Power Dissipation (W) 1

Four-Layer
The junction temperature should never exceed the
absolute maximum junction temperature T J(MAX), listed 4.0

under Absolute Maximum Ratings, to avoid permanent

damage to the device. The maximum allowable power 3.0
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow, 2.0
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be 1.0
calculated using the following formula:
PD(MAX) = (TJ(MAX) - TA) / JA 0.0
where TJ(MAX) is the maximum junction temperature; T A 0 25 50 75 100 125

is the ambient temperature; and JA is the junction-to- Ambient Temperature (°C)
ambient thermal resistance.
Figure 16. Derating Curve of Maximum Power
For continuous operation, the maximum operating
Dissipation
junction temperature indicated under Recommended
Operating Conditions is normally 125°C. The junction- Layout Considerations
to-ambient thermal resistance, JA, is highly package
The RT9756A layout guidelines are recommended as
dependent. For a WL-CSP-36B 2.8 x 2.8 (BSC)
below:
package, the thermal resistance, JA, is 29.26°C/W on
a standard JEDEC low effective-thermal-conductivity  Place low ESR bypass capacitor to GND for
two-layer test board. The maximum power dissipation PMID/VOUT/VBUS pin. The bypass capacitor
at TA = 25°C can be calculated as below: needs to be placed as close as possible to the
PD(MAX) = (125°C - 25°C) / (29.26°C/W) = 3.42W for a RT9756A.
WL-CSP-36B 2.8 x 2.8 (BSC) package.
 The capacitor of REGN/BST1/BST2 should be
The maximum power dissipation depends on the
placed as close as possible to the RT9756A.
operating ambient temperature for the fixed T J(MAX) and
 Place flying caps with the RT9756A on same layer.
the thermal resistance, JA. The derating curves in
Figure 16 allows the designer to inspect the effect of The flying caps should be placed as close as
rising ambient temperature on the maximum power possible to the RT9756A. The path of flying caps
dissipation. should be as small as possible. Two phases’ flying
caps trace and copper pour should be as
symmetrical as possible
 The VBUS and VOUT traces should be as wide as
possible to accommodate high charge current.
 Place differential line for VBATP/VBATN and
SRP/SRN. Do not route the differential line across
power pad especially the flying caps.

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RT9756A

VOUT

TOP Layer
Inner Layer1
COUT1 COUT2
Inner Layer2
Bottom Layer
Blind via
CREGN 0603C 0603C

0402C
GND

GND GND REGN AGND GND GND F

CCFLY6 CCFLY5 CCFLY4 CCFLY3 CCFLY2 CCFLY1
CFL2 CFL2 INT BATP CFL1 CFL1 E

BATN/S
SRN_A
0603C 0603C 0603C VOUT VOUT
DDR
RP_SY
NCIN
VOUT VOUT D 0603C 0603C 0603C

CFH2 CFH2 SCL SDA CFH1 CFH1 C

DP_SY
BST2 PMID DM_TS
NCOUT
PMID BST1 B
CBST2

CBST1
OVPGA
TE
VBUS VBUS VBUS VBUS VAC A
0201C 0201C
6 5 4 3 2 1
GND PMID
CVBUS
CPMID

0603C 0402C GND

Figure 17. PCB Layout Guide

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 RT9756A
Outline Dimension

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.500 0.600 0.020 0.024
A1 0.170 0.230 0.007 0.009
b 0.240 0.300 0.009 0.012
D 2.765 2.835 0.109 0.112
D1 2.000 0.079
E 2.765 2.835 0.109 0.112
E1 2.000 0.079
e 0.400 0.016
ccc 0.020 0.001

36B WL-CSP 2.8x2.8 Package (BSC)

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RT9756A
Footprint Information

Number of Footprint Dimension (mm)

Package Type Tolerance
Pin e A B
NSMD 0.240 0.340
WL-CSP2.8x2.8-36(BSC) 36 0.400 ±0.025
SMD 0.270 0.240

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 RT9756A
Packing Information
Tape and Reel Data - RT9756AP-A

Tape Size Pocket Pitch Reel Size (A) Units Trailer Leader Reel Width (W2)
Package Type (mm) (mm)
(W1) (mm) (P) (mm) per Reel Min./Max. (mm)
(mm) (in)

WL-CSP
8 4 180 7 3,000 160 600 8.4/9.9
2.8x2.8

C, D, and K are determined by component size.

The clearance between the components and

the cavity is as follows:

- For 8mm carrier tape: 0.5mm max.

W1 P B F ØJ H
Tape Size
Max. Min. Max. Min. Max. Min. Max. Min. Max. Max.

8mm 8.3mm 3.9mm 4.1mm 1.65mm 1.85mm 3.9mm 4.1mm 1.5mm 1.6mm 0.6mm

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RT9756A
Tape and Reel Data - RT9756AP-B

Tape Size Pocket Pitch Reel Size (A) Units Trailer Leader Reel Width (W2)
Package Type (mm) (mm)
(W1) (mm) (P) (mm) per Reel Min./Max. (mm)
(mm) (in)

WL-CSP
12 8 180 7 1,500 160 600 12.4/14.4
2.8x2.8

C, D, and K are determined by component size.

The clearance between the components and

the cavity is as follows:

- For 12mm carrier tape: 0.5mm max.

W1 P B F ØJ H
Tape Size
Max. Min. Max. Min. Max. Min. Max. Min. Max. Max.

12mm 12.3mm 7.9mm 8.1mm 1.65mm 1.85mm 3.9mm 4.1mm 1.5mm 1.6mm 0.6mm

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 RT9756A
Tape and Reel Packing - RT9756AP-A

Step Photo/Description Step Photo/Description

1 4

Reel 7” 12 inner boxes per outer box

2 5

Packing by Anti-Static Bag Outer box Carton A

3 6

3 reels per inner box Box A

Container Reel Box Carton

Package Size Units Item Size(cm) Reels Units Item Size(cm) Boxes Unit

WL-CSP Box A 18.3*18.3*8.0 3 9,000 Carton A 38.3*27.2*38.3 12 108,000

7” 3,000
2.8x2.8 Box E 18.6*18.6*3.5 1 3,000 For Combined or Partial Reel.

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RT9756A
Tape and Reel Packing - RT9756AP-B

Step Photo/Description Step Photo/Description

1 4

Reel 7” 3 reels per inner box Box A

2 5

HIC & Desiccant (1 Unit) inside 12 inner boxes per outer box

3 6

Caution label is on backside of Al bag Outer box Carton A

Container Reel Box Carton

Package Size Units Item Size(cm) Reels Units Item Size(cm) Boxes Unit

WL-CSP Box A 18.3*18.3*8.0 3 4,500 Carton A 38.3*27.2*38.3 12 54,000

7” 1,500
2.8x2.8 Box E 18.6*18.6*3.5 1 1,500 For Combined or Partial Reel.

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 RT9756A
Packing Material Anti-ESD Property

Surface
Aluminum Bag Reel Cover tape Carrier tape Tube Protection Band
Resistance
/cm2 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011 104 to 1011

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable.
However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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RT9756A
Datasheet Revision History
Version Date Description Item
Features on P1, 2
Ordering Information on P2
Functional Pin Description on P3, 4
Absolute Maximum Ratings on P5
00 2023/7/7 Modify Electrical Characteristics on P6 to 16
Typical Application Circuit on P20
Typical Operating Characteristics on P21
Register Description on P22, 23, 24, 25, 26, 28, 39, 42, 51
Application Information on P59, 60, 73, 74, 75, 76, 77
General Description on P1
Ordering Information on P2
01 2024/1/18 Modify Recommended Operating Conditions on P6
Electrical Characteristics on P10
Packing Information on P83, 84, 85, 86

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88