AN INDUSTRIAL ORIENTED MINI PROJECT REPORT ON

IMPLEMENTATION OF EFFICIENT AND LOW POWER

TEST PATTERN GENERATORS
Submitted in partial fulfillment of the requirement for the award of the Degree of

BACHELOR OF TECHNOLOGY
Submitted to

Jawaharlal Nehru Technology University Hyderabad, Hyderabad

Submitted By
KANEEZ FATIMA 216B1A0447
Under the Esteemed Guidance of
Dr. S. SELVAKUMAR RAJA
M.E, Ph. D

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

KAKATIYA INSTITUTE OF TECHNOLOGY AND SCIENCE FOR WOMEN
MANIKBHANDAR, NIZAMABAD, 503003
Approved by AICTE and Affiliated to JNTUH.
(2021-2025)
 KAKATIYA INSTITUTE OF TECHNOLOGY &
SCIENCE FOR WOMEN
Approved by AICTE and affiliated to JNTUH-Hyderabad.
Manikbhandar Nizamabad-503003.Ph:08462_281077

Date:

CERTIFICATE
This is to certify that the Industrial Oriented Mini Project entitled “IMPLEMENTATION OF
EFFICIENT AND LOW POWER TEST PATTERN GENERATORS” is a record of bonafied
work carried out by KANEEZ FATIMA (216B1A0447),students of B.Tech, under our
supervision and guidance in partial fulfilment for the award of Bachelor of Technology in
Electronics and Communication Engineering during the academic year 2024-2025.

PROJECT GUIDE HEAD OF THE DEPARTMENT

Dr. S. SELVAKUMAR RAJA Mr. M. MAHIPAL
M.E., Ph. D M. Tech
Principal Dept. of ECE
PRINCIPAL
Dr. S. SELVAKUMAR RAJA
M.E., Ph. D
EXAMINERS:
1.
2.
 ACKNOWLEDGEMENT
I would like to express our sincere gratitude to our guide Dr. S. SELVAKUMAR, of
Electronics and Communication Engineering. KITSW who extended his unconditional
support and spared his valuable time with his patience and valuable suggestions during the
project. We also extend our special thanks for the encouragement and constant supervision
throughout the project.
I would like to wish to give special vote of thanks to HOD, Mr. M. MAHIPAL, M.
Tech, ECE Dept. KITSW, for his unique way of inspiring students through clarity of
thoughts, Enthusiasm and care. His constant encouragement and assistance were very helpful
and made my effort a success.
I are also grateful to Dr. S. SELVAKUMAR RAJA, M.E., Ph.D. Principal, KITSW,
for providing me with the facilities and resources required for the successful completion our
Industrial Oriented Mini project. We even thank him for his valuable suggestions at that time
of Seminars which encouraged me to give my best in Industrial Oriented Mini project.
I would also like to thank our faculty and supporting staff of Electronics and
Communications Engineering Department and all other departments for their kind co-
operation directly or indirectly in making the Industrial Oriented Mini project successful one.
Finally, we want to deeply acknowledge all my friends and family members who
have encouraged me during the preparation of Our Industrial Oriented Mini project.

By
KANEEZ FATIMA 216B1A0447
 DECLARATION

I KANEEZ FATIMA (216B1A0447), thereby declare that this Industrial Oriented

Mini Project has been carried out entirely under the esteemed guidance of Dr. S.
SELVAKUMAR RAJA, for the partial fulfilment of the award of the degree of B. Tech in
Electronics and Communication Engineering at Kakatiya Institute of Technology and
Science for Women, Manikbhandar , Nizamabad, Affiliated to JNTUH and further it has not
been submitted to any other university or institutions for the award of any other degree.

By
KANEEZ FATIMA 216B1A0447
 ABSTRACT
I are aware that during testing when the device’s normal functioning mode is off, the
dissipation of power is approximately 200% more than that of normal functioning mode. In
this project 32-bit test pattern generator has been proposed for testing the VLSI design. This
32-bit test pattern generator is implemented with efficient LFSR and with extra
combinational circuitry which achieved low power consumption. The switching activity
between the tests vector are reduced, this results in low power consumption.

Pattern injection based on RI Method:

A test pattern generator (TPG) is used to generate test patterns for testing the functionality
and performance of integrated circuits (ICs).

The TPG generates input patterns that are applied to the inputs of the IC to check the
correctness of the circuit's functionality. The output responses of the circuit are compared
against expected output responses to determine if the circuit is operating correctly.

The generated test patterns are designed to detect faults in the IC, such as stuck-at faults,
transition faults, and delay faults. The TPG can be either built into the design of the IC or
used externally as a standalone device.

In VLSI design, the testing process is critical to ensuring that the IC operates correctly under
various operating conditions. Test pattern generation is an essential step in the testing
process, and the TPG plays a crucial role in generating test patterns efficiently and accurately.

There are various types of TPGs available for VLSI design, including deterministic TPGs,
pseudorandom TPGs, and built-in self-test (BIST) TPGs. These TPGs differ in their
complexity, speed, and effectiveness in detecting faults.
 INDEX
CONTENTS PAGE NO
LIST OF FIGURES i

LIST OF TABLES ii
LIST OF ABBREVIATIONS iii
CHAPTER 1
INTRODUCTION TO THE PROJECT 1-2
CHAPTER 2
LITERATURE SURVEY 3-4
CHAPTER 3
INTRODUCTION TO VLSI 5-11
3.1 VLSI Technology 5-6
3.2 History 6
3.3 Integrated circuits 6-7
3.4 Developments and Generations 7-10
3.5 Structured design 10
3.6 challenges 10-11

CHAPTER 4
PROJECT DESCRIPTION 12-18
4.1 Existing system 12-15
4.2 Proposed system 15-18

CHAPTER 5
HARDWARE DESCRIPTION LANGUAGES & TOOLS USED 19-33
5.1 HDL 19-22
5.2 VHDL 22-24
5.3 Types of architectures 24-25
5.4 Verilog HDL 25-26
5.5 Verilog vs VHDL 26-27
5.6 Tools used 28-33

CHAPTER 6
RESULTS 34-36
6.1 Simulation results 34
6.2 Schematic 35
6.3 Area report 36
6.4 Power report 36

CHAPTER 7
APPLICATIONS & ADVANTAGES 37-38
7.1 Advantages 37
7.2 Applications 38

CHAPTER 8
CONCLUSION 39
FUTURE SCOPE 39
REFERENCES 40
 LIST OF FIGURES
Fig no. Name of the figure page no.

1 A 3-bit shift register 14

Example of RI Injection 16
3.1 Structure of LFSR 16
3.2 Structure of Bipartite LFSR 16
4 Architecture of LP-LFSR 18
5.1 Steps in HDL based design flow 19
5.2 VHDL Structure 24
6 Simulation 34
7.1 Schematic random injection 35
7.2 Schematic control FSM 35
7.3 Schematic LP-LFSR 35

ⅰ
 LIST OF TABLES
Table no. Name of the table Page no.
1 Pattern generation seed values 14
2 Language supported by ISE 31
3 Features supported by ISE 32
4 Area report 36
5 Power report 36

ⅱ
 LIST OF ABBREVATIONS

LFSR - Linear feedback shift register

LP-LFSR - Low power linear feedback shift register
IC - Integrated circuit
RAM - Random access memory
ROM - Read only memory
VLSI - Very large integrated circuit
FPGA - Field programmable gate array
SOC - System on chip
DUT - Design under test
HDL - Hardware description language
ASIC - Application specific integrated circuit
DFT - Design for test
DFM - Design for manufacturing

iii