IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO.

4, APRIL 2012 569

Laser-Enabled Advanced Packaging of Ultrathin

Bare Dice in Flexible Substrates
Val Marinov, Orven Swenson, Ross Miller, Ferdous Sarwar, Yuriy Atanasov, Matthew Semler, and Samali Datta

Abstract— Embedding ultrathin semiconductor dice in flexible integrated circuit (IC) packages are not meant to be supported
substrates provides unique capabilities for product designers by a thin, flexible substrate. Their use would compromise
and makes products such as smart bank cards and radio- the quintessential property of a flexible electronic device–its
frequency identification banknotes possible. Most of the current
work in this area is directed toward handling, embedding, and flexibility. Flexible substrates require not only a small but a
interconnecting the ultrathin chips. Relatively little attention is flexible chip. This can be achieved only if the thickness of the
paid to another critical process step–placing the flexible and very silicon is reduced to about 50 μm or less [3], [4].
fragile ultrathin die onto the flexible substrate reliably and in a Embedding bare dice in the substrate allows the entire
cost-efficient manner, suitable for high throughput assembly. The device to bend and flex uniformly like one homogeneous mate-
presented laser-enabled technology for embedding ultrathin dice
in a flexible substrate was developed at the Center for Nanoscale rial. Since the die can be placed at or near the neutral plane,
Science and Engineering, North Dakota State University, Fargo, the bending stresses in the silicon will be minimized thus
ND, to address this problem. The technology has been successfully reducing the probability for fracture failure. Die embedding
demonstrated and proven for the fabrication of an RFID tag. provides a solution for realizing a 3-D packaging integration
Index Terms— Embedded chips, flexible electronics, with the highest level of miniaturization [2], [5]–[7] as well
laser-induced forward transfer, ultrathin semiconductor die. as designing hybrid systems in which the thin silicon IC
technology compliments the printable electronics to create
I. I NTRODUCTION highly efficient and inexpensive devices [2].
Cost is of a paramount importance especially for disposable
M ICROELECTRONIC devices assembled on flexible
substrates and based on ultrathin chips find new and
exciting applications in wearable and low-cost disposable
electronics. Cost of silicon is often the largest contributor to
the total cost of a disposable electronic device such as an
electronics, health care and space applications, microelectro- RFID tag [8]. It is well known in the trade that the cost of the
mechanical systems, solar cells, document security, biomed- semiconductor die scales with area raised to the 1.5–2 power
ical, and other fields [1], [2]. [6]. Therefore, reducing the die size by half would reduce the
Flexible electronics is still an evolving and highly dynamic cost of silicon by a factor of 8–16. Cost depends also on the
area compared to the traditional electronics packaging technol- die thickness. Thinner wafers mean more slices from the ingot,
ogy where discrete electronic components are attached to rigid, ergo, less cost per wafer.
laminate-based printed wiring board using the surface-mount
or/and pin-in-hole methods. Fabricating a flexible electronic A. Ultrathin Die Onto or Into a Flexible Substrate
device is not as simple as just replacing the rigid board with a In the conventional flip-chip technology, also called chip-
flexible substrate. Bulky, heavy, rigid components such as most last approach [9], the ultrathin dice are flip-chip bonded
face down and then assembled either using reflow soldering
Manuscript received July 8, 2011; revised October 25, 2011; accepted
November 6, 2011. Date of publication December 29, 2011; date of [10]–[12] or thermode bonding [12]–[14]. The major advan-
current version March 30, 2012. This work was supported in part by tage of the flip-chip technology is its maturity. The drawbacks
the Defense Microelectronics Activity under Agreement 08-2-0805, are the larger overall thickness of the assembly, the need for
Agreement H94003-09-2-0905, and Agreement H94003-11-2-1102. The
United States Government is authorized to reproduce and distribute reprints underfill, and placing the fragile die away from the bending
for government purposes, notwithstanding any copyright notation thereon. neutral plane. The overall thickness can be reduced if the
Recommended for publication by Associate Editor B. Dang upon evaluation of flip chips are soldered to pads on the opposite site of the
reviewers’comments.
V. Marinov is with the Center for Nanoscale Science and Engineering and substrate by placing solder or stud bumps into through vias
the Department of Industrial and Manufacturing Engineering, North Dakota [12], [15]–[17].
State University, Fargo, ND 58102 USA (e-mail: [email protected]). In the chip-first approach, the die is first bonded to the
O. Swenson is with the Center for Nanoscale Science and Engineering and
the Department of Physics, North Dakota State University, Fargo, ND 58102 substrate face up and then covered with a dielectric layer,
USA (e-mail: [email protected]). which is exposed and developed to access the die pads
R. Miller, F. Sarwar, Y. Atanasov, M. Semler, and S. Datta are with the for electrical interconnection. In another implementation of
Center for Nanoscale Science and Engineering, North Dakota State University,
Fargo, ND 58102 USA (e-mail: [email protected]; ferdous.sarwar@ this method, called isoplanar interconnection [18]–[20], the
ndsu.edu; [email protected]; [email protected]; samali. conductor lines are led across the die edge and then connected
[email protected]). to the circuitry on the top of the coverlayer. The chip-first
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. approach has been and is still being actively developed mostly
Digital Object Identifier 10.1109/TCPMT.2011.2176941 in Europe, especially by the Fraunhofer group in Germany
2156–3950/$26.00 © 2011 IEEE
570 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012

[1], [7], and [18]–[22]. Similar techniques were developed in silicon-on-insulator material technology, has been developed
Belgium [5], [9], and [23] and by Samsung [24]. Alternative and published extensively by the J. A. Rogers group at the
chip-first methods are discussed in [25]. University of Illinois at Urbana-Champaign [35].
The ultrathin dice can be also embedded directly into the
substrate as suggested by Texas Instruments [26]. In the B. Pick-and-Place Assembly of Thin Dice
process developed at the Helsinki University of Technology
The pick-and-place equipment conventionally used for
[27], the bare die is placed face down into through holes
direct chip attach cannot satisfactorily handle ultrathin dice
drilled in the substrate and then encapsulated. The electrical
[18], [36]. Consequently, the industry relies on prototype
interconnections are realized on the back side of the substrate.
and/or adapted die bonders [7], [21], [27], [37] but the
Alternatively, the cavity is not fabricated in the substrate but
results are far from optimal and the equipment is unique and
in a thick layer of photo-definable polyimide spincoated onto
costly [10].
the base polyimide layer [28].
Picking the ultrathin die from the carrier tape by the “pick-
and-place” machine is a challenging task. If the die is not
B. Application Potential somehow fixed to the carrier tape, stiction may become a prob-
An application area with a huge marketing potential for lem, especially for components with a characteristic length
ultrathin chips are the low-cost, disposable single-chip elec- of less than 300 μm [38] for which the gravitational force
tronic products such as RFID tags and bank cards for which may become comparable to the surface forces of attraction.
flexibility is an essential requirement. The RFID market is The stiction problem can be alleviated if the dice are fixed
already estimated in trillions of tags per year [29]. The bank to the carrier tape with adhesive. Then the question is how
cards used in the U.S. usually store data on a magnetic stripe. to lift the die from the adhesive film without damaging
Most of the developed countries are already replacing the it. Various approaches using penetrating and nonpenetrating
magstripe cards with the so-called “smart cards” in which the needle ejectors as well as thermal release tapes were attempted
encrypted data are stored in an embedded chip. Replacing all with variable success [18], [27], [39] but this step is very
cards only in the U.S. could cost as much as $2.85 billion [30], critical and can easily destroy the ultrathin die [18], [19].
offering yet another big market segment for the embedded The problems do not end with picking the die from the tape.
ultrathin chip technology. Placement down-force is used to establish contact between the
Another exciting new application is the RFID banknote. die bumps and the pads on the substrate. The ultrathin dice
The European Central Bank [31] and the Bank of Japan are so delicate that the down-force of the placement nozzle
[32] are considering embedding chips into the banknotes to often cracks the die when it is placed on the substrate [18].
foil counterfeiters. Banknote paper is typically 80–100-μm R. W. Johnson’s group at Auburn University [12],
thick, which necessitates the use of ultrathin dice. To address [15]–[17] suggested using a thick “releasable handle” to
this application, Hitachi Ltd. has developed its 7.5-μm thick support the thinned die during flip-chip assembly, allowing
μ-Chip [33]. It is unclear though what technology the com- the stack to be handled by the traditional pick-and-place
pany uses to embed this chip into the banknotes. equipment. The limitations of this approach include material
waste and the need for an additional process step for removing
II. U LTRATHIN D ICE A SSEMBLY: S TATE - OF - THE -A RT the handles prior to underfilling by soaking the assembly in
A. Dicing and Handling Thinned Wafers acetone.
Flexible electronic products with embedded chips are typi-
The methods for wafer handling and component assem-
cally used in mass-produced devices where roll-to-roll (R2R)
bly used for thick wafers can be modified and adapted for
manufacturing is the industry standard for cost effective pro-
assembly of ultrathin dice on flexible substrates but this is
duction [40]. Each step in the manufacturing process, from
not a trivial task [19], [27]. Dicing of the thinned wafer can
the wafer to the final packaging, must be scalable to high
be accomplished by sawing, laser dicing, deep reactive ion
volume, low cost manufacturing. The die bonders can process
etching, or by the recently developed “dicing-by-thinning”
thick dice at a rate of 3000 cph [41]. This rate should be
process [11], [18], [20], [34].
much lower for precision assembly of ultrathin dice because
The singulated bare dice are placed on a tape carrier for
placement accuracy and rate are inversely correlated. Though
use in the component placement equipment. When applied
a single-nozzle placement machine may have the precision to
to ultrathin dice, this process requires handling of ultrathin
place extremely fine pitch components [42], this equipment
wafers, which is a major challenge because the ultrathin wafers
cannot handle ultrathin dice and similar components at a
are fragile and tend to warp making the use of automated robot
rate sufficient for high throughput assembly (>10 cps) [18].
handling difficult if possible at all [27].
Therefore, the die placement is increasingly becoming the
The Chipfilm technology recently developed by Burghartz
limiting factor for the widespread use of ultrathin dice.
et al. [2] includes narrow cavity formation underneath the
die areas on wafers. The target die thickness is set above
III. L ASER -E NABLED A DVANCED PACKAGING (LEAP)
these cavities by epitaxial growth of silicon. The dice are
detached by breaking the anchors underneath the chips, and A. Principles
then supported and transferred to the substrate using the Pick, The LEAP process described here is a comprehen-
Crack & Place process. A similar method, based on the sive wafer-to-product electronic packaging technology for
MARINOV et al.: LEAP OF ULTRATHIN BARE DICE IN FLEXIBLE SUBSTRATES 571

Laser or
dicing saw
Bumped dice Thinned wafer
Wafer preparation Lamination
UV-transparent carrier Dynamic release layer
UV laser pulse

Discretes
Thermo-mechanical
selective laser-assisted SMT
die transfer (tmSLADT)

Laser Squeegee

Die receptacles Flexible substrate

w/conductors Conductive paste
& via holes
Substrate preparation PTF-I

Fig. 1. LEAP process flow. The die is embedded and the vias plugged using the tmSLADT and PTF-I methods described below.

high-throughput, low-cost contactless assembly of ultrathin

bare dice onto rigid and flexible substrates. LEAP has been
under development at the North Dakota State University’s
Center for Nanoscale Science and Engineering in Fargo, ND,
since 2008. LEAP can be used for flip-chip surface bonding
of bumped dice or for embedding of ultrathin dice in the
substrate. Fig. 2. Optical microscope pictures of (a) wafer immediately after dicing
showing the debris haze around the cuts, (b) wafer after stripping the
The major steps in the LEAP process, shown schematically photoresist (the dots on the sample are intrinsic to the silicon and were
in Fig. 1, are discussed in detail in the next sections. In brief, observed before dicing), and (c) bottom of the wafer after dicing.
the process sequence starts with bonding the thinned wafer
to an UV-transparent carrier face up. The layer that bonds
or create microcracks, damaging the circuitry of the dice.
the wafer is herein referred to as the dynamic releasing layer
The jet of cooling water streaming on the sample could also
(DRL). Next, the wafer is bumped and laser-diced. Alterna-
potentially remove the dice and affect the adhesion of the
tively, the wafer can be diced by following the dicing-by-
wafer to the carrier. Laser dicing not only reduces the amount
thinning routine. The diced wafer is now ready for die transfer
of stress imparted on the die, but does not require a jet of
by the thermo-mechanical selective laser-assisted die transfer
water streaming on the sample. In order to reduce the amount
(tmSLADT) method. In a separate operation, die receptor and
of debris produced, in our proof-of-concept experiments, the
via holes are laser machined in the flexible substrate with the
wafer was scanned 70 times with a high speed (400 mm/s)
patterned conductor lines. Depending on the substrate material,
and high repetition rate (80 kHz), using a flat-top 355 nm
some of these features can be produced by other methods,
HIPPO laser, as suggested in [43]. An average power of 3.0 W
for example, hot embossing and punching. After the laser
was used and the pulse energy was calculated as 37.5 μJ. To
die transfer, the polymer thick film inlaid (PTF-I) technique
prevent debris on the die bumps, a thin layer of photoresist
is used to plug the vias with conductive paste and connect
was coated on the wafer, prior to dicing, and was stripped
the dice to the conductor lines. Alternatively, the vias can be
afterwards (Fig. 2). After stripping, however, some debris
plugged with stencil printing. Additional components can be
still remained along the streets, which can be removed by
surface mounted on the top and bottom surfaces of the flexible
wiping the wafer with acetone. The number of scans is also
substrate. To minimize the tensile and/or compression bending
important because too many scans will result in a damaged
stresses in the components and conductors, all components,
DRL. The optimum number of scans needed to cut through
including the bare dice, should be positioned as close to the
the silicon was found, and, as seen in Fig. 2(c), the DRL is
neutral plane as possible. This condition can be satisfied if
slightly affected by the scanning, but the dice remain adhered
all components are located at or close to the middle of the
to the carrier.
substrate because this is where the neutral plane is located if
2) Die Bumping: Previous work indicated that the wafer
the bending radii are greater than two times the substrate thick-
bumping should be carried out prior to thinning [1], [9]. Prob-
ness. This concept is realized in the finished product in Fig. 1.
lems with this approach include the possibility of damaging
the bumps during wafer thinning [20] and the difficult control
B. Wafer Preparation of the thinning process [16]. These problems can be eliminated
1) Wafer Dicing: Due to the thinness of the dice needed for if the wafer is bumped after attaching it to the UV-transparent
flexible electronics and the bonding of the wafer to the carrier carrier and prior to laser dicing.
in the LEAP process, diamond sawing of the wafer is not Stud-bump bonding (SBB) technology proved useful and
an option. Stresses induced by the saw can crack the wafer reliable in overcoming the thermal stress problems in the
572 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012

Fig. 3. (a) 76-μm tall Au stud bumped on a test die. (b) 100-μm tall
electroplated Cu bump on a laser diced Si wafer. (c) Laser-ablated microvia Fig. 4. SEM photographs of (a) laser ablated receptor hole and vias (top side
in an unmodified THB151N film, and (d) same in a modified THB151N film. of the substrate) and (b) dual step trench on the bottom side of the substrate,
showing the exposed through the substrate Cu pad (the grainy area).

microelectronics assembly [44]. The assembly can be done

using conductive adhesives, still the lowest-cost assembly for control to make sure that the via bottom is clean and at the
lower-density products [45], eliminates solder defects such as same time the chip is not thermally damaged [23]. Almost
flux residues that may cause problems with underfill adhesion always this step requires lasers with a shaped, top-hat beam
and corrosion [46]. profile and die bumping with an additional thick metal layer.
In our experiments, Au studs were fabricated using a K&S In our approach, the via holes are not blind but through and
8028 wire bonding machine. A 25-μm (1-mil) diameter AW-9 are drilled before the die was attached, which simplifies the
Au wire (K&S) was used to make the studs on the 80×80 μm laser via drilling process significantly and alternatively allows
bond pads of a test die. The AW-9 wire was chosen based on the vias to be simply punched. The only blind vias are the
the results reported by Wei et al. [46] because of its wider ones that reach the copper conductors (Fig. 1). Cleaning the
bonding window, lower force and power requirements, and bottom of these via is not a problem because the copper
better bond ability than the traditional wires. After the initial layer is much thicker and can tolerate more aggressive laser
screening experiments, five parameters (separation height, drilling.
bump height, smoothing speed, fab diameter, and bond force) In our technology demonstration experiment, the substrate
were selected for a further optimization study with an objective was a Cu-clad 50-μm thick nylon with an etched RFID
of maximizing the length of the studs. A 25 full factorial design antenna. The top surface of the substrate was laminated with
with a total of 32 experiments was carried out with these a 37.5-μm (1.5-mil) thick PC1515 dry etch film (DuPont)
parameters. Their optimum values were identified and then to provide extra thickness for the laser machining of the
used to fabricate 76-μm tall stud bumps as the one shown in 50-μm deep receptor hole for the transferred die. The lam-
Fig. 3(a). ination was carried out for 10 s on an Optek Laminator with
Recently, the fabrication of copper column array area preset temperature and pressures preceded by a 25 s vacuum
studs using thick photoresist molds and electrodeposition pull. In the next step, the as prepared “sandwich” was trans-
process has gained much attention. The higher stand-off is ferred to an Optekshort-pulse 248 nm excimer laser system
an important factor in the package reliability [47] and the for receptor hole and trench micromachining. Typical ablation
thick photoresist shows promising results in fabricating more parameters were 10 bursts at a rate of 50 Hz with pulse energy
reliable interconnects with high aspect ratios. In our work, of around 140 μJ measured at the sample stage. Stage speed
a negative photoresist, THB151N (JSR Corporation, Japan), was set at 100 μm/sec giving ablation rates of about 16 μm per
was used as a mold to electroplate Cu studs, Fig. 3(b). As pass in both the substrate and laminate material. The targeted
the development of the unexposed portion of the negative dimension on the bottom of the receptor hole [Fig. 4(a)]
photoresist becomes difficult with the increase in the aspect was 740 × 740 μm (die size is 680 μm square). Dual-step,
ratio, a laser dry etching technique [48] was used to open 200-μm wide trenches for interconnecting the die to the Cu
up the microvias before the electroplating. There are some traces on the opposite side were ablated into the substrate
reported problems associated with dry etching, such as low material with varying depth - targeted at 25 μm over the
absorption coefficient [49], material carbonization [50], and receptor hole and through the whole substrate over the Cu
debris contamination [51]. In order to mitigate these problems, trace in order to expose the copper material as seen in Fig. 4(b)
a novel photopolymer based on the stock THB151N resist (see also Fig. 1 for the cross-section of the plugged via). Vias
was developed and optimized for laser ablation at 248 nm were drilled in the last micromachining step to connect the
wavelength. Examples of laser ablated microvias in the stock receptor hole on one side with the trench on the other. Based
and modified resists are compared in Fig. 3. The laser ablated on the targeted receptor hole and trench thicknesses, the via
microvias in the stock resist were conically shaped, the ablated depth was in the order of 15 μm. Micromachining debris were
surface very rough, and the ablation rate low [Fig. 3(c)]. removed in an ultrasonic cleaner for 5 min prior to device
After the material modification, the ablation rate showed fabrication.
significant improvements and microvias with nearly straight
walls were easily achieved [Fig. 3(d)]. Further details about D. Laser-Assisted Die Assembly
these experiments are presented elsewhere [52]. The basic concept of the technique known as “laser induced
forward transfer” (LIFT) includes using a polymeric sacrificial
C. Substrate Preparation layer to attach the components to be transferred to a laser-
Laser drilling the blind microvias needed to reach the transparent carrier. The sacrificial material coated on the
embedded die is a critical process step requiring precise opposite side of the target substrate is heated or ablated by
MARINOV et al.: LEAP OF ULTRATHIN BARE DICE IN FLEXIBLE SUBSTRATES 573

a laser pulse to generate gases that propel the component

toward a receiving substrate placed in close proximity. LIFT
is a unique contactless technology for placement of small-size
individual components on surfaces that may not be compatible
with the traditional pick-and-place equipment. It seems to be
the most promising, if not the only one feasible, method for a
high-volume assembly of small size, ultrathin semiconductor
bare dice. LIFT, if properly controlled, can safely assemble
Si tiles still attached to the Laser-transferred Si tiles
components with footprints of 2.6 × 2.6 mm to 100 × 100 μm releasing substrate on the receiving substrate
and thicknesses as small as 10 μm [53]. It is also capable of
much higher speed of placement −100 components per second Fig. 5. Two 65-μm thick Si tiles after tmSLADT. In this optical photograph,
compared to 1–2 components per second for the conventional the receiving substrate lies in the focal plane. The tiles were transferred from
the releasing substrate, which is in the background.
pick-and-place machines [53], [54].
The use of a laser for the transfer and placement of
discrete components onto a receiving substrate was first It provides a distinct advantage over previously proposed
reported by Holmes and Saidam [55], [56]. Recently, LIFT LIFT methods by confining, within a two-part DRL, the
has been applied to the transfer of semiconductor bare dice volatile plume of gas generated by laser ablation. A laser
by Karlitskaya et al. [54], [57]. In a number of publications, pulse vaporizes a shallow region of the absorbing/actuating
Piqué et al. have reported LIFT of various electronic layer which generates a pocket of high pressure gas. The
components [58]–[62]. elastic properties of the remaining absorbing/actuating layer
Karlitskaya et al. [54] have proposed two mechanisms of and the adhesive layer allow the pocket of gas to expand,
die release–ablative, in which a high-fluence single laser pulse forming a blister. This blister response of the DRL pro-
creates a high-velocity jet of evaporated release material that vides a mechanical actuator for placing dice on an electronic
releases the die at high speed, and the less intensive thermal substrate.
process in which the release material is heated gradually until tmSLADT is a rapid, more deliberate, and repeatable
it starts to decompose, literally dropping the die onto the process than the ablative LIFT technique. Also, the blister-
receiving substrate. actuator provides the bonded discrete component with suf-
Our results as well as the results published in the literature ficient kinetic energy to overcome surface forces which may
are indicative of one major problem with the ablative releasing hinder the thermal LIFT technique as die aspect ratios become
– the placement precision and accuracy. This problem is smaller. Evaluation of the tmSLADT concept performed with
inherent to the ablative laser process in which a relatively low 65-μm thick Si tiles indicates the nonoptimized method is
density gas pushes a higher density object. These effects can promising for placing ultrathin dice (Fig. 5). A tile transfer
be mitigated by controlling the release velocity. For example, rate as high as 90% was observed. The mean lateral translation
in the thermal releasing experiments with a green laser, the of dice from their initial bonded position was 50 μm, demon-
placement of the components was found to be ±35 μm over strated with a 195-μm gap between the releasing and receiving
a gap of 0.5 mm [54]. The problem with the thermal releasing substrates.
mechanism is the need to precisely control the process and The ability to place ultrathin dice without permanent
the release material properties in order to achieve the desired warpage or bending is critical for the subsequent interconnec-
effect. The separation of the die from the softened release tion of large number I/O fine pitch components. Permanent
layer relies on the gravitational force that has to overcome warpage post placement is not a concern with the contactless
the forces of attraction acting on the interface between the tmSLADT technique. This is evident by the results shown
die and release layer. For a die with a larger mass and higher in Fig. 6 indicating a maximum deviation from the ideal die
aspect ratio (thickness-to-projected area), this should not be a flatness of less than 0.6 μm.
problem but this may not be the case when the aspect ratio or An article more thoroughly describing the tmSLADT
the mass of a die become much smaller, which may happen process and the aforementioned evaluation results has recently
if the die is very thin or very small. been submitted by the authors of this paper [63].
During the last decade at least three research teams from
Europe (U.K. and the Netherlands) and the U.S. have stud-
ied this technology, all reporting successful results but no E. Die Interconnection: PTF-I
one suggesting how this advanced packaging method can be The thick-film methods used today to fabricate conduc-
interfaced with the existing technologies and integrated in tive traces on flexible boards are largely ineffective for
the entire production cycle, from the wafer to the completed resolutions below 50 μm. Thin-film technologies can fabri-
device. The technology integration is critical for the industry to cate high resolution patterns, however, they are prohibitively
start seriously considering LIFT as an alternative to the well- expensive for the low-cost flexible electronics. To address this
established pick-and-place technique. The tmSLADT process need, a modified mill-and-fill interconnect technology, referred
for placing ultrathin semiconductor dice was developed by our to as PTF-I was developed by our team [64], [65], in which
group with precisely this objective in mind – to become an trenches with the desired width, depth, and configuration are
integral and indispensable part of the entire LEAP process. formed and then filled with a conductive paste to produce, after
574 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 4, APRIL 2012

x-x Profile
nm
600
mm
1.3
500

1.0
400
0.8
x x 300
0.6
200
0.4

0.2
100

0.0
mm
0 mm
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.3 0.00 0.20 0.40 0.60 0.80 1.00

Fig. 6. Optical profile of a 1 mm square Si tile as it rests on a receiving

substrate after being placed by tmSLADT.
Laser transferred
bare die embedded
in the flex substrate

Fig. 8. Close up view of the laser-transferred and embedded RFID die.

Fig. 7. (a) Close-up of PTF-I-ed high-density silver lines next to a penny,

(Inset) a high-magnification SEM photograph of the same conductor lines
compared to a human hair. (b) Cured PTF-I line showing no cracking in the
material or delamination from the walls of the trench after bend testing.

TABLE I
C ONDUCTIVE S ILVER PASTE F ORMULATION

Component Description
Combination of acrylatedepoxidized soybean
oil, and trifunctional acrylate (19.8 wt.%)
Binder
and small concentration of benzoyl peroxide
as thermal initiator.
Solvent Tert-butyl acetate (approx. 2 wt.%) Fig. 9. Fully functional flexible electronic device (an RFID tag based on the
Alien technology’s Squiggle tag) fabricated using the LEAP technology.
Conductive particles Silver flakes, 2–4 μm. (78.2 wt.%)

exempt solvent and therefore the formulation is environmen-

curing, a high-resolution conductive trace pattern. A similar tally friendly. More details about this paper are available
method is currently under investigation in the Holst Centre in in [67].
the Netherlands [40], [66]. To test the mechanical properties of the material, 25-mm
In our proof-of-concept PTF-I experiments, high-precision long, 100-μm wide trenches were laser micromachined into a
conductive traces with an excellent edge definition, linewidths polyimide substrate and PTF-I filled with the paste. A total of
of less than 20 μm and a distance between lines as low as 25 samples were prepared and sintered at 150 °C overnight
6 μm were fabricated [Fig. 7(a)]. The minimum linewidth after which resistance measurements were taken. The mean
was only limited by the laser micromachining capabilities and line resistance measured was 1.81  with a standard deviation
the size of the metal particulates in the PTF. Arguably, no of 0.2 . The substrates were then subjected to bend tests
other thick-film method can match this process’s capability (100 repetitions each) onto a 50-mm diameter mandrel and the
for fabricating conductive traces with such high quality, high resistance was measured after each test. In the first test, the Ag
density, and high precision, at low cost and high throughput. filled trenches were facing the mandrel, essentially subjecting
The use of small size conductive particles in the PTF-I the Ag conductor lines to compression and in the second test,
material is especially important because previous PTF-I exper- the trenches were facing away from the mandrel surface thus
iments with off-the-shelf conductive pastes indicated that small stretching the Ag material. The measurements after the first
linewidths are possible but only if the particle size was and second bend tests showed mean resistances of 1.86  and
very small [64]. A conductive paste having low electrical 1.90  with standard deviations of 0.22  and 0.26 , respec-
resistivity and suitable for applications by the PTF-I method tively. A complete line filling and no cracking or delamination
was developed by using a mixture of acrylate oligomers as were observed in the lines under optical microscope and SEM
binder, tert-butyl acetate as solvent and micrometer-sized silver imaging [Fig. 7(b)]. The conclusion from these experiments
flakes as conductive filler. A typical paste formulation is was that the in-house prepared conductive paste possesses the
shown in Table I. The solvent tert-butyl acetate is a VOC- required flexibility, conductivity, and morphology required for
MARINOV et al.: LEAP OF ULTRATHIN BARE DICE IN FLEXIBLE SUBSTRATES 575

creating reliable and small linewidth printed conductors on a V. C ONCLUSION

flexible substrate.
One current limitation hindering the widespread use of
F. Reliability Testing of Embedded Dice embedded ultrathin dice is the lack of high volume placement
techniques with sufficient accuracy and precision for ultra-
Thermal cycling and mechanical bend tests were carried
fine pitch components. The laser-enabled “thinned wafer-to-
out to evaluate the reliability of the embedded bare dice.
finished product” electronics packaging method reported in
100-μm thick copper-clad (18 μm) liquid crystal polymer
this paper is an enabling process that shows promise of
(LCP) substrates (Ultralam 3850, Rogers Corporation) were
overcoming this obstacle and will ultimately contribute to
prepared for dice embedding following the procedure in Sec-
assembling flex substrate electronics with embedded ultrathin
tion III-C. The dice used in these tests were 690 × 690 μm,
dice at significantly lower cost and a higher production rate.
50-μm thick silicon tiles, blanket sputtered with 0.3-μm thick
The LEAP technology was successfully demonstrated for an
Cu layer. The embedded dice were connected to the test
EPC Global Gen2 UHF passive RFID tag. The tags proved to
pads on the LCP substrate through four via holes at the die
be functional and able to communicate with the RFID reader.
corners using the PTF-I method explained in Section III-E.
The reliability of the package was verified by measuring the
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[66] J. Van den Brand, R. Kusters, M. Barink, and A. Dietzel, “Flexible Ferdous Sarwar received the B.Sc. (summa cum
embedded circuitry: A novel process for high density, cost effective laude) and M.Sc. degrees in industrial and produc-
electronics,” Microelectron. Eng., vol. 87, no. 10, pp. 1861–1867, Oct. tion engineering from the Bangladesh University
2010. of Engineering and Technology (BUET), Dhaka,
[67] S. Datta, K. Keller, D. L. Schulz, and D. C. Webster, “Conductive Bangladesh, in 2004 and 2007, respectively. He is
adhesives from low-VOC silver inks for advanced microelectronics currently pursuing the Ph.D. degree in manufactur-
applications,” IEEE Trans. Comp., Packag. Manuf. Technol., vol. 1, no. 1, ing engineering at North Dakota State University
pp. 69–75, Jan. 2011. (NDSU), Fargo.
He was a Lecturer at BUET in 2004 and promoted
to Assistant Professor in 2007. He has been with
the Center for Nanoscale Science and Engineering
Val R. Marinov received the B.Sc. (magna cum (CNSE), NDSU, as a Graduate Research Assistant, since 2008. He has been
laude) and M.Sc. degrees in manufacturing engineer- involved in the micro-lithography and reliability analysis of ultra-thin chip
ing from Technical University, Rousse, Bulgaria, in packaging at CNSE.
1979. He received the Ph.D. degree in manufacturing Mr. Sarwar is a Student Member of the International Microelectronics
engineering from the Technical University of Sofia, and Packaging Society, the Surface Mount Technology Association, and the
Sofia, Bulgaria, in 1992. Institute of Industrial Engineers. He is currently the President of the NDSU
He has seven years of industrial and more than International Microelectronics and Packaging Society Student Chapter.
23 years of academic experience in the areas of
manufacturing engineering for metal, plastic, and
electronic products. He is currently an Associate
Professor of manufacturing engineering with North
Dakota State University (NDSU), Fargo. Prior to joining NDSU, he served on
the Faculty with Eastern Mediterranean University, Famagusta, Cyprus, from
1997 to 2000. His prior affiliations include Technical University in Plovdiv,
Plovdiv, Bulgaria, from 1987 to 1997, and the Laboratory for Precision
Machining and Machine Tools, Korea Advanced Institute of Science and
Yuriy A. Atanasov received the B.Sc. degree in
Technology, Taejon, South Korea, from 1993 to 1994. Since 2002, he has been mechanical engineering and the M.Sc. degree in
associated with the Center for Nanoscale Science and Engineering, NDSU, manufacturing engineering from North Dakota State
where he is a Research Team Leader managing numerous research projects in University (NDSU), Fargo. He is currently pursuing
the area of advanced packaging methods for flexible microelectronics systems.
the Ph.D. degree in materials and nanotechnology
He has co-authored over 40 publications in broad and diversified areas, with the same university.
including theory of material removal, finite-element modeling, tribology, and He has been with the Center for Nanoscale Science
most recently, advanced packaging methods for flexible electronics. and Engineering (CNSE), NDSU, since 2004, as
a Research Assistant. He has been involved with
various projects in the areas of advanced packaging
Orven F. Swenson received the B.Sc. and M.Sc. methods for flexible electronics and microfabrication
degrees in physics from North Dakota State Uni- at CNSE.
versity (NDSU), Fargo, in 1970 and 1971, respec-
tively, and the Ph.D. degree in laser optics from the
Air Force Institute of Technology, Wright-Patterson
AFB, Dayton, OH, in 1982.
He is an Associate Professor of physics with
NDSU and has been affiliated with the Center for
Nanoscale Science and Engineering, Fargo, as a
Faculty Associate for the past five years. He had
over eight years of research management experience Matthew Semler received the B.Sc. (magna cum
in the Air Force before joining NDSU in 1993. He was an Associate Professor laude) degree in physics from North Dakota State
of physics with U.S. Air Force Academy, Colorado Springs. University (NDSU), Fargo, in 2011.
Dr. Swenson has been instrumental in establishing an interdisciplinary He has been a Research Assistant with the Center
undergraduate Optical Science and Engineering Program at NDSU and has for Nanoscale Science and Engineering (CNSE),
developed a sequence of senior undergraduate/graduate courses that includes NDSU, since 2008, in the areas of micromachining
crystalline and polymeric materials with a pulsed
Optics for Scientists and Engineers, Lasers for Scientists and Engineers, and
Elements of Photonics. These courses are specifically designed for students lasers. While working at CNSE, he has presented
in any science or engineering major and emphasize hands-on learning in a two posters and co-authored a paper.
state-of-the-art optics teaching laboratory. He is a member of the American
Physical Society, the Optical Society of America, and the International Society
for Optical Engineering.

Ross Miller received the B.Sc. degree in physics

from U.S. Air Force Academy, Colorado Springs,
and the M.Sc. degree in electrical engineering from
North Dakota State University (NDSU), Fargo, in Samali Datta received the B.Sc. degree in chemistry
2005 and 2011, respectively. and the B.Tech. degree in polymer science and
He served as an active duty Air Force Officer technology from the University of Calcutta, Kolkata,
at DoD Space and Missiles System Center, Los India, the M.Tech. degree in polymer science and
Angeles AFB, CA, from 2005 to 2008, and was with engineering from the Indian Institute of Technology,
Microsoft from 2008 to 2009. He has been asso- New Delhi, India, and the Ph.D. degree in 2009.
ciated with the Center for Nanoscale Science and She was a Graduate Student in Prof. Dean Web-
Engineering, NDSU, since 2009, first as a Graduate ster’s Group with North Dakota State University
Research Assistant and currently as a Research Engineer Apprentice. His (NDSU), Fargo, researching the development of con-
current research interests include the areas of laser processing of materials, ductive ink formulations for microelectronics appli-
laser induced forward transfers, microfabrication, and advanced packaging cation. She is currently working on carbon-based
methods. conductive materials at NDSU.