CMT2390F64 Datasheet EN - V0.3 202406 - 1719450855
CMT2390F64 Datasheet EN - V0.3 202406 - 1719450855
CMT2390F64
Ultra-low Power Sub-1GHz Wireless Transceiver
MCU Features
A 32-bit general-purpose micro-controller based on the Arm® Cortex®-M0 core,single cycle hardware multiply
instrction
Up to 64 KByte on-chip Flash
- supports encrypted storage and hardware ECC verification
- endurance more than 100,000 cycles, 10 years of data retention
8 KByte on-chip SRAM,supports hardware parity
Programming method:
- SWD online debugging interface
- UART Bootloader
23 general IO (4 with SPI multiplexing in RF part)
Low-power management:
- Stop mode: RTC Runs, maximum 8 KByte SRAM retention, CPU register retention, all IO retention
- Power Down mode (PD): supports 3 IO wakeup
Clock:Up to 48 MHz
- LSE:32.768 KHz,external low-speed crystal
- HSI:Internal high-speed RC OSC 8 MHz
- LSI:Internal low-speed RC OSC 30 kHz
- Built-in high-speed PLL
- One channel clock output, which can be configured as configurable system clock, HSI or PLL
post-divided output
Reset
- Supports power-on/power-down/external pin reset
- Supports programmable low voltage detection and reset
- Supports watchdog reset
Communication Interface
- 3 x UART interface, with a maximum rate of 3 Mbps, of which 2 USART interfaces support 1xISO7816 ,
1xIrDA, LIN,1 of which supports low power consumption (LPUART), the highest communication rate in this
mode is 9600bps and stop mode can be awakened.
- 2 x SPI, the rate is up to 18 MHz, one of which supports multiplexing with I2S
- 2 x I2C, the rate is up to 1 MHz, master-slave mode is configurable, and dual-address response is supported
in slave mode
Analog interface
- 1 x 12 bit high-speed ADC, 1 Msps, up to 6 external single-ended input channels
- 1 x OPAMP, built-in programmable gain amplifier up to 32 times
- 1 x COMP, built-in 64-level adjustable comparison benchmark
- 1x high speed 5-channel DMA control, source address and destination address can be configured arbitrarily
Timer/Counter
- 1xRTC (real-time clock), supports leap year perpetual calendar, alarm event, periodic wake-up, supports
internal and external clock calibration
- 2x16 bit Advanced Timer Counters, supports input capture, complementary output, quadrature encoding input,
4 independent channels, of which 3 channels support 6 complementary PWM outputs
- 1x16 bit General Timer, 4 independent channels, supports input capture/output comparison/PWM output
- 1x16 bit Basic Timer
- 1 x 16 bit Low-Power Timer
RF Features
Working frequency: 113 - 960 MHz
Modulation style: 2 (G)FSK, 4 (G)FSK, OOK
Data rate: 0.1 - 1000 kbps
Sensitivity: 2 FSK, -122 dBm DR=2.4 kbps, 433.92 MHz
4 FSK, -88 dBm DR=1 Mbps,433.92 MHz
OOK, -94 dBm DR= 300 kbps, 433.92 MHz
RX current: 9.6 mA (DCDC) @ 433.92 MHz,FSK
( Only apply for the RF operation current )
TX current: 30 mA @ 13 dBm, 433.92 MHz, FSK / 82 mA@ 20 dBm,433.92 MHz, FSK
( Only apply for the RF operation current )
Supporting both direct and packet modes, with configurable packet handler and 128-Byte FIFO
System Features
Working voltage: 1.8 – 3.6 V
Working temperature: - 40 – 85 ℃
Package: QFN 48 6x6
Application
Auto metering
Home security and building automation
Wireless sensor nodes and industrial monitoring
ISM band data communication
Tag reader and writer
C13
C14
X1
32MHz
L6
GPIO0
GPIO1
NIRQ
VBAT
C7
C19
L8
L7
48
47
42
40
39
38
43
46
45
44
41
37
PB15/RF_SDI
PB14/RF_SDO
MCU_VDD
PB13/RF_SCK
PA8/RF_CSB
GPIO0
GPIO1
GND
NIRQ
XO
PB12
XI
C6
GPIO0
1 36
AGND PB3
2 35
RXP PB4
3 34
RXN PB5
L9 L5 L4 L3 L2 C1
4 NC 33
TX PB6
5 32
P1 PA_VDD PB7
CMT2390F64
6 31
C5 C4 C3 C2 L1 VIO QFN48_6x6_0.4 PA6
VBAT 7 30
GPIO4 GPIO4 49
PA4
8 29
GPIO5 GPIO5_RST U1 PA3
C12 C11 C10 9 28
RF_DVDD PA2
10 27
RF_AVDD PA1
11 26
VBAT DC_VSW PA0
12 25
GPIO2 GPIO2 MCU_AVDD VBAT
MCU_DVDD
C15 C8
MCU_NRST
C18
BOOT0
GPIO3
VBAT
PC14
PC13
PC15
PA10
PA13
PA14
PA9
13
14
15
17
18
19
21
22
23
16
20
24
GPIO3 VBAT
VBAT
C9 C16 C17
Figure 1-1. CMT2390F64 (QFN 48 6x6) Typical Application Diagram (disable DC-DC)
C13
C14
X1
32MHz
L6
GPIO0
GPIO1
NIRQ
VBAT
C7
C19
L8
L7
48
47
42
40
39
38
43
46
45
44
41
37
PB15/RF_SDI
PB14/RF_SDO
MCU_VDD
PB13/RF_SCK
PA8/RF_CSB
GPIO0
GPIO1
GND
NIRQ
XO
PB12
XI
C6
GPIO0
1 36
AGND PB3
2 35
RXP PB4
3 34
RXN PB5
L9 L5 L4 L3 L2 C1
4 NC 33
TX PB6
5 32
P1 PA_VDD PB7
CMT2390F64
6 31
C5 C4 C3 C2 L1 VIO QFN48_6x6_0.4 PA6
VBAT 7 30
GPIO4 GPIO4 49
PA4
8 29
GPIO5 GPIO5_RST U1 PA3
C12 C11 C10 9 28
RF_DVDD PA2
10 27
RF_AVDD PA1
L10
11 26
RF_VDD DC_VSW PA0
12 25
GPIO2 GPIO2 MCU_AVDD VBAT
MCU_DVDD
C15 C8
MCU_NRST
C18
BOOT0
GPIO3
VBAT
PC14
PC13
PC15
PA10
PA13
PA14
PA9
13
14
15
17
18
19
21
22
23
16
20
24
GPIO3 VBAT
VBAT
C9 C16 C17
Figure 1-2. CMT2390F64 (QFN 48 6x6) Typical Application Diagram (enable DC-DC)
Component Value
Signal Description 315 MHz 433 MHz 868 MHz 915 MHz Unit Supplier
+20 dBm +20 dBm +20 dBm +20 dBm
C1 ±5%, 0402 NP0, 50 V 22 12 12 12 pF
Component Value
Signal Description 315 MHz 433 MHz 868 MHz 915 MHz Unit Supplier
+20 dBm +20 dBm +20 dBm +20 dBm
±10%, 0603 Ceramic
R1 10k Ω
Chip Resistance
X1 ±10 ppm, SMD 32 MHz EPSON
CMT2390F64 RF
U1 Receiver and - CMOSTEK
Transmitter
1 Electrical Characteristic
VDD= 3.3 V,TOP= 25 °C,FRF = 433.92 MHz, sensitivity is measured by receiving a PN9 coded data and matching
impedance to 50Ω under 0.1% BER standard.Unless otherwise stated, all results are tested on the CMT2390F64-EM
evaluation board.
Notes:
[1]. Exceeding the Absolute Maximum Ratings may cause permanent damage to the equipment. This value is a pressure
rating and does not imply that the function of the equipment is affected under this pressure condition, but if it is exposed to
absolute maximum ratings for extended periods of time, it may affect equipment reliability.
[2]. The CMT2390F64 is a high-performance RF integrated circuit. The operation and assembly of this chip should only be
performed on a workbench with good ESD protection.
Caution! ESD sensitive device. Precaution should be used when handling the device in order to
prevent permanent damage.
Ready current
IReady 2.1 1.9 mA
[1]
315 MHz 74 / mA
433 MHz 82 81 mA
20 dBm[2] mA
868 MHz 88 87
915 MHz 88 87 mA
315 MHz 26.7 / mA
433 MHz 30 29 mA
13 dBm [3] 32 mA
868 MHz 33
915 MHz 34 33 mA
TX current [1] ITx mA
315 MHz 21 15
433 MHz 25 24 mA
10 dBm [3] mA
868 MHz 27 26
915 MHz 27 26 mA
315 MHz 10.3 7 mA
433 MHz 11 10 mA
-10 dBm [3] mA
868 MHz 12 11
915 MHz 12 11 mA
Notes:
Co-channel
DR = 2.4 kbps; FDEV = 1.2 kHz;
rejection
CCR BW = 4.8 kHz -7 dBc
@ 433 MHz,
CW interference, BER<0.1%
868 MHz
Adjacent
DR = 2.4 kbps; FDEV = 1.2 kHz;
channel
ACR-I433 BW = 4.8 kHz, Channel Space = 12.5 kHz, 62 dBc
rejection
CW interference, BER<0.1%
@ 433 MHz
Adjacent
DR = 2.4 kbps;FDEV = 1.2 kHz;
channel
ACR-I868 BW = 4.8 kHz, Channel Space = 12.5 kHz, 56 dBc
rejection
CW interference, BER < 0.1%
@ 868 MHz
±1 MHz offset 76 dBc
DR = 2.4 kbps; FDEV = 1.2 kHz;
Blocking
BI433 BW = 4.8 kHz, ±2 MHz offset 80 dBc
@ 433 MHz
CW interference, BER < 0.1%
±10 MHz offset 84 dBc
Input 3rd
order DR = 2.4 kbps; FDEV = 1.2 kHz;
IIP3433 -13 dBm
intercept point two-tone test with 10 MHz and 20 MHz deviations.
@ 433 MHz
Input 3rd
order DR = 2.4 kbps; FDEV = 1.2 kHz;
IIP3868 -12 dBm
intercept point two-tone test with 10 MHz and 20 MHz deviations.
@ 868 MHz
Harmonic output[1] H2433 2nd harmonic, +20 dBm POUT -56 dBm
for FRF= 433 MHz H3433 3rd harmonic, +20 dBm POUT -71 dBm
nd
Harmonic output[1] H2868 2 harmonic, +20 dBm POUT -47 dBm
for FRF= 868 MHz H3868 rd
3 harmonic, +20 dBm POUT -72 dBm
Harmonic output[1] H2433 2nd harmonic, +13 dBm POUT -44 dBm
for FRF= 433 MHz H3433 3rd harmonic, +13 dBm POUT -58 dBm
nd
Harmonic output[1] H2868 2 harmonic, +13 dBm POUT -50 dBm
for FRF= 868 MHz H3868 rd
3 harmonic, +13 dBm POUT -71 dBm
Harmonic output[1] H2915 2nd harmonic, +13 dBm POUT -54 dBm
for FRF= 915 MHz H3915 3rd harmonic, +13 dBm POUT -73 dBm
Notes:
[1]. The harmonic level mainly depends on the quality of matching network. The parameters above are measured on
CMT2390F64-EM.
[1]. TSLP-RX and TSLP-TX mainly depend on crystal oscillating, which is largely related to crystal itself.
[1]. For 2 FSK and 4 FSK, FDEV represents the frequency difference between the frequency points at the far ends (left and
right) and the centered frequency point.
1. The minimum sampling time was obtained from multiple cycles in application.
48 MHz 8.4
External clock(2) ,enable all
24 MHz 5.0
the peripherals
Operating current in the 8 MHz 2.8
IDD mA
operating mode 48 MHz 5.0
(2)
External clock ,disable all
24 MHz 3.3
the peripherals
8 MHz 2.3
1. Guaranteed by design and comprehensive assessment, not tested in production.
2. External clock, PLL is enabled when the fHCLK is 24 MHz or 48 MHz.
48 MHz 6.2
External clock(2) ,enable all
the peripherals 24 MHz 4.1
8 MHz 2.6
1. Guaranteed by design and comprehensive assessment, not tested in production.
2. External clock, PLL is enabled when the fHCLK is 24 MHz or 48 MHz.
48 MHz 6.5
External clock(2) ,enable all the peripherals 24 MHz 3.9
8 MHz 1.4
1. According to the comprehensive assessment, VDDmax and fHCLKmax enabling peripherals are the test condition.
2. External clock, PLL is enabled when the fHCLK is 24 MHz or 48 MHz.
2.7 5 mA
SLEEP mode Kernel stopped, all peripherals including Cortex-M 0
current core peripherals such as NVIC, system ticking clock
(SysTick) still running
1.5 2.5 uA
STOP mode current RTC is disabled, SRAM, registers and all I/O states
retain
0.5 1 uA
PD mode current VDD power down mode, 3 WAKEUP IO and NRST
can be awakened
The characteristic parameters in the following table are measured under a high-speed external clock source and the ambient
temperature and supply voltage meet the conditions in the following table.
VHSEH
90%
10%
VHSEL
t
tr(HSE) tf(HSE) tW(HSE) tW(HSE)
THSE
External clock
source
fHSE_ext OSC_IN
tr(LSE) ns
OSC32_IN up/ down time (1)
- - 10
tf(LSE)
VLSEH
90%
10%
VLSEL
t
tr(LSE) tf(LSE) tW(LSE) tW(LSE)
TLSE
External clock
source
fLSE_ext OSC32_IN
The high speed external clock (HSE) can be generated using an oscillator consisting of a 4~20 MHz crystal/ceramic
oscillator. The information given in this section is based on the use of typical external components listed in the table below. In
applications where the oscillator and load capacitance must be as close to the oscillator pin as possible to reduce output
distortion and stability time at startup. For detailed parameters of crystal oscillator (frequency, package, accuracy, etc.),
please consult the corresponding manufacturer (the crystal resonators mentioned here are usually referred to the passive
crystal oscillator).
1. The parameters of the resonator are given by the crystal resonator manufacturer.
2. Guaranteed by design and comprehensive assessment, not tested in production.
3. For CL1 and CL2, it is recommended to use high quality ceramic dielectric capacitance (typically) between 5pF and 25pF
designed for high-frequency applications, and to select suitable crystals or resonators. Usually CL1 and CL2 have the same
parameters. Crystal manufacturers usually give parameters for load capacitance as serial combinations of CL1 and CL2. The
capacitive reactance of PCB and MCU pins should be taken into account when selecting CL1 and CL2.
4. tSU(HSE) is the startup time. It is measured from the time when HSE is enabled by software until a stable 8 MHz oscillation is
obtained. This value is measured on a standard crystal resonator and can vary widely depending on the crystal manufacturer.
Integrated OSC_IN
capacitance CL1
oscillator fHSE
8 MHz Gain
RF
oscillator control
CL2
REXT OSC_OUT
Recommended load
CL1 capacitance and
RS: 30 KΩ ~ 65 KΩ
CL2(2) corresponding crystal serial - - 20 pF
impedance (RS)(3)
VDD = 3.3 V
CL1 = CL2 = 12.5 pF
I2 LSE drive current - 0.3 - μA
RS = 30 KΩ
tSU(LSE)(4) Startup time VDD is stable - 2 -
s
1. Guaranteed by design and comprehensive assessment, not tested in production.
2. See the attention and warning paragraph above this table.
3. Choose high quality oscillator with a small RS value that can optimize current consumption. Check with the crystal
manufacturer for more details.
4. tSU(LSE) is the start time, measured from the software enabling LSE, until the stable 32.768 KHz oscillation is stabled.This value
is measured on a standard crystal oscillator, which may vary greatly by the crystal manufacturer.
Integrated
capacitance CL1
oscillator
32.768 kHz Gain
Osillator control
CL2
Num.
Symbol Parameter Min Typ Max(1) Unit
PLL input clock (2) 4 8 20 MHz
fPLL_IN
PLL input clock duty cycle 40 - 60 %
fPLL_OUT PLL multiplier output clock 48 - 72 MHz
tLOCK PLL Ready indicates signal output time - - 50 μs
All I/O ports are CMOS and TTL compatible (no software configuration required) and their features take most of the strict
CMOS process or TTL parameters into account.
50%V1 50%V1
90%V1
tdf tdr
10%V1 10%V1
50%V1 50%V1
tf tr
VDD
Internal
MCU_NRST reset
Filter
VDD VDD
100Ω
SDA
I2C总线
SCL
100Ω
Repetitive
startup
Startup condition
condition
tsu(STA)
SDA
开始条件
tsu(SDA)
tf(SDA) tr(SDA) tv(SDA)
th(SDA) Stop
condition tw(STA STO)
tw(SCLH) tv(ACK)
SCL
tf(SCL)
tw(SCLL) tr(SCL) tsu(STO)
9th Clock
1/fSCL
1st clock
SPI 1 19.84 -
tsu(MI )(1) Master mode
SPI 2 20.5 -
Data input setup time ns
SPI 1 4.16 -
tsu(SI)(1) Slave mode
SPI 2 4.16 -
th(MI)(1) Master mode 0 -
Data input retention time
th(SI)(1) Slave mode 4 ns
-
ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK ns
Disabled time for data
tdis(SO)(1)(3) Slave mode 2 10 ns
output
Slave mode SPI 1 - 32
tv(SO)(1) (after the enabled edge) SPI 2 - 30
Valid time of data output
Mastermode SPI 1 - 28
ns
tv(MO)(1) (after theenabled edge) SPI 2 - 28
Slave mode
th(SO)(1) 0 -
(after the enabled edge)
Data output retention time
Master mode ns
th(MO)(1) 0 -
(after the enabled edge)
1. Guaranteed by design and comprehensive evaluation, not tested in production.
2. The minimum value means the minimum time to drive the output, and the maximum value means the maximum time to get the
data correctly.
3. The minimum value means the minimum time to turn off the output, and the maximum value means the maximum time to put the
data line in the high resistance state.
4. Test voltage is 3.3 V.
NSS input
CLKPOL=0 tw(SCLKH)
tw(SCLKL)
CLKPOL=1
ta(SO) tv(SO) th(SO) tdis(SO)
tr(SCLK)
tf(SCLK)
MISO output MSB out Bit 6~1 out LSB out
tsu(SI)
CLKPHA=1
NSS input
tc(SCLK) th(NSS)
tsu(NSS)
CLKPOL=0
tw(SCLKH)
tw(SCLKL)
CLKPOL=1 tr(SCLK)
ta(SO) tf(SCLK) tdis(SO)
tv(SO) th(SO)
1. The measurement points are set at CMOS level: 0.3 VDD and 0.7 VDD.
tc(SCLK)
CLKPHA=0
CLKPOL=0
CLKPHA=0
CLKPOL=1
CLKPHA=1
CLKPOL=0
CLKPHA=1 tr(SCLK)
CLKPOL=1 tf(SCLK)
tsu(MI) tw(SCLKH)
tw(SCLKL)
th(MI)
tv(MO) th(MO)
tc(CLK)
CLKPOL=0
CLKPOL=1
WS input
tv(SD_ST) th(SD_ST)
tsu(WS)
Last bit
SD transmit Last bit transmit(2) MSB transmit Bit n transmit
transmit
tsu(SD_SR) th(SD_SR)
Last bit
SD receive Last bit receive(2) MSB receive Bit n receive
receive
CLKPOL=0
CLKPOL=1
tsu(WS) tw(CLKH) tw(CLKL) th(WS)
WS input
tv(SD_MT) th(SD_ST)
Last bit
SD transmit Last bit transmit(2) MSB transmit Bit n transmit
transmit
tsu(SD_SR) th(SD_MR)
Last bit
SD receive Last bit receive(2) MSB receive Bit n receive
receive
VAIN Cparasitic
CADC
Parasitic
capacitance
PGA Gain = 2,
Cload = 25 pF, - 1 -
Rload = 10 KΩ
GA Gain = 4,
Cload = 25 pF, - 0.5 -
PGA bandwidth for Rload = 10 KΩ
PGA BW different non MHz
inverting gain GA Gain = 16,
Cload = 25 pF, - 0.125 -
Rload = 10 KΩ
GA Gain = 32,
Cload = 25 pF, - 0.0625 -
Rload = 10 KΩ
1. Guaranteed by design and comprehensive evaluation, not tested in production.
25
20
mA
15
10
kbps
0
2.4 4.8 10 20 50 100 200 300 400 500
-80
-90
dBm
-100
-110
-120
kbps
-130
2.4 4.8 10 20 50 100 200 300 400 500
20
15
dBm
10
0 V
1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8
434 MHz TX
span = 4 MHz, rbw = 1 kHz
30
20
10
-10
dBm
-20
-30
-40
-50
-60
-70
431.94
432.045
432.15
432.255
432.36
432.465
432.57
432.675
432.78
432.885
432.99
433.095
433.2
433.305
433.41
433.515
433.62
433.725
433.83
433.935
434.04
434.145
434.25
434.355
434.46
434.565
434.67
434.775
434.88
434.985
435.09
435.195
435.3
435.405
435.51
435.615
435.72
435.825
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
866.05
866.156
866.262
866.368
866.474
866.58
866.686
866.792
866.898
867.004
867.11
867.216
867.322
867.428
867.534
867.64
867.746
867.852
867.958
Rev 0.3 | 39 / 73
868.064
868.17
868.276
868 MHz TX
868.594
868.7
868.806
868.912
869.018
869.124
869.23
869.336
869.442
869.548
869.654
869.76
869.866
869.972
CMT2390F64
www.hoperf.com
CMT2390F64
2 Pin Description
PB14/RF_SDO
PB13/RF_SCK
PB15/RF_SDI
PA8/RF_CSB
MCU_VDD
GPIO1
GPIO0
NIQR
PB12
GND
XO
XI
48 47 46 45 44 43 42 41 40 39 38 37
AGND 1 36 PB3
RXP 2 35 PB4
RXN 3 34 PB5
TX 4 33 PB6
PA_VDD 5 32 PB7
CMT2390F64
VIO 6 QFN48_6x6_0.40 31 PA6
GPIO4 7 30 PA4
GPIO5_RST 8 29 PA3
GND
RF_DVDD 9 28 PA2
RF_AVDD 10 27 PA1
DC_VSW 11 26 PA0
GPIO2 12 25 MCU_AVDD
13 14 15 16 17 18 19 20 21 22 23 24
MCU_DVDD
MCU_NRST
VBAT
PA14
PA13
PA9
PC13
PC14
PC15
GPIO3
BOOT0
PA10
VCO VDD
Band-
LOOP LFXO LFOSC LDOs POR
CP PFD gap GND
FILTER
32 Mhz
XO
TX
PA D-DIV M-DIV GPIO 0
ANT
GPIO 1
AFC LOOP
GPIO 2
TRX IO
Matching GPIO 3
Ctrl
Network MODEM
Packet Handler GPIO 4
PGA ADC FIFO GPIO 5 (RSTn)
RXP
RXN LNA nIRQ
PGA ADC
Flash SDO
Flash Registers
Control
MaX: 48MHz
SRAM
SW
System Bus
AHB Bus Matrix
NVIC
AHB System Bus1
HDIV
DMA
DMA
SQRT
RCC
CRC
AHB
System Bus2
PWR
RTC SPI1/I2S1
APB2 Max: 48MHz
APB1 Max: 48MHz
CMT2390F64 is an integrated Sub-G high-performance wireless transceiver single chip. The internal system block diagram of
CMT2390F64 is shown in the above figure 3-1.
In OOK mode, when PA is switched on and off rapidly according to the transmitted data, it is easy to cause spectral spurts and
burrs near the carrier. These spurts and burrs can be minimized by a Ramping mechanism. In FSK mode, CMT2390F64
supports signal transmission after Gaussian filtering, namely GFSK, so that the transmission spectrum is more concentrated.
According to different application requirements, users can design a PA matching network to optimize the transmitting efficiency.
The transmitter can operate in direct mode and packet mode. In direct mode, the data can be sent to the chip by the DIN pin
and transmitted directly. In the packet mode, the data can be pre-loaded into theTX FIFO in STBY state, and transmitted
together with other package elements. Data can only be transmitted from FIFO in 4 FSK mode.
4.2 Receiver
CMT2390F64 has a built-in ultra-low power, high performance low-IF OOK, FSK receiver. The RF signal induced by the
antenna is amplified by a low noise amplifier, and is converted to an intermediate frequency by an orthogonal mixer. The signal
is filtered by the image rejection filter, and is amplified by the limiting amplifier and then sent to the digital domain for digital
demodulation. During power on reset (POR) each analog block is calibrated to the internal reference voltage. This allows the
chip to remain its best performance at different temperatures and voltages. Baseband filtering and demodulation is done by the
digital demodulator. The AGC loop adjust the system gain by the broad band power detector and attenuation network nearby
LNA, so as to obtain the best system linearity,selectivity, sensitivity and other performance.
Owing to CMOSTEK's low power design technic, the receiver consumes very low power when it is turned on.The periodic
operation mode and wake up function can further reduce the average power consumption of the system in the application with
strict requirements of power consumption.
Similar to the transmitter, the CMT2390F64 receiver can operate in direct mode and packet mode. In the direct mode,the
demodulator output data can be directly output through the DOUT pin of the chip.DOUT can be assigned to GPIO1/2/3. In the
packet mode, the demodulator data output is sent to the data packet handler, get decoded and is filled in the FIFO. MCU can
read the FIFO by the SPI interface.
RF-VDD
POR
VDD
POR
RSSI_AVG_MODE<2:0>
RSSI_DET_SEL<1:0>
COMPARE to RESULT
RSSI_TRIG_TH<7:0>
2 2 1 1 1 1
SYM SYM SYM SYM SYM SYM
COUNTING system – The system is designed for the symbol rates to be more accurate. If the symbol rate is100%
aligned, the unlimited length of 0 can be received continuously without error.
TRACING system – The system is designed to correct the symbol rate error. It has the tracking function. It can
automatically detect the symbol rate transmitted byTX, and adjust quickly the local symbol rate of RX at the sametime,
so as to minimize the error between them. The system can withstand up to 15.6% symbol rate error. Other similar
products in the industry cannot reach this level.
MANCHESTER system–This system evolves from the COUNTING system. The basic feature is the same. The only
difference is that the system is specially designed for Manchester codec. Special processing can be done when the TX
symbol rate has unexpected changes
𝐅𝐅𝐅𝐅𝐅𝐅𝐅𝐅 = 𝐁𝐁𝐁𝐁𝐁𝐁𝐁𝐁 𝐅𝐅𝐅𝐅𝐅𝐅𝐅𝐅 + 𝟏𝟏 𝐤𝐤𝐤𝐤𝐤𝐤 × 𝐅𝐅𝐅𝐅_𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎𝐎 < 𝟕𝟕: 𝟎𝟎 >× 𝐅𝐅𝐅𝐅_𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂𝐂 < 𝟕𝟕: 𝟎𝟎 >
In general, users can configure FH_OFFSET<7:0> during the chip initialization process. And then in the application, users
can switch the channel by changing FH_CHANNEL<7:0>.
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 X
register address
r/w = 1
SDO X 7 6 5 4 3 2 1 0 X
register read data
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
register address register write data
r/w = 0
SDO X 7 6 5 4 3 2 1 0 X
old register read data
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
For 3-wire read register, both MCU and CMT2390F64 will switch the IO (SDIO) port between address 0 and 7. At this point,
CMT2390F64 will switch the IO port from input to output, and MCU will switch the IO port from output to input. Please note the
dotted line in the middle. It is strongly recommended that MCU switch the IO port to input before sending out the falling edge of
SCLK. The CMT2390F64 does not switch IO to output until a falling edge happened. This avoids the situation when both of the
MCU and CMT2390F64 sets SDIO to output at the same time, which will result in electrical conflict. For some MCUs, this may
cause a reset or other abnormal behavior.
CSB
SCLK
SDI X X X
FIFO access port (0x7A)
r/w = 1
SDO X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
first-byte read data last-byte read data
following. For the following continuous read or write phase, it is up to users.
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
FIFO access port (0x7A) first-byte write data last-byte write data
r/w = 0
SDO X X X
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
r/w = 1 FIFO access port (0x7A) first-byte read data last-byte read data
CSB
SCLK
SDI X 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 X
r/w = 0 FIFO access port (0x7A) first-byte write data last-byte write data
SYNC_OK
RX_FIFO_WBYTE
RX_FIFO_NMTY
(FIFO_TH = 16)
RX_FIFO_TH
RX_FIFO_FULL
RX_FIFO_OVF
TX_FIFO_NMTY
(FIFO_TH = 16)
TX_FIFO_TH
TX_FIFO_FULL
RF-VDD
POR
POR Release XTAL Start up XTAL Stablize Block Calibrations Enters the SLEEP State Ready
<= 1 ms <= N ms <= 2.48 ms <= 6.5 ms for customer initializing
The chip enters SLEEP state after calibration. And then, the MCU can control the chip to switch to different operation states through
setting the register CHIP_MODE_SWT<7:0>.
Operation State
CMT2390F64 has 7 operation states: IDLE, SLEEP, STBY, RFS, RX, TFS and TX, as shown below.
IDLE
0x00
power_up
SLEEP
0x81
go_sleep
go_sleep
go_rx
go_ready
go_sleep
go_tx
go_tx go_rx
READY
0x82
go_sleep
go_sleep
go_ready go_ready
go_rfs
go_tfs
TFS RFS
0x88 0x84
go_rfs
go_tfs
go_rx
go_tx
TX go_tx RX
0xA0 go_rx 0x90
SLEEP State
The chip power consumption is the lowest in SLEEP state, and almost all the modules are turned off. SPI is open, the registers of
the configuration bank and control bank 1 will be saved, and the contents filled in the FIFO before will remain unchanged.
However, users cannot operate the FIFO and cannot change the contents of the register. If the user opens the wake-up function, the
LFOSC and the sleep counter will turn on and start working. The time required to switch from IDLE to SLEEP is the power up time.
Switch from other state to SLEEP will be completed immediately.
RFS State
RFS is a transition state before switching to RX. Except that the receiver RF module is off, the other modules are turned on, and the
current will be larger than STBY. Because PLL has been locked in the RX frequency, RFS cannot switch to TX. Switching from STBY
to RFS probably requires PLL calibration and stability time of 350 us. Switching from SLEEP to RFS needs to add the crystal
start-up and stability time. Switching from other state to RFS will be completed immediately.
TFS State
TFS is a transition state before switching to TX. Except that the transmitter RF module is off, the other modules are turned on, and
the current will be larger than STBY. Because PLL has been locked in the TX frequency, TFS cannot switch to RX. Switching from
STBY to TFS probably requires PLL calibration and stability time of 350us. Switching from SLEEP to TFS needs to add the crystal
start-up and settled time. Switching from other state to TFS will be completed immediately.
RX State
All modules on the receiver will be opened in RX state. Switching from RFS to RX requires only 20 us. Switching from STBY to
RX needs to add the PLL calibration and settled time of 350 us. Switching from SLEEP to RX needs to add the crystal start-up
and settled time. TX can be quickly switched to RX by sending go_switch command. Whether the TX and RX setting frequency is
the same, the user need to wait for the PLL re-calibration and settled time of 350 us to switch successfully.
TX State
All modules on the transmitter will be opened in TX state. Switching from TFS to TX requires only 20 us. Switching from STBY to
TX needs to add the PLL calibration and settled time of 350 us. Switching from SLEEP to TX needs to add the crystal start-up
and settled time. RX can be quickly switched to TX by sending go_switch command. Whether the RX and TX setting frequency is
the same, the user need to wait for the PLL re-calibration and settled time of 350 us to switch successfully. GPIO Function
and Interrupt Mapping
CMT2390F64 has 7 GPIO ports(GPIO0~GPIO5 and NIRQ). Each GPIO can be configured as a different input or output.
CMT2390F64 has 3 interrupt ports(INT1、INT2、INT3). They can be configured to different GPIO mapping output.
Below shows the Interrupt mapping in table 4-4. INT 1 and INT 2 mapping is the same. Take INT 1 as an example.
Interrupt is enabled when register value is 1 by default. Users can set the INT_POLAR register bit to 1 to make all interrupts
enabled when the register value is 0. Take INT1 as an example, the control and selection of two different types of interrupt sources
is shown in the figure below. The control and mapping ofINT1 and INT2 is the same and both can be mapped to any
GPIO.INT_MIX is the only source for INT3, which can only be mapped to GPIO0 and GPIO2. In application, users can choose
either to map all interrupt sources to the interrupt port through INT_MIX (identify which interrupt is valid by checking the interrupt
flag) or directly map a specific interrupt source to the interrupt port.
GPIO5_SEL <1:0>
GPIO5
GPIO4_SEL <1:0>
TX_FIFO_NMTY_FLG
GPIO1
GPIO0_SEL <1:0>
100010
GPIO1
nIRQ_SEL <1:0>
nIRQ
AHB
Reserved Reserved 0x4002_0C00 – 0x4002_0FFF
ADC 0x4002_0800 – 0x4002_0BFF
SQRT 0x4002_0400 – 0x4002_07FF
DMA 0x4002_0000 – 0x4002_03FF
Reserved 0x4001_8000 – 0x4001_FFFF
APB2
GPIOF 0x4001_1C00 – 0x4001_1FFF
0x4002_8400 – 0x5FFF_FFFF Reserved Reserved 0x4001_1400 – 0x4001_1BFF
0x4001_8000 – 0x4002_83FF AHB Peripheral GPIOC 0x4001_1000 – 0x4001_13FF
0x4001_5800 – 0x4001_7FFF Reserved GPIOB 0x4001_0C00 – 0x4001_0FFF
0x4001_0000 – 0x4001_57FF APB2 Peripheral GPIOA 0x4001_0800 – 0x4001_0BFF
0x4000_7800 – 0x4000_FFFF Reserved EXTI 0x4001_0400 – 0x4001_07FF
0x4000_0000 – 0x4000_77FF APB1 Peripheral AFIO 0x4001_0000 – 0x4001_03FF
;
32 maskable interrupt channels( not including 16 Cortex®-M0 interrupt lines)
4 programmable priority levels (using 2-bit interrupt priority levels );
The module provides flexible interrupt management functions with minimal interrupt delay.
The HSI clock is selected as the default system clock during reset. When needed, it is possible to take safe interrupt management
of the PLL clock (for example, when the indirect external oscillator fails).Users can configure the frequency of AHB and APB (APB1
and APB2) domains through multiple prescalers. The maximum allowable frequency of AHB domain, APB 1 domain and APB 2
domain is 48MHz.Figure 5-2 is a clock block diagram tree.
ADC1MSEL
HSE
ADC 1M
Prescaler ADC_CLK 1M
HSI
/1/2/…/32
FLASH_CLK
to Flash Programming
I2S_CLK
ADCPLLPRES[4]
ADC PLL ADC_PLLCLK
Prescaler
/1/2/…/256 ADC_CLK
ADC_HCLK
SCLKSW
ADC HCLK
LSE Prescaler CKMOD(ADC_CTRL3)
/1/2/…/32
HSI RC
LSI FCLK
8MHz
AHB CPU AHB BUS
SYSCLK HCLK
PLLMULFCT HSI
Prescaler /8 SysTick
Max. 48MHz
/1/2/…/512 DMA_CLK/CRC_CLK
PLLCLK
OSC_OUT PLL
HSE OSC APB1 Max. 48MHz
4-20MHz HSE Prescaler PCLK1 to APB1 peripherals
/1/2/4/8/16
OSC_IN PREDIV &
PLLSRC POSTDIV
TIM3/TIM6
CLKSSEN If(APB1 prescaler TIM3/TIM6_CLK
= 1) x1; else x2
TIM1/TIM8
OSC32_OUT If(APB2 prescaler
LSE OSC = 1) x1; else x2
32.768kHz RTC_CLK
LSE
OSC32_IN
SYSCLK
TIM1/TIM8_CLK
RTCSEL
MCO
For the values of VPOR/PDR and VPVD, please refer to the table for Embedded Reset and Power Control Module Features
SLEEP mode(the core is stopped, all peripherals including Cortex®-M0 core peripherals (such as NVIC, SysTick are still
running)
STOP mode(most of the clocks are turned off, the voltage regulator is still running in low power consumption mode)
PD mode(VDDD power-down mode,VDD hold,3 WAKEUP IO and NRST can be wake up)
In addition,the following methods can also reduce the power consumption in RUN mode:
Reduce the system clock frequency
Turn off the unused peripheral clocks on the APB and AHB buses
Optional configuration of PWR_CTRL4.STBFLH in RUN mode allows FLASH to enter deep standby mode; when
exiting, the system needs to wait about 10 us before re-accessing FLASH
In debug mode, the counter can be frozen and the PWM outputs are disabled, thereby cutting off the switches controlled
by these outputs. Many of the functions are the same as the standard TIM timer, and they also have the same internal
structure, so the advanced control timer can operate in collaboration with the TIM timer through the timer link function to
provide the synchronization or event link function.
This timer is specific used for real-time operating system and can also be used as a standard decrement counter.
It has the following characteristics:
24 bit decrement counter
Automatic reload function
A maskable system interrupt can be generated when the counter is 0
Programmable clock source
Independent watchdog(IWDG)
The independent watchdog is based on a 12-bit decline counter and an 8-bit prescaler, driven by an independent low- speed RC
oscillator that remains effective in the event of a master clock failure and operates in STOP mode. Once activated, IWDG
generates a reset when the counter counts to 0x000if the dog is not fed within the set time (clearing the watchdog counter). It can
be used to reset the entire system in the event of an application problem, or as a free timer to provide timeout management for the
application. The option byte can be configured to be software or hardware enabled watchdog. Reset and low power wake-up are
available.
Window watchdog(WWDG)
Window watchdogs are usually used to monitor software failures caused by external interference or unforeseen logic conditions
that cause the application to deviate from the normal operating sequence. Unless the value of the down counter is refreshed
before the T6 bit becomes 0, the watchdog circuit will generate an MCU reset when the preset time period is reached. Before the
down counter reaches the window register value, if the 7-bit down counter value (in the control register) is refreshed, an MCU reset
will also be generated. This indicates that the down counter needs to be refreshed in a limited time window.
Main features:
WWDG is driven by the clock after the APB 1 clock is divided;
Progranmable free running decrement counter;
Conditional reset;
When the decrement counter value is less than 0x40,(if the watchdog is started) a reset is generated;
Reset when the decrement counter is reloaded outside the window (if the watchdog is activated);
If the watchdag is enabled and interrupts are allowed, an early wake-up interrupt (EWI) is generated when the
decrements counter equals 0x40, which can be used to reload the counter to aviod a WWDG reset.
5.20 BEEPER
The BEEPER module supports complementary outputs and can generate periodic signals to drive external passive beeper. Used
to generate prompt sound or alarm sound.
7 Package Outline
Package information of CMT2390F64 is shown as followed.
D b e
48 48
1 L
2 1
2
D2
Ne
E
E2
K
EXPOSED THERMAL
Nd
Top View PAD ZONE Bottom View
A1
A
c
Side View
Size (mm)
Symbol
Min. Typ. Max.
A1 0 0.02 0.05
A3 —— 0.203 ——
e 0.40
D2 —— 4.20 ——
E2 —— 4.20 ——
L —— 0.40 ——
K —— 0.50 ——
R —— 0.05 ——
2 3 9 0 F 6 4
E 9 ①②
Y WW
Third line silk Date code, assigned by packaging plant, Y represents the last digit of the year and WW
printing represents the working week
9 Relevant Documents
Table 9-1. Other Related Application Documents
Number File Name
10 Revise History
Table 10-1. Revise History
Version Chapter Modify Date
0.1 All Initial 2023-01-03
Change the Unit of Co-channel rejection,Adjacent channel
0.2 1.4 2023-05-24
rejection,Blocking,Image Rejection from dBc to dB.
0.3 1.8/4.4 Update the crystal load capacitance from 15pF to 12pF 2024/6/20
11 Contacts
Shenzhen Hope Microelectronics Co., Ltd.
Address: 30th floor of 8th Building, C Zone, Vanke Cloud City, Xili Sub-district, Nanshan, Shenzhen, GD, P.R. China
Copyright. Shenzhen Hope Microelectronics Co., Ltd. All rights are reserved.
The information furnished by HOPERF is believed to be accurate and reliable. However, no responsibility is assumed for
inaccuracies and specifications within this document are subject to change without notice. The material contained herein is
the exclusive property of HOPERF and shall not be distributed, reproduced, or disclosed in whole or in part without prior
written permission of HOPERF. HOPERF products are not authorized for use as critical components in life support devices
or systems without express written approval of HOPERF. The HOPERF logo is a registered trademark of Shenzhen Hope
Microelectronics Co., Ltd. All other names are the property of their respective owners.