Lab Experiment-2
Title of the Experiment: To design and Implement adder and subtractor using Verilog code and Verify
output waveform (or) Response with respective truth tables.
Objective/Motivation: In this lab, a half adder, full adder, half subtractor and full subtractor are
designed. The objective will be to test these designs on Xilinx simulation tool. The tests will be performed
for all the possible combinations of inputs to verify their functionality. Moreover, the knowledge gained
will be used to design much larger and complex logic designs.
Equipment required:
S No Name of The Components/Tool Version Quantity
Xilinx Vivado Design Suite / EDA play Ground
1. V23.1 1
software
2. Zybo board Zynq XC7Z010 1
3. Personal Computer - 1
Logic diagram(s) and Truth tables:
Logic Circuit name Logic Diagram Logical Expression Truth Table
Inputs Outputs
A B Sum Carry
0 0 0 0
Half Adder
0 1 1 0
1 0 1 0
1 1 0 1
Inputs Outputs
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Full Adder
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Inputs Outputs
A B Diff Barrow
0 0 0 0
Half Subtractor
0 1 1 1
1 0 1 0
1 1 0 0
Inputs Outputs
A B Bin Diff Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
Full Subtractor
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Verilog Source Code for adder and subtractor in various Models or various Level of Abstrction:
Gate Level /
Gate name Data Flow Model Behavioral Model Test Bench
Structural Model
module Half_adder_d_tb();
reg t_a,t_b;
wire SUM,CARRY;
Half_adder
//Half Adder using data dut(.a(t_a),.b(t_b),.sum(SUM)
flow modeling ,.carry(CARRY));
module
Half_adder(a,b,sum,carry)
initial begin
;
// Half Adder using t_a=0;t_b=0;
input a,b;
Structural modeling // Half Adder using
#10
output sum,carry; behavioural modeling
Half Adder
t_a=0;t_b=1;
#10
assign sum=a^b;
t_a=1;t_b=0;
assign carry=a&b;
#10
t_a=1;t_b=1;
endmodule
#10
$stop;
end
endmodule
module full_adder_d_tb();
reg t_a,t_b,t_cin;
wire SUM,Cout;
//Full adder using
structural modeling
full_adder_d
module full_adder_d uut(.a(t_a),.b(t_b),.cin(t_cin),.
(a,b,cin,sum,carry); sum(SUM),.cout(Cout));
input a,b,cin;
output sum,cout initial begin
//full adder using data-
flow modeling t_a=0;t_b=0;t_cin=0;
module full_adder_d wire w1,w2,w3,w4; #10
(a,b,cin,sum,cout); //Internal connections
t_a=0;t_b=0;t_cin=1;
input a,b,cin;
#10
output sum,cout; xor(w1,a,b);
t_a=0;t_b=1;t_cin=0;
xor(sum,w1,cin);
Full Adder
//Sum output #10
assign sum=a^b^cin;
t_a=0;t_b=1;t_cin=1;
assign carry=(a&b)|(b &
cin)|(cin&a); and(w2,a,b); #10
and(w3,b,cin); t_a=1;t_b=0;t_cin=0;
endmodule and(w4,cin,a); #10
t_a=1;t_b=0;t_cin=1;
or(carry,w2,w3,w4); #10
//carry output
t_a=1;t_b=1;t_cin=0;
#10
endmodule
t_a=1;t_b=1;t_cin=1;
#10
$stop;
end
endmodule
module Half_
subtractor_d_tb();
reg t_a,t_b;
wire DIFF,BARROW;
Half_adder_d
//Half subtractot using dut(.a(t_a),.b(t_b),.diff(DIFF),
data flow modeling
.barrow(BARROW));
module
Half_subtractor_d(a,b,
diff,barrow); initial begin
input a,b; t_a=0;t_b=0;
Half output diff, barrow; #10
Subtractor
t_a=0;t_b=1;
assign diff=a^b; #10
assign barrow=(~a)&b; t_a=1;t_b=0;
#10
endmodule t_a=1;t_b=1;
#10
$stop;
end
endmodule
module
full_subtractor_d_tb();
reg t_a,t_b,t_bin;
wire DIFF,Bout;
full_subtractor_d
uut(.a(t_a),.b(t_b),.bin(t_bin),
.diff(DIFF),.bout(Bout));
initial begin
//full subtractor using
data-flow modeling t_a=0;t_b=0;t_cin=0;
module #10
full_subtractor_d
t_a=0;t_b=0;t_cin=1;
(a,b,bin,diff,bout);
#10
input a,b,Bin;
t_a=0;t_b=1;t_cin=0;
output diff,bout;
Full #10
Subtractor
t_a=0;t_b=1;t_cin=1;
assign diff=a^b^bin;
#10
assign bout=(~(a)&b)|
(b &bin)|(bin&~(a));
t_a=1;t_b=0;t_cin=0;
#10
endmodule
t_a=1;t_b=0;t_cin=1;
#10
t_a=1;t_b=1;t_cin=0;
#10
t_a=1;t_b=1;t_cin=1;
#10
$stop;
end
endmodule
//Half Adder subtractor using data flow modeling Test Bench
module Half_ AS_d_tb();
reg t_a,t_b;
wire SUM,CARRY,DIFF, BARROW;
//Half Adder subtractor
using data flow modeling
Half_AS _d
dut(.a(t_a),.b(t_b),.sum(SUM),.carry(CARRY).diff(DIFF),.barrow(BARROW));
module Half_AS_d(a,b,
sum, carry, diff,barrow);
input a,b; initial begin
output sum,carry,diff, t_a=0;t_b=0;
barrow;
Half Adder #10
&Subtractor
t_a=0;t_b=1;
assign sum=a^b;
#10
assign carry=a&b;
t_a=1;t_b=0;
assign diff=a^b;
#10
assign barrow=(~a)&b;
t_a=1;t_b=1;
#10
endmodule
$stop;
end
endmodule
//Full Adder subtractor using data flow modeling Test Bench
module full_AS_d_tb();
reg t_a,t_b,t_c;
wire SUM,CARRY,DIFF,BARROW;
full_AS_d
uut(.a(t_a),.b(t_b),.c(t_c),.sum(SUM),.carry(CARRY),.diff(DIFF),.barrow(BARROW));
//full adder using data-
flow modeling
initial begin
module full_AS_d
(a,b,c,sum,carry,diff,bar t_a=0;t_b=0;t_c=0;
row); #10
input a,b,c; t_a=0;t_b=0;t_c=1;
output #10
sum,carry,diff,barrow;
t_a=0;t_b=1;t_c=0;
Full Adder #10
assign sum=a^b^c;
&Subtractor
t_a=0;t_b=1;t_c=1;
assign carry=(a&b)|(b &
c)|(c&a); #10
assign diff=a^b^c; t_a=1;t_b=0;t_c=0;
assign barrow=(~ #10
(a)&b)|(b &c)|(c&~(a));
t_a=1;t_b=0;t_c=1;
#10
endmodule
t_a=1;t_b=1;t_c=0;
#10
t_a=1;t_b=1;t_c=1;
#10
$stop;
end
endmodule
Observation / Output Waveforms:
Result: The simulation waveforms are obtained with various input combination of binary data and
verified with the expected waveforms.
