SA9137

July 2018

SA9137 USB Audio Streaming Controller

1. Features 3. Applications

• Supply Range of 1.8 V to 3.3 V

• Control and I/O The SA9137 is a high-performance up to 32bit,
˗ I2C bus Master 384KHz PCM and DSD64/128/256 streaming USB
˗ FWIOs High-Speed compliant audio steaming controller. It
• Support iAP2
features one IEC60958 S/PDIF transmit streaming
• USB 2.0 High-Speed Compliant
output. The SA9137 is ideal for both one stereo-in
• USB Audio Class v1.0 and v2.0 supported
and one stereo-out professional digital audio
• Support Dynamic Consumption Adjustment
interface applications. Its PCM resolution and
• One interrupt endpoint for HID
sampling rate can be configurable with 16/24/32
• Support DSD64 / DSD128 / DSD256 both of
native and DoP in Async mode
• Support DSD L/R data line swap feature
• Support resolutions up to 32-bit and Device Information
sampling rates up to 384KHz PART NUMBER PACKAGE BODY SIZE
SA9137 QFN-48 6mm x 6mm
• Support 2ch playback
• Support 2ch record
• Support fixed DMCLK mode
4. Simplified Schematic
˗ 11.2896/ 12 / 12.288 / 22.5792/
24.576MHz
• One I2S input and one I2S output pairs for
USB HOST
PCM
Mobile Phone SA9137
˗ Independent sample rates for each
Computer etc
pair
˗ 32/ 44.1/ 48/ 88.2/ 96/ 176.4/ 192/
352.8/ 384 KHz sampling rates
˗ 16/24/32-bit resolution
• 48-pin QFN package

CODEC

2. Description

• Mobile Phone Audio Accessary

• Type-C Audio
• USB Audio
SA9137
July 2018

Table of Contents

1. Features .................................................................................................................................................... 1
2. Description................................................................................................................................................ 1
3. Applications .............................................................................................................................................. 1
4. Simplified Schematic .............................................................................................................................. 1
5. Pin Configuration and Functions........................................................................................................... 3
5.1 Pin Configuration ..................................................................................................................... 3
5.2 Pin Functions ........................................................................................................................... 4
6. Specifications ........................................................................................................................................... 6
6.1 DC Characteristics .................................................................................................................. 6
6.2 AC Timing Characteristics ..................................................................................................... 7
6.2.1 System Clocking Timing ................................................................................................. 7
6.2.2 Audio Interface Timing – Master Mode ........................................................................ 7
6.2.3 Audio Interface Timing – Slave Mode .......................................................................... 8
6.3 Dynamic Electrical Characteristics (DP/DM) ...................................................................... 9
7. Serial Audio Interfaces Formats .......................................................................................................... 10
7.1 L - Justified Format ............................................................................................................... 10
7.2 I2S Format .............................................................................................................................. 11
7.3 Fixed DMCLK Mode.............................................................................................................. 12
8. DSD Audio Data Interfaces .................................................................................................................. 13
9. iDevice Support ..................................................................................................................................... 14
10. S/PDIF TX Interface .............................................................................................................................. 15
11. I2C Master Interfaces ............................................................................................................................ 16
12. Chip Status Flags .................................................................................................................................. 17
13. Application and Implementation .......................................................................................................... 18
13.1 Typical Application................................................................................................................. 18
13.1.1 Serial Audio Interfaces Configuration-DAC (Master Mode) .................................... 18
13.1.2 Serial Audio Interfaces Configuration-DAC (Slave Mode) ...................................... 19
13.1.3 Serial Audio Interfaces Configuration-ADC ............................................................... 20
13.1.4 DSD External Control Signals ..................................................................................... 21
14. Package Outline (QFN-48) .................................................................................................................. 23
15. Revision History..................................................................................................................................... 24

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July 2018

5. Pin Configuration and Functions

5.1 Pin Configuration

DLRCLK
ALRCLK

DMCLK
REFCLK

AMCLK

ADATA
VDD18
VDDIO

VDDIO

ABCLK
TEST1

NC
48

47

42

41
36 DDATA
TEST0 1

VDDIO 2 35 NC

34 VDD18
GND 3

VDD18O 4 33 DBCLK

VDDIO 32 SDA

SA9137
5

VDDIO 6 31 SCL

QFN-48
VDD18 7 30 VDDIO

SOF_FLAG 8 29 RESETN

DSD_FLAG 9 28 GPIO6

DSD_128_FLAG 10 27 GPIO5

REXT 11 26 GPIO4

VDD33P 12 25 GPIO1
13

14

15

16

17

18

19

VDD33PLL 20

VDD33PLL 21

VDD33PLL 22

23

24
VDD18U
VDD33P

VSS33P

VDD18

VDDIO
DM

XO
DP

XI

Figure 5-1. QFN-48 Pin Diagram (Top View)

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July 2018

5.2 Pin Functions

PIN TYPE DESCRIPTION

NAME TQFP-80

TEST0 1 Ground normal mode: connect to GND

VDDIO 2 Power VDDIO 1.8V to 3.3V

GND 3 Ground GND

VDD18O 4 Power Connect 1uF to Ground

VDDIO 5 Power VDDIO 1.8V to 3.3V

VDDIO 6 Power VDDIO 1.8V to 3.3V

VDD18 7 Power 1.8V Core power

SOF_FLAG 8 O USB Start-Of-Frame indicator

DSD_FLAG 9 O DSD/PCM indicator

DSD_128_FLAG 10 O DSD64/DSD128 indicator

REXT 11 I Connect to 270ohm resistor to ground

VDD33P 12 Power USB2.0 PHY 3.3V power

VDD33P 13 Power USB2.0 PHY 3.3V power

DP 14 I/O USB2.0 signals

DM 15 I/O USB2.0 signals

VSS33P 16 Ground Ground

XI 17 I 12MHz X’stal input

XO 18 O 12MHz X’stal output

VDD18U 19 Power USB2.0 PHY 1.8V power

VDD33PLL 20 Power 3.3V PLL Power

VDD33PLL 21 Power 3.3V PLL Power

VDD33PLL 22 Power 3.3V PLL Power

VDD18 23 Power 1.8V Core power

VDDIO 24 Power VDDIO 1.8V to 3.3V

GPIO1 25 I/O Firmware assign function I/O port*1

GPIO4 26 I/O Firmware assign function I/O port*1

GPIO5 27 I/O Firmware assign function I/O port*1

GPIO6 28 I/O Firmware assign function I/O port*1

RESETN 29 I Power-on reset signal (Active low)

VDDIO 30 Power VDDIO 1.8V to 3.3V

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July 2018
SCL 31 O Master I2C clock

SDA 32 I/O Master I2C data

DBCLK 33 I/O I2S Playback BCLK

VDD18 34 Power 1.8V Core power

NC 35 - floating

DDATA 36 O I2S Playback DATA

DMCLK 37 I/O I2S Playback MCLK

DLRCLK 38 I/O I2S Playback LRCK

ABCLK 39 I/O I2S Record BCLK

ADATA 40 I I2S Record DATA

AMCLK 41 I/O I2S Record MCLK

NC 42 - floating

ALRCLK 43 I/O I2S Record LRCLK

VDDIO 44 Power VDDIO 1.8V to 3.3V

REFCLKIN 45 I External reference clock input

VDD18 46 Power 1.8V Core power

VDDIO 47 Power VDDIO 1.8V to 3.3V

TEST1 48 Ground normal mode: connect to GND

*1. All FWIOs are firmware assign function input/output, contact FAE to customize.

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July 2018

6. Specifications

6.1 DC Characteristics

Test Conditions: Ta = 25°C; VDD33 = +3.0 ∼ +3.6V; fs = 48 kHz-32bit sine wave

MIN TYP MAX UNIT

Input Low Voltage VDD33 = 3.3V 0.3*VDD33 V
VIL
Input High Voltage VDD33 = 3.3V 0.7*VDD33 V
VIH
Output Low Voltage IOL = 2mA 0.2 V
VOL
Output High Voltage IOH =2mA VDD33-0.2 V
VOH
VIN = 0V
Input Low Leakage Current IIL uA
VDD33 = 3.6V 10
VIN = 3.6V
Input High Leakage Current IIH 10 uA
VDD33 = 3.6V
VDD33 = 3.3V
Operation Current Idle*1 30 mA
VDD18 = Ext. DC-DC
Up to 192KHz VDD33 = 3.3V
Operation Current 45 mA
Playback*1 VDD18 = Ext. DC-DC
Up to 384KHz & VDD33 = 3.3V
Operation Current 66 mA
DSD Playback*2 VDD18 = Ext. DC-DC
Total 3.3V rail 2 3
Suspend mA
Suspend Current Total 1.8V rail 2 3

*1 The power mode is controlled by F/W. This mode can not support DSD.

*2 Support DSD up to DSD128 by DoP and DSD256 by native DSD.

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July 2018

6.2 AC Timing Characteristics

6.2.1 System Clocking Timing

tMCLKL

DMCLK/
AMCLK
tMCLKH

tMCLKY

Test Conditions: VDD = 3.3V, VSS = 0V, TA = +25°C, Master Mode fs = 48kHz, MCLK = 256fs, 24-‐bit data.

PARAMETER SYMBOL MIN TYP MAX UNIT

DMCLK/AMCLK System clock pulse width high tMCLKL 41.13 ns

DMCLK/AMCLK System clock pulse width low tMCLKH 40.23 ns

DMCLK/AMCLK System clock cycle time tMCLKY 81.36 ns

6.2.2 Audio Interface Timing – Master Mode

DBCLK
(output)

DLRCK
(output)
tDL

DDATA

tDD

Test Conditions: VDD = 3.3V, VSS = 0V, TA = +25°C, Master Mode fs = 48kHz, MCLK = 256fs, 24-‐bit data.

PARAMETER SYMBOL MIN TYP MAX UNIT

DLRCK propagation delay from DBCLK falling edge tDL 5 ns

DDATA propagation delay from DBCLK falling edge tDD 5 ns

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6.2.3 Audio Interface Timing – Slave Mode

tSCL

ABCLK

tSCH tLRSU

ALRCK
tSCY
tLRH

ADATA

tDD

Test Conditions: VDD = 3.3V, VSS = 0V, TA = +25°C, Master Mode fs = 48kHz, MCLK = 256fs, 24-‐bit data.

PARAMETER SYMBOL MIN TYP MAX UNIT

ABCLK cycle time tSCY 293 325 358 ns

ALRCK pulse width high tSCH 144 163 178 ns

ABCLK pulse width low tSCL 144 163 179 ns

ALRCK set-up time to ABCLK rising edge tLRSU 10

ALRCK hold time from ABCLK rising edge tLRH 10

ADATA propagation delay from ABCLK falling edge tDD 5

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6.3 Dynamic Electrical Characteristics (DP/DM)

Driver Characteristics:

PARAMETER SYMBOL MIN MAX UNIT

High – Speed Mode

High – speed differential rise time (10% - 90%) tHSR 500 ps

High – speed differential fall time (10% - 90%) tHSF 500 ps

Full – Speed Mode

Rise Time for DP/DM tFR 4 20 ns

Fall Time for DP/DM tFF 4 20 ns

Differential Rise/Fall Time Matching (tFR/tFF) tFRFM 90 110 %

Output Signal Crossover Voltage VCRS 1.3 2.0 V

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July 2018

7. Serial Audio Interfaces Formats

7.1 L - Justified Format

In Left Justified mode, the MSB is available on the first rising edge of DBCLK following an DLRCK transition. The other bits up to

the LSB are then transmitted in order. Depending on word length, DBCLK frequency and sample rate, there may be unused

DBCLK cycles before each DLRCK transition.

1/Fs

LEFT RIGHT
CHANNEL CHANNEL

DLRCK

DBCLK

DDATA 1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

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July 2018

7.2 I2S Format

In I2S mode, the MSB is available on the second rising edge of DBCLK following an DLRCK transition. The other bits up to the LSB

are then transmitted in order. Depending on word length, DBCLK frequency and sample rate, there may be unused DBCLK cycles

between the LSB of one sample and the MSB of the next.

1/Fs

LEFT RIGHT
CHANNEL CHANNEL

DLRCK

DBCLK

BCLK BCLK

1 2 n 1 2 n
DDATA n-2 n-1 n-2 n-1

MSB LSB MSB LSB

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July 2018

7.3 Fixed DMCLK Mode

SA9137 supports four different MCLKs during fix mode*1 which can generate high precision clock for DAC/CODEC/ADC.

- 11.2896Mhz

- 12Mhz

- 12.288Mhz

- 22.5792Mhz

- 24.576Mhz

*1 The fix mode is controlled by F/W.

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SA9137
July 2018

8. DSD Audio Data Interfaces

SA9137 supports five modes for playback DSD data over USB Audio streaming

PARAMETER DCLK DSD Mode

DSD 64 for 88.2K 32-bit DCLK(2.8224MHz) Direct DSD

DSD 128 for 176.4K 32-bit DCLK(5.6448MHz) Direct DSD

DSD 256 for 352.8K 32-bit DCLK(11.2896MHz) Direct DSD

DSD 64 for 176.4K 24-bit DCLK(5.6448MHz) DoP/dCS

DSD 128 for 352.8K 24-bit DCLK(11.2896MHz) DoP/dCS

tDCK

tDCKL
tDCKH
VIH
DCLK
VIL

tDDD

VIH
DSDL
DSDR VIL

The DSDL and DSDR are all output by negative edge of DCLK. And DSD DAC will sample them by post edge of DCLK.

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July 2018

9. iDevice Support

Apple strongly recommends the use of digital audio paths to and from accessories. Apple device in USB Host Mode

audio is the recommended approach. SA9137 will authenticate and identify itself to Apple device using iAP2 CP

before the iDevice will enumerate and start using USB Audio interface.

- Support 16 /24-bit linear PCM

- Support 44.1 / 48KHz sampling rate and up to 384KHz for future.
- Support input and output audio interface
- Support Volume Control Feature Unit
- Support iAP2 by CP2.0B and CP2.0C.

AMCLK

ALRCK
ADC
ABCLK

ADATA

HOST / iDevice SA9137

DMCLK

DLRCK

DBCLK
DAC

DDATA

FWIO8 I2C
(RST)

APPLE CP
(Coprocessor)

Digital USB Audio Application For iDevice

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July 2018

10. S/PDIF TX Interface

SA9137 support one S/PDIF TX interface, each can support up to 24-bit 384K sampling rate. Built in IEC60958

professional S/PDIF TX.

• AES/EBU supported
• DSD stream output on S/PDIF TX
• 32/ 44.1/ 48/ 88.2/ 96/ 176.4/ 192/ 325.8/ 384KHz sampling rates

• 16/24 bit resolution

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11. I2C Master Interfaces

One serial I²C master is supported in SA9137 to control external peripheral devices (EEPROM). SA9137 need an

EEPROM to load Firmware code from it.

SA9137 support use I²C Master Interfaces to read/write CP to support Apple MFi.

Byte Write

Ｓ Ｗ
Ｔ Ｒ Ｓ
Ａ Ｉ Ｔ
Ｒ Ｔ Ｏ
Ｔ DEVICE Ｅ Ｐ
ADDRESS WORD ADDRESS DATA

SDA LINE *

Ｍ Ｌ Ｒ Ａ Ｍ Ｌ Ａ Ａ
Ｓ Ｓ ／ Ｃ Ｓ Ｓ Ｃ Ｃ
Ｂ Ｂ Ｗ Ｋ Ｂ Ｂ Ｋ Ｋ

Random Read

Ｓ Ｗ Ｓ
Ｔ Ｒ Ｔ Ｒ Ｓ
Ａ DEVICE Ｉ Ａ DEVICE Ｅ Ｔ
Ｒ Ｔ Ｒ Ａ Ｏ
Ｔ ADDRESS WORD ADDRESS n Ｔ ADDRESS DATA n Ｐ
Ｅ Ｄ

SDA LINE *

Ｍ Ｌ Ｒ Ａ Ｍ Ｌ Ａ Ｍ Ｌ Ａ Ｎ
Ｓ Ｓ ／ Ｃ Ｓ Ｓ Ｃ Ｓ Ｓ Ｃ Ｏ
Ｂ Ｂ Ｗ Ｋ Ｂ Ｂ Ｋ Ｂ Ｂ Ｋ
Ａ
Ｃ
Ｋ

DUMMY WRITE

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12. Chip Status Flags

SA9137 provide these pins for display chip status flag

FLAG Definition

User can check this pin to understand DSD mode is detected or not

DSD_FLAG 0: PCM mode

1: DSD mode

User can check this pin to understand which DSD mode is played now (DSD64 or

DSD128 mode)
DSD_128_FLAG
0: DSD 64 mode

1: DSD 128 mode

SOF_FLAG USB Start-Of-Frame indicator

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July 2018

13. Application and Implementation

13.1 Typical Application

Typical application for SA9137 connecting with DAC / ADC. The following section shows how the SA9137 works with different serial

data format including PCM & DSD.

13.1.1 Serial Audio Interfaces Configuration-DAC (Master Mode)

SA9137 supports master mode for following configuration

DMCLK

DLRCK
SA9137 DAC
DBCLK

DDATA

MASTER SLAVE

SA9137 I2S Mater Mode Connection

Clock
Generator

REFCLKIN
Sampling Rate
(Replace DMCLK)

DMCLK

DLRCK
SA9137 DAC
DBCLK

DDATA

MASTER SLAVE
Master Mode (with external REFCLKIN), Mode 0

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OSC1
MUX
OSC2

REFCLKIN
(Replace DMCLK)
Sampling Rate
CLK1(45.1584MHz)
CLK2(49.152MHz)

DMCLK

DLRCK
SA9137 DAC
DBCLK

DDATA

MASTER SLAVE

Master Mode (with external REFCLKIN), Mode 1

13.1.2 Serial Audio Interfaces Configuration-DAC (Slave Mode)

SA9137 supports slave mode for following configuration

DMCLK

DLRCK
SA9137 DAC
DBCLK

DDATA

SLAVE MASTER

SA9137 I2S Slave Mode Connection

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13.1.3 Serial Audio Interfaces Configuration-ADC

SA9137 supports slave mode for following configuration

OSC

AMCLK

ALRCK
SA9137 ADC
ABCLK

ADATA

SLAVE MASTER

SA9137 I2S Slave Mode Connection

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13.1.4 DSD External Control Signals

• DSD_FLAG : (0 : RESET, 1: Normal Operation in DSD format):

Used to RESETN DSD DAC.

• DSD_FLAG : (0 : in PCM mode, 1: in DSD mode):

Used to witch DSD or PCM DAC.

• DSD_128 : (0 : in DSD 64 mode, 1: in DSD 128 mode):

Used to switch DSD64 and DSD128 format for DSD DAC

DSD_128_FLAG

RESETN
DSD DAC

DMCLK
DSD_CLK
DSD_DL
DSD_DR
DSD_FLAG

SA9137 SWITCH
2
I S / DSD

DMCLK
DBCLK
DLRCK
DDATA
PCM DAC
MUTE

Application with PCM DAC And DSD DAC

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DSD_128_FLAG
DSD64/128/256

DSD_FLAG
RESETN

PCM / DSD
SA9137
I2S / DSD DAC

MUTE
/MUTE

Application with PCM/DSD Multi Function DAC

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July 2018

14. Package Outline (QFN-48)

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July 2018

15. Revision History

Date (Y/M/D) Revision Reason Page Contents

Information furnished is believed to be accurate and reliable. However, SAVITECH assumes no responsibility for the consequences of use of such information

nor for any infringement of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent

or patent rights of SAVITECH. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces

all information previously supplied. SAVITECH products are not authorized for use as critical components in life support devices or systems without express

written approval of SAVITECH.

The SAVITECH logo is a registered trademark of Savitech Corporation.

All other names are the property of their respective owners

© 2011 Savitech Corporation - All Rights Reserved

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